Collaboration diagram for PLL Configuration:
Macros | |
| #define | __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) |
| #define | __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) |
| #define | __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) |
| #define | __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) |
| #define | __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) |
| Macros to enable or disable the main PLL. More... | |
| #define | __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) |
| Macros to enable or disable the main PLL. More... | |
| #define | __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) |
| Macros to enable or disable the main PLL. More... | |
| #define | __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) |
| Macros to enable or disable the main PLL. More... | |
| #define | __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) |
| Macro to configure the PLL multiplication factor. More... | |
| #define | __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) |
| Macro to configure the PLL multiplication factor. More... | |
| #define | __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) |
| Macro to configure the PLL multiplication factor. More... | |
| #define | __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) |
| Macro to configure the PLL multiplication factor. More... | |
| #define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) |
| Macro to configure the PLL clock source. More... | |
| #define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) |
| Macro to configure the PLL clock source. More... | |
| #define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) |
| Macro to configure the PLL clock source. More... | |
| #define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) |
| Macro to configure the PLL clock source. More... | |
Detailed Description
Macro Definition Documentation
◆ __HAL_RCC_PLL_DISABLE [1/4]
| #define __HAL_RCC_PLL_DISABLE | ( | ) | CLEAR_BIT(RCC->CR, RCC_CR_PLLON) |
Definition at line 886 of file stm32f7xx_hal_rcc.h.
◆ __HAL_RCC_PLL_DISABLE [2/4]
| #define __HAL_RCC_PLL_DISABLE | ( | ) | (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) |
Definition at line 1038 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.
◆ __HAL_RCC_PLL_DISABLE [3/4]
| #define __HAL_RCC_PLL_DISABLE | ( | ) | (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) |
Definition at line 1038 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.
◆ __HAL_RCC_PLL_DISABLE [4/4]
| #define __HAL_RCC_PLL_DISABLE | ( | ) | (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) |
Definition at line 1038 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.
◆ __HAL_RCC_PLL_ENABLE [1/4]
| #define __HAL_RCC_PLL_ENABLE | ( | ) | SET_BIT(RCC->CR, RCC_CR_PLLON) |
Macros to enable or disable the main PLL.
- Note
- After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
- The main PLL can not be disabled if it is used as system clock source
- The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Definition at line 885 of file stm32f7xx_hal_rcc.h.
◆ __HAL_RCC_PLL_ENABLE [2/4]
| #define __HAL_RCC_PLL_ENABLE | ( | ) | (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) |
Macros to enable or disable the main PLL.
- Note
- After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
- The main PLL can not be disabled if it is used as system clock source
- The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Definition at line 1037 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.
◆ __HAL_RCC_PLL_ENABLE [3/4]
| #define __HAL_RCC_PLL_ENABLE | ( | ) | (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) |
Macros to enable or disable the main PLL.
- Note
- After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
- The main PLL can not be disabled if it is used as system clock source
- The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Definition at line 1037 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.
◆ __HAL_RCC_PLL_ENABLE [4/4]
| #define __HAL_RCC_PLL_ENABLE | ( | ) | (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) |
Macros to enable or disable the main PLL.
- Note
- After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
- The main PLL can not be disabled if it is used as system clock source
- The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Definition at line 1037 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.
◆ __HAL_RCC_PLL_PLLM_CONFIG [1/4]
| #define __HAL_RCC_PLL_PLLM_CONFIG | ( | __PLLM__ | ) | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) |
Macro to configure the PLL multiplication factor.
- Note
- This function must be used only when the main PLL is disabled.
- Parameters
-
<strong>PLLM</strong> specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.
- Note
- You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.
Definition at line 907 of file stm32f7xx_hal_rcc.h.
◆ __HAL_RCC_PLL_PLLM_CONFIG [2/4]
| #define __HAL_RCC_PLL_PLLM_CONFIG | ( | __PLLM__ | ) | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) |
Macro to configure the PLL multiplication factor.
- Note
- This function must be used only when the main PLL is disabled.
- Parameters
-
<strong>PLLM</strong> specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.
- Note
- You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.
Definition at line 1059 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.
◆ __HAL_RCC_PLL_PLLM_CONFIG [3/4]
| #define __HAL_RCC_PLL_PLLM_CONFIG | ( | __PLLM__ | ) | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) |
Macro to configure the PLL multiplication factor.
- Note
- This function must be used only when the main PLL is disabled.
- Parameters
-
<strong>PLLM</strong> specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.
- Note
- You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.
Definition at line 1059 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.
◆ __HAL_RCC_PLL_PLLM_CONFIG [4/4]
| #define __HAL_RCC_PLL_PLLM_CONFIG | ( | __PLLM__ | ) | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) |
Macro to configure the PLL multiplication factor.
- Note
- This function must be used only when the main PLL is disabled.
- Parameters
-
<strong>PLLM</strong> specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.
- Note
- You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.
Definition at line 1059 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.
◆ __HAL_RCC_PLL_PLLSOURCE_CONFIG [1/4]
| #define __HAL_RCC_PLL_PLLSOURCE_CONFIG | ( | __PLLSOURCE__ | ) | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) |
Macro to configure the PLL clock source.
- Note
- This function must be used only when the main PLL is disabled.
- Parameters
-
<strong>PLLSOURCE</strong> specifies the PLL entry clock source. This parameter can be one of the following values: - RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
- RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Definition at line 896 of file stm32f7xx_hal_rcc.h.
◆ __HAL_RCC_PLL_PLLSOURCE_CONFIG [2/4]
| #define __HAL_RCC_PLL_PLLSOURCE_CONFIG | ( | __PLLSOURCE__ | ) | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) |
Macro to configure the PLL clock source.
- Note
- This function must be used only when the main PLL is disabled.
- Parameters
-
<strong>PLLSOURCE</strong> specifies the PLL entry clock source. This parameter can be one of the following values: - RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
- RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Definition at line 1048 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.
◆ __HAL_RCC_PLL_PLLSOURCE_CONFIG [3/4]
| #define __HAL_RCC_PLL_PLLSOURCE_CONFIG | ( | __PLLSOURCE__ | ) | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) |
Macro to configure the PLL clock source.
- Note
- This function must be used only when the main PLL is disabled.
- Parameters
-
<strong>PLLSOURCE</strong> specifies the PLL entry clock source. This parameter can be one of the following values: - RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
- RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Definition at line 1048 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.
◆ __HAL_RCC_PLL_PLLSOURCE_CONFIG [4/4]
| #define __HAL_RCC_PLL_PLLSOURCE_CONFIG | ( | __PLLSOURCE__ | ) | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) |
Macro to configure the PLL clock source.
- Note
- This function must be used only when the main PLL is disabled.
- Parameters
-
<strong>PLLSOURCE</strong> specifies the PLL entry clock source. This parameter can be one of the following values: - RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
- RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Definition at line 1048 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.