STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c
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1 
58 /* Includes ------------------------------------------------------------------*/
59 #include "stm32f4xx_rcc.h"
60 
70 /* Private typedef -----------------------------------------------------------*/
71 /* Private define ------------------------------------------------------------*/
72 /* ------------ RCC registers bit address in the alias region ----------- */
73 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
74 /* --- CR Register ---*/
75 /* Alias word address of HSION bit */
76 #define CR_OFFSET (RCC_OFFSET + 0x00)
77 #define HSION_BitNumber 0x00
78 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
79 /* Alias word address of CSSON bit */
80 #define CSSON_BitNumber 0x13
81 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
82 /* Alias word address of PLLON bit */
83 #define PLLON_BitNumber 0x18
84 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
85 /* Alias word address of PLLI2SON bit */
86 #define PLLI2SON_BitNumber 0x1A
87 #define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
88 
89 /* --- CFGR Register ---*/
90 /* Alias word address of I2SSRC bit */
91 #define CFGR_OFFSET (RCC_OFFSET + 0x08)
92 #define I2SSRC_BitNumber 0x17
93 #define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
94 
95 /* --- BDCR Register ---*/
96 /* Alias word address of RTCEN bit */
97 #define BDCR_OFFSET (RCC_OFFSET + 0x70)
98 #define RTCEN_BitNumber 0x0F
99 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
100 /* Alias word address of BDRST bit */
101 #define BDRST_BitNumber 0x10
102 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
103 
104 /* --- CSR Register ---*/
105 /* Alias word address of LSION bit */
106 #define CSR_OFFSET (RCC_OFFSET + 0x74)
107 #define LSION_BitNumber 0x00
108 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
109 
110 /* --- DCKCFGR Register ---*/
111 /* Alias word address of TIMPRE bit */
112 #define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
113 #define TIMPRE_BitNumber 0x18
114 #define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
115 /* ---------------------- RCC registers bit mask ------------------------ */
116 /* CFGR register bit mask */
117 #define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF)
118 #define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF)
119 
120 /* RCC Flag Mask */
121 #define FLAG_MASK ((uint8_t)0x1F)
122 
123 /* CR register byte 3 (Bits[23:16]) base address */
124 #define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
125 
126 /* CIR register byte 2 (Bits[15:8]) base address */
127 #define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
128 
129 /* CIR register byte 3 (Bits[23:16]) base address */
130 #define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
131 
132 /* BDCR register base address */
133 #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
134 
135 /* Private macro -------------------------------------------------------------*/
136 /* Private variables ---------------------------------------------------------*/
137 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
138 
139 /* Private function prototypes -----------------------------------------------*/
140 /* Private functions ---------------------------------------------------------*/
141 
205 void RCC_DeInit(void)
206 {
207  /* Set HSION bit */
208  RCC->CR |= (uint32_t)0x00000001;
209 
210  /* Reset CFGR register */
211  RCC->CFGR = 0x00000000;
212 
213  /* Reset HSEON, CSSON, PLLON and PLLI2S bits */
214  RCC->CR &= (uint32_t)0xFAF6FFFF;
215 
216  /* Reset PLLCFGR register */
217  RCC->PLLCFGR = 0x24003010;
218 
219  /* Reset PLLI2SCFGR register */
220  RCC->PLLI2SCFGR = 0x20003000;
221 
222  /* Reset HSEBYP bit */
223  RCC->CR &= (uint32_t)0xFFFBFFFF;
224 
225  /* Disable all interrupts */
226  RCC->CIR = 0x00000000;
227 
228 #ifdef STM32F427X
229  /* Disable Timers clock prescalers selection */
230  RCC->DCKCFGR = 0x00000000;
231 #endif /* STM32F427X */
232 
233 }
234 
255 void RCC_HSEConfig(uint8_t RCC_HSE)
256 {
257  /* Check the parameters */
258  assert_param(IS_RCC_HSE(RCC_HSE));
259 
260  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
261  *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
262 
263  /* Set the new HSE configuration -------------------------------------------*/
264  *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
265 }
266 
280 {
281  __IO uint32_t startupcounter = 0;
283  FlagStatus hsestatus = RESET;
284  /* Wait till HSE is ready and if Time out is reached exit */
285  do
286  {
287  hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
288  startupcounter++;
289  } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));
290 
292  {
293  status = SUCCESS;
294  }
295  else
296  {
297  status = ERROR;
298  }
299  return (status);
300 }
301 
310 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
311 {
312  uint32_t tmpreg = 0;
313  /* Check the parameters */
314  assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
315 
316  tmpreg = RCC->CR;
317 
318  /* Clear HSITRIM[4:0] bits */
319  tmpreg &= ~RCC_CR_HSITRIM;
320 
321  /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
322  tmpreg |= (uint32_t)HSICalibrationValue << 3;
323 
324  /* Store the new value */
325  RCC->CR = tmpreg;
326 }
327 
346 void RCC_HSICmd(FunctionalState NewState)
347 {
348  /* Check the parameters */
350 
351  *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
352 }
353 
371 void RCC_LSEConfig(uint8_t RCC_LSE)
372 {
373  /* Check the parameters */
374  assert_param(IS_RCC_LSE(RCC_LSE));
375 
376  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
377  /* Reset LSEON bit */
378  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
379 
380  /* Reset LSEBYP bit */
381  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
382 
383  /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
384  switch (RCC_LSE)
385  {
386  case RCC_LSE_ON:
387  /* Set LSEON bit */
388  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
389  break;
390  case RCC_LSE_Bypass:
391  /* Set LSEBYP and LSEON bits */
392  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
393  break;
394  default:
395  break;
396  }
397 }
398 
411 void RCC_LSICmd(FunctionalState NewState)
412 {
413  /* Check the parameters */
415 
416  *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
417 }
418 
454 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
455 {
456  /* Check the parameters */
457  assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
462 
463  RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
464  (PLLQ << 24);
465 }
466 
477 void RCC_PLLCmd(FunctionalState NewState)
478 {
479  /* Check the parameters */
481  *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
482 }
483 
503 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
504 {
505  /* Check the parameters */
508 
509  RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
510 }
511 
518 void RCC_PLLI2SCmd(FunctionalState NewState)
519 {
520  /* Check the parameters */
522  *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
523 }
524 
537 {
538  /* Check the parameters */
540  *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
541 }
542 
561 void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
562 {
563  uint32_t tmpreg = 0;
564 
565  /* Check the parameters */
566  assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source));
567  assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div));
568 
569  tmpreg = RCC->CFGR;
570 
571  /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */
572  tmpreg &= CFGR_MCO1_RESET_MASK;
573 
574  /* Select MCO1 clock source and prescaler */
575  tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
576 
577  /* Store the new value */
578  RCC->CFGR = tmpreg;
579 }
580 
599 void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
600 {
601  uint32_t tmpreg = 0;
602 
603  /* Check the parameters */
604  assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source));
605  assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));
606 
607  tmpreg = RCC->CFGR;
608 
609  /* Clear MCO2 and MCO2PRE[2:0] bits */
610  tmpreg &= CFGR_MCO2_RESET_MASK;
611 
612  /* Select MCO2 clock source and prescaler */
613  tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
614 
615  /* Store the new value */
616  RCC->CFGR = tmpreg;
617 }
618 
706 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
707 {
708  uint32_t tmpreg = 0;
709 
710  /* Check the parameters */
711  assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
712 
713  tmpreg = RCC->CFGR;
714 
715  /* Clear SW[1:0] bits */
716  tmpreg &= ~RCC_CFGR_SW;
717 
718  /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
719  tmpreg |= RCC_SYSCLKSource;
720 
721  /* Store the new value */
722  RCC->CFGR = tmpreg;
723 }
724 
734 uint8_t RCC_GetSYSCLKSource(void)
735 {
736  return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
737 }
738 
759 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
760 {
761  uint32_t tmpreg = 0;
762 
763  /* Check the parameters */
764  assert_param(IS_RCC_HCLK(RCC_SYSCLK));
765 
766  tmpreg = RCC->CFGR;
767 
768  /* Clear HPRE[3:0] bits */
769  tmpreg &= ~RCC_CFGR_HPRE;
770 
771  /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
772  tmpreg |= RCC_SYSCLK;
773 
774  /* Store the new value */
775  RCC->CFGR = tmpreg;
776 }
777 
778 
791 void RCC_PCLK1Config(uint32_t RCC_HCLK)
792 {
793  uint32_t tmpreg = 0;
794 
795  /* Check the parameters */
796  assert_param(IS_RCC_PCLK(RCC_HCLK));
797 
798  tmpreg = RCC->CFGR;
799 
800  /* Clear PPRE1[2:0] bits */
801  tmpreg &= ~RCC_CFGR_PPRE1;
802 
803  /* Set PPRE1[2:0] bits according to RCC_HCLK value */
804  tmpreg |= RCC_HCLK;
805 
806  /* Store the new value */
807  RCC->CFGR = tmpreg;
808 }
809 
822 void RCC_PCLK2Config(uint32_t RCC_HCLK)
823 {
824  uint32_t tmpreg = 0;
825 
826  /* Check the parameters */
827  assert_param(IS_RCC_PCLK(RCC_HCLK));
828 
829  tmpreg = RCC->CFGR;
830 
831  /* Clear PPRE2[2:0] bits */
832  tmpreg &= ~RCC_CFGR_PPRE2;
833 
834  /* Set PPRE2[2:0] bits according to RCC_HCLK value */
835  tmpreg |= RCC_HCLK << 3;
836 
837  /* Store the new value */
838  RCC->CFGR = tmpreg;
839 }
840 
874 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
875 {
876  uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
877 
878  /* Get SYSCLK source -------------------------------------------------------*/
879  tmp = RCC->CFGR & RCC_CFGR_SWS;
880 
881  switch (tmp)
882  {
883  case 0x00: /* HSI used as system clock source */
884  RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
885  break;
886  case 0x04: /* HSE used as system clock source */
887  RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
888  break;
889  case 0x08: /* PLL used as system clock source */
890 
891  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
892  SYSCLK = PLL_VCO / PLLP
893  */
894  pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
895  pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
896 
897  if (pllsource != 0)
898  {
899  /* HSE used as PLL clock source */
900  pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
901  }
902  else
903  {
904  /* HSI used as PLL clock source */
905  pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
906  }
907 
908  pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
909  RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
910  break;
911  default:
912  RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
913  break;
914  }
915  /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
916 
917  /* Get HCLK prescaler */
918  tmp = RCC->CFGR & RCC_CFGR_HPRE;
919  tmp = tmp >> 4;
920  presc = APBAHBPrescTable[tmp];
921  /* HCLK clock frequency */
922  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
923 
924  /* Get PCLK1 prescaler */
925  tmp = RCC->CFGR & RCC_CFGR_PPRE1;
926  tmp = tmp >> 10;
927  presc = APBAHBPrescTable[tmp];
928  /* PCLK1 clock frequency */
929  RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
930 
931  /* Get PCLK2 prescaler */
932  tmp = RCC->CFGR & RCC_CFGR_PPRE2;
933  tmp = tmp >> 13;
934  presc = APBAHBPrescTable[tmp];
935  /* PCLK2 clock frequency */
936  RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
937 }
938 
999 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
1000 {
1001  uint32_t tmpreg = 0;
1002 
1003  /* Check the parameters */
1004  assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
1005 
1006  if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
1007  { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
1008  tmpreg = RCC->CFGR;
1009 
1010  /* Clear RTCPRE[4:0] bits */
1011  tmpreg &= ~RCC_CFGR_RTCPRE;
1012 
1013  /* Configure HSE division factor for RTC clock */
1014  tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);
1015 
1016  /* Store the new value */
1017  RCC->CFGR = tmpreg;
1018  }
1019 
1020  /* Select the RTC clock source */
1021  RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);
1022 }
1023 
1031 void RCC_RTCCLKCmd(FunctionalState NewState)
1032 {
1033  /* Check the parameters */
1034  assert_param(IS_FUNCTIONAL_STATE(NewState));
1035 
1036  *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
1037 }
1038 
1048 void RCC_BackupResetCmd(FunctionalState NewState)
1049 {
1050  /* Check the parameters */
1051  assert_param(IS_FUNCTIONAL_STATE(NewState));
1052  *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
1053 }
1054 
1065 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
1066 {
1067  /* Check the parameters */
1068  assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
1069 
1070  *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
1071 }
1072 
1090 void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
1091 {
1092  /* Check the parameters */
1093  assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler));
1094 
1095  *(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler;
1096 
1097 }
1098 
1130 void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
1131 {
1132  /* Check the parameters */
1133  assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
1134 
1135  assert_param(IS_FUNCTIONAL_STATE(NewState));
1136  if (NewState != DISABLE)
1137  {
1138  RCC->AHB1ENR |= RCC_AHB1Periph;
1139  }
1140  else
1141  {
1142  RCC->AHB1ENR &= ~RCC_AHB1Periph;
1143  }
1144 }
1145 
1162 void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
1163 {
1164  /* Check the parameters */
1165  assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
1166  assert_param(IS_FUNCTIONAL_STATE(NewState));
1167 
1168  if (NewState != DISABLE)
1169  {
1170  RCC->AHB2ENR |= RCC_AHB2Periph;
1171  }
1172  else
1173  {
1174  RCC->AHB2ENR &= ~RCC_AHB2Periph;
1175  }
1176 }
1177 
1190 void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
1191 {
1192  /* Check the parameters */
1193  assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
1194  assert_param(IS_FUNCTIONAL_STATE(NewState));
1195 
1196  if (NewState != DISABLE)
1197  {
1198  RCC->AHB3ENR |= RCC_AHB3Periph;
1199  }
1200  else
1201  {
1202  RCC->AHB3ENR &= ~RCC_AHB3Periph;
1203  }
1204 }
1205 
1242 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
1243 {
1244  /* Check the parameters */
1245  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
1246  assert_param(IS_FUNCTIONAL_STATE(NewState));
1247 
1248  if (NewState != DISABLE)
1249  {
1250  RCC->APB1ENR |= RCC_APB1Periph;
1251  }
1252  else
1253  {
1254  RCC->APB1ENR &= ~RCC_APB1Periph;
1255  }
1256 }
1257 
1285 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
1286 {
1287  /* Check the parameters */
1288  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
1289  assert_param(IS_FUNCTIONAL_STATE(NewState));
1290 
1291  if (NewState != DISABLE)
1292  {
1293  RCC->APB2ENR |= RCC_APB2Periph;
1294  }
1295  else
1296  {
1297  RCC->APB2ENR &= ~RCC_APB2Periph;
1298  }
1299 }
1300 
1324 void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
1325 {
1326  /* Check the parameters */
1327  assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));
1328  assert_param(IS_FUNCTIONAL_STATE(NewState));
1329 
1330  if (NewState != DISABLE)
1331  {
1332  RCC->AHB1RSTR |= RCC_AHB1Periph;
1333  }
1334  else
1335  {
1336  RCC->AHB1RSTR &= ~RCC_AHB1Periph;
1337  }
1338 }
1339 
1353 void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
1354 {
1355  /* Check the parameters */
1356  assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
1357  assert_param(IS_FUNCTIONAL_STATE(NewState));
1358 
1359  if (NewState != DISABLE)
1360  {
1361  RCC->AHB2RSTR |= RCC_AHB2Periph;
1362  }
1363  else
1364  {
1365  RCC->AHB2RSTR &= ~RCC_AHB2Periph;
1366  }
1367 }
1368 
1378 void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
1379 {
1380  /* Check the parameters */
1381  assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
1382  assert_param(IS_FUNCTIONAL_STATE(NewState));
1383 
1384  if (NewState != DISABLE)
1385  {
1386  RCC->AHB3RSTR |= RCC_AHB3Periph;
1387  }
1388  else
1389  {
1390  RCC->AHB3RSTR &= ~RCC_AHB3Periph;
1391  }
1392 }
1393 
1427 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
1428 {
1429  /* Check the parameters */
1430  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
1431  assert_param(IS_FUNCTIONAL_STATE(NewState));
1432  if (NewState != DISABLE)
1433  {
1434  RCC->APB1RSTR |= RCC_APB1Periph;
1435  }
1436  else
1437  {
1438  RCC->APB1RSTR &= ~RCC_APB1Periph;
1439  }
1440 }
1441 
1466 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
1467 {
1468  /* Check the parameters */
1469  assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));
1470  assert_param(IS_FUNCTIONAL_STATE(NewState));
1471  if (NewState != DISABLE)
1472  {
1473  RCC->APB2RSTR |= RCC_APB2Periph;
1474  }
1475  else
1476  {
1477  RCC->APB2RSTR &= ~RCC_APB2Periph;
1478  }
1479 }
1480 
1512 void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
1513 {
1514  /* Check the parameters */
1515  assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));
1516  assert_param(IS_FUNCTIONAL_STATE(NewState));
1517  if (NewState != DISABLE)
1518  {
1519  RCC->AHB1LPENR |= RCC_AHB1Periph;
1520  }
1521  else
1522  {
1523  RCC->AHB1LPENR &= ~RCC_AHB1Periph;
1524  }
1525 }
1526 
1544 void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
1545 {
1546  /* Check the parameters */
1547  assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
1548  assert_param(IS_FUNCTIONAL_STATE(NewState));
1549  if (NewState != DISABLE)
1550  {
1551  RCC->AHB2LPENR |= RCC_AHB2Periph;
1552  }
1553  else
1554  {
1555  RCC->AHB2LPENR &= ~RCC_AHB2Periph;
1556  }
1557 }
1558 
1572 void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
1573 {
1574  /* Check the parameters */
1575  assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
1576  assert_param(IS_FUNCTIONAL_STATE(NewState));
1577  if (NewState != DISABLE)
1578  {
1579  RCC->AHB3LPENR |= RCC_AHB3Periph;
1580  }
1581  else
1582  {
1583  RCC->AHB3LPENR &= ~RCC_AHB3Periph;
1584  }
1585 }
1586 
1624 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
1625 {
1626  /* Check the parameters */
1627  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
1628  assert_param(IS_FUNCTIONAL_STATE(NewState));
1629  if (NewState != DISABLE)
1630  {
1631  RCC->APB1LPENR |= RCC_APB1Periph;
1632  }
1633  else
1634  {
1635  RCC->APB1LPENR &= ~RCC_APB1Periph;
1636  }
1637 }
1638 
1667 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
1668 {
1669  /* Check the parameters */
1670  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
1671  assert_param(IS_FUNCTIONAL_STATE(NewState));
1672  if (NewState != DISABLE)
1673  {
1674  RCC->APB2LPENR |= RCC_APB2Periph;
1675  }
1676  else
1677  {
1678  RCC->APB2LPENR &= ~RCC_APB2Periph;
1679  }
1680 }
1681 
1713 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
1714 {
1715  /* Check the parameters */
1716  assert_param(IS_RCC_IT(RCC_IT));
1717  assert_param(IS_FUNCTIONAL_STATE(NewState));
1718  if (NewState != DISABLE)
1719  {
1720  /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */
1721  *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
1722  }
1723  else
1724  {
1725  /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */
1726  *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
1727  }
1728 }
1729 
1749 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
1750 {
1751  uint32_t tmp = 0;
1752  uint32_t statusreg = 0;
1753  FlagStatus bitstatus = RESET;
1754 
1755  /* Check the parameters */
1756  assert_param(IS_RCC_FLAG(RCC_FLAG));
1757 
1758  /* Get the RCC register index */
1759  tmp = RCC_FLAG >> 5;
1760  if (tmp == 1) /* The flag to check is in CR register */
1761  {
1762  statusreg = RCC->CR;
1763  }
1764  else if (tmp == 2) /* The flag to check is in BDCR register */
1765  {
1766  statusreg = RCC->BDCR;
1767  }
1768  else /* The flag to check is in CSR register */
1769  {
1770  statusreg = RCC->CSR;
1771  }
1772 
1773  /* Get the flag position */
1774  tmp = RCC_FLAG & FLAG_MASK;
1775  if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
1776  {
1777  bitstatus = SET;
1778  }
1779  else
1780  {
1781  bitstatus = RESET;
1782  }
1783  /* Return the flag status */
1784  return bitstatus;
1785 }
1786 
1794 void RCC_ClearFlag(void)
1795 {
1796  /* Set RMVF bit to clear the reset flags */
1797  RCC->CSR |= RCC_CSR_RMVF;
1798 }
1799 
1813 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
1814 {
1815  ITStatus bitstatus = RESET;
1816 
1817  /* Check the parameters */
1818  assert_param(IS_RCC_GET_IT(RCC_IT));
1819 
1820  /* Check the status of the specified RCC interrupt */
1821  if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
1822  {
1823  bitstatus = SET;
1824  }
1825  else
1826  {
1827  bitstatus = RESET;
1828  }
1829  /* Return the RCC_IT status */
1830  return bitstatus;
1831 }
1832 
1846 void RCC_ClearITPendingBit(uint8_t RCC_IT)
1847 {
1848  /* Check the parameters */
1849  assert_param(IS_RCC_CLEAR_IT(RCC_IT));
1850 
1851  /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
1852  pending bits */
1853  *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
1854 }
1855 
1872 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
#define RCC_PLLCFGR_PLLP
Definition: stm32f4xx.h:8609
FlagStatus
Definition: stm32f4xx.h:706
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
Selects the clock source to output on MCO2 pin(PC9).
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
Configures the PLLI2S clock multiplication and division factors.
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the Low Speed APB (APB1) peripheral clock.
ErrorStatus RCC_WaitForHSEStartUp(void)
Waits for HSE start-up.
FunctionalState
Definition: stm32f4xx.h:708
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
Configures the RTC clock (RTCCLK).
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Enables or disables the AHB3 peripheral clock.
#define RCC_CFGR_PPRE2
Definition: stm32f4xx.h:8691
#define RCC_CFGR_HPRE
Definition: stm32f4xx.h:8656
#define RCC_CSR_RMVF
Definition: stm32f4xx.h:9100
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Forces or releases AHB1 peripheral reset.
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Forces or releases AHB3 peripheral reset.
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
Configures the system clock (SYSCLK).
void assert_param(int val)
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Enables or disables the AHB1 peripheral clock.
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the High Speed APB (APB2) peripheral clock.
#define RCC_PLLCFGR_PLLM
Definition: stm32f4xx.h:8590
void RCC_BackupResetCmd(FunctionalState NewState)
Forces or releases the Backup domain reset.
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
#define __I
Definition: core_cm0.h:195
static volatile uint8_t * status
Definition: drv_i2c.c:102
#define HSE_STARTUP_TIMEOUT
Comment the line below if you will not use the peripherals drivers. In this case, these drivers will ...
Definition: stm32f4xx.h:146
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
void RCC_PLLCmd(FunctionalState NewState)
Enables or disables the main PLL.
Definition: stm32f4xx.h:706
#define RCC_PLLCFGR_PLLSRC
Definition: stm32f4xx.h:8613
ITStatus RCC_GetITStatus(uint8_t RCC_IT)
Checks whether the specified RCC interrupt has occurred or not.
#define HSI_VALUE
Definition: stm32f4xx.h:150
enum FlagStatus ITStatus
#define RCC_PLLCFGR_PLLN
Definition: stm32f4xx.h:8598
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
Configures the main PLL clock source, multiplication and division factors.
#define __IO
Definition: core_cm0.h:198
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Enables or disables the AHB2 peripheral clock.
void RCC_LSEConfig(uint8_t RCC_LSE)
Configures the External Low Speed oscillator (LSE).
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
Configures the I2S clock source (I2SCLK).
void RCC_RTCCLKCmd(FunctionalState NewState)
Enables or disables the RTC clock.
#define HSE_VALUE
Comment the line below if you will not use the peripherals drivers. In this case, these drivers will ...
Definition: stm32f10x.h:119
void RCC_PCLK1Config(uint32_t RCC_HCLK)
Configures the Low Speed APB clock (PCLK1).
void RCC_LSICmd(FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
#define RCC
Definition: stm32f4xx.h:2122
static __I uint8_t APBAHBPrescTable[16]
void RCC_DeInit(void)
Resets the RCC clock configuration to the default reset state.
void RCC_HSICmd(FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void RCC_PCLK2Config(uint32_t RCC_HCLK)
Configures the High Speed APB clock (PCLK2).
ErrorStatus
Definition: stm32f4xx.h:711
#define RCC_CFGR_SWS
Definition: stm32f4xx.h:8644
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
#define IS_RCC_SYSCLK_SOURCE(SOURCE)
void RCC_ClearFlag(void)
Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
Enables or disables the Clock Security System.
#define RCC_CFGR_PPRE1
Definition: stm32f4xx.h:8679
#define RCC_CFGR_SW
Definition: stm32f4xx.h:8632
void RCC_PLLI2SCmd(FunctionalState NewState)
Enables or disables the PLLI2S.
void RCC_HSEConfig(uint8_t RCC_HSE)
Configures the External High Speed oscillator (HSE).
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
#define IS_RCC_I2SCLK_SOURCE(SOURCE)
void RCC_ClearITPendingBit(uint8_t RCC_IT)
Clears the RCC&#39;s interrupt pending bits.
#define RCC_CR_HSITRIM
Definition: stm32f4xx.h:8561
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
Checks whether the specified RCC flag is set or not.
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
Enables or disables the specified RCC interrupts.
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
Selects the clock source to output on MCO1 pin(PA8).
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.
uint8_t RCC_GetSYSCLKSource(void)
Returns the clock source used as system clock.
#define IS_RCC_AHB3_PERIPH(PERIPH)
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Forces or releases AHB2 peripheral reset.
#define RCC_CFGR_RTCPRE
Definition: stm32f4xx.h:8703
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
Configures the AHB clock (HCLK).
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
Configures the Timers clocks prescalers selection.


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19