CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c
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1 
58 /* Includes ------------------------------------------------------------------*/
59 #include "stm32f4xx_rcc.h"
60 
70 /* Private typedef -----------------------------------------------------------*/
71 /* Private define ------------------------------------------------------------*/
72 /* ------------ RCC registers bit address in the alias region ----------- */
73 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
74 /* --- CR Register ---*/
75 /* Alias word address of HSION bit */
76 #define CR_OFFSET (RCC_OFFSET + 0x00)
77 #define HSION_BitNumber 0x00
78 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
79 /* Alias word address of CSSON bit */
80 #define CSSON_BitNumber 0x13
81 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
82 /* Alias word address of PLLON bit */
83 #define PLLON_BitNumber 0x18
84 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
85 /* Alias word address of PLLI2SON bit */
86 #define PLLI2SON_BitNumber 0x1A
87 #define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
88 
89 /* Alias word address of PLLSAION bit */
90 #define PLLSAION_BitNumber 0x1C
91 #define CR_PLLSAION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
92 
93 /* --- CFGR Register ---*/
94 /* Alias word address of I2SSRC bit */
95 #define CFGR_OFFSET (RCC_OFFSET + 0x08)
96 #define I2SSRC_BitNumber 0x17
97 #define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
98 
99 /* --- BDCR Register ---*/
100 /* Alias word address of RTCEN bit */
101 #define BDCR_OFFSET (RCC_OFFSET + 0x70)
102 #define RTCEN_BitNumber 0x0F
103 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
104 /* Alias word address of BDRST bit */
105 #define BDRST_BitNumber 0x10
106 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
107 
108 /* --- CSR Register ---*/
109 /* Alias word address of LSION bit */
110 #define CSR_OFFSET (RCC_OFFSET + 0x74)
111 #define LSION_BitNumber 0x00
112 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
113 
114 /* --- DCKCFGR Register ---*/
115 /* Alias word address of TIMPRE bit */
116 #define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
117 #define TIMPRE_BitNumber 0x18
118 #define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
119 
120 /* --- CFGR Register ---*/
121 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
122  #if defined(STM32F410xx)
123 /* Alias word address of MCO1EN bit */
124 #define RCC_MCO1EN_BIT_NUMBER 0x8
125 #define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4))
126 
127 /* Alias word address of MCO2EN bit */
128 #define RCC_MCO2EN_BIT_NUMBER 0x9
129 #define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4))
130 #endif /* STM32F410xx */
131 /* ---------------------- RCC registers bit mask ------------------------ */
132 /* CFGR register bit mask */
133 #define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF)
134 #define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF)
135 
136 /* RCC Flag Mask */
137 #define FLAG_MASK ((uint8_t)0x1F)
138 
139 /* CR register byte 3 (Bits[23:16]) base address */
140 #define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
141 
142 /* CIR register byte 2 (Bits[15:8]) base address */
143 #define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
144 
145 /* CIR register byte 3 (Bits[23:16]) base address */
146 #define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
147 
148 /* BDCR register base address */
149 #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
150 
151 /* Private macro -------------------------------------------------------------*/
152 /* Private variables ---------------------------------------------------------*/
153 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
154 
155 /* Private function prototypes -----------------------------------------------*/
156 /* Private functions ---------------------------------------------------------*/
157 
225 void RCC_DeInit(void)
226 {
227  /* Set HSION bit */
228  RCC->CR |= (uint32_t)0x00000001;
229 
230  /* Reset CFGR register */
231  RCC->CFGR = 0x00000000;
232 
233  /* Reset HSEON, CSSON, PLLON, PLLI2S and PLLSAI(STM32F42xxx/43xxx/446xx/469xx/479xx devices) bits */
234  RCC->CR &= (uint32_t)0xEAF6FFFF;
235 
236  /* Reset PLLCFGR register */
237  RCC->PLLCFGR = 0x24003010;
238 
239 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469_479xx)
240  /* Reset PLLI2SCFGR register */
241  RCC->PLLI2SCFGR = 0x20003000;
242 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F469_479xx */
243 
244 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
245  /* Reset PLLSAICFGR register, only available for STM32F42xxx/43xxx/446xx/469xx/479xx devices */
246  RCC->PLLSAICFGR = 0x24003000;
247 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
248 
249  /* Reset HSEBYP bit */
250  RCC->CR &= (uint32_t)0xFFFBFFFF;
251 
252  /* Disable all interrupts */
253  RCC->CIR = 0x00000000;
254 
255  /* Disable Timers clock prescalers selection, only available for STM32F42/43xxx devices */
256  RCC->DCKCFGR = 0x00000000;
257 
258 #if defined(STM32F410xx)
259  /* Disable LPTIM and FMPI2C clock prescalers selection, only available for STM32F410xx devices */
260  RCC->DCKCFGR2 = 0x00000000;
261 #endif /* STM32F410xx */
262 }
263 
284 void RCC_HSEConfig(uint8_t RCC_HSE)
285 {
286  /* Check the parameters */
287  assert_param(IS_RCC_HSE(RCC_HSE));
288 
289  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
290  *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
291 
292  /* Set the new HSE configuration -------------------------------------------*/
293  *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
294 }
295 
309 {
310  __IO uint32_t startupcounter = 0;
312  FlagStatus hsestatus = RESET;
313  /* Wait till HSE is ready and if Time out is reached exit */
314  do
315  {
316  hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
317  startupcounter++;
318  } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));
319 
321  {
322  status = SUCCESS;
323  }
324  else
325  {
326  status = ERROR;
327  }
328  return (status);
329 }
330 
339 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
340 {
341  uint32_t tmpreg = 0;
342  /* Check the parameters */
343  assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
344 
345  tmpreg = RCC->CR;
346 
347  /* Clear HSITRIM[4:0] bits */
348  tmpreg &= ~RCC_CR_HSITRIM;
349 
350  /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
351  tmpreg |= (uint32_t)HSICalibrationValue << 3;
352 
353  /* Store the new value */
354  RCC->CR = tmpreg;
355 }
356 
376 {
377  /* Check the parameters */
379 
380  *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
381 }
382 
400 void RCC_LSEConfig(uint8_t RCC_LSE)
401 {
402  /* Check the parameters */
403  assert_param(IS_RCC_LSE(RCC_LSE));
404 
405  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
406  /* Reset LSEON bit */
407  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
408 
409  /* Reset LSEBYP bit */
410  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
411 
412  /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
413  switch (RCC_LSE)
414  {
415  case RCC_LSE_ON:
416  /* Set LSEON bit */
417  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
418  break;
419  case RCC_LSE_Bypass:
420  /* Set LSEBYP and LSEON bits */
421  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
422  break;
423  default:
424  break;
425  }
426 }
427 
441 {
442  /* Check the parameters */
444 
445  *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
446 }
447 
448 #if defined(STM32F410xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
449 
488 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR)
489 {
490  /* Check the parameters */
491  assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
496  assert_param(IS_RCC_PLLR_VALUE(PLLR));
497 
498  RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
499  (PLLQ << 24) | (PLLR << 28);
500 }
501 #endif /* STM32F410xx || STM32F446xx || STM32F469_479xx */
502 
503 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
504 
539 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
540 {
541  /* Check the parameters */
542  assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
547 
548  RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
549  (PLLQ << 24);
550 }
551 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
552 
564 {
565  /* Check the parameters */
567  *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
568 }
569 
570 #if defined(STM32F40_41xxx) || defined(STM32F401xx)
571 
593 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
594 {
595  /* Check the parameters */
598 
599  RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
600 }
601 #endif /* STM32F40_41xxx || STM32F401xx */
602 
603 #if defined(STM32F411xE)
604 
631 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM)
632 {
633  /* Check the parameters */
637 
638  RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28) | PLLI2SM;
639 }
640 #endif /* STM32F411xE */
641 
642 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
643 
667 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR)
668 {
669  /* Check the parameters */
673 
674  RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SQ << 24) | (PLLI2SR << 28);
675 }
676 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
677 
678 #if defined(STM32F446xx)
679 
713 void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR)
714 {
715  /* Check the parameters */
718  assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SP));
721 
722  RCC->PLLI2SCFGR = PLLI2SM | (PLLI2SN << 6) | (((PLLI2SP >> 1) -1) << 16) | (PLLI2SQ << 24) | (PLLI2SR << 28);
723 }
724 #endif /* STM32F446xx */
725 
733 {
734  /* Check the parameters */
736  *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
737 }
738 
739 #if defined(STM32F469_479xx)
740 
765 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR)
766 {
767  /* Check the parameters */
769  assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIP));
772 
773  RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIP << 16) | (PLLSAIQ << 24) | (PLLSAIR << 28);
774 }
775 #endif /* STM32F469_479xx */
776 
777 #if defined(STM32F446xx)
778 
806 void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ)
807 {
808  /* Check the parameters */
809  assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIM));
811  assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIP));
813 
814  RCC->PLLSAICFGR = PLLSAIM | (PLLSAIN << 6) | (((PLLSAIP >> 1) -1) << 16) | (PLLSAIQ << 24);
815 }
816 #endif /* STM32F446xx */
817 
818 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
819 
841 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR)
842 {
843  /* Check the parameters */
847 
848  RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIQ << 24) | (PLLSAIR << 28);
849 }
850 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
851 
862 {
863  /* Check the parameters */
865  *(__IO uint32_t *) CR_PLLSAION_BB = (uint32_t)NewState;
866 }
867 
880 {
881  /* Check the parameters */
883  *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
884 }
885 
904 void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
905 {
906  uint32_t tmpreg = 0;
907 
908  /* Check the parameters */
909  assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source));
910  assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div));
911 
912  tmpreg = RCC->CFGR;
913 
914  /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */
915  tmpreg &= CFGR_MCO1_RESET_MASK;
916 
917  /* Select MCO1 clock source and prescaler */
918  tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
919 
920  /* Store the new value */
921  RCC->CFGR = tmpreg;
922 
923 #if defined(STM32F410xx)
924  RCC_MCO1Cmd(ENABLE);
925 #endif /* STM32F410xx */
926 }
927 
949 void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
950 {
951  uint32_t tmpreg = 0;
952 
953  /* Check the parameters */
954  assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source));
955  assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));
956 
957  tmpreg = RCC->CFGR;
958 
959  /* Clear MCO2 and MCO2PRE[2:0] bits */
960  tmpreg &= CFGR_MCO2_RESET_MASK;
961 
962  /* Select MCO2 clock source and prescaler */
963  tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
964 
965  /* Store the new value */
966  RCC->CFGR = tmpreg;
967 
968 #if defined(STM32F410xx)
969  RCC_MCO2Cmd(ENABLE);
970 #endif /* STM32F410xx */
971 }
972 
1149 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
1150 {
1151  uint32_t tmpreg = 0;
1152 
1153  /* Check the parameters */
1154  assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
1155 
1156  tmpreg = RCC->CFGR;
1157 
1158  /* Clear SW[1:0] bits */
1159  tmpreg &= ~RCC_CFGR_SW;
1160 
1161  /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
1162  tmpreg |= RCC_SYSCLKSource;
1163 
1164  /* Store the new value */
1165  RCC->CFGR = tmpreg;
1166 }
1167 
1178 uint8_t RCC_GetSYSCLKSource(void)
1179 {
1180  return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
1181 }
1182 
1203 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
1204 {
1205  uint32_t tmpreg = 0;
1206 
1207  /* Check the parameters */
1208  assert_param(IS_RCC_HCLK(RCC_SYSCLK));
1209 
1210  tmpreg = RCC->CFGR;
1211 
1212  /* Clear HPRE[3:0] bits */
1213  tmpreg &= ~RCC_CFGR_HPRE;
1214 
1215  /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
1216  tmpreg |= RCC_SYSCLK;
1217 
1218  /* Store the new value */
1219  RCC->CFGR = tmpreg;
1220 }
1221 
1234 void RCC_PCLK1Config(uint32_t RCC_HCLK)
1235 {
1236  uint32_t tmpreg = 0;
1237 
1238  /* Check the parameters */
1239  assert_param(IS_RCC_PCLK(RCC_HCLK));
1240 
1241  tmpreg = RCC->CFGR;
1242 
1243  /* Clear PPRE1[2:0] bits */
1244  tmpreg &= ~RCC_CFGR_PPRE1;
1245 
1246  /* Set PPRE1[2:0] bits according to RCC_HCLK value */
1247  tmpreg |= RCC_HCLK;
1248 
1249  /* Store the new value */
1250  RCC->CFGR = tmpreg;
1251 }
1252 
1265 void RCC_PCLK2Config(uint32_t RCC_HCLK)
1266 {
1267  uint32_t tmpreg = 0;
1268 
1269  /* Check the parameters */
1270  assert_param(IS_RCC_PCLK(RCC_HCLK));
1271 
1272  tmpreg = RCC->CFGR;
1273 
1274  /* Clear PPRE2[2:0] bits */
1275  tmpreg &= ~RCC_CFGR_PPRE2;
1276 
1277  /* Set PPRE2[2:0] bits according to RCC_HCLK value */
1278  tmpreg |= RCC_HCLK << 3;
1279 
1280  /* Store the new value */
1281  RCC->CFGR = tmpreg;
1282 }
1283 
1318 {
1319  uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
1320 #if defined(STM32F446xx)
1321  uint32_t pllr = 2;
1322 #endif /* STM32F446xx */
1323 
1324  /* Get SYSCLK source -------------------------------------------------------*/
1325  tmp = RCC->CFGR & RCC_CFGR_SWS;
1326 
1327  switch (tmp)
1328  {
1329  case 0x00: /* HSI used as system clock source */
1330  RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
1331  break;
1332  case 0x04: /* HSE used as system clock source */
1333  RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
1334  break;
1335  case 0x08: /* PLL P used as system clock source */
1336 
1337  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1338  SYSCLK = PLL_VCO / PLLP
1339  */
1340  pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
1341  pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
1342 
1343  if (pllsource != 0)
1344  {
1345  /* HSE used as PLL clock source */
1346  pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
1347  }
1348  else
1349  {
1350  /* HSI used as PLL clock source */
1351  pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
1352  }
1353 
1354  pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
1355  RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
1356  break;
1357 
1358 #if defined(STM32F446xx)
1359  case 0x0C: /* PLL R used as system clock source */
1360  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1361  SYSCLK = PLL_VCO / PLLR
1362  */
1363  pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
1364  pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
1365 
1366  if (pllsource != 0)
1367  {
1368  /* HSE used as PLL clock source */
1369  pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
1370  }
1371  else
1372  {
1373  /* HSI used as PLL clock source */
1374  pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
1375  }
1376 
1377  pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2;
1378  RCC_Clocks->SYSCLK_Frequency = pllvco/pllr;
1379  break;
1380 #endif /* STM32F446xx */
1381 
1382  default:
1383  RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
1384  break;
1385  }
1386  /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
1387 
1388  /* Get HCLK prescaler */
1389  tmp = RCC->CFGR & RCC_CFGR_HPRE;
1390  tmp = tmp >> 4;
1391  presc = APBAHBPrescTable[tmp];
1392  /* HCLK clock frequency */
1393  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
1394 
1395  /* Get PCLK1 prescaler */
1396  tmp = RCC->CFGR & RCC_CFGR_PPRE1;
1397  tmp = tmp >> 10;
1398  presc = APBAHBPrescTable[tmp];
1399  /* PCLK1 clock frequency */
1400  RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
1401 
1402  /* Get PCLK2 prescaler */
1403  tmp = RCC->CFGR & RCC_CFGR_PPRE2;
1404  tmp = tmp >> 13;
1405  presc = APBAHBPrescTable[tmp];
1406  /* PCLK2 clock frequency */
1407  RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
1408 }
1409 
1470 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
1471 {
1472  uint32_t tmpreg = 0;
1473 
1474  /* Check the parameters */
1475  assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
1476 
1477  if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
1478  { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
1479  tmpreg = RCC->CFGR;
1480 
1481  /* Clear RTCPRE[4:0] bits */
1482  tmpreg &= ~RCC_CFGR_RTCPRE;
1483 
1484  /* Configure HSE division factor for RTC clock */
1485  tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);
1486 
1487  /* Store the new value */
1488  RCC->CFGR = tmpreg;
1489  }
1490 
1491  /* Select the RTC clock source */
1492  RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);
1493 }
1494 
1503 {
1504  /* Check the parameters */
1505  assert_param(IS_FUNCTIONAL_STATE(NewState));
1506 
1507  *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
1508 }
1509 
1520 {
1521  /* Check the parameters */
1522  assert_param(IS_FUNCTIONAL_STATE(NewState));
1523  *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
1524 }
1525 
1526 #if defined(STM32F446xx)
1527 
1545 void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource)
1546 {
1547  /* Check the parameters */
1548  assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
1549  assert_param(IS_RCC_I2S_APBx(RCC_I2SAPBx));
1550 
1551  if(RCC_I2SAPBx == RCC_I2SBus_APB1)
1552  {
1553  /* Clear APB1 I2Sx clock source selection bits */
1554  RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S1SRC;
1555  /* Set new APB1 I2Sx clock source*/
1556  RCC->DCKCFGR |= RCC_I2SCLKSource;
1557  }
1558  else
1559  {
1560  /* Clear APB2 I2Sx clock source selection bits */
1561  RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S2SRC;
1562  /* Set new APB2 I2Sx clock source */
1563  RCC->DCKCFGR |= (RCC_I2SCLKSource << 2);
1564  }
1565 }
1566 
1584 void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource)
1585 {
1586  /* Check the parameters */
1587  assert_param(IS_RCC_SAICLK_SOURCE(RCC_SAICLKSource));
1588  assert_param(IS_RCC_SAI_INSTANCE(RCC_SAIInstance));
1589 
1590  if(RCC_SAIInstance == RCC_SAIInstance_SAI1)
1591  {
1592  /* Clear SAI1 clock source selection bits */
1593  RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI1SRC;
1594  /* Set new SAI1 clock source */
1595  RCC->DCKCFGR |= RCC_SAICLKSource;
1596  }
1597  else
1598  {
1599  /* Clear SAI2 clock source selection bits */
1600  RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI2SRC;
1601  /* Set new SAI2 clock source */
1602  RCC->DCKCFGR |= (RCC_SAICLKSource << 2);
1603  }
1604 }
1605 #endif /* STM32F446xx */
1606 
1607 #if defined(STM32F410xx)
1608 
1619 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
1620 {
1621  /* Check the parameters */
1622  assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
1623 
1624  /* Clear I2Sx clock source selection bits */
1625  RCC->DCKCFGR &= ~RCC_DCKCFGR_I2SSRC;
1626  /* Set new I2Sx clock source*/
1627  RCC->DCKCFGR |= RCC_I2SCLKSource;
1628 }
1629 #endif /* STM32F410xx */
1630 
1631 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
1632 
1642 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
1643 {
1644  /* Check the parameters */
1645  assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
1646 
1647  *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
1648 }
1649 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
1650 
1651 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
1652 
1669 void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource)
1670 {
1671  uint32_t tmpreg = 0;
1672 
1673  /* Check the parameters */
1674  assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource));
1675 
1676  tmpreg = RCC->DCKCFGR;
1677 
1678  /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */
1679  tmpreg &= ~RCC_DCKCFGR_SAI1ASRC;
1680 
1681  /* Set SAI Block A source selection value */
1682  tmpreg |= RCC_SAIBlockACLKSource;
1683 
1684  /* Store the new value */
1685  RCC->DCKCFGR = tmpreg;
1686 }
1687 
1705 void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource)
1706 {
1707  uint32_t tmpreg = 0;
1708 
1709  /* Check the parameters */
1710  assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource));
1711 
1712  tmpreg = RCC->DCKCFGR;
1713 
1714  /* Clear RCC_DCKCFGR_SAI1BSRC[1:0] bits */
1715  tmpreg &= ~RCC_DCKCFGR_SAI1BSRC;
1716 
1717  /* Set SAI Block B source selection value */
1718  tmpreg |= RCC_SAIBlockBCLKSource;
1719 
1720  /* Store the new value */
1721  RCC->DCKCFGR = tmpreg;
1722 }
1723 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
1724 
1738 void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ)
1739 {
1740  uint32_t tmpreg = 0;
1741 
1742  /* Check the parameters */
1743  assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(RCC_PLLI2SDivQ));
1744 
1745  tmpreg = RCC->DCKCFGR;
1746 
1747  /* Clear PLLI2SDIVQ[4:0] bits */
1748  tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVQ);
1749 
1750  /* Set PLLI2SDIVQ values */
1751  tmpreg |= (RCC_PLLI2SDivQ - 1);
1752 
1753  /* Store the new value */
1754  RCC->DCKCFGR = tmpreg;
1755 }
1756 
1770 void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ)
1771 {
1772  uint32_t tmpreg = 0;
1773 
1774  /* Check the parameters */
1775  assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(RCC_PLLSAIDivQ));
1776 
1777  tmpreg = RCC->DCKCFGR;
1778 
1779  /* Clear PLLI2SDIVQ[4:0] and PLLSAIDIVQ[4:0] bits */
1780  tmpreg &= ~(RCC_DCKCFGR_PLLSAIDIVQ);
1781 
1782  /* Set PLLSAIDIVQ values */
1783  tmpreg |= ((RCC_PLLSAIDivQ - 1) << 8);
1784 
1785  /* Store the new value */
1786  RCC->DCKCFGR = tmpreg;
1787 }
1788 
1806 void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR)
1807 {
1808  uint32_t tmpreg = 0;
1809 
1810  /* Check the parameters */
1811  assert_param(IS_RCC_PLLSAI_DIVR_VALUE(RCC_PLLSAIDivR));
1812 
1813  tmpreg = RCC->DCKCFGR;
1814 
1815  /* Clear PLLSAIDIVR[2:0] bits */
1816  tmpreg &= ~RCC_DCKCFGR_PLLSAIDIVR;
1817 
1818  /* Set PLLSAIDIVR values */
1819  tmpreg |= RCC_PLLSAIDivR;
1820 
1821  /* Store the new value */
1822  RCC->DCKCFGR = tmpreg;
1823 }
1824 
1843 void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
1844 {
1845  /* Check the parameters */
1846  assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler));
1847 
1848  *(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler;
1849 }
1850 
1885 void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
1886 {
1887  /* Check the parameters */
1888  assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
1889 
1890  assert_param(IS_FUNCTIONAL_STATE(NewState));
1891  if (NewState != DISABLE)
1892  {
1893  RCC->AHB1ENR |= RCC_AHB1Periph;
1894  }
1895  else
1896  {
1897  RCC->AHB1ENR &= ~RCC_AHB1Periph;
1898  }
1899 }
1900 
1917 void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
1918 {
1919  /* Check the parameters */
1920  assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
1921  assert_param(IS_FUNCTIONAL_STATE(NewState));
1922 
1923  if (NewState != DISABLE)
1924  {
1925  RCC->AHB2ENR |= RCC_AHB2Periph;
1926  }
1927  else
1928  {
1929  RCC->AHB2ENR &= ~RCC_AHB2Periph;
1930  }
1931 }
1932 
1933 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
1934 
1947 void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
1948 {
1949  /* Check the parameters */
1950  assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
1951  assert_param(IS_FUNCTIONAL_STATE(NewState));
1952 
1953  if (NewState != DISABLE)
1954  {
1955  RCC->AHB3ENR |= RCC_AHB3Periph;
1956  }
1957  else
1958  {
1959  RCC->AHB3ENR &= ~RCC_AHB3Periph;
1960  }
1961 }
1962 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
1963 
2004 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
2005 {
2006  /* Check the parameters */
2007  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
2008  assert_param(IS_FUNCTIONAL_STATE(NewState));
2009 
2010  if (NewState != DISABLE)
2011  {
2012  RCC->APB1ENR |= RCC_APB1Periph;
2013  }
2014  else
2015  {
2016  RCC->APB1ENR &= ~RCC_APB1Periph;
2017  }
2018 }
2019 
2051 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
2052 {
2053  /* Check the parameters */
2054  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
2055  assert_param(IS_FUNCTIONAL_STATE(NewState));
2056 
2057  if (NewState != DISABLE)
2058  {
2059  RCC->APB2ENR |= RCC_APB2Periph;
2060  }
2061  else
2062  {
2063  RCC->APB2ENR &= ~RCC_APB2Periph;
2064  }
2065 }
2066 
2094 void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
2095 {
2096  /* Check the parameters */
2097  assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));
2098  assert_param(IS_FUNCTIONAL_STATE(NewState));
2099 
2100  if (NewState != DISABLE)
2101  {
2102  RCC->AHB1RSTR |= RCC_AHB1Periph;
2103  }
2104  else
2105  {
2106  RCC->AHB1RSTR &= ~RCC_AHB1Periph;
2107  }
2108 }
2109 
2123 void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
2124 {
2125  /* Check the parameters */
2126  assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
2127  assert_param(IS_FUNCTIONAL_STATE(NewState));
2128 
2129  if (NewState != DISABLE)
2130  {
2131  RCC->AHB2RSTR |= RCC_AHB2Periph;
2132  }
2133  else
2134  {
2135  RCC->AHB2RSTR &= ~RCC_AHB2Periph;
2136  }
2137 }
2138 
2139 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
2140 
2150 void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
2151 {
2152  /* Check the parameters */
2153  assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
2154  assert_param(IS_FUNCTIONAL_STATE(NewState));
2155 
2156  if (NewState != DISABLE)
2157  {
2158  RCC->AHB3RSTR |= RCC_AHB3Periph;
2159  }
2160  else
2161  {
2162  RCC->AHB3RSTR &= ~RCC_AHB3Periph;
2163  }
2164 }
2165 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
2166 
2204 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
2205 {
2206  /* Check the parameters */
2207  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
2208  assert_param(IS_FUNCTIONAL_STATE(NewState));
2209  if (NewState != DISABLE)
2210  {
2211  RCC->APB1RSTR |= RCC_APB1Periph;
2212  }
2213  else
2214  {
2215  RCC->APB1RSTR &= ~RCC_APB1Periph;
2216  }
2217 }
2218 
2247 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
2248 {
2249  /* Check the parameters */
2250  assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));
2251  assert_param(IS_FUNCTIONAL_STATE(NewState));
2252  if (NewState != DISABLE)
2253  {
2254  RCC->APB2RSTR |= RCC_APB2Periph;
2255  }
2256  else
2257  {
2258  RCC->APB2RSTR &= ~RCC_APB2Periph;
2259  }
2260 }
2261 
2296 void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
2297 {
2298  /* Check the parameters */
2299  assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));
2300  assert_param(IS_FUNCTIONAL_STATE(NewState));
2301  if (NewState != DISABLE)
2302  {
2303  RCC->AHB1LPENR |= RCC_AHB1Periph;
2304  }
2305  else
2306  {
2307  RCC->AHB1LPENR &= ~RCC_AHB1Periph;
2308  }
2309 }
2310 
2328 void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
2329 {
2330  /* Check the parameters */
2331  assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
2332  assert_param(IS_FUNCTIONAL_STATE(NewState));
2333  if (NewState != DISABLE)
2334  {
2335  RCC->AHB2LPENR |= RCC_AHB2Periph;
2336  }
2337  else
2338  {
2339  RCC->AHB2LPENR &= ~RCC_AHB2Periph;
2340  }
2341 }
2342 
2343 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
2344 
2358 void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
2359 {
2360  /* Check the parameters */
2361  assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
2362  assert_param(IS_FUNCTIONAL_STATE(NewState));
2363  if (NewState != DISABLE)
2364  {
2365  RCC->AHB3LPENR |= RCC_AHB3Periph;
2366  }
2367  else
2368  {
2369  RCC->AHB3LPENR &= ~RCC_AHB3Periph;
2370  }
2371 }
2372 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
2373 
2415 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
2416 {
2417  /* Check the parameters */
2418  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
2419  assert_param(IS_FUNCTIONAL_STATE(NewState));
2420  if (NewState != DISABLE)
2421  {
2422  RCC->APB1LPENR |= RCC_APB1Periph;
2423  }
2424  else
2425  {
2426  RCC->APB1LPENR &= ~RCC_APB1Periph;
2427  }
2428 }
2429 
2462 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
2463 {
2464  /* Check the parameters */
2465  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
2466  assert_param(IS_FUNCTIONAL_STATE(NewState));
2467  if (NewState != DISABLE)
2468  {
2469  RCC->APB2LPENR |= RCC_APB2Periph;
2470  }
2471  else
2472  {
2473  RCC->APB2LPENR &= ~RCC_APB2Periph;
2474  }
2475 }
2476 
2486 void RCC_LSEModeConfig(uint8_t RCC_Mode)
2487 {
2488  /* Check the parameters */
2489  assert_param(IS_RCC_LSE_MODE(RCC_Mode));
2490 
2491  if(RCC_Mode == RCC_LSE_HIGHDRIVE_MODE)
2492  {
2493  SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
2494  }
2495  else
2496  {
2497  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
2498  }
2499 }
2500 
2501 #if defined(STM32F410xx)
2502 
2513 void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource)
2514 {
2515  /* Check the parameters */
2516  assert_param(IS_RCC_LPTIM1_CLOCKSOURCE(RCC_ClockSource));
2517 
2518  /* Clear LPTIM1 clock source selection source bits */
2519  RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_LPTIM1SEL;
2520  /* Set new LPTIM1 clock source */
2521  RCC->DCKCFGR2 |= RCC_ClockSource;
2522 }
2523 #endif /* STM32F410xx */
2524 
2525 #if defined(STM32F469_479xx)
2526 
2535 void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource)
2536 {
2537  /* Check the parameters */
2538  assert_param(IS_RCC_DSI_CLOCKSOURCE(RCC_ClockSource));
2539 
2540  if(RCC_ClockSource == RCC_DSICLKSource_PLLR)
2541  {
2542  SET_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL);
2543  }
2544  else
2545  {
2546  CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL);
2547  }
2548 }
2549 #endif /* STM32F469_479xx */
2550 
2551 #if defined(STM32F446xx) || defined(STM32F469_479xx)
2552 
2561 void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource)
2562 {
2563  /* Check the parameters */
2564  assert_param(IS_RCC_48MHZ_CLOCKSOURCE(RCC_ClockSource));
2565 #if defined(STM32F469_479xx)
2566  if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI)
2567  {
2568  SET_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL);
2569  }
2570  else
2571  {
2572  CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL);
2573  }
2574 #elif defined(STM32F446xx)
2575  if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI)
2576  {
2577  SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL);
2578  }
2579  else
2580  {
2581  CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL);
2582  }
2583 #else
2584 #endif /* STM32F469_479xx */
2585 }
2586 
2596 void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource)
2597 {
2598  /* Check the parameters */
2599  assert_param(IS_RCC_SDIO_CLOCKSOURCE(RCC_ClockSource));
2600 #if defined(STM32F469_479xx)
2601  if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK)
2602  {
2603  SET_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL);
2604  }
2605  else
2606  {
2607  CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL);
2608  }
2609 #elif defined(STM32F446xx)
2610  if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK)
2611  {
2612  SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL);
2613  }
2614  else
2615  {
2616  CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL);
2617  }
2618 #else
2619 #endif /* STM32F469_479xx */
2620 }
2621 #endif /* STM32F446xx || STM32F469_479xx */
2622 
2623 #if defined(STM32F446xx)
2624 
2640 void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState)
2641 {
2642  /* Check the parameters */
2643  assert_param(IS_RCC_AHB1_CLOCKGATING(RCC_AHB1ClockGating));
2644 
2645  assert_param(IS_FUNCTIONAL_STATE(NewState));
2646  if (NewState != DISABLE)
2647  {
2648  RCC->CKGATENR &= ~RCC_AHB1ClockGating;
2649  }
2650  else
2651  {
2652  RCC->CKGATENR |= RCC_AHB1ClockGating;
2653  }
2654 }
2655 
2665 void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource)
2666 {
2667  /* Check the parameters */
2668  assert_param(IS_RCC_SPDIFRX_CLOCKSOURCE(RCC_ClockSource));
2669 
2670  if(RCC_ClockSource == RCC_SPDIFRXCLKSource_PLLI2SP)
2671  {
2672  SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL);
2673  }
2674  else
2675  {
2676  CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL);
2677  }
2678 }
2679 
2689 void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource)
2690 {
2691  /* Check the parameters */
2692  assert_param(IS_RCC_CEC_CLOCKSOURCE(RCC_ClockSource));
2693 
2694  if(RCC_ClockSource == RCC_CECCLKSource_LSE)
2695  {
2696  SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL);
2697  }
2698  else
2699  {
2700  CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL);
2701  }
2702 }
2703 #endif /* STM32F446xx */
2704 
2705 #if defined(STM32F410xx) || defined(STM32F446xx)
2706 
2716 void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource)
2717 {
2718  /* Check the parameters */
2719  assert_param(IS_RCC_FMPI2C1_CLOCKSOURCE(RCC_ClockSource));
2720 
2721  /* Clear FMPI2C1 clock source selection source bits */
2722  RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_FMPI2C1SEL;
2723  /* Set new FMPI2C1 clock source */
2724  RCC->DCKCFGR2 |= RCC_ClockSource;
2725 }
2726 #endif /* STM32F410xx || STM32F446xx */
2727 
2731 #if defined(STM32F410xx)
2732 
2738 void RCC_MCO1Cmd(FunctionalState NewState)
2739 {
2740  /* Check the parameters */
2741  assert_param(IS_FUNCTIONAL_STATE(NewState));
2742 
2743  *(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = (uint32_t)NewState;
2744 }
2745 
2752 void RCC_MCO2Cmd(FunctionalState NewState)
2753 {
2754  /* Check the parameters */
2755  assert_param(IS_FUNCTIONAL_STATE(NewState));
2756 
2757  *(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = (uint32_t)NewState;
2758 }
2759 #endif /* STM32F410xx */
2760 
2788 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
2789 {
2790  /* Check the parameters */
2791  assert_param(IS_RCC_IT(RCC_IT));
2792  assert_param(IS_FUNCTIONAL_STATE(NewState));
2793  if (NewState != DISABLE)
2794  {
2795  /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */
2796  *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
2797  }
2798  else
2799  {
2800  /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */
2801  *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
2802  }
2803 }
2804 
2826 {
2827  uint32_t tmp = 0;
2828  uint32_t statusreg = 0;
2829  FlagStatus bitstatus = RESET;
2830 
2831  /* Check the parameters */
2832  assert_param(IS_RCC_FLAG(RCC_FLAG));
2833 
2834  /* Get the RCC register index */
2835  tmp = RCC_FLAG >> 5;
2836  if (tmp == 1) /* The flag to check is in CR register */
2837  {
2838  statusreg = RCC->CR;
2839  }
2840  else if (tmp == 2) /* The flag to check is in BDCR register */
2841  {
2842  statusreg = RCC->BDCR;
2843  }
2844  else /* The flag to check is in CSR register */
2845  {
2846  statusreg = RCC->CSR;
2847  }
2848 
2849  /* Get the flag position */
2850  tmp = RCC_FLAG & FLAG_MASK;
2851  if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
2852  {
2853  bitstatus = SET;
2854  }
2855  else
2856  {
2857  bitstatus = RESET;
2858  }
2859  /* Return the flag status */
2860  return bitstatus;
2861 }
2862 
2870 void RCC_ClearFlag(void)
2871 {
2872  /* Set RMVF bit to clear the reset flags */
2873  RCC->CSR |= RCC_CSR_RMVF;
2874 }
2875 
2890 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
2891 {
2892  ITStatus bitstatus = RESET;
2893 
2894  /* Check the parameters */
2895  assert_param(IS_RCC_GET_IT(RCC_IT));
2896 
2897  /* Check the status of the specified RCC interrupt */
2898  if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
2899  {
2900  bitstatus = SET;
2901  }
2902  else
2903  {
2904  bitstatus = RESET;
2905  }
2906  /* Return the RCC_IT status */
2907  return bitstatus;
2908 }
2909 
2924 void RCC_ClearITPendingBit(uint8_t RCC_IT)
2925 {
2926  /* Check the parameters */
2927  assert_param(IS_RCC_CLEAR_IT(RCC_IT));
2928 
2929  /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
2930  pending bits */
2931  *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
2932 }
2933 
2950 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
#define RCC_PLLCFGR_PLLP
Definition: stm32f4xx.h:8609
FlagStatus
Definition: stm32f4xx.h:706
#define RCC_DCKCFGR_PLLSAIDIVR
Definition: stm32f4xx.h:9194
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
Selects the clock source to output on MCO2 pin(PC9).
void RCC_PLLSAICmd(FunctionalState NewState)
Enables or disables the PLLSAI.
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the Low Speed APB (APB1) peripheral clock.
ErrorStatus RCC_WaitForHSEStartUp(void)
Waits for HSE start-up.
FunctionalState
Definition: stm32f4xx.h:708
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
Configures the RTC clock (RTCCLK).
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
Configures the main PLL clock source, multiplication and division factors.
#define RCC_CFGR_PPRE2
Definition: stm32f4xx.h:8691
#define RCC_CFGR_HPRE
Definition: stm32f4xx.h:8656
#define RCC_DCKCFGR_SAI1BSRC
Definition: stm32f4xx.h:9205
#define RCC_CSR_RMVF
Definition: stm32f4xx.h:9100
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Forces or releases AHB1 peripheral reset.
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
Configures the system clock (SYSCLK).
void assert_param(int val)
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Enables or disables the AHB1 peripheral clock.
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the High Speed APB (APB2) peripheral clock.
#define RCC_PLLCFGR_PLLM
Definition: stm32f4xx.h:8590
void RCC_BackupResetCmd(FunctionalState NewState)
Forces or releases the Backup domain reset.
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
#define __I
Definition: core_cm0.h:195
static volatile uint8_t * status
Definition: drv_i2c.c:102
#define HSE_STARTUP_TIMEOUT
Comment the line below if you will not use the peripherals drivers. In this case, these drivers will ...
Definition: stm32f4xx.h:146
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
#define RCC_DCKCFGR_SAI1ASRC
Definition: stm32f4xx.h:9196
void RCC_LSEModeConfig(uint8_t RCC_Mode)
Configures the External Low Speed oscillator mode (LSE mode).
void RCC_PLLCmd(FunctionalState NewState)
Enables or disables the main PLL.
Definition: stm32f4xx.h:706
#define RCC_PLLCFGR_PLLSRC
Definition: stm32f4xx.h:8613
ITStatus RCC_GetITStatus(uint8_t RCC_IT)
Checks whether the specified RCC interrupt has occurred or not.
#define HSI_VALUE
Definition: stm32f4xx.h:150
enum FlagStatus ITStatus
#define RCC_PLLCFGR_PLLN
Definition: stm32f4xx.h:8598
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
#define __IO
Definition: core_cm0.h:198
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Enables or disables the AHB2 peripheral clock.
void RCC_LSEConfig(uint8_t RCC_LSE)
Configures the External Low Speed oscillator (LSE).
void RCC_RTCCLKCmd(FunctionalState NewState)
Enables or disables the RTC clock.
#define HSE_VALUE
Comment the line below if you will not use the peripherals drivers. In this case, these drivers will ...
Definition: stm32f10x.h:119
void RCC_PCLK1Config(uint32_t RCC_HCLK)
Configures the Low Speed APB clock (PCLK1).
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
Configures the I2S clock source (I2SCLK).
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
Configures the PLLI2S clock multiplication and division factors.
void RCC_LSICmd(FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
#define RCC
Definition: stm32f4xx.h:2122
static __I uint8_t APBAHBPrescTable[16]
void RCC_DeInit(void)
Resets the RCC clock configuration to the default reset state.
void RCC_HSICmd(FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Forces or releases AHB3 peripheral reset.
void RCC_PCLK2Config(uint32_t RCC_HCLK)
Configures the High Speed APB clock (PCLK2).
void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR)
Configures the LTDC clock Divider coming from PLLSAI.
ErrorStatus
Definition: stm32f4xx.h:711
#define RCC_CFGR_SWS
Definition: stm32f4xx.h:8644
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
#define IS_RCC_SYSCLK_SOURCE(SOURCE)
void RCC_ClearFlag(void)
Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
Enables or disables the Clock Security System.
#define RCC_CFGR_PPRE1
Definition: stm32f4xx.h:8679
#define RCC_CFGR_SW
Definition: stm32f4xx.h:8632
void RCC_PLLI2SCmd(FunctionalState NewState)
Enables or disables the PLLI2S.
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Enables or disables the AHB3 peripheral clock.
#define RCC_DCKCFGR_PLLSAIDIVQ
Definition: stm32f4xx.h:9193
void RCC_HSEConfig(uint8_t RCC_HSE)
Configures the External High Speed oscillator (HSE).
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
#define IS_RCC_I2SCLK_SOURCE(SOURCE)
#define RCC_BDCR_LSEMOD
Definition: stm32f4xx.h:9088
void RCC_ClearITPendingBit(uint8_t RCC_IT)
Clears the RCC&#39;s interrupt pending bits.
#define RCC_CR_HSITRIM
Definition: stm32f4xx.h:8561
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
Checks whether the specified RCC flag is set or not.
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
Enables or disables the specified RCC interrupts.
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
Selects the clock source to output on MCO1 pin(PA8).
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.
uint8_t RCC_GetSYSCLKSource(void)
Returns the clock source used as system clock.
#define SET_BIT(REG, BIT)
Definition: stm32f4xx.h:11419
#define IS_RCC_AHB3_PERIPH(PERIPH)
void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ)
Configures the SAI clock Divider coming from PLLSAI.
void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ)
Configures the SAI clock Divider coming from PLLI2S.
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Forces or releases AHB2 peripheral reset.
#define CLEAR_BIT(REG, BIT)
Definition: stm32f4xx.h:11421
#define RCC_CFGR_RTCPRE
Definition: stm32f4xx.h:8703
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
Configures the AHB clock (HCLK).
#define RCC_DCKCFGR_PLLI2SDIVQ
Definition: stm32f4xx.h:9192
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
Configures the Timers clocks prescalers selection.


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19