Functions

Peripheral clocks configuration functions. More...

Collaboration diagram for Peripheral clocks configuration functions:

Functions

void RCC_ADCCLKConfig (uint32_t RCC_PLLCLK)
 Configures the ADC clock (ADCCLK). More...
 
void RCC_AHB1PeriphClockCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
 Enables or disables the AHB1 peripheral clock. More...
 
void RCC_AHB1PeriphClockLPModeCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
 Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_AHB1PeriphResetCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
 Forces or releases AHB1 peripheral reset. More...
 
void RCC_AHB2PeriphClockCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
 Enables or disables the AHB2 peripheral clock. More...
 
void RCC_AHB2PeriphClockLPModeCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
 Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_AHB2PeriphResetCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
 Forces or releases AHB2 peripheral reset. More...
 
void RCC_AHB3PeriphClockCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
 Enables or disables the AHB3 peripheral clock. More...
 
void RCC_AHB3PeriphClockLPModeCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
 Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_AHB3PeriphResetCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
 Forces or releases AHB3 peripheral reset. More...
 
void RCC_AHBPeriphClockCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
 Enables or disables the AHB peripheral clock. More...
 
void RCC_AHBPeriphResetCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
 Forces or releases AHB peripheral reset. More...
 
void RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Enables or disables the Low Speed APB (APB1) peripheral clock. More...
 
void RCC_APB1PeriphClockLPModeCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Forces or releases Low Speed APB (APB1) peripheral reset. More...
 
void RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Enables or disables the High Speed APB (APB2) peripheral clock. More...
 
void RCC_APB2PeriphClockLPModeCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Forces or releases High Speed APB (APB2) peripheral reset. More...
 
void RCC_BackupResetCmd (FunctionalState NewState)
 Forces or releases the Backup domain reset. More...
 
void RCC_HRTIM1CLKConfig (uint32_t RCC_HRTIMCLK)
 Configures the HRTIM1 clock sources(HRTIM1CLK). More...
 
void RCC_I2CCLKConfig (uint32_t RCC_I2CCLK)
 Configures the I2C clock (I2CCLK). More...
 
void RCC_I2SCLKConfig (uint32_t RCC_I2SCLKSource)
 Configures the I2S clock source (I2SCLK). More...
 
void RCC_LSEModeConfig (uint8_t RCC_Mode)
 Configures the External Low Speed oscillator mode (LSE mode). More...
 
void RCC_LTDCCLKDivConfig (uint32_t RCC_PLLSAIDivR)
 Configures the LTDC clock Divider coming from PLLSAI. More...
 
void RCC_RTCCLKCmd (FunctionalState NewState)
 Enables or disables the RTC clock. More...
 
void RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
 Configures the RTC clock (RTCCLK). More...
 
void RCC_SAIPLLI2SClkDivConfig (uint32_t RCC_PLLI2SDivQ)
 Configures the SAI clock Divider coming from PLLI2S. More...
 
void RCC_SAIPLLSAIClkDivConfig (uint32_t RCC_PLLSAIDivQ)
 Configures the SAI clock Divider coming from PLLSAI. More...
 
void RCC_TIMCLKConfig (uint32_t RCC_TIMCLK)
 Configures the TIMx clock sources(TIMCLK). More...
 
void RCC_TIMCLKPresConfig (uint32_t RCC_TIMCLKPrescaler)
 Configures the Timers clocks prescalers selection. More...
 
void RCC_USARTCLKConfig (uint32_t RCC_USARTCLK)
 Configures the USART clock (USARTCLK). More...
 
void RCC_USBCLKConfig (uint32_t RCC_USBCLKSource)
 Configures the USB clock (USBCLK). More...
 

Detailed Description

Peripheral clocks configuration functions.

 ===============================================================================
              ##### Peripheral clocks configuration functions #####
 ===============================================================================  
    [..] This section provide functions allowing to configure the Peripheral clocks. 
  
      (#) The RTC clock which is derived from the LSI, LSE or HSE clock divided 
          by 2 to 31.
     
      (#) After restart from Reset or wakeup from STANDBY, all peripherals are off
          except internal SRAM, Flash and JTAG. Before to start using a peripheral 
          you have to enable its interface clock. You can do this using 
          RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.

      (#) To reset the peripherals configuration (to the default state after device reset)
          you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and 
          RCC_APB1PeriphResetCmd() functions.
     
      (#) To further reduce power consumption in SLEEP mode the peripheral clocks 
          can be disabled prior to executing the WFI or WFE instructions. 
          You can do this using RCC_AHBPeriphClockLPModeCmd(), 
          RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions.  
 ===============================================================================
            ##### Peripheral clocks configuration functions #####
 ===============================================================================  
    [..] This section provide functions allowing to configure the Peripheral clocks. 
         (#) The RTC clock which is derived from the LSE, LSI or  HSE_Div32 
             (HSE divided by 32).
         (#) After restart from Reset or wakeup from STANDBY, all peripherals are 
             off except internal SRAM, Flash and SWD. Before to start using 
             a peripheral you have to enable its interface clock. You can do this 
             using RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() 
             and RCC_APB1PeriphClockCmd() functions.
         (#) To reset the peripherals configuration (to the default state after 
             device reset) you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() 
             and RCC_APB1PeriphResetCmd() functions.

Function Documentation

void RCC_ADCCLKConfig ( uint32_t  RCC_PLLCLK)

Configures the ADC clock (ADCCLK).

Parameters
RCC_PLLCLKdefines the ADC clock divider. This clock is derived from the PLL Clock. This parameter can be one of the following values:
  • RCC_ADC12PLLCLK_OFF: ADC12 clock disabled
  • RCC_ADC12PLLCLK_Div1: ADC12 clock = PLLCLK/1
  • RCC_ADC12PLLCLK_Div2: ADC12 clock = PLLCLK/2
  • RCC_ADC12PLLCLK_Div4: ADC12 clock = PLLCLK/4
  • RCC_ADC12PLLCLK_Div6: ADC12 clock = PLLCLK/6
  • RCC_ADC12PLLCLK_Div8: ADC12 clock = PLLCLK/8
  • RCC_ADC12PLLCLK_Div10: ADC12 clock = PLLCLK/10
  • RCC_ADC12PLLCLK_Div12: ADC12 clock = PLLCLK/12
  • RCC_ADC12PLLCLK_Div16: ADC12 clock = PLLCLK/16
  • RCC_ADC12PLLCLK_Div32: ADC12 clock = PLLCLK/32
  • RCC_ADC12PLLCLK_Div64: ADC12 clock = PLLCLK/64
  • RCC_ADC12PLLCLK_Div128: ADC12 clock = PLLCLK/128
  • RCC_ADC12PLLCLK_Div256: ADC12 clock = PLLCLK/256
  • RCC_ADC34PLLCLK_OFF: ADC34 clock disabled
  • RCC_ADC34PLLCLK_Div1: ADC34 clock = PLLCLK/1
  • RCC_ADC34PLLCLK_Div2: ADC34 clock = PLLCLK/2
  • RCC_ADC34PLLCLK_Div4: ADC34 clock = PLLCLK/4
  • RCC_ADC34PLLCLK_Div6: ADC34 clock = PLLCLK/6
  • RCC_ADC34PLLCLK_Div8: ADC34 clock = PLLCLK/8
  • RCC_ADC34PLLCLK_Div10: ADC34 clock = PLLCLK/10
  • RCC_ADC34PLLCLK_Div12: ADC34 clock = PLLCLK/12
  • RCC_ADC34PLLCLK_Div16: ADC34 clock = PLLCLK/16
  • RCC_ADC34PLLCLK_Div32: ADC34 clock = PLLCLK/32
  • RCC_ADC34PLLCLK_Div64: ADC34 clock = PLLCLK/64
  • RCC_ADC34PLLCLK_Div128: ADC34 clock = PLLCLK/128
  • RCC_ADC34PLLCLK_Div256: ADC34 clock = PLLCLK/256
Return values
None

Definition at line 1235 of file stm32f30x_rcc.c.

void RCC_AHB1PeriphClockCmd ( uint32_t  RCC_AHB1Periph,
FunctionalState  NewState 
)

Enables or disables the AHB1 peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters
RCC_AHBPeriphspecifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_AHB1Periph_GPIOA: GPIOA clock
  • RCC_AHB1Periph_GPIOB: GPIOB clock
  • RCC_AHB1Periph_GPIOC: GPIOC clock
  • RCC_AHB1Periph_GPIOD: GPIOD clock
  • RCC_AHB1Periph_GPIOE: GPIOE clock
  • RCC_AHB1Periph_GPIOF: GPIOF clock
  • RCC_AHB1Periph_GPIOG: GPIOG clock
  • RCC_AHB1Periph_GPIOG: GPIOG clock
  • RCC_AHB1Periph_GPIOI: GPIOI clock
  • RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
  • RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices)
  • RCC_AHB1Periph_CRC: CRC clock
  • RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
  • RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
  • RCC_AHB1Periph_DMA1: DMA1 clock
  • RCC_AHB1Periph_DMA2: DMA2 clock
  • RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
  • RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
  • RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
  • RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
  • RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
  • RCC_AHB1Periph_OTG_HS: USB OTG HS clock
  • RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters
RCC_AHBPeriphspecifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_AHB1Periph_GPIOA: GPIOA clock
  • RCC_AHB1Periph_GPIOB: GPIOB clock
  • RCC_AHB1Periph_GPIOC: GPIOC clock
  • RCC_AHB1Periph_GPIOD: GPIOD clock
  • RCC_AHB1Periph_GPIOE: GPIOE clock
  • RCC_AHB1Periph_GPIOF: GPIOF clock
  • RCC_AHB1Periph_GPIOG: GPIOG clock
  • RCC_AHB1Periph_GPIOG: GPIOG clock
  • RCC_AHB1Periph_GPIOI: GPIOI clock
  • RCC_AHB1Periph_CRC: CRC clock
  • RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
  • RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
  • RCC_AHB1Periph_DMA1: DMA1 clock
  • RCC_AHB1Periph_DMA2: DMA2 clock
  • RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
  • RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
  • RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
  • RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
  • RCC_AHB1Periph_OTG_HS: USB OTG HS clock
  • RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 1885 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_AHB1PeriphClockLPModeCmd ( uint32_t  RCC_AHB1Periph,
FunctionalState  NewState 
)

Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.

Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.
Parameters
RCC_AHBPeriphspecifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_AHB1Periph_GPIOA: GPIOA clock
  • RCC_AHB1Periph_GPIOB: GPIOB clock
  • RCC_AHB1Periph_GPIOC: GPIOC clock
  • RCC_AHB1Periph_GPIOD: GPIOD clock
  • RCC_AHB1Periph_GPIOE: GPIOE clock
  • RCC_AHB1Periph_GPIOF: GPIOF clock
  • RCC_AHB1Periph_GPIOG: GPIOG clock
  • RCC_AHB1Periph_GPIOG: GPIOG clock
  • RCC_AHB1Periph_GPIOI: GPIOI clock
  • RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
  • RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices)
  • RCC_AHB1Periph_CRC: CRC clock
  • RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
  • RCC_AHB1Periph_DMA1: DMA1 clock
  • RCC_AHB1Periph_DMA2: DMA2 clock
  • RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
  • RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
  • RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
  • RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
  • RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
  • RCC_AHB1Periph_OTG_HS: USB OTG HS clock
  • RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None
Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.
Parameters
RCC_AHBPeriphspecifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_AHB1Periph_GPIOA: GPIOA clock
  • RCC_AHB1Periph_GPIOB: GPIOB clock
  • RCC_AHB1Periph_GPIOC: GPIOC clock
  • RCC_AHB1Periph_GPIOD: GPIOD clock
  • RCC_AHB1Periph_GPIOE: GPIOE clock
  • RCC_AHB1Periph_GPIOF: GPIOF clock
  • RCC_AHB1Periph_GPIOG: GPIOG clock
  • RCC_AHB1Periph_GPIOG: GPIOG clock
  • RCC_AHB1Periph_GPIOI: GPIOI clock
  • RCC_AHB1Periph_CRC: CRC clock
  • RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
  • RCC_AHB1Periph_DMA1: DMA1 clock
  • RCC_AHB1Periph_DMA2: DMA2 clock
  • RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
  • RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
  • RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
  • RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
  • RCC_AHB1Periph_OTG_HS: USB OTG HS clock
  • RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 2296 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_AHB1PeriphResetCmd ( uint32_t  RCC_AHB1Periph,
FunctionalState  NewState 
)

Forces or releases AHB1 peripheral reset.

Parameters
RCC_AHB1Periphspecifies the AHB1 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_AHB1Periph_GPIOA: GPIOA clock
  • RCC_AHB1Periph_GPIOB: GPIOB clock
  • RCC_AHB1Periph_GPIOC: GPIOC clock
  • RCC_AHB1Periph_GPIOD: GPIOD clock
  • RCC_AHB1Periph_GPIOE: GPIOE clock
  • RCC_AHB1Periph_GPIOF: GPIOF clock
  • RCC_AHB1Periph_GPIOG: GPIOG clock
  • RCC_AHB1Periph_GPIOG: GPIOG clock
  • RCC_AHB1Periph_GPIOI: GPIOI clock
  • RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
  • RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices)
  • RCC_AHB1Periph_CRC: CRC clock
  • RCC_AHB1Periph_DMA1: DMA1 clock
  • RCC_AHB1Periph_DMA2: DMA2 clock
  • RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
  • RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
  • RCC_AHB1Periph_OTG_HS: USB OTG HS clock
  • RCC_AHB1Periph_RNG: RNG clock for STM32F410xx devices
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values
None
Parameters
RCC_AHB1Periphspecifies the AHB1 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_AHB1Periph_GPIOA: GPIOA clock
  • RCC_AHB1Periph_GPIOB: GPIOB clock
  • RCC_AHB1Periph_GPIOC: GPIOC clock
  • RCC_AHB1Periph_GPIOD: GPIOD clock
  • RCC_AHB1Periph_GPIOE: GPIOE clock
  • RCC_AHB1Periph_GPIOF: GPIOF clock
  • RCC_AHB1Periph_GPIOG: GPIOG clock
  • RCC_AHB1Periph_GPIOG: GPIOG clock
  • RCC_AHB1Periph_GPIOI: GPIOI clock
  • RCC_AHB1Periph_CRC: CRC clock
  • RCC_AHB1Periph_DMA1: DMA1 clock
  • RCC_AHB1Periph_DMA2: DMA2 clock
  • RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
  • RCC_AHB1Periph_OTG_HS: USB OTG HS clock
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 2094 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_AHB2PeriphClockCmd ( uint32_t  RCC_AHB2Periph,
FunctionalState  NewState 
)

Enables or disables the AHB2 peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters
RCC_AHBPeriphspecifies the AHB2 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_AHB2Periph_DCMI: DCMI clock
  • RCC_AHB2Periph_CRYP: CRYP clock
  • RCC_AHB2Periph_HASH: HASH clock
  • RCC_AHB2Periph_RNG: RNG clock
  • RCC_AHB2Periph_OTG_FS: USB OTG FS clock
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 1917 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_AHB2PeriphClockLPModeCmd ( uint32_t  RCC_AHB2Periph,
FunctionalState  NewState 
)

Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.

Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.
Parameters
RCC_AHBPeriphspecifies the AHB2 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_AHB2Periph_DCMI: DCMI clock
  • RCC_AHB2Periph_CRYP: CRYP clock
  • RCC_AHB2Periph_HASH: HASH clock
  • RCC_AHB2Periph_RNG: RNG clock
  • RCC_AHB2Periph_OTG_FS: USB OTG FS clock
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 2328 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_AHB2PeriphResetCmd ( uint32_t  RCC_AHB2Periph,
FunctionalState  NewState 
)

Forces or releases AHB2 peripheral reset.

Parameters
RCC_AHB2Periphspecifies the AHB2 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_AHB2Periph_DCMI: DCMI clock
  • RCC_AHB2Periph_CRYP: CRYP clock
  • RCC_AHB2Periph_HASH: HASH clock
  • RCC_AHB2Periph_RNG: RNG clock for STM32F40_41xxx/STM32F427_437xx/STM32F429_439xx/STM32F469_479xx devices
  • RCC_AHB2Periph_OTG_FS: USB OTG FS clock
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values
None
Parameters
RCC_AHB2Periphspecifies the AHB2 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_AHB2Periph_DCMI: DCMI clock
  • RCC_AHB2Periph_CRYP: CRYP clock
  • RCC_AHB2Periph_HASH: HASH clock
  • RCC_AHB2Periph_RNG: RNG clock
  • RCC_AHB2Periph_OTG_FS: USB OTG FS clock
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 2123 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_AHB3PeriphClockCmd ( uint32_t  RCC_AHB3Periph,
FunctionalState  NewState 
)

Enables or disables the AHB3 peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters
RCC_AHBPeriphspecifies the AHB3 peripheral to gates its clock. This parameter must be: RCC_AHB3Periph_FSMC
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 1190 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.

void RCC_AHB3PeriphClockLPModeCmd ( uint32_t  RCC_AHB3Periph,
FunctionalState  NewState 
)

Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.

Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.
Parameters
RCC_AHBPeriphspecifies the AHB3 peripheral to gates its clock. This parameter must be: RCC_AHB3Periph_FSMC
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 1572 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.

void RCC_AHB3PeriphResetCmd ( uint32_t  RCC_AHB3Periph,
FunctionalState  NewState 
)

Forces or releases AHB3 peripheral reset.

Parameters
RCC_AHB3Periphspecifies the AHB3 peripheral to reset. This parameter must be: RCC_AHB3Periph_FSMC
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 1378 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.

void RCC_AHBPeriphClockCmd ( uint32_t  RCC_AHBPeriph,
FunctionalState  NewState 
)

Enables or disables the AHB peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters
RCC_AHBPeriphspecifies the AHB peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_AHBPeriph_GPIOA
  • RCC_AHBPeriph_GPIOB
  • RCC_AHBPeriph_GPIOC
  • RCC_AHBPeriph_GPIOD
  • RCC_AHBPeriph_GPIOE
  • RCC_AHBPeriph_GPIOF
  • RCC_AHBPeriph_TS
  • RCC_AHBPeriph_CRC
  • RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
  • RCC_AHBPeriph_SRAM
  • RCC_AHBPeriph_DMA2
  • RCC_AHBPeriph_DMA1
  • RCC_AHBPeriph_ADC34
  • RCC_AHBPeriph_ADC12
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 1545 of file stm32f30x_rcc.c.

void RCC_AHBPeriphResetCmd ( uint32_t  RCC_AHBPeriph,
FunctionalState  NewState 
)

Forces or releases AHB peripheral reset.

Parameters
RCC_AHBPeriphspecifies the AHB peripheral to reset. This parameter can be any combination of the following values:
  • RCC_AHBPeriph_GPIOA
  • RCC_AHBPeriph_GPIOB
  • RCC_AHBPeriph_GPIOC
  • RCC_AHBPeriph_GPIOD
  • RCC_AHBPeriph_GPIOE
  • RCC_AHBPeriph_GPIOF
  • RCC_AHBPeriph_TS
  • RCC_AHBPeriph_ADC34
  • RCC_AHBPeriph_ADC12
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 1660 of file stm32f30x_rcc.c.

void RCC_APB1PeriphClockCmd ( uint32_t  RCC_APB1Periph,
FunctionalState  NewState 
)

Enables or disables the Low Speed APB (APB1) peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters
RCC_APB1Periphspecifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB1Periph_TIM2: TIM2 clock
  • RCC_APB1Periph_TIM3: TIM3 clock
  • RCC_APB1Periph_TIM4: TIM4 clock
  • RCC_APB1Periph_TIM5: TIM5 clock
  • RCC_APB1Periph_TIM6: TIM6 clock
  • RCC_APB1Periph_TIM7: TIM7 clock
  • RCC_APB1Periph_TIM12: TIM12 clock
  • RCC_APB1Periph_TIM13: TIM13 clock
  • RCC_APB1Periph_TIM14: TIM14 clock
  • RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx devices)
  • RCC_APB1Periph_WWDG: WWDG clock
  • RCC_APB1Periph_SPI2: SPI2 clock
  • RCC_APB1Periph_SPI3: SPI3 clock
  • RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
  • RCC_APB1Periph_USART2: USART2 clock
  • RCC_APB1Periph_USART3: USART3 clock
  • RCC_APB1Periph_UART4: UART4 clock
  • RCC_APB1Periph_UART5: UART5 clock
  • RCC_APB1Periph_I2C1: I2C1 clock
  • RCC_APB1Periph_I2C2: I2C2 clock
  • RCC_APB1Periph_I2C3: I2C3 clock
  • RCC_APB1Periph_FMPI2C1: FMPI2C1 clock
  • RCC_APB1Periph_CAN1: CAN1 clock
  • RCC_APB1Periph_CAN2: CAN2 clock
  • RCC_APB1Periph_CEC: CEC clock (STM32F446xx devices)
  • RCC_APB1Periph_PWR: PWR clock
  • RCC_APB1Periph_DAC: DAC clock
  • RCC_APB1Periph_UART7: UART7 clock
  • RCC_APB1Periph_UART8: UART8 clock
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters
RCC_APB1Periphspecifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB1Periph_TIM2: TIM2 clock
  • RCC_APB1Periph_TIM3: TIM3 clock
  • RCC_APB1Periph_TIM4: TIM4 clock
  • RCC_APB1Periph_TIM5: TIM5 clock
  • RCC_APB1Periph_TIM6: TIM6 clock
  • RCC_APB1Periph_TIM7: TIM7 clock
  • RCC_APB1Periph_TIM12: TIM12 clock
  • RCC_APB1Periph_TIM13: TIM13 clock
  • RCC_APB1Periph_TIM14: TIM14 clock
  • RCC_APB1Periph_WWDG: WWDG clock
  • RCC_APB1Periph_SPI2: SPI2 clock
  • RCC_APB1Periph_SPI3: SPI3 clock
  • RCC_APB1Periph_USART2: USART2 clock
  • RCC_APB1Periph_USART3: USART3 clock
  • RCC_APB1Periph_UART4: UART4 clock
  • RCC_APB1Periph_UART5: UART5 clock
  • RCC_APB1Periph_I2C1: I2C1 clock
  • RCC_APB1Periph_I2C2: I2C2 clock
  • RCC_APB1Periph_I2C3: I2C3 clock
  • RCC_APB1Periph_CAN1: CAN1 clock
  • RCC_APB1Periph_CAN2: CAN2 clock
  • RCC_APB1Periph_PWR: PWR clock
  • RCC_APB1Periph_DAC: DAC clock
  • RCC_APB1Periph_UART7: UART7 clock
  • RCC_APB1Periph_UART8: UART8 clock
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters
RCC_APB1Periphspecifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB1Periph_TIM2
  • RCC_APB1Periph_TIM3
  • RCC_APB1Periph_TIM4
  • RCC_APB1Periph_TIM6
  • RCC_APB1Periph_TIM7
  • RCC_APB1Periph_WWDG
  • RCC_APB1Periph_SPI2
  • RCC_APB1Periph_SPI3
  • RCC_APB1Periph_USART2
  • RCC_APB1Periph_USART3
  • RCC_APB1Periph_UART4
  • RCC_APB1Periph_UART5
  • RCC_APB1Periph_I2C1
  • RCC_APB1Periph_I2C2
  • RCC_APB1Periph_USB
  • RCC_APB1Periph_CAN1
  • RCC_APB1Periph_PWR
  • RCC_APB1Periph_DAC1
  • RCC_APB1Periph_DAC2
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 2004 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_APB1PeriphClockLPModeCmd ( uint32_t  RCC_APB1Periph,
FunctionalState  NewState 
)

Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.

Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.
Parameters
RCC_APB1Periphspecifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB1Periph_TIM2: TIM2 clock
  • RCC_APB1Periph_TIM3: TIM3 clock
  • RCC_APB1Periph_TIM4: TIM4 clock
  • RCC_APB1Periph_TIM5: TIM5 clock
  • RCC_APB1Periph_TIM6: TIM6 clock
  • RCC_APB1Periph_TIM7: TIM7 clock
  • RCC_APB1Periph_TIM12: TIM12 clock
  • RCC_APB1Periph_TIM13: TIM13 clock
  • RCC_APB1Periph_TIM14: TIM14 clock
  • RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx devices)
  • RCC_APB1Periph_WWDG: WWDG clock
  • RCC_APB1Periph_SPI2: SPI2 clock
  • RCC_APB1Periph_SPI3: SPI3 clock
  • RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
  • RCC_APB1Periph_USART2: USART2 clock
  • RCC_APB1Periph_USART3: USART3 clock
  • RCC_APB1Periph_UART4: UART4 clock
  • RCC_APB1Periph_UART5: UART5 clock
  • RCC_APB1Periph_I2C1: I2C1 clock
  • RCC_APB1Periph_I2C2: I2C2 clock
  • RCC_APB1Periph_I2C3: I2C3 clock
  • RCC_APB1Periph_FMPI2C1: FMPI2C1 clock
  • RCC_APB1Periph_CAN1: CAN1 clock
  • RCC_APB1Periph_CAN2: CAN2 clock
  • RCC_APB1Periph_CEC: CEC clock (STM32F446xx devices)
  • RCC_APB1Periph_PWR: PWR clock
  • RCC_APB1Periph_DAC: DAC clock
  • RCC_APB1Periph_UART7: UART7 clock
  • RCC_APB1Periph_UART8: UART8 clock
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None
Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.
Parameters
RCC_APB1Periphspecifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB1Periph_TIM2: TIM2 clock
  • RCC_APB1Periph_TIM3: TIM3 clock
  • RCC_APB1Periph_TIM4: TIM4 clock
  • RCC_APB1Periph_TIM5: TIM5 clock
  • RCC_APB1Periph_TIM6: TIM6 clock
  • RCC_APB1Periph_TIM7: TIM7 clock
  • RCC_APB1Periph_TIM12: TIM12 clock
  • RCC_APB1Periph_TIM13: TIM13 clock
  • RCC_APB1Periph_TIM14: TIM14 clock
  • RCC_APB1Periph_WWDG: WWDG clock
  • RCC_APB1Periph_SPI2: SPI2 clock
  • RCC_APB1Periph_SPI3: SPI3 clock
  • RCC_APB1Periph_USART2: USART2 clock
  • RCC_APB1Periph_USART3: USART3 clock
  • RCC_APB1Periph_UART4: UART4 clock
  • RCC_APB1Periph_UART5: UART5 clock
  • RCC_APB1Periph_I2C1: I2C1 clock
  • RCC_APB1Periph_I2C2: I2C2 clock
  • RCC_APB1Periph_I2C3: I2C3 clock
  • RCC_APB1Periph_CAN1: CAN1 clock
  • RCC_APB1Periph_CAN2: CAN2 clock
  • RCC_APB1Periph_PWR: PWR clock
  • RCC_APB1Periph_DAC: DAC clock
  • RCC_APB1Periph_UART7: UART7 clock
  • RCC_APB1Periph_UART8: UART8 clock
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 2415 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_APB1PeriphResetCmd ( uint32_t  RCC_APB1Periph,
FunctionalState  NewState 
)

Forces or releases Low Speed APB (APB1) peripheral reset.

Parameters
RCC_APB1Periphspecifies the APB1 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_APB1Periph_TIM2: TIM2 clock
  • RCC_APB1Periph_TIM3: TIM3 clock
  • RCC_APB1Periph_TIM4: TIM4 clock
  • RCC_APB1Periph_TIM5: TIM5 clock
  • RCC_APB1Periph_TIM6: TIM6 clock
  • RCC_APB1Periph_TIM7: TIM7 clock
  • RCC_APB1Periph_TIM12: TIM12 clock
  • RCC_APB1Periph_TIM13: TIM13 clock
  • RCC_APB1Periph_TIM14: TIM14 clock
  • RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx devices)
  • RCC_APB1Periph_WWDG: WWDG clock
  • RCC_APB1Periph_SPI2: SPI2 clock
  • RCC_APB1Periph_SPI3: SPI3 clock
  • RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
  • RCC_APB1Periph_USART2: USART2 clock
  • RCC_APB1Periph_USART3: USART3 clock
  • RCC_APB1Periph_UART4: UART4 clock
  • RCC_APB1Periph_UART5: UART5 clock
  • RCC_APB1Periph_I2C1: I2C1 clock
  • RCC_APB1Periph_I2C2: I2C2 clock
  • RCC_APB1Periph_I2C3: I2C3 clock
  • RCC_APB1Periph_FMPI2C1: FMPI2C1 clock
  • RCC_APB1Periph_CAN1: CAN1 clock
  • RCC_APB1Periph_CAN2: CAN2 clock
  • RCC_APB1Periph_CEC: CEC clock(STM32F446xx devices)
  • RCC_APB1Periph_PWR: PWR clock
  • RCC_APB1Periph_DAC: DAC clock
  • RCC_APB1Periph_UART7: UART7 clock
  • RCC_APB1Periph_UART8: UART8 clock
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values
None
Parameters
RCC_APB1Periphspecifies the APB1 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_APB1Periph_TIM2: TIM2 clock
  • RCC_APB1Periph_TIM3: TIM3 clock
  • RCC_APB1Periph_TIM4: TIM4 clock
  • RCC_APB1Periph_TIM5: TIM5 clock
  • RCC_APB1Periph_TIM6: TIM6 clock
  • RCC_APB1Periph_TIM7: TIM7 clock
  • RCC_APB1Periph_TIM12: TIM12 clock
  • RCC_APB1Periph_TIM13: TIM13 clock
  • RCC_APB1Periph_TIM14: TIM14 clock
  • RCC_APB1Periph_WWDG: WWDG clock
  • RCC_APB1Periph_SPI2: SPI2 clock
  • RCC_APB1Periph_SPI3: SPI3 clock
  • RCC_APB1Periph_USART2: USART2 clock
  • RCC_APB1Periph_USART3: USART3 clock
  • RCC_APB1Periph_UART4: UART4 clock
  • RCC_APB1Periph_UART5: UART5 clock
  • RCC_APB1Periph_I2C1: I2C1 clock
  • RCC_APB1Periph_I2C2: I2C2 clock
  • RCC_APB1Periph_I2C3: I2C3 clock
  • RCC_APB1Periph_CAN1: CAN1 clock
  • RCC_APB1Periph_CAN2: CAN2 clock
  • RCC_APB1Periph_PWR: PWR clock
  • RCC_APB1Periph_DAC: DAC clock
  • RCC_APB1Periph_UART7: UART7 clock
  • RCC_APB1Periph_UART8: UART8 clock
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values
None
Parameters
RCC_APB1Periphspecifies the APB1 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_APB1Periph_TIM2
  • RCC_APB1Periph_TIM3
  • RCC_APB1Periph_TIM4
  • RCC_APB1Periph_TIM6
  • RCC_APB1Periph_TIM7
  • RCC_APB1Periph_WWDG
  • RCC_APB1Periph_SPI2
  • RCC_APB1Periph_SPI3
  • RCC_APB1Periph_USART2
  • RCC_APB1Periph_USART3
  • RCC_APB1Periph_UART4
  • RCC_APB1Periph_UART5
  • RCC_APB1Periph_I2C1
  • RCC_APB1Periph_I2C2
  • RCC_APB1Periph_I2C3
  • RCC_APB1Periph_USB
  • RCC_APB1Periph_CAN1
  • RCC_APB1Periph_PWR
  • RCC_APB1Periph_DAC
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 2204 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_APB2PeriphClockCmd ( uint32_t  RCC_APB2Periph,
FunctionalState  NewState 
)

Enables or disables the High Speed APB (APB2) peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters
RCC_APB2Periphspecifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB2Periph_TIM1: TIM1 clock
  • RCC_APB2Periph_TIM8: TIM8 clock
  • RCC_APB2Periph_USART1: USART1 clock
  • RCC_APB2Periph_USART6: USART6 clock
  • RCC_APB2Periph_ADC1: ADC1 clock
  • RCC_APB2Periph_ADC2: ADC2 clock
  • RCC_APB2Periph_ADC3: ADC3 clock
  • RCC_APB2Periph_SDIO: SDIO clock
  • RCC_APB2Periph_SPI1: SPI1 clock
  • RCC_APB2Periph_SPI4: SPI4 clock
  • RCC_APB2Periph_SYSCFG: SYSCFG clock
  • RCC_APB2Periph_TIM9: TIM9 clock
  • RCC_APB2Periph_TIM10: TIM10 clock
  • RCC_APB2Periph_TIM11: TIM11 clock
  • RCC_APB2Periph_SPI5: SPI5 clock
  • RCC_APB2Periph_SPI6: SPI6 clock
  • RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx devices)
  • RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
  • RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
  • RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters
RCC_APB2Periphspecifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB2Periph_TIM1: TIM1 clock
  • RCC_APB2Periph_TIM8: TIM8 clock
  • RCC_APB2Periph_USART1: USART1 clock
  • RCC_APB2Periph_USART6: USART6 clock
  • RCC_APB2Periph_ADC1: ADC1 clock
  • RCC_APB2Periph_ADC2: ADC2 clock
  • RCC_APB2Periph_ADC3: ADC3 clock
  • RCC_APB2Periph_SDIO: SDIO clock
  • RCC_APB2Periph_SPI1: SPI1 clock
  • RCC_APB2Periph_SPI4: SPI4 clock
  • RCC_APB2Periph_SYSCFG: SYSCFG clock
  • RCC_APB2Periph_TIM9: TIM9 clock
  • RCC_APB2Periph_TIM10: TIM10 clock
  • RCC_APB2Periph_TIM11: TIM11 clock
  • RCC_APB2Periph_SPI5: SPI5 clock
  • RCC_APB2Periph_SPI6: SPI6 clock
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters
RCC_APB2Periphspecifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB2Periph_SYSCFG
  • RCC_APB2Periph_SPI1
  • RCC_APB2Periph_USART1
  • RCC_APB2Periph_TIM15
  • RCC_APB2Periph_TIM16
  • RCC_APB2Periph_TIM17
  • RCC_APB2Periph_TIM1
  • RCC_APB2Periph_TIM8
  • RCC_APB2Periph_HRTIM1
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 2051 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_APB2PeriphClockLPModeCmd ( uint32_t  RCC_APB2Periph,
FunctionalState  NewState 
)

Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.

Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.
Parameters
RCC_APB2Periphspecifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB2Periph_TIM1: TIM1 clock
  • RCC_APB2Periph_TIM8: TIM8 clock
  • RCC_APB2Periph_USART1: USART1 clock
  • RCC_APB2Periph_USART6: USART6 clock
  • RCC_APB2Periph_ADC1: ADC1 clock
  • RCC_APB2Periph_ADC2: ADC2 clock
  • RCC_APB2Periph_ADC3: ADC3 clock
  • RCC_APB2Periph_SDIO: SDIO clock
  • RCC_APB2Periph_SPI1: SPI1 clock
  • RCC_APB2Periph_SPI4: SPI4 clock
  • RCC_APB2Periph_SYSCFG: SYSCFG clock
  • RCC_APB2Periph_TIM9: TIM9 clock
  • RCC_APB2Periph_TIM10: TIM10 clock
  • RCC_APB2Periph_TIM11: TIM11 clock
  • RCC_APB2Periph_SPI5: SPI5 clock
  • RCC_APB2Periph_SPI6: SPI6 clock
  • RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx devices)
  • RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
  • RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
  • RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None
Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.
Parameters
RCC_APB2Periphspecifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB2Periph_TIM1: TIM1 clock
  • RCC_APB2Periph_TIM8: TIM8 clock
  • RCC_APB2Periph_USART1: USART1 clock
  • RCC_APB2Periph_USART6: USART6 clock
  • RCC_APB2Periph_ADC1: ADC1 clock
  • RCC_APB2Periph_ADC2: ADC2 clock
  • RCC_APB2Periph_ADC3: ADC3 clock
  • RCC_APB2Periph_SDIO: SDIO clock
  • RCC_APB2Periph_SPI1: SPI1 clock
  • RCC_APB2Periph_SPI4: SPI4 clock
  • RCC_APB2Periph_SYSCFG: SYSCFG clock
  • RCC_APB2Periph_TIM9: TIM9 clock
  • RCC_APB2Periph_TIM10: TIM10 clock
  • RCC_APB2Periph_TIM11: TIM11 clock
  • RCC_APB2Periph_SPI5: SPI5 clock
  • RCC_APB2Periph_SPI6: SPI6 clock
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 2462 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_APB2PeriphResetCmd ( uint32_t  RCC_APB2Periph,
FunctionalState  NewState 
)

Forces or releases High Speed APB (APB2) peripheral reset.

Parameters
RCC_APB2Periphspecifies the APB2 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_APB2Periph_TIM1: TIM1 clock
  • RCC_APB2Periph_TIM8: TIM8 clock
  • RCC_APB2Periph_USART1: USART1 clock
  • RCC_APB2Periph_USART6: USART6 clock
  • RCC_APB2Periph_ADC1: ADC1 clock
  • RCC_APB2Periph_ADC2: ADC2 clock
  • RCC_APB2Periph_ADC3: ADC3 clock
  • RCC_APB2Periph_SDIO: SDIO clock
  • RCC_APB2Periph_SPI1: SPI1 clock
  • RCC_APB2Periph_SPI4: SPI4 clock
  • RCC_APB2Periph_SYSCFG: SYSCFG clock
  • RCC_APB2Periph_TIM9: TIM9 clock
  • RCC_APB2Periph_TIM10: TIM10 clock
  • RCC_APB2Periph_TIM11: TIM11 clock
  • RCC_APB2Periph_SPI5: SPI5 clock
  • RCC_APB2Periph_SPI6: SPI6 clock
  • RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx devices)
  • RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
  • RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
  • RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values
None
Parameters
RCC_APB2Periphspecifies the APB2 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_APB2Periph_TIM1: TIM1 clock
  • RCC_APB2Periph_TIM8: TIM8 clock
  • RCC_APB2Periph_USART1: USART1 clock
  • RCC_APB2Periph_USART6: USART6 clock
  • RCC_APB2Periph_ADC1: ADC1 clock
  • RCC_APB2Periph_ADC2: ADC2 clock
  • RCC_APB2Periph_ADC3: ADC3 clock
  • RCC_APB2Periph_SDIO: SDIO clock
  • RCC_APB2Periph_SPI1: SPI1 clock
  • RCC_APB2Periph_SPI4: SPI4 clock
  • RCC_APB2Periph_SYSCFG: SYSCFG clock
  • RCC_APB2Periph_TIM9: TIM9 clock
  • RCC_APB2Periph_TIM10: TIM10 clock
  • RCC_APB2Periph_TIM11: TIM11 clock
  • RCC_APB2Periph_SPI5: SPI5 clock
  • RCC_APB2Periph_SPI6: SPI6 clock
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values
None
Parameters
RCC_APB2Periphspecifies the APB2 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_APB2Periph_SYSCFG
  • RCC_APB2Periph_SPI1
  • RCC_APB2Periph_USART1
  • RCC_APB2Periph_TIM15
  • RCC_APB2Periph_TIM16
  • RCC_APB2Periph_TIM17
  • RCC_APB2Periph_TIM1
  • RCC_APB2Periph_TIM8
  • RCC_APB2Periph_HRTIM1
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 2247 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_BackupResetCmd ( FunctionalState  NewState)

Forces or releases the Backup domain reset.

Note
This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_CSR register.
The BKPSRAM is not affected by this reset.
Parameters
NewStatenew state of the Backup domain reset. This parameter can be: ENABLE or DISABLE.
Return values
None
Note
This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_BDCR register.
Parameters
NewStatenew state of the Backup domain reset. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 1519 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_HRTIM1CLKConfig ( uint32_t  RCC_HRTIMCLK)

Configures the HRTIM1 clock sources(HRTIM1CLK).

Note
The configuration of the HRTIM1 clock source is only possible when the SYSCLK = PLL and HCLK and PCLK2 clocks are not divided in respect to SYSCLK
If one of the previous conditions is missed, the TIM clock source configuration is lost and calling again this function becomes mandatory.
Parameters
RCC_HRTIMCLKdefines the TIMx clock source. This parameter can be one of the following values:
  • RCC_HRTIM1CLK_HCLK: TIMx clock = APB high speed clock (doubled frequency when prescaled)
  • RCC_HRTIM1CLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz) (x can be 1 or 8).
Return values
None

Definition at line 1361 of file stm32f30x_rcc.c.

void RCC_I2CCLKConfig ( uint32_t  RCC_I2CCLK)

Configures the I2C clock (I2CCLK).

Parameters
RCC_I2CCLKdefines the I2C clock source. This clock is derived from the HSI or System clock. This parameter can be one of the following values:
  • RCC_I2CxCLK_HSI: I2Cx clock = HSI
  • RCC_I2CxCLK_SYSCLK: I2Cx clock = System Clock (x can be 1 or 2 or 3).
Return values
None

Definition at line 1268 of file stm32f30x_rcc.c.

void RCC_I2SCLKConfig ( uint32_t  RCC_I2SCLKSource)

Configures the I2S clock source (I2SCLK).

Note
This function must be called before enabling the I2S APB clock.
Parameters
RCC_I2SCLKSourcespecifies the I2S clock source. This parameter can be one of the following values:
  • RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
  • RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin used as I2S clock source
Return values
None
Note
This function must be called before enabling the SPI2 and SPI3 clocks.
Parameters
RCC_I2SCLKSourcespecifies the I2S clock source. This parameter can be one of the following values:
  • RCC_I2S2CLKSource_SYSCLK: SYSCLK clock used as I2S clock source
  • RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin used as I2S clock source
Return values
None

Definition at line 1065 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.

void RCC_LSEModeConfig ( uint8_t  RCC_Mode)

Configures the External Low Speed oscillator mode (LSE mode).

Note
This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices.
Parameters
Modespecifies the LSE mode. This parameter can be one of the following values:
  • RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode.
  • RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode.
Return values
None

Definition at line 2486 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_LTDCCLKDivConfig ( uint32_t  RCC_PLLSAIDivR)

Configures the LTDC clock Divider coming from PLLSAI.

Note
The LTDC peripheral is only available with STM32F42xxx/43xxx/446xx/469xx/479xx Devices.
This function must be called before enabling the PLLSAI.
Parameters
RCC_PLLSAIDivRspecifies the PLLSAI division factor for LTDC clock . LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR This parameter can be one of the following values:
  • RCC_PLLSAIDivR_Div2: LTDC clock = f(PLLSAI_R)/2
  • RCC_PLLSAIDivR_Div4: LTDC clock = f(PLLSAI_R)/4
  • RCC_PLLSAIDivR_Div8: LTDC clock = f(PLLSAI_R)/8
  • RCC_PLLSAIDivR_Div16: LTDC clock = f(PLLSAI_R)/16
Return values
None

Definition at line 1806 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_RTCCLKCmd ( FunctionalState  NewState)

Enables or disables the RTC clock.

Note
This function must be used only after the RTC clock source was selected using the RCC_RTCCLKConfig function.
Parameters
NewStatenew state of the RTC clock. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 1502 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_RTCCLKConfig ( uint32_t  RCC_RTCCLKSource)

Configures the RTC clock (RTCCLK).

Note
As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the RTC clock source (to be done once after reset).
Once the RTC clock is configured it can't be changed unless the Backup domain is reset using RCC_BackupResetCmd() function, or by a Power On Reset (POR).
Parameters
RCC_RTCCLKSourcespecifies the RTC clock source. This parameter can be one of the following values:
  • RCC_RTCCLKSource_LSE: LSE selected as RTC clock
  • RCC_RTCCLKSource_LSI: LSI selected as RTC clock
  • RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected as RTC clock, where x:[2,31]
Note
If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).
Return values
None
Note
As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the RTC clock source (to be done once after reset).
Once the RTC clock is configured it can't be changed unless the RTC is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)
Parameters
RCC_RTCCLKSourcespecifies the RTC clock source. This parameter can be one of the following values:
  • RCC_RTCCLKSource_LSE: LSE selected as RTC clock
  • RCC_RTCCLKSource_LSI: LSI selected as RTC clock
  • RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock
Note
If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
The maximum input clock frequency for RTC is 2MHz (when using HSE as RTC clock source).
Return values
None

Definition at line 1470 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_SAIPLLI2SClkDivConfig ( uint32_t  RCC_PLLI2SDivQ)

Configures the SAI clock Divider coming from PLLI2S.

Note
This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.
This function must be called before enabling the PLLI2S.
Parameters
RCC_PLLI2SDivQspecifies the PLLI2S division factor for SAI1 clock . This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ
Return values
None

Definition at line 1738 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_SAIPLLSAIClkDivConfig ( uint32_t  RCC_PLLSAIDivQ)

Configures the SAI clock Divider coming from PLLSAI.

Note
This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.
This function must be called before enabling the PLLSAI.
Parameters
RCC_PLLSAIDivQspecifies the PLLSAI division factor for SAI1 clock . This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ
Return values
None

Definition at line 1770 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_TIMCLKConfig ( uint32_t  RCC_TIMCLK)

Configures the TIMx clock sources(TIMCLK).

Note
The configuration of the TIMx clock source is only possible when the SYSCLK = PLL and HCLK and PCLK2 clocks are not divided in respect to SYSCLK
If one of the previous conditions is missed, the TIM clock source configuration is lost and calling again this function becomes mandatory.
Parameters
RCC_TIMCLKdefines the TIMx clock source. This parameter can be one of the following values:
  • RCC_TIMxCLK_HCLK: TIMx clock = APB high speed clock (doubled frequency when prescaled)
  • RCC_TIMxCLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz) (x can be 1, 8, 15, 16, 17).
Return values
None

Definition at line 1311 of file stm32f30x_rcc.c.

void RCC_TIMCLKPresConfig ( uint32_t  RCC_TIMCLKPrescaler)

Configures the Timers clocks prescalers selection.

Note
This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
Parameters
RCC_TIMCLKPrescaler: specifies the Timers clocks prescalers selection This parameter can be one of the following values:
  • RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1 or 2, else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to division by 4 or more.
  • RCC_TIMPrescActivated: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding to division by 8 or more.
Return values
None
Note
This feature is only available with STM32F427x/437x Devices.
Parameters
RCC_TIMCLKPrescaler: specifies the Timers clocks prescalers selection This parameter can be one of the following values:
  • RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1 or 2, else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to division by 4 or more.
  • RCC_TIMPrescActivated: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding to division by 8 or more.
Return values
None

Definition at line 1843 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_USARTCLKConfig ( uint32_t  RCC_USARTCLK)

Configures the USART clock (USARTCLK).

Parameters
RCC_USARTCLKdefines the USART clock source. This clock is derived from the HSI or System clock. This parameter can be one of the following values:
  • RCC_USARTxCLK_PCLK: USART clock = APB Clock (PCLK)
  • RCC_USARTxCLK_SYSCLK: USART clock = System Clock
  • RCC_USARTxCLK_LSE: USART clock = LSE Clock
  • RCC_USARTxCLK_HSI: USART clock = HSI Clock (x can be 1, 2, 3, 4 or 5).
Return values
None

Definition at line 1385 of file stm32f30x_rcc.c.

void RCC_USBCLKConfig ( uint32_t  RCC_USBCLKSource)

Configures the USB clock (USBCLK).

Parameters
RCC_USBCLKSourcespecifies the USB clock source. This clock is derived from the PLL output. This parameter can be one of the following values:
  • RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB clock source
  • RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
Return values
None

Definition at line 1430 of file stm32f30x_rcc.c.



rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:21