Macros
Collaboration diagram for RCC_AHB_Clock_Source:

Macros

#define IS_RCC_HCLK(HCLK)
 
#define IS_RCC_HCLK(HCLK)
 
#define IS_RCC_HCLK(HCLK)
 
#define RCC_SYSCLK_Div1   ((uint32_t)0x00000000)
 
#define RCC_SYSCLK_Div1   ((uint32_t)0x00000000)
 
#define RCC_SYSCLK_Div1   RCC_CFGR_HPRE_DIV1
 
#define RCC_SYSCLK_Div128   ((uint32_t)0x000000D0)
 
#define RCC_SYSCLK_Div128   ((uint32_t)0x000000D0)
 
#define RCC_SYSCLK_Div128   RCC_CFGR_HPRE_DIV128
 
#define RCC_SYSCLK_Div16   ((uint32_t)0x000000B0)
 
#define RCC_SYSCLK_Div16   ((uint32_t)0x000000B0)
 
#define RCC_SYSCLK_Div16   RCC_CFGR_HPRE_DIV16
 
#define RCC_SYSCLK_Div2   ((uint32_t)0x00000080)
 
#define RCC_SYSCLK_Div2   ((uint32_t)0x00000080)
 
#define RCC_SYSCLK_Div2   RCC_CFGR_HPRE_DIV2
 
#define RCC_SYSCLK_Div256   ((uint32_t)0x000000E0)
 
#define RCC_SYSCLK_Div256   ((uint32_t)0x000000E0)
 
#define RCC_SYSCLK_Div256   RCC_CFGR_HPRE_DIV256
 
#define RCC_SYSCLK_Div4   ((uint32_t)0x00000090)
 
#define RCC_SYSCLK_Div4   ((uint32_t)0x00000090)
 
#define RCC_SYSCLK_Div4   RCC_CFGR_HPRE_DIV4
 
#define RCC_SYSCLK_Div512   ((uint32_t)0x000000F0)
 
#define RCC_SYSCLK_Div512   ((uint32_t)0x000000F0)
 
#define RCC_SYSCLK_Div512   RCC_CFGR_HPRE_DIV512
 
#define RCC_SYSCLK_Div64   ((uint32_t)0x000000C0)
 
#define RCC_SYSCLK_Div64   ((uint32_t)0x000000C0)
 
#define RCC_SYSCLK_Div64   RCC_CFGR_HPRE_DIV64
 
#define RCC_SYSCLK_Div8   ((uint32_t)0x000000A0)
 
#define RCC_SYSCLK_Div8   ((uint32_t)0x000000A0)
 
#define RCC_SYSCLK_Div8   RCC_CFGR_HPRE_DIV8
 

Detailed Description

Macro Definition Documentation

#define IS_RCC_HCLK (   HCLK)
#define IS_RCC_HCLK (   HCLK)
#define IS_RCC_HCLK (   HCLK)
Value:
(((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
((HCLK) == RCC_SYSCLK_Div512))
#define RCC_SYSCLK_Div2
#define RCC_SYSCLK_Div64
#define RCC_SYSCLK_Div8
#define RCC_SYSCLK_Div128
#define RCC_SYSCLK_Div256
#define RCC_SYSCLK_Div16
#define RCC_SYSCLK_Div4
#define RCC_SYSCLK_Div512
#define RCC_SYSCLK_Div1

Definition at line 197 of file stm32f30x_rcc.h.

#define RCC_SYSCLK_Div1   ((uint32_t)0x00000000)
#define RCC_SYSCLK_Div1   ((uint32_t)0x00000000)
#define RCC_SYSCLK_Div1   RCC_CFGR_HPRE_DIV1

Definition at line 188 of file stm32f30x_rcc.h.

#define RCC_SYSCLK_Div128   ((uint32_t)0x000000D0)
#define RCC_SYSCLK_Div128   ((uint32_t)0x000000D0)
#define RCC_SYSCLK_Div128   RCC_CFGR_HPRE_DIV128

Definition at line 194 of file stm32f30x_rcc.h.

#define RCC_SYSCLK_Div16   ((uint32_t)0x000000B0)
#define RCC_SYSCLK_Div16   ((uint32_t)0x000000B0)
#define RCC_SYSCLK_Div16   RCC_CFGR_HPRE_DIV16

Definition at line 192 of file stm32f30x_rcc.h.

#define RCC_SYSCLK_Div2   ((uint32_t)0x00000080)
#define RCC_SYSCLK_Div2   ((uint32_t)0x00000080)
#define RCC_SYSCLK_Div2   RCC_CFGR_HPRE_DIV2

Definition at line 189 of file stm32f30x_rcc.h.

#define RCC_SYSCLK_Div256   ((uint32_t)0x000000E0)
#define RCC_SYSCLK_Div256   ((uint32_t)0x000000E0)
#define RCC_SYSCLK_Div256   RCC_CFGR_HPRE_DIV256

Definition at line 195 of file stm32f30x_rcc.h.

#define RCC_SYSCLK_Div4   ((uint32_t)0x00000090)
#define RCC_SYSCLK_Div4   ((uint32_t)0x00000090)
#define RCC_SYSCLK_Div4   RCC_CFGR_HPRE_DIV4

Definition at line 190 of file stm32f30x_rcc.h.

#define RCC_SYSCLK_Div512   ((uint32_t)0x000000F0)
#define RCC_SYSCLK_Div512   ((uint32_t)0x000000F0)
#define RCC_SYSCLK_Div512   RCC_CFGR_HPRE_DIV512

Definition at line 196 of file stm32f30x_rcc.h.

#define RCC_SYSCLK_Div64   ((uint32_t)0x000000C0)
#define RCC_SYSCLK_Div64   ((uint32_t)0x000000C0)
#define RCC_SYSCLK_Div64   RCC_CFGR_HPRE_DIV64

Definition at line 193 of file stm32f30x_rcc.h.

#define RCC_SYSCLK_Div8   ((uint32_t)0x000000A0)
#define RCC_SYSCLK_Div8   ((uint32_t)0x000000A0)
#define RCC_SYSCLK_Div8   RCC_CFGR_HPRE_DIV8

Definition at line 191 of file stm32f30x_rcc.h.



rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Fri Apr 3 2020 03:19:29