stm32f10x.h
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1 
50 #ifndef __STM32F10x_H
51 #define __STM32F10x_H
52 
53 #ifdef __cplusplus
54  extern "C" {
55 #endif
56 
61 /* Uncomment the line below according to the target STM32 device used in your
62  application
63  */
64 
65 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
66  /* #define STM32F10X_LD */
67  /* #define STM32F10X_LD_VL */
68  /* #define STM32F10X_MD */
69  /* #define STM32F10X_MD_VL */
70  /* #define STM32F10X_HD */
71  /* #define STM32F10X_HD_VL */
72  /* #define STM32F10X_XL */
73  /* #define STM32F10X_CL */
74 #endif
75 /* Tip: To avoid modifying this file each time you need to switch between these
76  devices, you can define the device in your toolchain compiler preprocessor.
77 
78  - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
79  where the Flash memory density ranges between 16 and 32 Kbytes.
80  - Low-density value line devices are STM32F100xx microcontrollers where the Flash
81  memory density ranges between 16 and 32 Kbytes.
82  - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
83  where the Flash memory density ranges between 64 and 128 Kbytes.
84  - Medium-density value line devices are STM32F100xx microcontrollers where the
85  Flash memory density ranges between 64 and 128 Kbytes.
86  - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
87  the Flash memory density ranges between 256 and 512 Kbytes.
88  - High-density value line devices are STM32F100xx microcontrollers where the
89  Flash memory density ranges between 256 and 512 Kbytes.
90  - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
91  the Flash memory density ranges between 512 and 1024 Kbytes.
92  - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
93  */
94 
95 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
96  #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"
97 #endif
98 
99 #if !defined USE_STDPERIPH_DRIVER
100 
105  /*#define USE_STDPERIPH_DRIVER*/
106 #endif
107 
115 #if !defined HSE_VALUE
116  #ifdef STM32F10X_CL
117  #define HSE_VALUE ((uint32_t)25000000)
118  #else
119  #define HSE_VALUE ((uint32_t)8000000)
120  #endif /* STM32F10X_CL */
121 #endif /* HSE_VALUE */
122 
123 
128 #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500)
130 #define HSI_VALUE ((uint32_t)8000000)
135 #define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03)
136 #define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05)
137 #define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00)
138 #define __STM32F10X_STDPERIPH_VERSION_RC (0x00)
139 #define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
140  |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
141  |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
142  |(__STM32F10X_STDPERIPH_VERSION_RC))
143 
155 #ifdef STM32F10X_XL
156  #define __MPU_PRESENT 1
157 #else
158  #define __MPU_PRESENT 0
159 #endif /* STM32F10X_XL */
160 #define __NVIC_PRIO_BITS 4
161 #define __Vendor_SysTickConfig 0
167 typedef enum IRQn
168 {
169 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
174  SVCall_IRQn = -5,
176  PendSV_IRQn = -2,
179 /****** STM32 specific Interrupt Numbers *********************************************************/
180  WWDG_IRQn = 0,
181  PVD_IRQn = 1,
183  RTC_IRQn = 3,
185  RCC_IRQn = 5,
190  EXTI4_IRQn = 10,
199 #ifdef STM32F10X_LD
200  ADC1_2_IRQn = 18,
201  USB_HP_CAN1_TX_IRQn = 19,
202  USB_LP_CAN1_RX0_IRQn = 20,
203  CAN1_RX1_IRQn = 21,
204  CAN1_SCE_IRQn = 22,
205  EXTI9_5_IRQn = 23,
206  TIM1_BRK_IRQn = 24,
207  TIM1_UP_IRQn = 25,
208  TIM1_TRG_COM_IRQn = 26,
209  TIM1_CC_IRQn = 27,
210  TIM2_IRQn = 28,
211  TIM3_IRQn = 29,
212  I2C1_EV_IRQn = 31,
213  I2C1_ER_IRQn = 32,
214  SPI1_IRQn = 35,
215  USART1_IRQn = 37,
216  USART2_IRQn = 38,
217  EXTI15_10_IRQn = 40,
218  RTCAlarm_IRQn = 41,
219  USBWakeUp_IRQn = 42
220 #endif /* STM32F10X_LD */
221 
222 #ifdef STM32F10X_LD_VL
223  ADC1_IRQn = 18,
224  EXTI9_5_IRQn = 23,
225  TIM1_BRK_TIM15_IRQn = 24,
226  TIM1_UP_TIM16_IRQn = 25,
227  TIM1_TRG_COM_TIM17_IRQn = 26,
228  TIM1_CC_IRQn = 27,
229  TIM2_IRQn = 28,
230  TIM3_IRQn = 29,
231  I2C1_EV_IRQn = 31,
232  I2C1_ER_IRQn = 32,
233  SPI1_IRQn = 35,
234  USART1_IRQn = 37,
235  USART2_IRQn = 38,
236  EXTI15_10_IRQn = 40,
237  RTCAlarm_IRQn = 41,
238  CEC_IRQn = 42,
239  TIM6_DAC_IRQn = 54,
240  TIM7_IRQn = 55
241 #endif /* STM32F10X_LD_VL */
242 
243 #ifdef STM32F10X_MD
244  ADC1_2_IRQn = 18,
245  USB_HP_CAN1_TX_IRQn = 19,
246  USB_LP_CAN1_RX0_IRQn = 20,
247  CAN1_RX1_IRQn = 21,
248  CAN1_SCE_IRQn = 22,
249  EXTI9_5_IRQn = 23,
250  TIM1_BRK_IRQn = 24,
251  TIM1_UP_IRQn = 25,
252  TIM1_TRG_COM_IRQn = 26,
253  TIM1_CC_IRQn = 27,
254  TIM2_IRQn = 28,
255  TIM3_IRQn = 29,
256  TIM4_IRQn = 30,
257  I2C1_EV_IRQn = 31,
258  I2C1_ER_IRQn = 32,
259  I2C2_EV_IRQn = 33,
260  I2C2_ER_IRQn = 34,
261  SPI1_IRQn = 35,
262  SPI2_IRQn = 36,
263  USART1_IRQn = 37,
264  USART2_IRQn = 38,
265  USART3_IRQn = 39,
266  EXTI15_10_IRQn = 40,
267  RTCAlarm_IRQn = 41,
268  USBWakeUp_IRQn = 42
269 #endif /* STM32F10X_MD */
270 
271 #ifdef STM32F10X_MD_VL
272  ADC1_IRQn = 18,
273  EXTI9_5_IRQn = 23,
274  TIM1_BRK_TIM15_IRQn = 24,
275  TIM1_UP_TIM16_IRQn = 25,
276  TIM1_TRG_COM_TIM17_IRQn = 26,
277  TIM1_CC_IRQn = 27,
278  TIM2_IRQn = 28,
279  TIM3_IRQn = 29,
280  TIM4_IRQn = 30,
281  I2C1_EV_IRQn = 31,
282  I2C1_ER_IRQn = 32,
283  I2C2_EV_IRQn = 33,
284  I2C2_ER_IRQn = 34,
285  SPI1_IRQn = 35,
286  SPI2_IRQn = 36,
287  USART1_IRQn = 37,
288  USART2_IRQn = 38,
289  USART3_IRQn = 39,
290  EXTI15_10_IRQn = 40,
291  RTCAlarm_IRQn = 41,
292  CEC_IRQn = 42,
293  TIM6_DAC_IRQn = 54,
294  TIM7_IRQn = 55
295 #endif /* STM32F10X_MD_VL */
296 
297 #ifdef STM32F10X_HD
298  ADC1_2_IRQn = 18,
299  USB_HP_CAN1_TX_IRQn = 19,
300  USB_LP_CAN1_RX0_IRQn = 20,
301  CAN1_RX1_IRQn = 21,
302  CAN1_SCE_IRQn = 22,
303  EXTI9_5_IRQn = 23,
304  TIM1_BRK_IRQn = 24,
305  TIM1_UP_IRQn = 25,
306  TIM1_TRG_COM_IRQn = 26,
307  TIM1_CC_IRQn = 27,
308  TIM2_IRQn = 28,
309  TIM3_IRQn = 29,
310  TIM4_IRQn = 30,
311  I2C1_EV_IRQn = 31,
312  I2C1_ER_IRQn = 32,
313  I2C2_EV_IRQn = 33,
314  I2C2_ER_IRQn = 34,
315  SPI1_IRQn = 35,
316  SPI2_IRQn = 36,
317  USART1_IRQn = 37,
318  USART2_IRQn = 38,
319  USART3_IRQn = 39,
320  EXTI15_10_IRQn = 40,
321  RTCAlarm_IRQn = 41,
322  USBWakeUp_IRQn = 42,
323  TIM8_BRK_IRQn = 43,
324  TIM8_UP_IRQn = 44,
325  TIM8_TRG_COM_IRQn = 45,
326  TIM8_CC_IRQn = 46,
327  ADC3_IRQn = 47,
328  FSMC_IRQn = 48,
329  SDIO_IRQn = 49,
330  TIM5_IRQn = 50,
331  SPI3_IRQn = 51,
332  UART4_IRQn = 52,
333  UART5_IRQn = 53,
334  TIM6_IRQn = 54,
335  TIM7_IRQn = 55,
336  DMA2_Channel1_IRQn = 56,
337  DMA2_Channel2_IRQn = 57,
338  DMA2_Channel3_IRQn = 58,
339  DMA2_Channel4_5_IRQn = 59
340 #endif /* STM32F10X_HD */
341 
342 #ifdef STM32F10X_HD_VL
343  ADC1_IRQn = 18,
344  EXTI9_5_IRQn = 23,
345  TIM1_BRK_TIM15_IRQn = 24,
346  TIM1_UP_TIM16_IRQn = 25,
347  TIM1_TRG_COM_TIM17_IRQn = 26,
348  TIM1_CC_IRQn = 27,
349  TIM2_IRQn = 28,
350  TIM3_IRQn = 29,
351  TIM4_IRQn = 30,
352  I2C1_EV_IRQn = 31,
353  I2C1_ER_IRQn = 32,
354  I2C2_EV_IRQn = 33,
355  I2C2_ER_IRQn = 34,
356  SPI1_IRQn = 35,
357  SPI2_IRQn = 36,
358  USART1_IRQn = 37,
359  USART2_IRQn = 38,
360  USART3_IRQn = 39,
361  EXTI15_10_IRQn = 40,
362  RTCAlarm_IRQn = 41,
363  CEC_IRQn = 42,
364  TIM12_IRQn = 43,
365  TIM13_IRQn = 44,
366  TIM14_IRQn = 45,
367  TIM5_IRQn = 50,
368  SPI3_IRQn = 51,
369  UART4_IRQn = 52,
370  UART5_IRQn = 53,
371  TIM6_DAC_IRQn = 54,
372  TIM7_IRQn = 55,
373  DMA2_Channel1_IRQn = 56,
374  DMA2_Channel2_IRQn = 57,
375  DMA2_Channel3_IRQn = 58,
376  DMA2_Channel4_5_IRQn = 59,
377  DMA2_Channel5_IRQn = 60
380 #endif /* STM32F10X_HD_VL */
381 
382 #ifdef STM32F10X_XL
383  ADC1_2_IRQn = 18,
384  USB_HP_CAN1_TX_IRQn = 19,
385  USB_LP_CAN1_RX0_IRQn = 20,
386  CAN1_RX1_IRQn = 21,
387  CAN1_SCE_IRQn = 22,
388  EXTI9_5_IRQn = 23,
389  TIM1_BRK_TIM9_IRQn = 24,
390  TIM1_UP_TIM10_IRQn = 25,
391  TIM1_TRG_COM_TIM11_IRQn = 26,
392  TIM1_CC_IRQn = 27,
393  TIM2_IRQn = 28,
394  TIM3_IRQn = 29,
395  TIM4_IRQn = 30,
396  I2C1_EV_IRQn = 31,
397  I2C1_ER_IRQn = 32,
398  I2C2_EV_IRQn = 33,
399  I2C2_ER_IRQn = 34,
400  SPI1_IRQn = 35,
401  SPI2_IRQn = 36,
402  USART1_IRQn = 37,
403  USART2_IRQn = 38,
404  USART3_IRQn = 39,
405  EXTI15_10_IRQn = 40,
406  RTCAlarm_IRQn = 41,
407  USBWakeUp_IRQn = 42,
408  TIM8_BRK_TIM12_IRQn = 43,
409  TIM8_UP_TIM13_IRQn = 44,
410  TIM8_TRG_COM_TIM14_IRQn = 45,
411  TIM8_CC_IRQn = 46,
412  ADC3_IRQn = 47,
413  FSMC_IRQn = 48,
414  SDIO_IRQn = 49,
415  TIM5_IRQn = 50,
416  SPI3_IRQn = 51,
417  UART4_IRQn = 52,
418  UART5_IRQn = 53,
419  TIM6_IRQn = 54,
420  TIM7_IRQn = 55,
421  DMA2_Channel1_IRQn = 56,
422  DMA2_Channel2_IRQn = 57,
423  DMA2_Channel3_IRQn = 58,
424  DMA2_Channel4_5_IRQn = 59
425 #endif /* STM32F10X_XL */
426 
427 #ifdef STM32F10X_CL
428  ADC1_2_IRQn = 18,
429  CAN1_TX_IRQn = 19,
430  CAN1_RX0_IRQn = 20,
431  CAN1_RX1_IRQn = 21,
432  CAN1_SCE_IRQn = 22,
433  EXTI9_5_IRQn = 23,
434  TIM1_BRK_IRQn = 24,
435  TIM1_UP_IRQn = 25,
436  TIM1_TRG_COM_IRQn = 26,
437  TIM1_CC_IRQn = 27,
438  TIM2_IRQn = 28,
439  TIM3_IRQn = 29,
440  TIM4_IRQn = 30,
441  I2C1_EV_IRQn = 31,
442  I2C1_ER_IRQn = 32,
443  I2C2_EV_IRQn = 33,
444  I2C2_ER_IRQn = 34,
445  SPI1_IRQn = 35,
446  SPI2_IRQn = 36,
447  USART1_IRQn = 37,
448  USART2_IRQn = 38,
449  USART3_IRQn = 39,
450  EXTI15_10_IRQn = 40,
451  RTCAlarm_IRQn = 41,
452  OTG_FS_WKUP_IRQn = 42,
453  TIM5_IRQn = 50,
454  SPI3_IRQn = 51,
455  UART4_IRQn = 52,
456  UART5_IRQn = 53,
457  TIM6_IRQn = 54,
458  TIM7_IRQn = 55,
459  DMA2_Channel1_IRQn = 56,
460  DMA2_Channel2_IRQn = 57,
461  DMA2_Channel3_IRQn = 58,
462  DMA2_Channel4_IRQn = 59,
463  DMA2_Channel5_IRQn = 60,
464  ETH_IRQn = 61,
465  ETH_WKUP_IRQn = 62,
466  CAN2_TX_IRQn = 63,
467  CAN2_RX0_IRQn = 64,
468  CAN2_RX1_IRQn = 65,
469  CAN2_SCE_IRQn = 66,
470  OTG_FS_IRQn = 67
471 #endif /* STM32F10X_CL */
472 } IRQn_Type;
473 
478 #include "core_cm3.h"
479 #include "system_stm32f10x.h"
480 #include <stdint.h>
481 
487 typedef int32_t s32;
488 typedef int16_t s16;
489 typedef int8_t s8;
490 
491 typedef const int32_t sc32;
492 typedef const int16_t sc16;
493 typedef const int8_t sc8;
495 typedef __IO int32_t vs32;
496 typedef __IO int16_t vs16;
497 typedef __IO int8_t vs8;
498 
499 typedef __I int32_t vsc32;
500 typedef __I int16_t vsc16;
501 typedef __I int8_t vsc8;
503 typedef uint32_t u32;
504 typedef uint16_t u16;
505 typedef uint8_t u8;
506 
507 typedef const uint32_t uc32;
508 typedef const uint16_t uc16;
509 typedef const uint8_t uc8;
511 typedef __IO uint32_t vu32;
512 typedef __IO uint16_t vu16;
513 typedef __IO uint8_t vu8;
514 
515 typedef __I uint32_t vuc32;
516 typedef __I uint16_t vuc16;
517 typedef __I uint8_t vuc8;
519 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
520 
521 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
522 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
523 
524 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
525 
527 #define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
528 #define HSE_Value HSE_VALUE
529 #define HSI_Value HSI_VALUE
530 
542 typedef struct
543 {
544  __IO uint32_t SR;
545  __IO uint32_t CR1;
546  __IO uint32_t CR2;
547  __IO uint32_t SMPR1;
548  __IO uint32_t SMPR2;
549  __IO uint32_t JOFR1;
550  __IO uint32_t JOFR2;
551  __IO uint32_t JOFR3;
552  __IO uint32_t JOFR4;
553  __IO uint32_t HTR;
554  __IO uint32_t LTR;
555  __IO uint32_t SQR1;
556  __IO uint32_t SQR2;
557  __IO uint32_t SQR3;
558  __IO uint32_t JSQR;
559  __IO uint32_t JDR1;
560  __IO uint32_t JDR2;
561  __IO uint32_t JDR3;
562  __IO uint32_t JDR4;
563  __IO uint32_t DR;
564 } ADC_TypeDef;
565 
570 typedef struct
571 {
572  uint32_t RESERVED0;
573  __IO uint16_t DR1;
574  uint16_t RESERVED1;
575  __IO uint16_t DR2;
576  uint16_t RESERVED2;
577  __IO uint16_t DR3;
578  uint16_t RESERVED3;
579  __IO uint16_t DR4;
580  uint16_t RESERVED4;
581  __IO uint16_t DR5;
582  uint16_t RESERVED5;
583  __IO uint16_t DR6;
584  uint16_t RESERVED6;
585  __IO uint16_t DR7;
586  uint16_t RESERVED7;
587  __IO uint16_t DR8;
588  uint16_t RESERVED8;
589  __IO uint16_t DR9;
590  uint16_t RESERVED9;
591  __IO uint16_t DR10;
592  uint16_t RESERVED10;
593  __IO uint16_t RTCCR;
594  uint16_t RESERVED11;
595  __IO uint16_t CR;
596  uint16_t RESERVED12;
597  __IO uint16_t CSR;
598  uint16_t RESERVED13[5];
599  __IO uint16_t DR11;
600  uint16_t RESERVED14;
601  __IO uint16_t DR12;
602  uint16_t RESERVED15;
603  __IO uint16_t DR13;
604  uint16_t RESERVED16;
605  __IO uint16_t DR14;
606  uint16_t RESERVED17;
607  __IO uint16_t DR15;
608  uint16_t RESERVED18;
609  __IO uint16_t DR16;
610  uint16_t RESERVED19;
611  __IO uint16_t DR17;
612  uint16_t RESERVED20;
613  __IO uint16_t DR18;
614  uint16_t RESERVED21;
615  __IO uint16_t DR19;
616  uint16_t RESERVED22;
617  __IO uint16_t DR20;
618  uint16_t RESERVED23;
619  __IO uint16_t DR21;
620  uint16_t RESERVED24;
621  __IO uint16_t DR22;
622  uint16_t RESERVED25;
623  __IO uint16_t DR23;
624  uint16_t RESERVED26;
625  __IO uint16_t DR24;
626  uint16_t RESERVED27;
627  __IO uint16_t DR25;
628  uint16_t RESERVED28;
629  __IO uint16_t DR26;
630  uint16_t RESERVED29;
631  __IO uint16_t DR27;
632  uint16_t RESERVED30;
633  __IO uint16_t DR28;
634  uint16_t RESERVED31;
635  __IO uint16_t DR29;
636  uint16_t RESERVED32;
637  __IO uint16_t DR30;
638  uint16_t RESERVED33;
639  __IO uint16_t DR31;
640  uint16_t RESERVED34;
641  __IO uint16_t DR32;
642  uint16_t RESERVED35;
643  __IO uint16_t DR33;
644  uint16_t RESERVED36;
645  __IO uint16_t DR34;
646  uint16_t RESERVED37;
647  __IO uint16_t DR35;
648  uint16_t RESERVED38;
649  __IO uint16_t DR36;
650  uint16_t RESERVED39;
651  __IO uint16_t DR37;
652  uint16_t RESERVED40;
653  __IO uint16_t DR38;
654  uint16_t RESERVED41;
655  __IO uint16_t DR39;
656  uint16_t RESERVED42;
657  __IO uint16_t DR40;
658  uint16_t RESERVED43;
659  __IO uint16_t DR41;
660  uint16_t RESERVED44;
661  __IO uint16_t DR42;
662  uint16_t RESERVED45;
663 } BKP_TypeDef;
664 
669 typedef struct
670 {
671  __IO uint32_t TIR;
672  __IO uint32_t TDTR;
673  __IO uint32_t TDLR;
674  __IO uint32_t TDHR;
676 
681 typedef struct
682 {
683  __IO uint32_t RIR;
684  __IO uint32_t RDTR;
685  __IO uint32_t RDLR;
686  __IO uint32_t RDHR;
688 
693 typedef struct
694 {
695  __IO uint32_t FR1;
696  __IO uint32_t FR2;
698 
703 typedef struct
704 {
705  __IO uint32_t MCR;
706  __IO uint32_t MSR;
707  __IO uint32_t TSR;
708  __IO uint32_t RF0R;
709  __IO uint32_t RF1R;
710  __IO uint32_t IER;
711  __IO uint32_t ESR;
712  __IO uint32_t BTR;
713  uint32_t RESERVED0[88];
714  CAN_TxMailBox_TypeDef sTxMailBox[3];
715  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
716  uint32_t RESERVED1[12];
717  __IO uint32_t FMR;
718  __IO uint32_t FM1R;
719  uint32_t RESERVED2;
720  __IO uint32_t FS1R;
721  uint32_t RESERVED3;
722  __IO uint32_t FFA1R;
723  uint32_t RESERVED4;
724  __IO uint32_t FA1R;
725  uint32_t RESERVED5[8];
726 #ifndef STM32F10X_CL
727  CAN_FilterRegister_TypeDef sFilterRegister[14];
728 #else
729  CAN_FilterRegister_TypeDef sFilterRegister[28];
730 #endif /* STM32F10X_CL */
731 } CAN_TypeDef;
732 
736 typedef struct
737 {
738  __IO uint32_t CFGR;
739  __IO uint32_t OAR;
740  __IO uint32_t PRES;
741  __IO uint32_t ESR;
742  __IO uint32_t CSR;
743  __IO uint32_t TXD;
744  __IO uint32_t RXD;
745 } CEC_TypeDef;
746 
751 typedef struct
752 {
753  __IO uint32_t DR;
754  __IO uint8_t IDR;
755  uint8_t RESERVED0;
756  uint16_t RESERVED1;
757  __IO uint32_t CR;
758 } CRC_TypeDef;
759 
764 typedef struct
765 {
766  __IO uint32_t CR;
767  __IO uint32_t SWTRIGR;
768  __IO uint32_t DHR12R1;
769  __IO uint32_t DHR12L1;
770  __IO uint32_t DHR8R1;
771  __IO uint32_t DHR12R2;
772  __IO uint32_t DHR12L2;
773  __IO uint32_t DHR8R2;
774  __IO uint32_t DHR12RD;
775  __IO uint32_t DHR12LD;
776  __IO uint32_t DHR8RD;
777  __IO uint32_t DOR1;
778  __IO uint32_t DOR2;
779 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
780  __IO uint32_t SR;
781 #endif
782 } DAC_TypeDef;
783 
788 typedef struct
789 {
790  __IO uint32_t IDCODE;
791  __IO uint32_t CR;
793 
798 typedef struct
799 {
800  __IO uint32_t CCR;
801  __IO uint32_t CNDTR;
802  __IO uint32_t CPAR;
803  __IO uint32_t CMAR;
805 
806 typedef struct
807 {
808  __IO uint32_t ISR;
809  __IO uint32_t IFCR;
810 } DMA_TypeDef;
811 
816 typedef struct
817 {
818  __IO uint32_t MACCR;
819  __IO uint32_t MACFFR;
820  __IO uint32_t MACHTHR;
821  __IO uint32_t MACHTLR;
822  __IO uint32_t MACMIIAR;
823  __IO uint32_t MACMIIDR;
824  __IO uint32_t MACFCR;
825  __IO uint32_t MACVLANTR; /* 8 */
826  uint32_t RESERVED0[2];
827  __IO uint32_t MACRWUFFR; /* 11 */
828  __IO uint32_t MACPMTCSR;
829  uint32_t RESERVED1[2];
830  __IO uint32_t MACSR; /* 15 */
831  __IO uint32_t MACIMR;
832  __IO uint32_t MACA0HR;
833  __IO uint32_t MACA0LR;
834  __IO uint32_t MACA1HR;
835  __IO uint32_t MACA1LR;
836  __IO uint32_t MACA2HR;
837  __IO uint32_t MACA2LR;
838  __IO uint32_t MACA3HR;
839  __IO uint32_t MACA3LR; /* 24 */
840  uint32_t RESERVED2[40];
841  __IO uint32_t MMCCR; /* 65 */
842  __IO uint32_t MMCRIR;
843  __IO uint32_t MMCTIR;
844  __IO uint32_t MMCRIMR;
845  __IO uint32_t MMCTIMR; /* 69 */
846  uint32_t RESERVED3[14];
847  __IO uint32_t MMCTGFSCCR; /* 84 */
848  __IO uint32_t MMCTGFMSCCR;
849  uint32_t RESERVED4[5];
850  __IO uint32_t MMCTGFCR;
851  uint32_t RESERVED5[10];
852  __IO uint32_t MMCRFCECR;
853  __IO uint32_t MMCRFAECR;
854  uint32_t RESERVED6[10];
855  __IO uint32_t MMCRGUFCR;
856  uint32_t RESERVED7[334];
857  __IO uint32_t PTPTSCR;
858  __IO uint32_t PTPSSIR;
859  __IO uint32_t PTPTSHR;
860  __IO uint32_t PTPTSLR;
861  __IO uint32_t PTPTSHUR;
862  __IO uint32_t PTPTSLUR;
863  __IO uint32_t PTPTSAR;
864  __IO uint32_t PTPTTHR;
865  __IO uint32_t PTPTTLR;
866  uint32_t RESERVED8[567];
867  __IO uint32_t DMABMR;
868  __IO uint32_t DMATPDR;
869  __IO uint32_t DMARPDR;
870  __IO uint32_t DMARDLAR;
871  __IO uint32_t DMATDLAR;
872  __IO uint32_t DMASR;
873  __IO uint32_t DMAOMR;
874  __IO uint32_t DMAIER;
875  __IO uint32_t DMAMFBOCR;
876  uint32_t RESERVED9[9];
877  __IO uint32_t DMACHTDR;
878  __IO uint32_t DMACHRDR;
879  __IO uint32_t DMACHTBAR;
880  __IO uint32_t DMACHRBAR;
881 } ETH_TypeDef;
882 
887 typedef struct
888 {
889  __IO uint32_t IMR;
890  __IO uint32_t EMR;
891  __IO uint32_t RTSR;
892  __IO uint32_t FTSR;
893  __IO uint32_t SWIER;
894  __IO uint32_t PR;
895 } EXTI_TypeDef;
896 
901 typedef struct
902 {
903  __IO uint32_t ACR;
904  __IO uint32_t KEYR;
905  __IO uint32_t OPTKEYR;
906  __IO uint32_t SR;
907  __IO uint32_t CR;
908  __IO uint32_t AR;
909  __IO uint32_t RESERVED;
910  __IO uint32_t OBR;
911  __IO uint32_t WRPR;
912 #ifdef STM32F10X_XL
913  uint32_t RESERVED1[8];
914  __IO uint32_t KEYR2;
915  uint32_t RESERVED2;
916  __IO uint32_t SR2;
917  __IO uint32_t CR2;
918  __IO uint32_t AR2;
919 #endif /* STM32F10X_XL */
920 } FLASH_TypeDef;
921 
926 typedef struct
927 {
928  __IO uint16_t RDP;
929  __IO uint16_t USER;
930  __IO uint16_t Data0;
931  __IO uint16_t Data1;
932  __IO uint16_t WRP0;
933  __IO uint16_t WRP1;
934  __IO uint16_t WRP2;
935  __IO uint16_t WRP3;
936 } OB_TypeDef;
937 
942 typedef struct
943 {
944  __IO uint32_t BTCR[8];
946 
951 typedef struct
952 {
953  __IO uint32_t BWTR[7];
955 
960 typedef struct
961 {
962  __IO uint32_t PCR2;
963  __IO uint32_t SR2;
964  __IO uint32_t PMEM2;
965  __IO uint32_t PATT2;
966  uint32_t RESERVED0;
967  __IO uint32_t ECCR2;
969 
974 typedef struct
975 {
976  __IO uint32_t PCR3;
977  __IO uint32_t SR3;
978  __IO uint32_t PMEM3;
979  __IO uint32_t PATT3;
980  uint32_t RESERVED0;
981  __IO uint32_t ECCR3;
983 
988 typedef struct
989 {
990  __IO uint32_t PCR4;
991  __IO uint32_t SR4;
992  __IO uint32_t PMEM4;
993  __IO uint32_t PATT4;
994  __IO uint32_t PIO4;
996 
1001 typedef struct
1002 {
1003  __IO uint32_t CRL;
1004  __IO uint32_t CRH;
1005  __IO uint32_t IDR;
1006  __IO uint32_t ODR;
1007  __IO uint32_t BSRR;
1008  __IO uint32_t BRR;
1009  __IO uint32_t LCKR;
1010 } GPIO_TypeDef;
1011 
1016 typedef struct
1017 {
1018  __IO uint32_t EVCR;
1019  __IO uint32_t MAPR;
1020  __IO uint32_t EXTICR[4];
1021  uint32_t RESERVED0;
1022  __IO uint32_t MAPR2;
1023 } AFIO_TypeDef;
1028 typedef struct
1029 {
1030  __IO uint16_t CR1;
1031  uint16_t RESERVED0;
1032  __IO uint16_t CR2;
1033  uint16_t RESERVED1;
1034  __IO uint16_t OAR1;
1035  uint16_t RESERVED2;
1036  __IO uint16_t OAR2;
1037  uint16_t RESERVED3;
1038  __IO uint16_t DR;
1039  uint16_t RESERVED4;
1040  __IO uint16_t SR1;
1041  uint16_t RESERVED5;
1042  __IO uint16_t SR2;
1043  uint16_t RESERVED6;
1044  __IO uint16_t CCR;
1045  uint16_t RESERVED7;
1046  __IO uint16_t TRISE;
1047  uint16_t RESERVED8;
1048 } I2C_TypeDef;
1049 
1054 typedef struct
1055 {
1056  __IO uint32_t KR;
1057  __IO uint32_t PR;
1058  __IO uint32_t RLR;
1059  __IO uint32_t SR;
1060 } IWDG_TypeDef;
1061 
1066 typedef struct
1067 {
1068  __IO uint32_t CR;
1069  __IO uint32_t CSR;
1070 } PWR_TypeDef;
1071 
1076 typedef struct
1077 {
1078  __IO uint32_t CR;
1079  __IO uint32_t CFGR;
1080  __IO uint32_t CIR;
1081  __IO uint32_t APB2RSTR;
1082  __IO uint32_t APB1RSTR;
1083  __IO uint32_t AHBENR;
1084  __IO uint32_t APB2ENR;
1085  __IO uint32_t APB1ENR;
1086  __IO uint32_t BDCR;
1087  __IO uint32_t CSR;
1088 
1089 #ifdef STM32F10X_CL
1090  __IO uint32_t AHBRSTR;
1091  __IO uint32_t CFGR2;
1092 #endif /* STM32F10X_CL */
1093 
1094 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
1095  uint32_t RESERVED0;
1096  __IO uint32_t CFGR2;
1097 #endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */
1098 } RCC_TypeDef;
1099 
1104 typedef struct
1105 {
1106  __IO uint16_t CRH;
1107  uint16_t RESERVED0;
1108  __IO uint16_t CRL;
1109  uint16_t RESERVED1;
1110  __IO uint16_t PRLH;
1111  uint16_t RESERVED2;
1112  __IO uint16_t PRLL;
1113  uint16_t RESERVED3;
1114  __IO uint16_t DIVH;
1115  uint16_t RESERVED4;
1116  __IO uint16_t DIVL;
1117  uint16_t RESERVED5;
1118  __IO uint16_t CNTH;
1119  uint16_t RESERVED6;
1120  __IO uint16_t CNTL;
1121  uint16_t RESERVED7;
1122  __IO uint16_t ALRH;
1123  uint16_t RESERVED8;
1124  __IO uint16_t ALRL;
1125  uint16_t RESERVED9;
1126 } RTC_TypeDef;
1127 
1132 typedef struct
1133 {
1134  __IO uint32_t POWER;
1135  __IO uint32_t CLKCR;
1136  __IO uint32_t ARG;
1137  __IO uint32_t CMD;
1138  __I uint32_t RESPCMD;
1139  __I uint32_t RESP1;
1140  __I uint32_t RESP2;
1141  __I uint32_t RESP3;
1142  __I uint32_t RESP4;
1143  __IO uint32_t DTIMER;
1144  __IO uint32_t DLEN;
1145  __IO uint32_t DCTRL;
1146  __I uint32_t DCOUNT;
1147  __I uint32_t STA;
1148  __IO uint32_t ICR;
1149  __IO uint32_t MASK;
1150  uint32_t RESERVED0[2];
1151  __I uint32_t FIFOCNT;
1152  uint32_t RESERVED1[13];
1153  __IO uint32_t FIFO;
1154 } SDIO_TypeDef;
1155 
1160 typedef struct
1161 {
1162  __IO uint16_t CR1;
1163  uint16_t RESERVED0;
1164  __IO uint16_t CR2;
1165  uint16_t RESERVED1;
1166  __IO uint16_t SR;
1167  uint16_t RESERVED2;
1168  __IO uint16_t DR;
1169  uint16_t RESERVED3;
1170  __IO uint16_t CRCPR;
1171  uint16_t RESERVED4;
1172  __IO uint16_t RXCRCR;
1173  uint16_t RESERVED5;
1174  __IO uint16_t TXCRCR;
1175  uint16_t RESERVED6;
1176  __IO uint16_t I2SCFGR;
1177  uint16_t RESERVED7;
1178  __IO uint16_t I2SPR;
1179  uint16_t RESERVED8;
1180 } SPI_TypeDef;
1181 
1186 typedef struct
1187 {
1188  __IO uint16_t CR1;
1189  uint16_t RESERVED0;
1190  __IO uint16_t CR2;
1191  uint16_t RESERVED1;
1192  __IO uint16_t SMCR;
1193  uint16_t RESERVED2;
1194  __IO uint16_t DIER;
1195  uint16_t RESERVED3;
1196  __IO uint16_t SR;
1197  uint16_t RESERVED4;
1198  __IO uint16_t EGR;
1199  uint16_t RESERVED5;
1200  __IO uint16_t CCMR1;
1201  uint16_t RESERVED6;
1202  __IO uint16_t CCMR2;
1203  uint16_t RESERVED7;
1204  __IO uint16_t CCER;
1205  uint16_t RESERVED8;
1206  __IO uint16_t CNT;
1207  uint16_t RESERVED9;
1208  __IO uint16_t PSC;
1209  uint16_t RESERVED10;
1210  __IO uint16_t ARR;
1211  uint16_t RESERVED11;
1212  __IO uint16_t RCR;
1213  uint16_t RESERVED12;
1214  __IO uint16_t CCR1;
1215  uint16_t RESERVED13;
1216  __IO uint16_t CCR2;
1217  uint16_t RESERVED14;
1218  __IO uint16_t CCR3;
1219  uint16_t RESERVED15;
1220  __IO uint16_t CCR4;
1221  uint16_t RESERVED16;
1222  __IO uint16_t BDTR;
1223  uint16_t RESERVED17;
1224  __IO uint16_t DCR;
1225  uint16_t RESERVED18;
1226  __IO uint16_t DMAR;
1227  uint16_t RESERVED19;
1228 } TIM_TypeDef;
1229 
1234 typedef struct
1235 {
1236  __IO uint16_t SR;
1237  uint16_t RESERVED0;
1238  __IO uint16_t DR;
1239  uint16_t RESERVED1;
1240  __IO uint16_t BRR;
1241  uint16_t RESERVED2;
1242  __IO uint16_t CR1;
1243  uint16_t RESERVED3;
1244  __IO uint16_t CR2;
1245  uint16_t RESERVED4;
1246  __IO uint16_t CR3;
1247  uint16_t RESERVED5;
1248  __IO uint16_t GTPR;
1249  uint16_t RESERVED6;
1250 } USART_TypeDef;
1251 
1256 typedef struct
1257 {
1258  __IO uint32_t CR;
1259  __IO uint32_t CFR;
1260  __IO uint32_t SR;
1261 } WWDG_TypeDef;
1262 
1272 #define FLASH_BASE ((uint32_t)0x08000000)
1273 #define SRAM_BASE ((uint32_t)0x20000000)
1274 #define PERIPH_BASE ((uint32_t)0x40000000)
1276 #define SRAM_BB_BASE ((uint32_t)0x22000000)
1277 #define PERIPH_BB_BASE ((uint32_t)0x42000000)
1279 #define FSMC_R_BASE ((uint32_t)0xA0000000)
1282 #define APB1PERIPH_BASE PERIPH_BASE
1283 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
1284 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
1285 
1286 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
1287 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
1288 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
1289 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
1290 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
1291 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
1292 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
1293 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
1294 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
1295 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
1296 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
1297 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
1298 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
1299 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
1300 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
1301 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
1302 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
1303 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
1304 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
1305 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
1306 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
1307 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
1308 #define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
1309 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
1310 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
1311 #define CEC_BASE (APB1PERIPH_BASE + 0x7800)
1312 
1313 #define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
1314 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
1315 #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
1316 #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
1317 #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
1318 #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
1319 #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
1320 #define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
1321 #define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
1322 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
1323 #define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
1324 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
1325 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
1326 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
1327 #define USART1_BASE (APB2PERIPH_BASE + 0x3800)
1328 #define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
1329 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
1330 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
1331 #define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
1332 #define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)
1333 #define TIM10_BASE (APB2PERIPH_BASE + 0x5000)
1334 #define TIM11_BASE (APB2PERIPH_BASE + 0x5400)
1335 
1336 #define SDIO_BASE (PERIPH_BASE + 0x18000)
1337 
1338 #define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
1339 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
1340 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
1341 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
1342 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
1343 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
1344 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
1345 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
1346 #define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
1347 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
1348 #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
1349 #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
1350 #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
1351 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
1352 #define RCC_BASE (AHBPERIPH_BASE + 0x1000)
1353 #define CRC_BASE (AHBPERIPH_BASE + 0x3000)
1354 
1355 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
1356 #define OB_BASE ((uint32_t)0x1FFFF800)
1358 #define ETH_BASE (AHBPERIPH_BASE + 0x8000)
1359 #define ETH_MAC_BASE (ETH_BASE)
1360 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
1361 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
1362 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
1363 
1364 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
1365 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
1366 #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
1367 #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
1368 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
1370 #define DBGMCU_BASE ((uint32_t)0xE0042000)
1380 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1381 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1382 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1383 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1384 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1385 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1386 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1387 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1388 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1389 #define RTC ((RTC_TypeDef *) RTC_BASE)
1390 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1391 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1392 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1393 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1394 #define USART2 ((USART_TypeDef *) USART2_BASE)
1395 #define USART3 ((USART_TypeDef *) USART3_BASE)
1396 #define UART4 ((USART_TypeDef *) UART4_BASE)
1397 #define UART5 ((USART_TypeDef *) UART5_BASE)
1398 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1399 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1400 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1401 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1402 #define BKP ((BKP_TypeDef *) BKP_BASE)
1403 #define PWR ((PWR_TypeDef *) PWR_BASE)
1404 #define DAC ((DAC_TypeDef *) DAC_BASE)
1405 #define CEC ((CEC_TypeDef *) CEC_BASE)
1406 #define AFIO ((AFIO_TypeDef *) AFIO_BASE)
1407 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1408 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1409 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1410 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1411 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1412 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1413 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1414 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1415 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1416 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1417 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1418 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1419 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1420 #define USART1 ((USART_TypeDef *) USART1_BASE)
1421 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1422 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
1423 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
1424 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
1425 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1426 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1427 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1428 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1429 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1430 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1431 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1432 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1433 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1434 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1435 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1436 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1437 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1438 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1439 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1440 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1441 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1442 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1443 #define RCC ((RCC_TypeDef *) RCC_BASE)
1444 #define CRC ((CRC_TypeDef *) CRC_BASE)
1445 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1446 #define OB ((OB_TypeDef *) OB_BASE)
1447 #define ETH ((ETH_TypeDef *) ETH_BASE)
1448 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1449 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1450 #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
1451 #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
1452 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1453 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1454 
1467 /******************************************************************************/
1468 /* Peripheral Registers_Bits_Definition */
1469 /******************************************************************************/
1470 
1471 /******************************************************************************/
1472 /* */
1473 /* CRC calculation unit */
1474 /* */
1475 /******************************************************************************/
1476 
1477 /******************* Bit definition for CRC_DR register *********************/
1478 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF)
1481 /******************* Bit definition for CRC_IDR register ********************/
1482 #define CRC_IDR_IDR ((uint8_t)0xFF)
1485 /******************** Bit definition for CRC_CR register ********************/
1486 #define CRC_CR_RESET ((uint8_t)0x01)
1488 /******************************************************************************/
1489 /* */
1490 /* Power Control */
1491 /* */
1492 /******************************************************************************/
1493 
1494 /******************** Bit definition for PWR_CR register ********************/
1495 #define PWR_CR_LPDS ((uint16_t)0x0001)
1496 #define PWR_CR_PDDS ((uint16_t)0x0002)
1497 #define PWR_CR_CWUF ((uint16_t)0x0004)
1498 #define PWR_CR_CSBF ((uint16_t)0x0008)
1499 #define PWR_CR_PVDE ((uint16_t)0x0010)
1501 #define PWR_CR_PLS ((uint16_t)0x00E0)
1502 #define PWR_CR_PLS_0 ((uint16_t)0x0020)
1503 #define PWR_CR_PLS_1 ((uint16_t)0x0040)
1504 #define PWR_CR_PLS_2 ((uint16_t)0x0080)
1507 #define PWR_CR_PLS_2V2 ((uint16_t)0x0000)
1508 #define PWR_CR_PLS_2V3 ((uint16_t)0x0020)
1509 #define PWR_CR_PLS_2V4 ((uint16_t)0x0040)
1510 #define PWR_CR_PLS_2V5 ((uint16_t)0x0060)
1511 #define PWR_CR_PLS_2V6 ((uint16_t)0x0080)
1512 #define PWR_CR_PLS_2V7 ((uint16_t)0x00A0)
1513 #define PWR_CR_PLS_2V8 ((uint16_t)0x00C0)
1514 #define PWR_CR_PLS_2V9 ((uint16_t)0x00E0)
1516 #define PWR_CR_DBP ((uint16_t)0x0100)
1519 /******************* Bit definition for PWR_CSR register ********************/
1520 #define PWR_CSR_WUF ((uint16_t)0x0001)
1521 #define PWR_CSR_SBF ((uint16_t)0x0002)
1522 #define PWR_CSR_PVDO ((uint16_t)0x0004)
1523 #define PWR_CSR_EWUP ((uint16_t)0x0100)
1525 /******************************************************************************/
1526 /* */
1527 /* Backup registers */
1528 /* */
1529 /******************************************************************************/
1530 
1531 /******************* Bit definition for BKP_DR1 register ********************/
1532 #define BKP_DR1_D ((uint16_t)0xFFFF)
1534 /******************* Bit definition for BKP_DR2 register ********************/
1535 #define BKP_DR2_D ((uint16_t)0xFFFF)
1537 /******************* Bit definition for BKP_DR3 register ********************/
1538 #define BKP_DR3_D ((uint16_t)0xFFFF)
1540 /******************* Bit definition for BKP_DR4 register ********************/
1541 #define BKP_DR4_D ((uint16_t)0xFFFF)
1543 /******************* Bit definition for BKP_DR5 register ********************/
1544 #define BKP_DR5_D ((uint16_t)0xFFFF)
1546 /******************* Bit definition for BKP_DR6 register ********************/
1547 #define BKP_DR6_D ((uint16_t)0xFFFF)
1549 /******************* Bit definition for BKP_DR7 register ********************/
1550 #define BKP_DR7_D ((uint16_t)0xFFFF)
1552 /******************* Bit definition for BKP_DR8 register ********************/
1553 #define BKP_DR8_D ((uint16_t)0xFFFF)
1555 /******************* Bit definition for BKP_DR9 register ********************/
1556 #define BKP_DR9_D ((uint16_t)0xFFFF)
1558 /******************* Bit definition for BKP_DR10 register *******************/
1559 #define BKP_DR10_D ((uint16_t)0xFFFF)
1561 /******************* Bit definition for BKP_DR11 register *******************/
1562 #define BKP_DR11_D ((uint16_t)0xFFFF)
1564 /******************* Bit definition for BKP_DR12 register *******************/
1565 #define BKP_DR12_D ((uint16_t)0xFFFF)
1567 /******************* Bit definition for BKP_DR13 register *******************/
1568 #define BKP_DR13_D ((uint16_t)0xFFFF)
1570 /******************* Bit definition for BKP_DR14 register *******************/
1571 #define BKP_DR14_D ((uint16_t)0xFFFF)
1573 /******************* Bit definition for BKP_DR15 register *******************/
1574 #define BKP_DR15_D ((uint16_t)0xFFFF)
1576 /******************* Bit definition for BKP_DR16 register *******************/
1577 #define BKP_DR16_D ((uint16_t)0xFFFF)
1579 /******************* Bit definition for BKP_DR17 register *******************/
1580 #define BKP_DR17_D ((uint16_t)0xFFFF)
1582 /****************** Bit definition for BKP_DR18 register ********************/
1583 #define BKP_DR18_D ((uint16_t)0xFFFF)
1585 /******************* Bit definition for BKP_DR19 register *******************/
1586 #define BKP_DR19_D ((uint16_t)0xFFFF)
1588 /******************* Bit definition for BKP_DR20 register *******************/
1589 #define BKP_DR20_D ((uint16_t)0xFFFF)
1591 /******************* Bit definition for BKP_DR21 register *******************/
1592 #define BKP_DR21_D ((uint16_t)0xFFFF)
1594 /******************* Bit definition for BKP_DR22 register *******************/
1595 #define BKP_DR22_D ((uint16_t)0xFFFF)
1597 /******************* Bit definition for BKP_DR23 register *******************/
1598 #define BKP_DR23_D ((uint16_t)0xFFFF)
1600 /******************* Bit definition for BKP_DR24 register *******************/
1601 #define BKP_DR24_D ((uint16_t)0xFFFF)
1603 /******************* Bit definition for BKP_DR25 register *******************/
1604 #define BKP_DR25_D ((uint16_t)0xFFFF)
1606 /******************* Bit definition for BKP_DR26 register *******************/
1607 #define BKP_DR26_D ((uint16_t)0xFFFF)
1609 /******************* Bit definition for BKP_DR27 register *******************/
1610 #define BKP_DR27_D ((uint16_t)0xFFFF)
1612 /******************* Bit definition for BKP_DR28 register *******************/
1613 #define BKP_DR28_D ((uint16_t)0xFFFF)
1615 /******************* Bit definition for BKP_DR29 register *******************/
1616 #define BKP_DR29_D ((uint16_t)0xFFFF)
1618 /******************* Bit definition for BKP_DR30 register *******************/
1619 #define BKP_DR30_D ((uint16_t)0xFFFF)
1621 /******************* Bit definition for BKP_DR31 register *******************/
1622 #define BKP_DR31_D ((uint16_t)0xFFFF)
1624 /******************* Bit definition for BKP_DR32 register *******************/
1625 #define BKP_DR32_D ((uint16_t)0xFFFF)
1627 /******************* Bit definition for BKP_DR33 register *******************/
1628 #define BKP_DR33_D ((uint16_t)0xFFFF)
1630 /******************* Bit definition for BKP_DR34 register *******************/
1631 #define BKP_DR34_D ((uint16_t)0xFFFF)
1633 /******************* Bit definition for BKP_DR35 register *******************/
1634 #define BKP_DR35_D ((uint16_t)0xFFFF)
1636 /******************* Bit definition for BKP_DR36 register *******************/
1637 #define BKP_DR36_D ((uint16_t)0xFFFF)
1639 /******************* Bit definition for BKP_DR37 register *******************/
1640 #define BKP_DR37_D ((uint16_t)0xFFFF)
1642 /******************* Bit definition for BKP_DR38 register *******************/
1643 #define BKP_DR38_D ((uint16_t)0xFFFF)
1645 /******************* Bit definition for BKP_DR39 register *******************/
1646 #define BKP_DR39_D ((uint16_t)0xFFFF)
1648 /******************* Bit definition for BKP_DR40 register *******************/
1649 #define BKP_DR40_D ((uint16_t)0xFFFF)
1651 /******************* Bit definition for BKP_DR41 register *******************/
1652 #define BKP_DR41_D ((uint16_t)0xFFFF)
1654 /******************* Bit definition for BKP_DR42 register *******************/
1655 #define BKP_DR42_D ((uint16_t)0xFFFF)
1657 /****************** Bit definition for BKP_RTCCR register *******************/
1658 #define BKP_RTCCR_CAL ((uint16_t)0x007F)
1659 #define BKP_RTCCR_CCO ((uint16_t)0x0080)
1660 #define BKP_RTCCR_ASOE ((uint16_t)0x0100)
1661 #define BKP_RTCCR_ASOS ((uint16_t)0x0200)
1663 /******************** Bit definition for BKP_CR register ********************/
1664 #define BKP_CR_TPE ((uint8_t)0x01)
1665 #define BKP_CR_TPAL ((uint8_t)0x02)
1667 /******************* Bit definition for BKP_CSR register ********************/
1668 #define BKP_CSR_CTE ((uint16_t)0x0001)
1669 #define BKP_CSR_CTI ((uint16_t)0x0002)
1670 #define BKP_CSR_TPIE ((uint16_t)0x0004)
1671 #define BKP_CSR_TEF ((uint16_t)0x0100)
1672 #define BKP_CSR_TIF ((uint16_t)0x0200)
1674 /******************************************************************************/
1675 /* */
1676 /* Reset and Clock Control */
1677 /* */
1678 /******************************************************************************/
1679 
1680 /******************** Bit definition for RCC_CR register ********************/
1681 #define RCC_CR_HSION ((uint32_t)0x00000001)
1682 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
1683 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
1684 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
1685 #define RCC_CR_HSEON ((uint32_t)0x00010000)
1686 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
1687 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
1688 #define RCC_CR_CSSON ((uint32_t)0x00080000)
1689 #define RCC_CR_PLLON ((uint32_t)0x01000000)
1690 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
1692 #ifdef STM32F10X_CL
1693  #define RCC_CR_PLL2ON ((uint32_t)0x04000000)
1694  #define RCC_CR_PLL2RDY ((uint32_t)0x08000000)
1695  #define RCC_CR_PLL3ON ((uint32_t)0x10000000)
1696  #define RCC_CR_PLL3RDY ((uint32_t)0x20000000)
1697 #endif /* STM32F10X_CL */
1698 
1699 /******************* Bit definition for RCC_CFGR register *******************/
1701 #define RCC_CFGR_SW ((uint32_t)0x00000003)
1702 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001)
1703 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002)
1705 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000)
1706 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001)
1707 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002)
1710 #define RCC_CFGR_SWS ((uint32_t)0x0000000C)
1711 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004)
1712 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008)
1714 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000)
1715 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004)
1716 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008)
1719 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0)
1720 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010)
1721 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020)
1722 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040)
1723 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080)
1725 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000)
1726 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080)
1727 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090)
1728 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0)
1729 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0)
1730 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0)
1731 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0)
1732 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0)
1733 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0)
1736 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700)
1737 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100)
1738 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200)
1739 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400)
1741 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000)
1742 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400)
1743 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500)
1744 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600)
1745 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700)
1748 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800)
1749 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800)
1750 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000)
1751 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000)
1753 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000)
1754 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000)
1755 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800)
1756 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000)
1757 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800)
1760 #define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000)
1761 #define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000)
1762 #define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000)
1764 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000)
1765 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000)
1766 #define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000)
1767 #define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000)
1769 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000)
1771 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000)
1774 #define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000)
1775 #define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000)
1776 #define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000)
1777 #define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000)
1778 #define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000)
1780 #ifdef STM32F10X_CL
1781  #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000)
1782  #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000)
1784  #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000)
1785  #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000)
1787  #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000)
1788  #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000)
1789  #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000)
1790  #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000)
1791  #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000)
1792  #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000)
1793  #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000)
1795  #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000)
1798  #define RCC_CFGR_MCO ((uint32_t)0x0F000000)
1799  #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000)
1800  #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000)
1801  #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000)
1802  #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000)
1804  #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000)
1805  #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000)
1806  #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000)
1807  #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000)
1808  #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000)
1809  #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000)
1810  #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000)
1811  #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000)
1812  #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000)
1813 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
1814  #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000)
1815  #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000)
1817  #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000)
1818  #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000)
1820  #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000)
1821  #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000)
1822  #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000)
1823  #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000)
1824  #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000)
1825  #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000)
1826  #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000)
1827  #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000)
1828  #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000)
1829  #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000)
1830  #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000)
1831  #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000)
1832  #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000)
1833  #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000)
1834  #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000)
1837  #define RCC_CFGR_MCO ((uint32_t)0x07000000)
1838  #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000)
1839  #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000)
1840  #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000)
1842  #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000)
1843  #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000)
1844  #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000)
1845  #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000)
1846  #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000)
1847 #else
1848  #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000)
1849  #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000)
1851  #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000)
1852  #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000)
1854  #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000)
1855  #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000)
1856  #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000)
1857  #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000)
1858  #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000)
1859  #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000)
1860  #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000)
1861  #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000)
1862  #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000)
1863  #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000)
1864  #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000)
1865  #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000)
1866  #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000)
1867  #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000)
1868  #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000)
1869  #define RCC_CFGR_USBPRE ((uint32_t)0x00400000)
1872  #define RCC_CFGR_MCO ((uint32_t)0x07000000)
1873  #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000)
1874  #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000)
1875  #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000)
1877  #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000)
1878  #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000)
1879  #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000)
1880  #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000)
1881  #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000)
1882 #endif /* STM32F10X_CL */
1883 
1885 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
1886 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
1887 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
1888 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
1889 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
1890 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
1891 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
1892 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
1893 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
1894 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
1895 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
1896 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
1897 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
1898 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
1899 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
1900 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
1901 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
1903 #ifdef STM32F10X_CL
1904  #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020)
1905  #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040)
1906  #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000)
1907  #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000)
1908  #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000)
1909  #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000)
1910 #endif /* STM32F10X_CL */
1911 
1912 /***************** Bit definition for RCC_APB2RSTR register *****************/
1913 #define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001)
1914 #define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004)
1915 #define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008)
1916 #define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010)
1917 #define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020)
1918 #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200)
1920 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
1921 #define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400)
1922 #endif
1923 
1924 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800)
1925 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
1926 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000)
1928 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
1929 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000)
1930 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000)
1931 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000)
1932 #endif
1933 
1934 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
1935  #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040)
1936 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
1937 
1938 #if defined (STM32F10X_HD) || defined (STM32F10X_XL)
1939  #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080)
1940  #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100)
1941  #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000)
1942  #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000)
1943 #endif
1944 
1945 #if defined (STM32F10X_HD_VL)
1946  #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080)
1947  #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100)
1948 #endif
1949 
1950 #ifdef STM32F10X_XL
1951  #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000)
1952  #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000)
1953  #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000)
1954 #endif /* STM32F10X_XL */
1955 
1956 /***************** Bit definition for RCC_APB1RSTR register *****************/
1957 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
1958 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
1959 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
1960 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
1961 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
1963 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
1964 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
1965 #endif
1966 
1967 #define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000)
1968 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
1970 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
1971  #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
1972  #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
1973  #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
1974  #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
1975 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
1976 
1977 #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL)
1978  #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000)
1979 #endif
1980 
1981 #if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL)
1982  #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
1983  #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
1984  #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
1985  #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
1986  #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
1987  #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
1988  #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
1989 #endif
1990 
1991 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
1992  #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
1993  #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
1994  #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
1995  #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000)
1996 #endif
1997 
1998 #if defined (STM32F10X_HD_VL)
1999  #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
2000  #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
2001  #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
2002  #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
2003  #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
2004  #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
2005  #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
2006 #endif
2007 
2008 #ifdef STM32F10X_CL
2009  #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
2010 #endif /* STM32F10X_CL */
2011 
2012 #ifdef STM32F10X_XL
2013  #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
2014  #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
2015  #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
2016 #endif /* STM32F10X_XL */
2017 
2018 /****************** Bit definition for RCC_AHBENR register ******************/
2019 #define RCC_AHBENR_DMA1EN ((uint16_t)0x0001)
2020 #define RCC_AHBENR_SRAMEN ((uint16_t)0x0004)
2021 #define RCC_AHBENR_FLITFEN ((uint16_t)0x0010)
2022 #define RCC_AHBENR_CRCEN ((uint16_t)0x0040)
2024 #if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL)
2025  #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002)
2026 #endif
2027 
2028 #if defined (STM32F10X_HD) || defined (STM32F10X_XL)
2029  #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100)
2030  #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400)
2031 #endif
2032 
2033 #if defined (STM32F10X_HD_VL)
2034  #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100)
2035 #endif
2036 
2037 #ifdef STM32F10X_CL
2038  #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000)
2039  #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000)
2040  #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000)
2041  #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000)
2042 #endif /* STM32F10X_CL */
2043 
2044 /****************** Bit definition for RCC_APB2ENR register *****************/
2045 #define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001)
2046 #define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004)
2047 #define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008)
2048 #define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010)
2049 #define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020)
2050 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200)
2052 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
2053 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400)
2054 #endif
2055 
2056 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800)
2057 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
2058 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000)
2060 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
2061 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000)
2062 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000)
2063 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000)
2064 #endif
2065 
2066 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
2067  #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040)
2068 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
2069 
2070 #if defined (STM32F10X_HD) || defined (STM32F10X_XL)
2071  #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080)
2072  #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100)
2073  #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000)
2074  #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000)
2075 #endif
2076 
2077 #if defined (STM32F10X_HD_VL)
2078  #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080)
2079  #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100)
2080 #endif
2081 
2082 #ifdef STM32F10X_XL
2083  #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000)
2084  #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000)
2085  #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000)
2086 #endif
2087 
2088 /***************** Bit definition for RCC_APB1ENR register ******************/
2089 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
2090 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
2091 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
2092 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
2093 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
2095 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
2096 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
2097 #endif
2098 
2099 #define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000)
2100 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
2102 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
2103  #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
2104  #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
2105  #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
2106  #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
2107 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
2108 
2109 #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
2110  #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000)
2111 #endif
2112 
2113 #if defined (STM32F10X_HD) || defined (STM32F10X_CL)
2114  #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
2115  #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
2116  #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
2117  #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
2118  #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
2119  #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
2120  #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
2121 #endif
2122 
2123 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
2124  #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
2125  #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
2126  #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
2127  #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000)
2128 #endif
2129 
2130 #ifdef STM32F10X_HD_VL
2131  #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
2132  #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
2133  #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
2134  #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
2135  #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
2136  #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
2137  #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
2138 #endif /* STM32F10X_HD_VL */
2139 
2140 #ifdef STM32F10X_CL
2141  #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
2142 #endif /* STM32F10X_CL */
2143 
2144 #ifdef STM32F10X_XL
2145  #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
2146  #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
2147  #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
2148 #endif /* STM32F10X_XL */
2149 
2150 /******************* Bit definition for RCC_BDCR register *******************/
2151 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
2152 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
2153 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
2155 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
2156 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
2157 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
2160 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000)
2161 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100)
2162 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200)
2163 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300)
2165 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
2166 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
2168 /******************* Bit definition for RCC_CSR register ********************/
2169 #define RCC_CSR_LSION ((uint32_t)0x00000001)
2170 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
2171 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
2172 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000)
2173 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
2174 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
2175 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)
2176 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
2177 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
2179 #ifdef STM32F10X_CL
2180 /******************* Bit definition for RCC_AHBRSTR register ****************/
2181  #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000)
2182  #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000)
2184 /******************* Bit definition for RCC_CFGR2 register ******************/
2185 
2186  #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F)
2187  #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001)
2188  #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002)
2189  #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004)
2190  #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008)
2192  #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000)
2193  #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001)
2194  #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002)
2195  #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003)
2196  #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004)
2197  #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005)
2198  #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006)
2199  #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007)
2200  #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008)
2201  #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009)
2202  #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A)
2203  #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B)
2204  #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C)
2205  #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D)
2206  #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E)
2207  #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F)
2210  #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0)
2211  #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010)
2212  #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020)
2213  #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040)
2214  #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080)
2216  #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000)
2217  #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010)
2218  #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020)
2219  #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030)
2220  #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040)
2221  #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050)
2222  #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060)
2223  #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070)
2224  #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080)
2225  #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090)
2226  #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0)
2227  #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0)
2228  #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0)
2229  #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0)
2230  #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0)
2231  #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0)
2234  #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00)
2235  #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100)
2236  #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200)
2237  #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400)
2238  #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800)
2240  #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600)
2241  #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700)
2242  #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800)
2243  #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900)
2244  #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00)
2245  #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00)
2246  #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00)
2247  #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00)
2248  #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00)
2251  #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000)
2252  #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000)
2253  #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000)
2254  #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000)
2255  #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000)
2257  #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000)
2258  #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000)
2259  #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000)
2260  #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000)
2261  #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000)
2262  #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000)
2263  #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000)
2264  #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000)
2265  #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000)
2267  #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000)
2268  #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000)
2269  #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000)
2270  #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000)
2271  #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000)
2272 #endif /* STM32F10X_CL */
2273 
2274 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
2275 /******************* Bit definition for RCC_CFGR2 register ******************/
2277  #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F)
2278  #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001)
2279  #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002)
2280  #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004)
2281  #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008)
2283  #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000)
2284  #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001)
2285  #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002)
2286  #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003)
2287  #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004)
2288  #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005)
2289  #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006)
2290  #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007)
2291  #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008)
2292  #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009)
2293  #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A)
2294  #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B)
2295  #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C)
2296  #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D)
2297  #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E)
2298  #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F)
2299 #endif
2300 
2301 /******************************************************************************/
2302 /* */
2303 /* General Purpose and Alternate Function I/O */
2304 /* */
2305 /******************************************************************************/
2306 
2307 /******************* Bit definition for GPIO_CRL register *******************/
2308 #define GPIO_CRL_MODE ((uint32_t)0x33333333)
2310 #define GPIO_CRL_MODE0 ((uint32_t)0x00000003)
2311 #define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001)
2312 #define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002)
2314 #define GPIO_CRL_MODE1 ((uint32_t)0x00000030)
2315 #define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010)
2316 #define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020)
2318 #define GPIO_CRL_MODE2 ((uint32_t)0x00000300)
2319 #define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100)
2320 #define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200)
2322 #define GPIO_CRL_MODE3 ((uint32_t)0x00003000)
2323 #define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000)
2324 #define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000)
2326 #define GPIO_CRL_MODE4 ((uint32_t)0x00030000)
2327 #define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000)
2328 #define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000)
2330 #define GPIO_CRL_MODE5 ((uint32_t)0x00300000)
2331 #define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000)
2332 #define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000)
2334 #define GPIO_CRL_MODE6 ((uint32_t)0x03000000)
2335 #define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000)
2336 #define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000)
2338 #define GPIO_CRL_MODE7 ((uint32_t)0x30000000)
2339 #define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000)
2340 #define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000)
2342 #define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC)
2344 #define GPIO_CRL_CNF0 ((uint32_t)0x0000000C)
2345 #define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004)
2346 #define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008)
2348 #define GPIO_CRL_CNF1 ((uint32_t)0x000000C0)
2349 #define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040)
2350 #define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080)
2352 #define GPIO_CRL_CNF2 ((uint32_t)0x00000C00)
2353 #define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400)
2354 #define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800)
2356 #define GPIO_CRL_CNF3 ((uint32_t)0x0000C000)
2357 #define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000)
2358 #define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000)
2360 #define GPIO_CRL_CNF4 ((uint32_t)0x000C0000)
2361 #define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000)
2362 #define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000)
2364 #define GPIO_CRL_CNF5 ((uint32_t)0x00C00000)
2365 #define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000)
2366 #define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000)
2368 #define GPIO_CRL_CNF6 ((uint32_t)0x0C000000)
2369 #define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000)
2370 #define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000)
2372 #define GPIO_CRL_CNF7 ((uint32_t)0xC0000000)
2373 #define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000)
2374 #define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000)
2376 /******************* Bit definition for GPIO_CRH register *******************/
2377 #define GPIO_CRH_MODE ((uint32_t)0x33333333)
2379 #define GPIO_CRH_MODE8 ((uint32_t)0x00000003)
2380 #define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001)
2381 #define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002)
2383 #define GPIO_CRH_MODE9 ((uint32_t)0x00000030)
2384 #define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010)
2385 #define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020)
2387 #define GPIO_CRH_MODE10 ((uint32_t)0x00000300)
2388 #define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100)
2389 #define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200)
2391 #define GPIO_CRH_MODE11 ((uint32_t)0x00003000)
2392 #define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000)
2393 #define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000)
2395 #define GPIO_CRH_MODE12 ((uint32_t)0x00030000)
2396 #define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000)
2397 #define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000)
2399 #define GPIO_CRH_MODE13 ((uint32_t)0x00300000)
2400 #define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000)
2401 #define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000)
2403 #define GPIO_CRH_MODE14 ((uint32_t)0x03000000)
2404 #define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000)
2405 #define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000)
2407 #define GPIO_CRH_MODE15 ((uint32_t)0x30000000)
2408 #define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000)
2409 #define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000)
2411 #define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC)
2413 #define GPIO_CRH_CNF8 ((uint32_t)0x0000000C)
2414 #define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004)
2415 #define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008)
2417 #define GPIO_CRH_CNF9 ((uint32_t)0x000000C0)
2418 #define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040)
2419 #define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080)
2421 #define GPIO_CRH_CNF10 ((uint32_t)0x00000C00)
2422 #define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400)
2423 #define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800)
2425 #define GPIO_CRH_CNF11 ((uint32_t)0x0000C000)
2426 #define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000)
2427 #define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000)
2429 #define GPIO_CRH_CNF12 ((uint32_t)0x000C0000)
2430 #define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000)
2431 #define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000)
2433 #define GPIO_CRH_CNF13 ((uint32_t)0x00C00000)
2434 #define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000)
2435 #define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000)
2437 #define GPIO_CRH_CNF14 ((uint32_t)0x0C000000)
2438 #define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000)
2439 #define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000)
2441 #define GPIO_CRH_CNF15 ((uint32_t)0xC0000000)
2442 #define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000)
2443 #define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000)
2446 #define GPIO_IDR_IDR0 ((uint16_t)0x0001)
2447 #define GPIO_IDR_IDR1 ((uint16_t)0x0002)
2448 #define GPIO_IDR_IDR2 ((uint16_t)0x0004)
2449 #define GPIO_IDR_IDR3 ((uint16_t)0x0008)
2450 #define GPIO_IDR_IDR4 ((uint16_t)0x0010)
2451 #define GPIO_IDR_IDR5 ((uint16_t)0x0020)
2452 #define GPIO_IDR_IDR6 ((uint16_t)0x0040)
2453 #define GPIO_IDR_IDR7 ((uint16_t)0x0080)
2454 #define GPIO_IDR_IDR8 ((uint16_t)0x0100)
2455 #define GPIO_IDR_IDR9 ((uint16_t)0x0200)
2456 #define GPIO_IDR_IDR10 ((uint16_t)0x0400)
2457 #define GPIO_IDR_IDR11 ((uint16_t)0x0800)
2458 #define GPIO_IDR_IDR12 ((uint16_t)0x1000)
2459 #define GPIO_IDR_IDR13 ((uint16_t)0x2000)
2460 #define GPIO_IDR_IDR14 ((uint16_t)0x4000)
2461 #define GPIO_IDR_IDR15 ((uint16_t)0x8000)
2463 /******************* Bit definition for GPIO_ODR register *******************/
2464 #define GPIO_ODR_ODR0 ((uint16_t)0x0001)
2465 #define GPIO_ODR_ODR1 ((uint16_t)0x0002)
2466 #define GPIO_ODR_ODR2 ((uint16_t)0x0004)
2467 #define GPIO_ODR_ODR3 ((uint16_t)0x0008)
2468 #define GPIO_ODR_ODR4 ((uint16_t)0x0010)
2469 #define GPIO_ODR_ODR5 ((uint16_t)0x0020)
2470 #define GPIO_ODR_ODR6 ((uint16_t)0x0040)
2471 #define GPIO_ODR_ODR7 ((uint16_t)0x0080)
2472 #define GPIO_ODR_ODR8 ((uint16_t)0x0100)
2473 #define GPIO_ODR_ODR9 ((uint16_t)0x0200)
2474 #define GPIO_ODR_ODR10 ((uint16_t)0x0400)
2475 #define GPIO_ODR_ODR11 ((uint16_t)0x0800)
2476 #define GPIO_ODR_ODR12 ((uint16_t)0x1000)
2477 #define GPIO_ODR_ODR13 ((uint16_t)0x2000)
2478 #define GPIO_ODR_ODR14 ((uint16_t)0x4000)
2479 #define GPIO_ODR_ODR15 ((uint16_t)0x8000)
2481 /****************** Bit definition for GPIO_BSRR register *******************/
2482 #define GPIO_BSRR_BS0 ((uint32_t)0x00000001)
2483 #define GPIO_BSRR_BS1 ((uint32_t)0x00000002)
2484 #define GPIO_BSRR_BS2 ((uint32_t)0x00000004)
2485 #define GPIO_BSRR_BS3 ((uint32_t)0x00000008)
2486 #define GPIO_BSRR_BS4 ((uint32_t)0x00000010)
2487 #define GPIO_BSRR_BS5 ((uint32_t)0x00000020)
2488 #define GPIO_BSRR_BS6 ((uint32_t)0x00000040)
2489 #define GPIO_BSRR_BS7 ((uint32_t)0x00000080)
2490 #define GPIO_BSRR_BS8 ((uint32_t)0x00000100)
2491 #define GPIO_BSRR_BS9 ((uint32_t)0x00000200)
2492 #define GPIO_BSRR_BS10 ((uint32_t)0x00000400)
2493 #define GPIO_BSRR_BS11 ((uint32_t)0x00000800)
2494 #define GPIO_BSRR_BS12 ((uint32_t)0x00001000)
2495 #define GPIO_BSRR_BS13 ((uint32_t)0x00002000)
2496 #define GPIO_BSRR_BS14 ((uint32_t)0x00004000)
2497 #define GPIO_BSRR_BS15 ((uint32_t)0x00008000)
2499 #define GPIO_BSRR_BR0 ((uint32_t)0x00010000)
2500 #define GPIO_BSRR_BR1 ((uint32_t)0x00020000)
2501 #define GPIO_BSRR_BR2 ((uint32_t)0x00040000)
2502 #define GPIO_BSRR_BR3 ((uint32_t)0x00080000)
2503 #define GPIO_BSRR_BR4 ((uint32_t)0x00100000)
2504 #define GPIO_BSRR_BR5 ((uint32_t)0x00200000)
2505 #define GPIO_BSRR_BR6 ((uint32_t)0x00400000)
2506 #define GPIO_BSRR_BR7 ((uint32_t)0x00800000)
2507 #define GPIO_BSRR_BR8 ((uint32_t)0x01000000)
2508 #define GPIO_BSRR_BR9 ((uint32_t)0x02000000)
2509 #define GPIO_BSRR_BR10 ((uint32_t)0x04000000)
2510 #define GPIO_BSRR_BR11 ((uint32_t)0x08000000)
2511 #define GPIO_BSRR_BR12 ((uint32_t)0x10000000)
2512 #define GPIO_BSRR_BR13 ((uint32_t)0x20000000)
2513 #define GPIO_BSRR_BR14 ((uint32_t)0x40000000)
2514 #define GPIO_BSRR_BR15 ((uint32_t)0x80000000)
2516 /******************* Bit definition for GPIO_BRR register *******************/
2517 #define GPIO_BRR_BR0 ((uint16_t)0x0001)
2518 #define GPIO_BRR_BR1 ((uint16_t)0x0002)
2519 #define GPIO_BRR_BR2 ((uint16_t)0x0004)
2520 #define GPIO_BRR_BR3 ((uint16_t)0x0008)
2521 #define GPIO_BRR_BR4 ((uint16_t)0x0010)
2522 #define GPIO_BRR_BR5 ((uint16_t)0x0020)
2523 #define GPIO_BRR_BR6 ((uint16_t)0x0040)
2524 #define GPIO_BRR_BR7 ((uint16_t)0x0080)
2525 #define GPIO_BRR_BR8 ((uint16_t)0x0100)
2526 #define GPIO_BRR_BR9 ((uint16_t)0x0200)
2527 #define GPIO_BRR_BR10 ((uint16_t)0x0400)
2528 #define GPIO_BRR_BR11 ((uint16_t)0x0800)
2529 #define GPIO_BRR_BR12 ((uint16_t)0x1000)
2530 #define GPIO_BRR_BR13 ((uint16_t)0x2000)
2531 #define GPIO_BRR_BR14 ((uint16_t)0x4000)
2532 #define GPIO_BRR_BR15 ((uint16_t)0x8000)
2534 /****************** Bit definition for GPIO_LCKR register *******************/
2535 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
2536 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
2537 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
2538 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
2539 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
2540 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
2541 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
2542 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
2543 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
2544 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
2545 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
2546 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
2547 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
2548 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
2549 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
2550 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
2551 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
2553 /*----------------------------------------------------------------------------*/
2554 
2555 /****************** Bit definition for AFIO_EVCR register *******************/
2556 #define AFIO_EVCR_PIN ((uint8_t)0x0F)
2557 #define AFIO_EVCR_PIN_0 ((uint8_t)0x01)
2558 #define AFIO_EVCR_PIN_1 ((uint8_t)0x02)
2559 #define AFIO_EVCR_PIN_2 ((uint8_t)0x04)
2560 #define AFIO_EVCR_PIN_3 ((uint8_t)0x08)
2563 #define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00)
2564 #define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01)
2565 #define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02)
2566 #define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03)
2567 #define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04)
2568 #define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05)
2569 #define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06)
2570 #define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07)
2571 #define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08)
2572 #define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09)
2573 #define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A)
2574 #define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B)
2575 #define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C)
2576 #define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D)
2577 #define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E)
2578 #define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F)
2580 #define AFIO_EVCR_PORT ((uint8_t)0x70)
2581 #define AFIO_EVCR_PORT_0 ((uint8_t)0x10)
2582 #define AFIO_EVCR_PORT_1 ((uint8_t)0x20)
2583 #define AFIO_EVCR_PORT_2 ((uint8_t)0x40)
2586 #define AFIO_EVCR_PORT_PA ((uint8_t)0x00)
2587 #define AFIO_EVCR_PORT_PB ((uint8_t)0x10)
2588 #define AFIO_EVCR_PORT_PC ((uint8_t)0x20)
2589 #define AFIO_EVCR_PORT_PD ((uint8_t)0x30)
2590 #define AFIO_EVCR_PORT_PE ((uint8_t)0x40)
2592 #define AFIO_EVCR_EVOE ((uint8_t)0x80)
2594 /****************** Bit definition for AFIO_MAPR register *******************/
2595 #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001)
2596 #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002)
2597 #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004)
2598 #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008)
2600 #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030)
2601 #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010)
2602 #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020)
2604 /* USART3_REMAP configuration */
2605 #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000)
2606 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010)
2607 #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030)
2609 #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0)
2610 #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040)
2611 #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080)
2614 #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000)
2615 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040)
2616 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0)
2618 #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300)
2619 #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100)
2620 #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200)
2623 #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000)
2624 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100)
2625 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200)
2626 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300)
2628 #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00)
2629 #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400)
2630 #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800)
2633 #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000)
2634 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800)
2635 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00)
2637 #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000)
2639 #define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000)
2640 #define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000)
2641 #define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000)
2644 #define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000)
2645 #define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000)
2646 #define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000)
2648 #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000)
2649 #define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000)
2650 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000)
2651 #define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000)
2652 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000)
2653 #define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000)
2656 #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000)
2657 #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000)
2658 #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000)
2659 #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000)
2661 #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000)
2662 #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000)
2663 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000)
2664 #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000)
2666 #ifdef STM32F10X_CL
2667 
2668  #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000)
2671  #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000)
2674  #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000)
2677  #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000)
2680  #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000)
2683  #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000)
2684 #endif
2685 
2686 /***************** Bit definition for AFIO_EXTICR1 register *****************/
2687 #define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F)
2688 #define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0)
2689 #define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00)
2690 #define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000)
2693 #define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000)
2694 #define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001)
2695 #define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002)
2696 #define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003)
2697 #define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004)
2698 #define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005)
2699 #define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006)
2702 #define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000)
2703 #define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010)
2704 #define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020)
2705 #define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030)
2706 #define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040)
2707 #define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050)
2708 #define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060)
2711 #define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000)
2712 #define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100)
2713 #define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200)
2714 #define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300)
2715 #define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400)
2716 #define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500)
2717 #define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600)
2720 #define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000)
2721 #define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000)
2722 #define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000)
2723 #define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000)
2724 #define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000)
2725 #define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000)
2726 #define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000)
2728 /***************** Bit definition for AFIO_EXTICR2 register *****************/
2729 #define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F)
2730 #define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0)
2731 #define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00)
2732 #define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000)
2735 #define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000)
2736 #define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001)
2737 #define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002)
2738 #define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003)
2739 #define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004)
2740 #define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005)
2741 #define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006)
2743 /* EXTI5 configuration */
2744 #define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000)
2745 #define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010)
2746 #define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020)
2747 #define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030)
2748 #define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040)
2749 #define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050)
2750 #define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060)
2753 #define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000)
2754 #define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100)
2755 #define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200)
2756 #define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300)
2757 #define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400)
2758 #define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500)
2759 #define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600)
2762 #define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000)
2763 #define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000)
2764 #define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000)
2765 #define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000)
2766 #define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000)
2767 #define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000)
2768 #define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000)
2770 /***************** Bit definition for AFIO_EXTICR3 register *****************/
2771 #define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F)
2772 #define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0)
2773 #define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00)
2774 #define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000)
2777 #define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000)
2778 #define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001)
2779 #define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002)
2780 #define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003)
2781 #define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004)
2782 #define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005)
2783 #define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006)
2786 #define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000)
2787 #define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010)
2788 #define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020)
2789 #define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030)
2790 #define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040)
2791 #define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050)
2792 #define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060)
2795 #define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000)
2796 #define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100)
2797 #define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200)
2798 #define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300)
2799 #define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400)
2800 #define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500)
2801 #define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600)
2804 #define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000)
2805 #define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000)
2806 #define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000)
2807 #define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000)
2808 #define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000)
2809 #define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000)
2810 #define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000)
2812 /***************** Bit definition for AFIO_EXTICR4 register *****************/
2813 #define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F)
2814 #define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0)
2815 #define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00)
2816 #define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000)
2818 /* EXTI12 configuration */
2819 #define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000)
2820 #define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001)
2821 #define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002)
2822 #define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003)
2823 #define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004)
2824 #define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005)
2825 #define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006)
2827 /* EXTI13 configuration */
2828 #define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000)
2829 #define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010)
2830 #define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020)
2831 #define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030)
2832 #define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040)
2833 #define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050)
2834 #define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060)
2837 #define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000)
2838 #define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100)
2839 #define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200)
2840 #define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300)
2841 #define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400)
2842 #define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500)
2843 #define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600)
2846 #define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000)
2847 #define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000)
2848 #define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000)
2849 #define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000)
2850 #define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000)
2851 #define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000)
2852 #define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000)
2854 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
2855 /****************** Bit definition for AFIO_MAPR2 register ******************/
2856 #define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001)
2857 #define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002)
2858 #define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004)
2859 #define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008)
2860 #define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010)
2861 #endif
2862 
2863 #ifdef STM32F10X_HD_VL
2864 #define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100)
2865 #define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200)
2866 #define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400)
2867 #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800)
2868 #define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000)
2869 #define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000)
2870 #endif
2871 
2872 #ifdef STM32F10X_XL
2873 /****************** Bit definition for AFIO_MAPR2 register ******************/
2874 #define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020)
2875 #define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040)
2876 #define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080)
2877 #define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100)
2878 #define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200)
2879 #define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400)
2880 #endif
2881 
2882 /******************************************************************************/
2883 /* */
2884 /* SystemTick */
2885 /* */
2886 /******************************************************************************/
2887 
2888 /***************** Bit definition for SysTick_CTRL register *****************/
2889 #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001)
2890 #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002)
2891 #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004)
2892 #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000)
2894 /***************** Bit definition for SysTick_LOAD register *****************/
2895 #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF)
2897 /***************** Bit definition for SysTick_VAL register ******************/
2898 #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF)
2900 /***************** Bit definition for SysTick_CALIB register ****************/
2901 #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF)
2902 #define SysTick_CALIB_SKEW ((uint32_t)0x40000000)
2903 #define SysTick_CALIB_NOREF ((uint32_t)0x80000000)
2905 /******************************************************************************/
2906 /* */
2907 /* Nested Vectored Interrupt Controller */
2908 /* */
2909 /******************************************************************************/
2910 
2911 /****************** Bit definition for NVIC_ISER register *******************/
2912 #define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF)
2913 #define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001)
2914 #define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002)
2915 #define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004)
2916 #define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008)
2917 #define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010)
2918 #define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020)
2919 #define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040)
2920 #define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080)
2921 #define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100)
2922 #define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200)
2923 #define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400)
2924 #define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800)
2925 #define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000)
2926 #define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000)
2927 #define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000)
2928 #define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000)
2929 #define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000)
2930 #define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000)
2931 #define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000)
2932 #define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000)
2933 #define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000)
2934 #define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000)
2935 #define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000)
2936 #define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000)
2937 #define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000)
2938 #define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000)
2939 #define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000)
2940 #define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000)
2941 #define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000)
2942 #define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000)
2943 #define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000)
2944 #define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000)
2946 /****************** Bit definition for NVIC_ICER register *******************/
2947 #define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF)
2948 #define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001)
2949 #define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002)
2950 #define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004)
2951 #define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008)
2952 #define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010)
2953 #define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020)
2954 #define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040)
2955 #define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080)
2956 #define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100)
2957 #define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200)
2958 #define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400)
2959 #define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800)
2960 #define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000)
2961 #define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000)
2962 #define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000)
2963 #define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000)
2964 #define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000)
2965 #define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000)
2966 #define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000)
2967 #define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000)
2968 #define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000)
2969 #define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000)
2970 #define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000)
2971 #define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000)
2972 #define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000)
2973 #define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000)
2974 #define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000)
2975 #define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000)
2976 #define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000)
2977 #define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000)
2978 #define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000)
2979 #define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000)
2981 /****************** Bit definition for NVIC_ISPR register *******************/
2982 #define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF)
2983 #define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001)
2984 #define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002)
2985 #define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004)
2986 #define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008)
2987 #define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010)
2988 #define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020)
2989 #define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040)
2990 #define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080)
2991 #define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100)
2992 #define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200)
2993 #define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400)
2994 #define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800)
2995 #define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000)
2996 #define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000)
2997 #define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000)
2998 #define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000)
2999 #define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000)
3000 #define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000)
3001 #define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000)
3002 #define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000)
3003 #define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000)
3004 #define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000)
3005 #define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000)
3006 #define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000)
3007 #define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000)
3008 #define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000)
3009 #define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000)
3010 #define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000)
3011 #define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000)
3012 #define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000)
3013 #define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000)
3014 #define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000)
3016 /****************** Bit definition for NVIC_ICPR register *******************/
3017 #define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF)
3018 #define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001)
3019 #define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002)
3020 #define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004)
3021 #define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008)
3022 #define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010)
3023 #define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020)
3024 #define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040)
3025 #define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080)
3026 #define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100)
3027 #define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200)
3028 #define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400)
3029 #define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800)
3030 #define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000)
3031 #define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000)
3032 #define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000)
3033 #define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000)
3034 #define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000)
3035 #define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000)
3036 #define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000)
3037 #define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000)
3038 #define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000)
3039 #define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000)
3040 #define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000)
3041 #define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000)
3042 #define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000)
3043 #define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000)
3044 #define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000)
3045 #define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000)
3046 #define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000)
3047 #define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000)
3048 #define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000)
3049 #define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000)
3051 /****************** Bit definition for NVIC_IABR register *******************/
3052 #define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF)
3053 #define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001)
3054 #define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002)
3055 #define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004)
3056 #define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008)
3057 #define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010)
3058 #define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020)
3059 #define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040)
3060 #define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080)
3061 #define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100)
3062 #define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200)
3063 #define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400)
3064 #define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800)
3065 #define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000)
3066 #define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000)
3067 #define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000)
3068 #define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000)
3069 #define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000)
3070 #define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000)
3071 #define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000)
3072 #define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000)
3073 #define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000)
3074 #define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000)
3075 #define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000)
3076 #define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000)
3077 #define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000)
3078 #define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000)
3079 #define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000)
3080 #define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000)
3081 #define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000)
3082 #define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000)
3083 #define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000)
3084 #define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000)
3086 /****************** Bit definition for NVIC_PRI0 register *******************/
3087 #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF)
3088 #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00)
3089 #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000)
3090 #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000)
3092 /****************** Bit definition for NVIC_PRI1 register *******************/
3093 #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF)
3094 #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00)
3095 #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000)
3096 #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000)
3098 /****************** Bit definition for NVIC_PRI2 register *******************/
3099 #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF)
3100 #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00)
3101 #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000)
3102 #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000)
3104 /****************** Bit definition for NVIC_PRI3 register *******************/
3105 #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF)
3106 #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00)
3107 #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000)
3108 #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000)
3110 /****************** Bit definition for NVIC_PRI4 register *******************/
3111 #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF)
3112 #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00)
3113 #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000)
3114 #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000)
3116 /****************** Bit definition for NVIC_PRI5 register *******************/
3117 #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF)
3118 #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00)
3119 #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000)
3120 #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000)
3122 /****************** Bit definition for NVIC_PRI6 register *******************/
3123 #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF)
3124 #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00)
3125 #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000)
3126 #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000)
3128 /****************** Bit definition for NVIC_PRI7 register *******************/
3129 #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF)
3130 #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00)
3131 #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000)
3132 #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000)
3134 /****************** Bit definition for SCB_CPUID register *******************/
3135 #define SCB_CPUID_REVISION ((uint32_t)0x0000000F)
3136 #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0)
3137 #define SCB_CPUID_Constant ((uint32_t)0x000F0000)
3138 #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000)
3139 #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000)
3141 /******************* Bit definition for SCB_ICSR register *******************/
3142 #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF)
3143 #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800)
3144 #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000)
3145 #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000)
3146 #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000)
3147 #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000)
3148 #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000)
3149 #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000)
3150 #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000)
3151 #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000)
3153 /******************* Bit definition for SCB_VTOR register *******************/
3154 #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80)
3155 #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000)
3158 #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001)
3159 #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002)
3160 #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004)
3162 #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700)
3163 #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100)
3164 #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200)
3165 #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400)
3167 /* prority group configuration */
3168 #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000)
3169 #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100)
3170 #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200)
3171 #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300)
3172 #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400)
3173 #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500)
3174 #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600)
3175 #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700)
3177 #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000)
3178 #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000)
3180 /******************* Bit definition for SCB_SCR register ********************/
3181 #define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02)
3182 #define SCB_SCR_SLEEPDEEP ((uint8_t)0x04)
3183 #define SCB_SCR_SEVONPEND ((uint8_t)0x10)
3185 /******************** Bit definition for SCB_CCR register *******************/
3186 #define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001)
3187 #define SCB_CCR_USERSETMPEND ((uint16_t)0x0002)
3188 #define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008)
3189 #define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010)
3190 #define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100)
3191 #define SCB_CCR_STKALIGN ((uint16_t)0x0200)
3193 /******************* Bit definition for SCB_SHPR register ********************/
3194 #define SCB_SHPR_PRI_N ((uint32_t)0x000000FF)
3195 #define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00)
3196 #define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000)
3197 #define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000)
3199 /****************** Bit definition for SCB_SHCSR register *******************/
3200 #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001)
3201 #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002)
3202 #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008)
3203 #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080)
3204 #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100)
3205 #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400)
3206 #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800)
3207 #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000)
3208 #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000)
3209 #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000)
3210 #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000)
3211 #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000)
3212 #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000)
3213 #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000)
3215 /******************* Bit definition for SCB_CFSR register *******************/
3216 
3217 #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001)
3218 #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002)
3219 #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008)
3220 #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010)
3221 #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080)
3223 #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100)
3224 #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200)
3225 #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400)
3226 #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800)
3227 #define SCB_CFSR_STKERR ((uint32_t)0x00001000)
3228 #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000)
3230 #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000)
3231 #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000)
3232 #define SCB_CFSR_INVPC ((uint32_t)0x00040000)
3233 #define SCB_CFSR_NOCP ((uint32_t)0x00080000)
3234 #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000)
3235 #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000)
3237 /******************* Bit definition for SCB_HFSR register *******************/
3238 #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002)
3239 #define SCB_HFSR_FORCED ((uint32_t)0x40000000)
3240 #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000)
3242 /******************* Bit definition for SCB_DFSR register *******************/
3243 #define SCB_DFSR_HALTED ((uint8_t)0x01)
3244 #define SCB_DFSR_BKPT ((uint8_t)0x02)
3245 #define SCB_DFSR_DWTTRAP ((uint8_t)0x04)
3246 #define SCB_DFSR_VCATCH ((uint8_t)0x08)
3247 #define SCB_DFSR_EXTERNAL ((uint8_t)0x10)
3249 /******************* Bit definition for SCB_MMFAR register ******************/
3250 #define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF)
3252 /******************* Bit definition for SCB_BFAR register *******************/
3253 #define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF)
3255 /******************* Bit definition for SCB_afsr register *******************/
3256 #define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF)
3258 /******************************************************************************/
3259 /* */
3260 /* External Interrupt/Event Controller */
3261 /* */
3262 /******************************************************************************/
3263 
3264 /******************* Bit definition for EXTI_IMR register *******************/
3265 #define EXTI_IMR_MR0 ((uint32_t)0x00000001)
3266 #define EXTI_IMR_MR1 ((uint32_t)0x00000002)
3267 #define EXTI_IMR_MR2 ((uint32_t)0x00000004)
3268 #define EXTI_IMR_MR3 ((uint32_t)0x00000008)
3269 #define EXTI_IMR_MR4 ((uint32_t)0x00000010)
3270 #define EXTI_IMR_MR5 ((uint32_t)0x00000020)
3271 #define EXTI_IMR_MR6 ((uint32_t)0x00000040)
3272 #define EXTI_IMR_MR7 ((uint32_t)0x00000080)
3273 #define EXTI_IMR_MR8 ((uint32_t)0x00000100)
3274 #define EXTI_IMR_MR9 ((uint32_t)0x00000200)
3275 #define EXTI_IMR_MR10 ((uint32_t)0x00000400)
3276 #define EXTI_IMR_MR11 ((uint32_t)0x00000800)
3277 #define EXTI_IMR_MR12 ((uint32_t)0x00001000)
3278 #define EXTI_IMR_MR13 ((uint32_t)0x00002000)
3279 #define EXTI_IMR_MR14 ((uint32_t)0x00004000)
3280 #define EXTI_IMR_MR15 ((uint32_t)0x00008000)
3281 #define EXTI_IMR_MR16 ((uint32_t)0x00010000)
3282 #define EXTI_IMR_MR17 ((uint32_t)0x00020000)
3283 #define EXTI_IMR_MR18 ((uint32_t)0x00040000)
3284 #define EXTI_IMR_MR19 ((uint32_t)0x00080000)
3286 /******************* Bit definition for EXTI_EMR register *******************/
3287 #define EXTI_EMR_MR0 ((uint32_t)0x00000001)
3288 #define EXTI_EMR_MR1 ((uint32_t)0x00000002)
3289 #define EXTI_EMR_MR2 ((uint32_t)0x00000004)
3290 #define EXTI_EMR_MR3 ((uint32_t)0x00000008)
3291 #define EXTI_EMR_MR4 ((uint32_t)0x00000010)
3292 #define EXTI_EMR_MR5 ((uint32_t)0x00000020)
3293 #define EXTI_EMR_MR6 ((uint32_t)0x00000040)
3294 #define EXTI_EMR_MR7 ((uint32_t)0x00000080)
3295 #define EXTI_EMR_MR8 ((uint32_t)0x00000100)
3296 #define EXTI_EMR_MR9 ((uint32_t)0x00000200)
3297 #define EXTI_EMR_MR10 ((uint32_t)0x00000400)
3298 #define EXTI_EMR_MR11 ((uint32_t)0x00000800)
3299 #define EXTI_EMR_MR12 ((uint32_t)0x00001000)
3300 #define EXTI_EMR_MR13 ((uint32_t)0x00002000)
3301 #define EXTI_EMR_MR14 ((uint32_t)0x00004000)
3302 #define EXTI_EMR_MR15 ((uint32_t)0x00008000)
3303 #define EXTI_EMR_MR16 ((uint32_t)0x00010000)
3304 #define EXTI_EMR_MR17 ((uint32_t)0x00020000)
3305 #define EXTI_EMR_MR18 ((uint32_t)0x00040000)
3306 #define EXTI_EMR_MR19 ((uint32_t)0x00080000)
3308 /****************** Bit definition for EXTI_RTSR register *******************/
3309 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001)
3310 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002)
3311 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004)
3312 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008)
3313 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010)
3314 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020)
3315 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040)
3316 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080)
3317 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100)
3318 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200)
3319 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400)
3320 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800)
3321 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000)
3322 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000)
3323 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000)
3324 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000)
3325 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000)
3326 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000)
3327 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000)
3328 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000)
3330 /****************** Bit definition for EXTI_FTSR register *******************/
3331 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001)
3332 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002)
3333 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004)
3334 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008)
3335 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010)
3336 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020)
3337 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040)
3338 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080)
3339 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100)
3340 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200)
3341 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400)
3342 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800)
3343 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000)
3344 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000)
3345 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000)
3346 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000)
3347 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000)
3348 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000)
3349 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000)
3350 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000)
3352 /****************** Bit definition for EXTI_SWIER register ******************/
3353 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001)
3354 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002)
3355 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004)
3356 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008)
3357 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010)
3358 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020)
3359 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040)
3360 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080)
3361 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100)
3362 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200)
3363 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400)
3364 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800)
3365 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000)
3366 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000)
3367 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000)
3368 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000)
3369 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000)
3370 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000)
3371 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000)
3372 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000)
3374 /******************* Bit definition for EXTI_PR register ********************/
3375 #define EXTI_PR_PR0 ((uint32_t)0x00000001)
3376 #define EXTI_PR_PR1 ((uint32_t)0x00000002)
3377 #define EXTI_PR_PR2 ((uint32_t)0x00000004)
3378 #define EXTI_PR_PR3 ((uint32_t)0x00000008)
3379 #define EXTI_PR_PR4 ((uint32_t)0x00000010)
3380 #define EXTI_PR_PR5 ((uint32_t)0x00000020)
3381 #define EXTI_PR_PR6 ((uint32_t)0x00000040)
3382 #define EXTI_PR_PR7 ((uint32_t)0x00000080)
3383 #define EXTI_PR_PR8 ((uint32_t)0x00000100)
3384 #define EXTI_PR_PR9 ((uint32_t)0x00000200)
3385 #define EXTI_PR_PR10 ((uint32_t)0x00000400)
3386 #define EXTI_PR_PR11 ((uint32_t)0x00000800)
3387 #define EXTI_PR_PR12 ((uint32_t)0x00001000)
3388 #define EXTI_PR_PR13 ((uint32_t)0x00002000)
3389 #define EXTI_PR_PR14 ((uint32_t)0x00004000)
3390 #define EXTI_PR_PR15 ((uint32_t)0x00008000)
3391 #define EXTI_PR_PR16 ((uint32_t)0x00010000)
3392 #define EXTI_PR_PR17 ((uint32_t)0x00020000)
3393 #define EXTI_PR_PR18 ((uint32_t)0x00040000)
3394 #define EXTI_PR_PR19 ((uint32_t)0x00080000)
3396 /******************************************************************************/
3397 /* */
3398 /* DMA Controller */
3399 /* */
3400 /******************************************************************************/
3401 
3402 /******************* Bit definition for DMA_ISR register ********************/
3403 #define DMA_ISR_GIF1 ((uint32_t)0x00000001)
3404 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002)
3405 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004)
3406 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008)
3407 #define DMA_ISR_GIF2 ((uint32_t)0x00000010)
3408 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020)
3409 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040)
3410 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080)
3411 #define DMA_ISR_GIF3 ((uint32_t)0x00000100)
3412 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200)
3413 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400)
3414 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800)
3415 #define DMA_ISR_GIF4 ((uint32_t)0x00001000)
3416 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000)
3417 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000)
3418 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000)
3419 #define DMA_ISR_GIF5 ((uint32_t)0x00010000)
3420 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000)
3421 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000)
3422 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000)
3423 #define DMA_ISR_GIF6 ((uint32_t)0x00100000)
3424 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000)
3425 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000)
3426 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000)
3427 #define DMA_ISR_GIF7 ((uint32_t)0x01000000)
3428 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000)
3429 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000)
3430 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000)
3432 /******************* Bit definition for DMA_IFCR register *******************/
3433 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001)
3434 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002)
3435 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004)
3436 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008)
3437 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010)
3438 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020)
3439 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040)
3440 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080)
3441 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100)
3442 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200)
3443 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400)
3444 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800)
3445 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000)
3446 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000)
3447 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000)
3448 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000)
3449 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000)
3450 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000)
3451 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000)
3452 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000)
3453 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000)
3454 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000)
3455 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000)
3456 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000)
3457 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000)
3458 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000)
3459 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000)
3460 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000)
3462 /******************* Bit definition for DMA_CCR1 register *******************/
3463 #define DMA_CCR1_EN ((uint16_t)0x0001)
3464 #define DMA_CCR1_TCIE ((uint16_t)0x0002)
3465 #define DMA_CCR1_HTIE ((uint16_t)0x0004)
3466 #define DMA_CCR1_TEIE ((uint16_t)0x0008)
3467 #define DMA_CCR1_DIR ((uint16_t)0x0010)
3468 #define DMA_CCR1_CIRC ((uint16_t)0x0020)
3469 #define DMA_CCR1_PINC ((uint16_t)0x0040)
3470 #define DMA_CCR1_MINC ((uint16_t)0x0080)
3472 #define DMA_CCR1_PSIZE ((uint16_t)0x0300)
3473 #define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100)
3474 #define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200)
3476 #define DMA_CCR1_MSIZE ((uint16_t)0x0C00)
3477 #define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400)
3478 #define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800)
3480 #define DMA_CCR1_PL ((uint16_t)0x3000)
3481 #define DMA_CCR1_PL_0 ((uint16_t)0x1000)
3482 #define DMA_CCR1_PL_1 ((uint16_t)0x2000)
3484 #define DMA_CCR1_MEM2MEM ((uint16_t)0x4000)
3486 /******************* Bit definition for DMA_CCR2 register *******************/
3487 #define DMA_CCR2_EN ((uint16_t)0x0001)
3488 #define DMA_CCR2_TCIE ((uint16_t)0x0002)
3489 #define DMA_CCR2_HTIE ((uint16_t)0x0004)
3490 #define DMA_CCR2_TEIE ((uint16_t)0x0008)
3491 #define DMA_CCR2_DIR ((uint16_t)0x0010)
3492 #define DMA_CCR2_CIRC ((uint16_t)0x0020)
3493 #define DMA_CCR2_PINC ((uint16_t)0x0040)
3494 #define DMA_CCR2_MINC ((uint16_t)0x0080)
3496 #define DMA_CCR2_PSIZE ((uint16_t)0x0300)
3497 #define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100)
3498 #define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200)
3500 #define DMA_CCR2_MSIZE ((uint16_t)0x0C00)
3501 #define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400)
3502 #define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800)
3504 #define DMA_CCR2_PL ((uint16_t)0x3000)
3505 #define DMA_CCR2_PL_0 ((uint16_t)0x1000)
3506 #define DMA_CCR2_PL_1 ((uint16_t)0x2000)
3508 #define DMA_CCR2_MEM2MEM ((uint16_t)0x4000)
3510 /******************* Bit definition for DMA_CCR3 register *******************/
3511 #define DMA_CCR3_EN ((uint16_t)0x0001)
3512 #define DMA_CCR3_TCIE ((uint16_t)0x0002)
3513 #define DMA_CCR3_HTIE ((uint16_t)0x0004)
3514 #define DMA_CCR3_TEIE ((uint16_t)0x0008)
3515 #define DMA_CCR3_DIR ((uint16_t)0x0010)
3516 #define DMA_CCR3_CIRC ((uint16_t)0x0020)
3517 #define DMA_CCR3_PINC ((uint16_t)0x0040)
3518 #define DMA_CCR3_MINC ((uint16_t)0x0080)
3520 #define DMA_CCR3_PSIZE ((uint16_t)0x0300)
3521 #define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100)
3522 #define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200)
3524 #define DMA_CCR3_MSIZE ((uint16_t)0x0C00)
3525 #define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400)
3526 #define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800)
3528 #define DMA_CCR3_PL ((uint16_t)0x3000)
3529 #define DMA_CCR3_PL_0 ((uint16_t)0x1000)
3530 #define DMA_CCR3_PL_1 ((uint16_t)0x2000)
3532 #define DMA_CCR3_MEM2MEM ((uint16_t)0x4000)
3535 #define DMA_CCR4_EN ((uint16_t)0x0001)
3536 #define DMA_CCR4_TCIE ((uint16_t)0x0002)
3537 #define DMA_CCR4_HTIE ((uint16_t)0x0004)
3538 #define DMA_CCR4_TEIE ((uint16_t)0x0008)
3539 #define DMA_CCR4_DIR ((uint16_t)0x0010)
3540 #define DMA_CCR4_CIRC ((uint16_t)0x0020)
3541 #define DMA_CCR4_PINC ((uint16_t)0x0040)
3542 #define DMA_CCR4_MINC ((uint16_t)0x0080)
3544 #define DMA_CCR4_PSIZE ((uint16_t)0x0300)
3545 #define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100)
3546 #define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200)
3548 #define DMA_CCR4_MSIZE ((uint16_t)0x0C00)
3549 #define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400)
3550 #define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800)
3552 #define DMA_CCR4_PL ((uint16_t)0x3000)
3553 #define DMA_CCR4_PL_0 ((uint16_t)0x1000)
3554 #define DMA_CCR4_PL_1 ((uint16_t)0x2000)
3556 #define DMA_CCR4_MEM2MEM ((uint16_t)0x4000)
3558 /****************** Bit definition for DMA_CCR5 register *******************/
3559 #define DMA_CCR5_EN ((uint16_t)0x0001)
3560 #define DMA_CCR5_TCIE ((uint16_t)0x0002)
3561 #define DMA_CCR5_HTIE ((uint16_t)0x0004)
3562 #define DMA_CCR5_TEIE ((uint16_t)0x0008)
3563 #define DMA_CCR5_DIR ((uint16_t)0x0010)
3564 #define DMA_CCR5_CIRC ((uint16_t)0x0020)
3565 #define DMA_CCR5_PINC ((uint16_t)0x0040)
3566 #define DMA_CCR5_MINC ((uint16_t)0x0080)
3568 #define DMA_CCR5_PSIZE ((uint16_t)0x0300)
3569 #define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100)
3570 #define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200)
3572 #define DMA_CCR5_MSIZE ((uint16_t)0x0C00)
3573 #define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400)
3574 #define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800)
3576 #define DMA_CCR5_PL ((uint16_t)0x3000)
3577 #define DMA_CCR5_PL_0 ((uint16_t)0x1000)
3578 #define DMA_CCR5_PL_1 ((uint16_t)0x2000)
3580 #define DMA_CCR5_MEM2MEM ((uint16_t)0x4000)
3582 /******************* Bit definition for DMA_CCR6 register *******************/
3583 #define DMA_CCR6_EN ((uint16_t)0x0001)
3584 #define DMA_CCR6_TCIE ((uint16_t)0x0002)
3585 #define DMA_CCR6_HTIE ((uint16_t)0x0004)
3586 #define DMA_CCR6_TEIE ((uint16_t)0x0008)
3587 #define DMA_CCR6_DIR ((uint16_t)0x0010)
3588 #define DMA_CCR6_CIRC ((uint16_t)0x0020)
3589 #define DMA_CCR6_PINC ((uint16_t)0x0040)
3590 #define DMA_CCR6_MINC ((uint16_t)0x0080)
3592 #define DMA_CCR6_PSIZE ((uint16_t)0x0300)
3593 #define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100)
3594 #define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200)
3596 #define DMA_CCR6_MSIZE ((uint16_t)0x0C00)
3597 #define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400)
3598 #define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800)
3600 #define DMA_CCR6_PL ((uint16_t)0x3000)
3601 #define DMA_CCR6_PL_0 ((uint16_t)0x1000)
3602 #define DMA_CCR6_PL_1 ((uint16_t)0x2000)
3604 #define DMA_CCR6_MEM2MEM ((uint16_t)0x4000)
3606 /******************* Bit definition for DMA_CCR7 register *******************/
3607 #define DMA_CCR7_EN ((uint16_t)0x0001)
3608 #define DMA_CCR7_TCIE ((uint16_t)0x0002)
3609 #define DMA_CCR7_HTIE ((uint16_t)0x0004)
3610 #define DMA_CCR7_TEIE ((uint16_t)0x0008)
3611 #define DMA_CCR7_DIR ((uint16_t)0x0010)
3612 #define DMA_CCR7_CIRC ((uint16_t)0x0020)
3613 #define DMA_CCR7_PINC ((uint16_t)0x0040)
3614 #define DMA_CCR7_MINC ((uint16_t)0x0080)
3616 #define DMA_CCR7_PSIZE , ((uint16_t)0x0300)
3617 #define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100)
3618 #define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200)
3620 #define DMA_CCR7_MSIZE ((uint16_t)0x0C00)
3621 #define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400)
3622 #define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800)
3624 #define DMA_CCR7_PL ((uint16_t)0x3000)
3625 #define DMA_CCR7_PL_0 ((uint16_t)0x1000)
3626 #define DMA_CCR7_PL_1 ((uint16_t)0x2000)
3628 #define DMA_CCR7_MEM2MEM ((uint16_t)0x4000)
3630 /****************** Bit definition for DMA_CNDTR1 register ******************/
3631 #define DMA_CNDTR1_NDT ((uint16_t)0xFFFF)
3633 /****************** Bit definition for DMA_CNDTR2 register ******************/
3634 #define DMA_CNDTR2_NDT ((uint16_t)0xFFFF)
3636 /****************** Bit definition for DMA_CNDTR3 register ******************/
3637 #define DMA_CNDTR3_NDT ((uint16_t)0xFFFF)
3639 /****************** Bit definition for DMA_CNDTR4 register ******************/
3640 #define DMA_CNDTR4_NDT ((uint16_t)0xFFFF)
3642 /****************** Bit definition for DMA_CNDTR5 register ******************/
3643 #define DMA_CNDTR5_NDT ((uint16_t)0xFFFF)
3645 /****************** Bit definition for DMA_CNDTR6 register ******************/
3646 #define DMA_CNDTR6_NDT ((uint16_t)0xFFFF)
3648 /****************** Bit definition for DMA_CNDTR7 register ******************/
3649 #define DMA_CNDTR7_NDT ((uint16_t)0xFFFF)
3651 /****************** Bit definition for DMA_CPAR1 register *******************/
3652 #define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF)
3654 /****************** Bit definition for DMA_CPAR2 register *******************/
3655 #define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF)
3657 /****************** Bit definition for DMA_CPAR3 register *******************/
3658 #define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF)
3661 /****************** Bit definition for DMA_CPAR4 register *******************/
3662 #define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF)
3664 /****************** Bit definition for DMA_CPAR5 register *******************/
3665 #define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF)
3667 /****************** Bit definition for DMA_CPAR6 register *******************/
3668 #define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF)
3671 /****************** Bit definition for DMA_CPAR7 register *******************/
3672 #define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF)
3674 /****************** Bit definition for DMA_CMAR1 register *******************/
3675 #define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF)
3677 /****************** Bit definition for DMA_CMAR2 register *******************/
3678 #define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF)
3680 /****************** Bit definition for DMA_CMAR3 register *******************/
3681 #define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF)
3684 /****************** Bit definition for DMA_CMAR4 register *******************/
3685 #define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF)
3687 /****************** Bit definition for DMA_CMAR5 register *******************/
3688 #define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF)
3690 /****************** Bit definition for DMA_CMAR6 register *******************/
3691 #define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF)
3693 /****************** Bit definition for DMA_CMAR7 register *******************/
3694 #define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF)
3696 /******************************************************************************/
3697 /* */
3698 /* Analog to Digital Converter */
3699 /* */
3700 /******************************************************************************/
3701 
3702 /******************** Bit definition for ADC_SR register ********************/
3703 #define ADC_SR_AWD ((uint8_t)0x01)
3704 #define ADC_SR_EOC ((uint8_t)0x02)
3705 #define ADC_SR_JEOC ((uint8_t)0x04)
3706 #define ADC_SR_JSTRT ((uint8_t)0x08)
3707 #define ADC_SR_STRT ((uint8_t)0x10)
3709 /******************* Bit definition for ADC_CR1 register ********************/
3710 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F)
3711 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001)
3712 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002)
3713 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004)
3714 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008)
3715 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010)
3717 #define ADC_CR1_EOCIE ((uint32_t)0x00000020)
3718 #define ADC_CR1_AWDIE ((uint32_t)0x00000040)
3719 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080)
3720 #define ADC_CR1_SCAN ((uint32_t)0x00000100)
3721 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200)
3722 #define ADC_CR1_JAUTO ((uint32_t)0x00000400)
3723 #define ADC_CR1_DISCEN ((uint32_t)0x00000800)
3724 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000)
3726 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000)
3727 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000)
3728 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000)
3729 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000)
3731 #define ADC_CR1_DUALMOD ((uint32_t)0x000F0000)
3732 #define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000)
3733 #define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000)
3734 #define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000)
3735 #define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000)
3737 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000)
3738 #define ADC_CR1_AWDEN ((uint32_t)0x00800000)
3741 /******************* Bit definition for ADC_CR2 register ********************/
3742 #define ADC_CR2_ADON ((uint32_t)0x00000001)
3743 #define ADC_CR2_CONT ((uint32_t)0x00000002)
3744 #define ADC_CR2_CAL ((uint32_t)0x00000004)
3745 #define ADC_CR2_RSTCAL ((uint32_t)0x00000008)
3746 #define ADC_CR2_DMA ((uint32_t)0x00000100)
3747 #define ADC_CR2_ALIGN ((uint32_t)0x00000800)
3749 #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000)
3750 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000)
3751 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000)
3752 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000)
3754 #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000)
3756 #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000)
3757 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000)
3758 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000)
3759 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000)
3761 #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000)
3762 #define ADC_CR2_JSWSTART ((uint32_t)0x00200000)
3763 #define ADC_CR2_SWSTART ((uint32_t)0x00400000)
3764 #define ADC_CR2_TSVREFE ((uint32_t)0x00800000)
3766 /****************** Bit definition for ADC_SMPR1 register *******************/
3767 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007)
3768 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001)
3769 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002)
3770 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004)
3772 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038)
3773 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008)
3774 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010)
3775 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020)
3777 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0)
3778 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040)
3779 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080)
3780 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100)
3782 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00)
3783 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200)
3784 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400)
3785 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800)
3787 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000)
3788 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000)
3789 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000)
3790 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000)
3792 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000)
3793 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000)
3794 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000)
3795 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000)
3797 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000)
3798 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000)
3799 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000)
3800 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000)
3802 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000)
3803 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000)
3804 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000)
3805 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000)
3807 /****************** Bit definition for ADC_SMPR2 register *******************/
3808 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007)
3809 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001)
3810 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002)
3811 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004)
3813 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038)
3814 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008)
3815 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010)
3816 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020)
3818 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0)
3819 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040)
3820 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080)
3821 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100)
3823 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00)
3824 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200)
3825 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400)
3826 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800)
3828 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000)
3829 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000)
3830 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000)
3831 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000)
3833 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000)
3834 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000)
3835 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000)
3836 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000)
3838 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000)
3839 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000)
3840 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000)
3841 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000)
3843 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000)
3844 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000)
3845 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000)
3846 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000)
3848 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000)
3849 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000)
3850 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000)
3851 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000)
3853 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000)
3854 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000)
3855 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000)
3856 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000)
3858 /****************** Bit definition for ADC_JOFR1 register *******************/
3859 #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF)
3861 /****************** Bit definition for ADC_JOFR2 register *******************/
3862 #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF)
3864 /****************** Bit definition for ADC_JOFR3 register *******************/
3865 #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF)
3867 /****************** Bit definition for ADC_JOFR4 register *******************/
3868 #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF)
3870 /******************* Bit definition for ADC_HTR register ********************/
3871 #define ADC_HTR_HT ((uint16_t)0x0FFF)
3873 /******************* Bit definition for ADC_LTR register ********************/
3874 #define ADC_LTR_LT ((uint16_t)0x0FFF)
3876 /******************* Bit definition for ADC_SQR1 register *******************/
3877 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F)
3878 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001)
3879 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002)
3880 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004)
3881 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008)
3882 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010)
3884 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0)
3885 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020)
3886 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040)
3887 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080)
3888 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100)
3889 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200)
3891 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00)
3892 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400)
3893 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800)
3894 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000)
3895 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000)
3896 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000)
3898 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000)
3899 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000)
3900 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000)
3901 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000)
3902 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000)
3903 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000)
3905 #define ADC_SQR1_L ((uint32_t)0x00F00000)
3906 #define ADC_SQR1_L_0 ((uint32_t)0x00100000)
3907 #define ADC_SQR1_L_1 ((uint32_t)0x00200000)
3908 #define ADC_SQR1_L_2 ((uint32_t)0x00400000)
3909 #define ADC_SQR1_L_3 ((uint32_t)0x00800000)
3911 /******************* Bit definition for ADC_SQR2 register *******************/
3912 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F)
3913 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001)
3914 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002)
3915 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004)
3916 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008)
3917 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010)
3919 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0)
3920 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020)
3921 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040)
3922 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080)
3923 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100)
3924 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200)
3926 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00)
3927 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400)
3928 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800)
3929 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000)
3930 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000)
3931 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000)
3933 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000)
3934 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000)
3935 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000)
3936 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000)
3937 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000)
3938 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000)
3940 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000)
3941 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000)
3942 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000)
3943 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000)
3944 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000)
3945 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000)
3947 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000)
3948 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000)
3949 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000)
3950 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000)
3951 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000)
3952 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000)
3954 /******************* Bit definition for ADC_SQR3 register *******************/
3955 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F)
3956 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001)
3957 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002)
3958 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004)
3959 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008)
3960 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010)
3962 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0)
3963 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020)
3964 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040)
3965 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080)
3966 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100)
3967 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200)
3969 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00)
3970 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400)
3971 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800)
3972 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000)
3973 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000)
3974 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000)
3976 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000)
3977 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000)
3978 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000)
3979 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000)
3980 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000)
3981 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000)
3983 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000)
3984 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000)
3985 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000)
3986 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000)
3987 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000)
3988 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000)
3990 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000)
3991 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000)
3992 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000)
3993 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000)
3994 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000)
3995 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000)
3997 /******************* Bit definition for ADC_JSQR register *******************/
3998 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F)
3999 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001)
4000 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002)
4001 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004)
4002 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008)
4003 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010)
4005 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0)
4006 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020)
4007 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040)
4008 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080)
4009 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100)
4010 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200)
4012 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00)
4013 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400)
4014 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800)
4015 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000)
4016 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000)
4017 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000)
4019 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000)
4020 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000)
4021 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000)
4022 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000)
4023 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000)
4024 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000)
4026 #define ADC_JSQR_JL ((uint32_t)0x00300000)
4027 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000)
4028 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000)
4030 /******************* Bit definition for ADC_JDR1 register *******************/
4031 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF)
4033 /******************* Bit definition for ADC_JDR2 register *******************/
4034 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF)
4036 /******************* Bit definition for ADC_JDR3 register *******************/
4037 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF)
4039 /******************* Bit definition for ADC_JDR4 register *******************/
4040 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF)
4042 /******************** Bit definition for ADC_DR register ********************/
4043 #define ADC_DR_DATA ((uint32_t)0x0000FFFF)
4044 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000)
4046 /******************************************************************************/
4047 /* */
4048 /* Digital to Analog Converter */
4049 /* */
4050 /******************************************************************************/
4051 
4052 /******************** Bit definition for DAC_CR register ********************/
4053 #define DAC_CR_EN1 ((uint32_t)0x00000001)
4054 #define DAC_CR_BOFF1 ((uint32_t)0x00000002)
4055 #define DAC_CR_TEN1 ((uint32_t)0x00000004)
4057 #define DAC_CR_TSEL1 ((uint32_t)0x00000038)
4058 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008)
4059 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010)
4060 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020)
4062 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0)
4063 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040)
4064 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080)
4066 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00)
4067 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100)
4068 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200)
4069 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400)
4070 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800)
4072 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000)
4073 #define DAC_CR_EN2 ((uint32_t)0x00010000)
4074 #define DAC_CR_BOFF2 ((uint32_t)0x00020000)
4075 #define DAC_CR_TEN2 ((uint32_t)0x00040000)
4077 #define DAC_CR_TSEL2 ((uint32_t)0x00380000)
4078 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000)
4079 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000)
4080 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000)
4082 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000)
4083 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000)
4084 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000)
4086 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000)
4087 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000)
4088 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000)
4089 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000)
4090 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000)
4092 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000)
4094 /***************** Bit definition for DAC_SWTRIGR register ******************/
4095 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01)
4096 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02)
4098 /***************** Bit definition for DAC_DHR12R1 register ******************/
4099 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF)
4101 /***************** Bit definition for DAC_DHR12L1 register ******************/
4102 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0)
4104 /****************** Bit definition for DAC_DHR8R1 register ******************/
4105 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF)
4107 /***************** Bit definition for DAC_DHR12R2 register ******************/
4108 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF)
4110 /***************** Bit definition for DAC_DHR12L2 register ******************/
4111 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0)
4113 /****************** Bit definition for DAC_DHR8R2 register ******************/
4114 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF)
4116 /***************** Bit definition for DAC_DHR12RD register ******************/
4117 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF)
4118 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000)
4120 /***************** Bit definition for DAC_DHR12LD register ******************/
4121 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0)
4122 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000)
4124 /****************** Bit definition for DAC_DHR8RD register ******************/
4125 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF)
4126 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00)
4128 /******************* Bit definition for DAC_DOR1 register *******************/
4129 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF)
4131 /******************* Bit definition for DAC_DOR2 register *******************/
4132 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF)
4134 /******************** Bit definition for DAC_SR register ********************/
4135 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000)
4136 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000)
4138 /******************************************************************************/
4139 /* */
4140 /* CEC */
4141 /* */
4142 /******************************************************************************/
4143 /******************** Bit definition for CEC_CFGR register ******************/
4144 #define CEC_CFGR_PE ((uint16_t)0x0001)
4145 #define CEC_CFGR_IE ((uint16_t)0x0002)
4146 #define CEC_CFGR_BTEM ((uint16_t)0x0004)
4147 #define CEC_CFGR_BPEM ((uint16_t)0x0008)
4149 /******************** Bit definition for CEC_OAR register ******************/
4150 #define CEC_OAR_OA ((uint16_t)0x000F)
4151 #define CEC_OAR_OA_0 ((uint16_t)0x0001)
4152 #define CEC_OAR_OA_1 ((uint16_t)0x0002)
4153 #define CEC_OAR_OA_2 ((uint16_t)0x0004)
4154 #define CEC_OAR_OA_3 ((uint16_t)0x0008)
4156 /******************** Bit definition for CEC_PRES register ******************/
4157 #define CEC_PRES_PRES ((uint16_t)0x3FFF)
4159 /******************** Bit definition for CEC_ESR register ******************/
4160 #define CEC_ESR_BTE ((uint16_t)0x0001)
4161 #define CEC_ESR_BPE ((uint16_t)0x0002)
4162 #define CEC_ESR_RBTFE ((uint16_t)0x0004)
4163 #define CEC_ESR_SBE ((uint16_t)0x0008)
4164 #define CEC_ESR_ACKE ((uint16_t)0x0010)
4165 #define CEC_ESR_LINE ((uint16_t)0x0020)
4166 #define CEC_ESR_TBTFE ((uint16_t)0x0040)
4168 /******************** Bit definition for CEC_CSR register ******************/
4169 #define CEC_CSR_TSOM ((uint16_t)0x0001)
4170 #define CEC_CSR_TEOM ((uint16_t)0x0002)
4171 #define CEC_CSR_TERR ((uint16_t)0x0004)
4172 #define CEC_CSR_TBTRF ((uint16_t)0x0008)
4173 #define CEC_CSR_RSOM ((uint16_t)0x0010)
4174 #define CEC_CSR_REOM ((uint16_t)0x0020)
4175 #define CEC_CSR_RERR ((uint16_t)0x0040)
4176 #define CEC_CSR_RBTF ((uint16_t)0x0080)
4178 /******************** Bit definition for CEC_TXD register ******************/
4179 #define CEC_TXD_TXD ((uint16_t)0x00FF)
4181 /******************** Bit definition for CEC_RXD register ******************/
4182 #define CEC_RXD_RXD ((uint16_t)0x00FF)
4184 /******************************************************************************/
4185 /* */
4186 /* TIM */
4187 /* */
4188 /******************************************************************************/
4189 
4190 /******************* Bit definition for TIM_CR1 register ********************/
4191 #define TIM_CR1_CEN ((uint16_t)0x0001)
4192 #define TIM_CR1_UDIS ((uint16_t)0x0002)
4193 #define TIM_CR1_URS ((uint16_t)0x0004)
4194 #define TIM_CR1_OPM ((uint16_t)0x0008)
4195 #define TIM_CR1_DIR ((uint16_t)0x0010)
4197 #define TIM_CR1_CMS ((uint16_t)0x0060)
4198 #define TIM_CR1_CMS_0 ((uint16_t)0x0020)
4199 #define TIM_CR1_CMS_1 ((uint16_t)0x0040)
4201 #define TIM_CR1_ARPE ((uint16_t)0x0080)
4203 #define TIM_CR1_CKD ((uint16_t)0x0300)
4204 #define TIM_CR1_CKD_0 ((uint16_t)0x0100)
4205 #define TIM_CR1_CKD_1 ((uint16_t)0x0200)
4207 /******************* Bit definition for TIM_CR2 register ********************/
4208 #define TIM_CR2_CCPC ((uint16_t)0x0001)
4209 #define TIM_CR2_CCUS ((uint16_t)0x0004)
4210 #define TIM_CR2_CCDS ((uint16_t)0x0008)
4212 #define TIM_CR2_MMS ((uint16_t)0x0070)
4213 #define TIM_CR2_MMS_0 ((uint16_t)0x0010)
4214 #define TIM_CR2_MMS_1 ((uint16_t)0x0020)
4215 #define TIM_CR2_MMS_2 ((uint16_t)0x0040)
4217 #define TIM_CR2_TI1S ((uint16_t)0x0080)
4218 #define TIM_CR2_OIS1 ((uint16_t)0x0100)
4219 #define TIM_CR2_OIS1N ((uint16_t)0x0200)
4220 #define TIM_CR2_OIS2 ((uint16_t)0x0400)
4221 #define TIM_CR2_OIS2N ((uint16_t)0x0800)
4222 #define TIM_CR2_OIS3 ((uint16_t)0x1000)
4223 #define TIM_CR2_OIS3N ((uint16_t)0x2000)
4224 #define TIM_CR2_OIS4 ((uint16_t)0x4000)
4226 /******************* Bit definition for TIM_SMCR register *******************/
4227 #define TIM_SMCR_SMS ((uint16_t)0x0007)
4228 #define TIM_SMCR_SMS_0 ((uint16_t)0x0001)
4229 #define TIM_SMCR_SMS_1 ((uint16_t)0x0002)
4230 #define TIM_SMCR_SMS_2 ((uint16_t)0x0004)
4232 #define TIM_SMCR_TS ((uint16_t)0x0070)
4233 #define TIM_SMCR_TS_0 ((uint16_t)0x0010)
4234 #define TIM_SMCR_TS_1 ((uint16_t)0x0020)
4235 #define TIM_SMCR_TS_2 ((uint16_t)0x0040)
4237 #define TIM_SMCR_MSM ((uint16_t)0x0080)
4239 #define TIM_SMCR_ETF ((uint16_t)0x0F00)
4240 #define TIM_SMCR_ETF_0 ((uint16_t)0x0100)
4241 #define TIM_SMCR_ETF_1 ((uint16_t)0x0200)
4242 #define TIM_SMCR_ETF_2 ((uint16_t)0x0400)
4243 #define TIM_SMCR_ETF_3 ((uint16_t)0x0800)
4245 #define TIM_SMCR_ETPS ((uint16_t)0x3000)
4246 #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000)
4247 #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000)
4249 #define TIM_SMCR_ECE ((uint16_t)0x4000)
4250 #define TIM_SMCR_ETP ((uint16_t)0x8000)
4252 /******************* Bit definition for TIM_DIER register *******************/
4253 #define TIM_DIER_UIE ((uint16_t)0x0001)
4254 #define TIM_DIER_CC1IE ((uint16_t)0x0002)
4255 #define TIM_DIER_CC2IE ((uint16_t)0x0004)
4256 #define TIM_DIER_CC3IE ((uint16_t)0x0008)
4257 #define TIM_DIER_CC4IE ((uint16_t)0x0010)
4258 #define TIM_DIER_COMIE ((uint16_t)0x0020)
4259 #define TIM_DIER_TIE ((uint16_t)0x0040)
4260 #define TIM_DIER_BIE ((uint16_t)0x0080)
4261 #define TIM_DIER_UDE ((uint16_t)0x0100)
4262 #define TIM_DIER_CC1DE ((uint16_t)0x0200)
4263 #define TIM_DIER_CC2DE ((uint16_t)0x0400)
4264 #define TIM_DIER_CC3DE ((uint16_t)0x0800)
4265 #define TIM_DIER_CC4DE ((uint16_t)0x1000)
4266 #define TIM_DIER_COMDE ((uint16_t)0x2000)
4267 #define TIM_DIER_TDE ((uint16_t)0x4000)
4269 /******************** Bit definition for TIM_SR register ********************/
4270 #define TIM_SR_UIF ((uint16_t)0x0001)
4271 #define TIM_SR_CC1IF ((uint16_t)0x0002)
4272 #define TIM_SR_CC2IF ((uint16_t)0x0004)
4273 #define TIM_SR_CC3IF ((uint16_t)0x0008)
4274 #define TIM_SR_CC4IF ((uint16_t)0x0010)
4275 #define TIM_SR_COMIF ((uint16_t)0x0020)
4276 #define TIM_SR_TIF ((uint16_t)0x0040)
4277 #define TIM_SR_BIF ((uint16_t)0x0080)
4278 #define TIM_SR_CC1OF ((uint16_t)0x0200)
4279 #define TIM_SR_CC2OF ((uint16_t)0x0400)
4280 #define TIM_SR_CC3OF ((uint16_t)0x0800)
4281 #define TIM_SR_CC4OF ((uint16_t)0x1000)
4283 /******************* Bit definition for TIM_EGR register ********************/
4284 #define TIM_EGR_UG ((uint8_t)0x01)
4285 #define TIM_EGR_CC1G ((uint8_t)0x02)
4286 #define TIM_EGR_CC2G ((uint8_t)0x04)
4287 #define TIM_EGR_CC3G ((uint8_t)0x08)
4288 #define TIM_EGR_CC4G ((uint8_t)0x10)
4289 #define TIM_EGR_COMG ((uint8_t)0x20)
4290 #define TIM_EGR_TG ((uint8_t)0x40)
4291 #define TIM_EGR_BG ((uint8_t)0x80)
4293 /****************** Bit definition for TIM_CCMR1 register *******************/
4294 #define TIM_CCMR1_CC1S ((uint16_t)0x0003)
4295 #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001)
4296 #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002)
4298 #define TIM_CCMR1_OC1FE ((uint16_t)0x0004)
4299 #define TIM_CCMR1_OC1PE ((uint16_t)0x0008)
4301 #define TIM_CCMR1_OC1M ((uint16_t)0x0070)
4302 #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010)
4303 #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020)
4304 #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040)
4306 #define TIM_CCMR1_OC1CE ((uint16_t)0x0080)
4308 #define TIM_CCMR1_CC2S ((uint16_t)0x0300)
4309 #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100)
4310 #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200)
4312 #define TIM_CCMR1_OC2FE ((uint16_t)0x0400)
4313 #define TIM_CCMR1_OC2PE ((uint16_t)0x0800)
4315 #define TIM_CCMR1_OC2M ((uint16_t)0x7000)
4316 #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000)
4317 #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000)
4318 #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000)
4320 #define TIM_CCMR1_OC2CE ((uint16_t)0x8000)
4322 /*----------------------------------------------------------------------------*/
4323 
4324 #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C)
4325 #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004)
4326 #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008)
4328 #define TIM_CCMR1_IC1F ((uint16_t)0x00F0)
4329 #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010)
4330 #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020)
4331 #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040)
4332 #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080)
4334 #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00)
4335 #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400)
4336 #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800)
4338 #define TIM_CCMR1_IC2F ((uint16_t)0xF000)
4339 #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000)
4340 #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000)
4341 #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000)
4342 #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000)
4344 /****************** Bit definition for TIM_CCMR2 register *******************/
4345 #define TIM_CCMR2_CC3S ((uint16_t)0x0003)
4346 #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001)
4347 #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002)
4349 #define TIM_CCMR2_OC3FE ((uint16_t)0x0004)
4350 #define TIM_CCMR2_OC3PE ((uint16_t)0x0008)
4352 #define TIM_CCMR2_OC3M ((uint16_t)0x0070)
4353 #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010)
4354 #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020)
4355 #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040)
4357 #define TIM_CCMR2_OC3CE ((uint16_t)0x0080)
4359 #define TIM_CCMR2_CC4S ((uint16_t)0x0300)
4360 #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100)
4361 #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200)
4363 #define TIM_CCMR2_OC4FE ((uint16_t)0x0400)
4364 #define TIM_CCMR2_OC4PE ((uint16_t)0x0800)
4366 #define TIM_CCMR2_OC4M ((uint16_t)0x7000)
4367 #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000)
4368 #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000)
4369 #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000)
4371 #define TIM_CCMR2_OC4CE ((uint16_t)0x8000)
4373 /*----------------------------------------------------------------------------*/
4374 
4375 #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C)
4376 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004)
4377 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008)
4379 #define TIM_CCMR2_IC3F ((uint16_t)0x00F0)
4380 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010)
4381 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020)
4382 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040)
4383 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080)
4385 #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00)
4386 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400)
4387 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800)
4389 #define TIM_CCMR2_IC4F ((uint16_t)0xF000)
4390 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000)
4391 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000)
4392 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000)
4393 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000)
4395 /******************* Bit definition for TIM_CCER register *******************/
4396 #define TIM_CCER_CC1E ((uint16_t)0x0001)
4397 #define TIM_CCER_CC1P ((uint16_t)0x0002)
4398 #define TIM_CCER_CC1NE ((uint16_t)0x0004)
4399 #define TIM_CCER_CC1NP ((uint16_t)0x0008)
4400 #define TIM_CCER_CC2E ((uint16_t)0x0010)
4401 #define TIM_CCER_CC2P ((uint16_t)0x0020)
4402 #define TIM_CCER_CC2NE ((uint16_t)0x0040)
4403 #define TIM_CCER_CC2NP ((uint16_t)0x0080)
4404 #define TIM_CCER_CC3E ((uint16_t)0x0100)
4405 #define TIM_CCER_CC3P ((uint16_t)0x0200)
4406 #define TIM_CCER_CC3NE ((uint16_t)0x0400)
4407 #define TIM_CCER_CC3NP ((uint16_t)0x0800)
4408 #define TIM_CCER_CC4E ((uint16_t)0x1000)
4409 #define TIM_CCER_CC4P ((uint16_t)0x2000)
4410 #define TIM_CCER_CC4NP ((uint16_t)0x8000)
4412 /******************* Bit definition for TIM_CNT register ********************/
4413 #define TIM_CNT_CNT ((uint16_t)0xFFFF)
4415 /******************* Bit definition for TIM_PSC register ********************/
4416 #define TIM_PSC_PSC ((uint16_t)0xFFFF)
4418 /******************* Bit definition for TIM_ARR register ********************/
4419 #define TIM_ARR_ARR ((uint16_t)0xFFFF)
4421 /******************* Bit definition for TIM_RCR register ********************/
4422 #define TIM_RCR_REP ((uint8_t)0xFF)
4424 /******************* Bit definition for TIM_CCR1 register *******************/
4425 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF)
4427 /******************* Bit definition for TIM_CCR2 register *******************/
4428 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF)
4430 /******************* Bit definition for TIM_CCR3 register *******************/
4431 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF)
4433 /******************* Bit definition for TIM_CCR4 register *******************/
4434 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF)
4436 /******************* Bit definition for TIM_BDTR register *******************/
4437 #define TIM_BDTR_DTG ((uint16_t)0x00FF)
4438 #define TIM_BDTR_DTG_0 ((uint16_t)0x0001)
4439 #define TIM_BDTR_DTG_1 ((uint16_t)0x0002)
4440 #define TIM_BDTR_DTG_2 ((uint16_t)0x0004)
4441 #define TIM_BDTR_DTG_3 ((uint16_t)0x0008)
4442 #define TIM_BDTR_DTG_4 ((uint16_t)0x0010)
4443 #define TIM_BDTR_DTG_5 ((uint16_t)0x0020)
4444 #define TIM_BDTR_DTG_6 ((uint16_t)0x0040)
4445 #define TIM_BDTR_DTG_7 ((uint16_t)0x0080)
4447 #define TIM_BDTR_LOCK ((uint16_t)0x0300)
4448 #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100)
4449 #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200)
4451 #define TIM_BDTR_OSSI ((uint16_t)0x0400)
4452 #define TIM_BDTR_OSSR ((uint16_t)0x0800)
4453 #define TIM_BDTR_BKE ((uint16_t)0x1000)
4454 #define TIM_BDTR_BKP ((uint16_t)0x2000)
4455 #define TIM_BDTR_AOE ((uint16_t)0x4000)
4456 #define TIM_BDTR_MOE ((uint16_t)0x8000)
4458 /******************* Bit definition for TIM_DCR register ********************/
4459 #define TIM_DCR_DBA ((uint16_t)0x001F)
4460 #define TIM_DCR_DBA_0 ((uint16_t)0x0001)
4461 #define TIM_DCR_DBA_1 ((uint16_t)0x0002)
4462 #define TIM_DCR_DBA_2 ((uint16_t)0x0004)
4463 #define TIM_DCR_DBA_3 ((uint16_t)0x0008)
4464 #define TIM_DCR_DBA_4 ((uint16_t)0x0010)
4466 #define TIM_DCR_DBL ((uint16_t)0x1F00)
4467 #define TIM_DCR_DBL_0 ((uint16_t)0x0100)
4468 #define TIM_DCR_DBL_1 ((uint16_t)0x0200)
4469 #define TIM_DCR_DBL_2 ((uint16_t)0x0400)
4470 #define TIM_DCR_DBL_3 ((uint16_t)0x0800)
4471 #define TIM_DCR_DBL_4 ((uint16_t)0x1000)
4473 /******************* Bit definition for TIM_DMAR register *******************/
4474 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF)
4476 /******************************************************************************/
4477 /* */
4478 /* Real-Time Clock */
4479 /* */
4480 /******************************************************************************/
4481 
4482 /******************* Bit definition for RTC_CRH register ********************/
4483 #define RTC_CRH_SECIE ((uint8_t)0x01)
4484 #define RTC_CRH_ALRIE ((uint8_t)0x02)
4485 #define RTC_CRH_OWIE ((uint8_t)0x04)
4487 /******************* Bit definition for RTC_CRL register ********************/
4488 #define RTC_CRL_SECF ((uint8_t)0x01)
4489 #define RTC_CRL_ALRF ((uint8_t)0x02)
4490 #define RTC_CRL_OWF ((uint8_t)0x04)
4491 #define RTC_CRL_RSF ((uint8_t)0x08)
4492 #define RTC_CRL_CNF ((uint8_t)0x10)
4493 #define RTC_CRL_RTOFF ((uint8_t)0x20)
4495 /******************* Bit definition for RTC_PRLH register *******************/
4496 #define RTC_PRLH_PRL ((uint16_t)0x000F)
4498 /******************* Bit definition for RTC_PRLL register *******************/
4499 #define RTC_PRLL_PRL ((uint16_t)0xFFFF)
4501 /******************* Bit definition for RTC_DIVH register *******************/
4502 #define RTC_DIVH_RTC_DIV ((uint16_t)0x000F)
4504 /******************* Bit definition for RTC_DIVL register *******************/
4505 #define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF)
4507 /******************* Bit definition for RTC_CNTH register *******************/
4508 #define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF)
4510 /******************* Bit definition for RTC_CNTL register *******************/
4511 #define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF)
4513 /******************* Bit definition for RTC_ALRH register *******************/
4514 #define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF)
4516 /******************* Bit definition for RTC_ALRL register *******************/
4517 #define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF)
4519 /******************************************************************************/
4520 /* */
4521 /* Independent WATCHDOG */
4522 /* */
4523 /******************************************************************************/
4524 
4525 /******************* Bit definition for IWDG_KR register ********************/
4526 #define IWDG_KR_KEY ((uint16_t)0xFFFF)
4528 /******************* Bit definition for IWDG_PR register ********************/
4529 #define IWDG_PR_PR ((uint8_t)0x07)
4530 #define IWDG_PR_PR_0 ((uint8_t)0x01)
4531 #define IWDG_PR_PR_1 ((uint8_t)0x02)
4532 #define IWDG_PR_PR_2 ((uint8_t)0x04)
4534 /******************* Bit definition for IWDG_RLR register *******************/
4535 #define IWDG_RLR_RL ((uint16_t)0x0FFF)
4537 /******************* Bit definition for IWDG_SR register ********************/
4538 #define IWDG_SR_PVU ((uint8_t)0x01)
4539 #define IWDG_SR_RVU ((uint8_t)0x02)
4541 /******************************************************************************/
4542 /* */
4543 /* Window WATCHDOG */
4544 /* */
4545 /******************************************************************************/
4546 
4547 /******************* Bit definition for WWDG_CR register ********************/
4548 #define WWDG_CR_T ((uint8_t)0x7F)
4549 #define WWDG_CR_T0 ((uint8_t)0x01)
4550 #define WWDG_CR_T1 ((uint8_t)0x02)
4551 #define WWDG_CR_T2 ((uint8_t)0x04)
4552 #define WWDG_CR_T3 ((uint8_t)0x08)
4553 #define WWDG_CR_T4 ((uint8_t)0x10)
4554 #define WWDG_CR_T5 ((uint8_t)0x20)
4555 #define WWDG_CR_T6 ((uint8_t)0x40)
4557 #define WWDG_CR_WDGA ((uint8_t)0x80)
4559 /******************* Bit definition for WWDG_CFR register *******************/
4560 #define WWDG_CFR_W ((uint16_t)0x007F)
4561 #define WWDG_CFR_W0 ((uint16_t)0x0001)
4562 #define WWDG_CFR_W1 ((uint16_t)0x0002)
4563 #define WWDG_CFR_W2 ((uint16_t)0x0004)
4564 #define WWDG_CFR_W3 ((uint16_t)0x0008)
4565 #define WWDG_CFR_W4 ((uint16_t)0x0010)
4566 #define WWDG_CFR_W5 ((uint16_t)0x0020)
4567 #define WWDG_CFR_W6 ((uint16_t)0x0040)
4569 #define WWDG_CFR_WDGTB ((uint16_t)0x0180)
4570 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080)
4571 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100)
4573 #define WWDG_CFR_EWI ((uint16_t)0x0200)
4575 /******************* Bit definition for WWDG_SR register ********************/
4576 #define WWDG_SR_EWIF ((uint8_t)0x01)
4578 /******************************************************************************/
4579 /* */
4580 /* Flexible Static Memory Controller */
4581 /* */
4582 /******************************************************************************/
4583 
4584 /****************** Bit definition for FSMC_BCR1 register *******************/
4585 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001)
4586 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002)
4588 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C)
4589 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004)
4590 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008)
4592 #define FSMC_BCR1_MWID ((uint32_t)0x00000030)
4593 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010)
4594 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020)
4596 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040)
4597 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100)
4598 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200)
4599 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400)
4600 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800)
4601 #define FSMC_BCR1_WREN ((uint32_t)0x00001000)
4602 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000)
4603 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000)
4604 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000)
4605 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000)
4607 /****************** Bit definition for FSMC_BCR2 register *******************/
4608 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001)
4609 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002)
4611 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C)
4612 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004)
4613 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008)
4615 #define FSMC_BCR2_MWID ((uint32_t)0x00000030)
4616 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010)
4617 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020)
4619 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040)
4620 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100)
4621 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200)
4622 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400)
4623 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800)
4624 #define FSMC_BCR2_WREN ((uint32_t)0x00001000)
4625 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000)
4626 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000)
4627 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000)
4628 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000)
4630 /****************** Bit definition for FSMC_BCR3 register *******************/
4631 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001)
4632 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002)
4634 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C)
4635 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004)
4636 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008)
4638 #define FSMC_BCR3_MWID ((uint32_t)0x00000030)
4639 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010)
4640 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020)
4642 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040)
4643 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100)
4644 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200)
4645 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400)
4646 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800)
4647 #define FSMC_BCR3_WREN ((uint32_t)0x00001000)
4648 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000)
4649 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000)
4650 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000)
4651 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000)
4653 /****************** Bit definition for FSMC_BCR4 register *******************/
4654 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001)
4655 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002)
4657 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C)
4658 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004)
4659 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008)
4661 #define FSMC_BCR4_MWID ((uint32_t)0x00000030)
4662 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010)
4663 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020)
4665 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040)
4666 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100)
4667 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200)
4668 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400)
4669 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800)
4670 #define FSMC_BCR4_WREN ((uint32_t)0x00001000)
4671 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000)
4672 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000)
4673 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000)
4674 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000)
4676 /****************** Bit definition for FSMC_BTR1 register ******************/
4677 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F)
4678 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001)
4679 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002)
4680 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004)
4681 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008)
4683 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0)
4684 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010)
4685 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020)
4686 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040)
4687 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080)
4689 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00)
4690 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100)
4691 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200)
4692 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400)
4693 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800)
4695 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000)
4696 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000)
4697 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000)
4698 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000)
4699 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000)
4701 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000)
4702 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000)
4703 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000)
4704 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000)
4705 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000)
4707 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000)
4708 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000)
4709 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000)
4710 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000)
4711 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000)
4713 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000)
4714 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000)
4715 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000)
4717 /****************** Bit definition for FSMC_BTR2 register *******************/
4718 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F)
4719 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001)
4720 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002)
4721 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004)
4722 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008)
4724 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0)
4725 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010)
4726 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020)
4727 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040)
4728 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080)
4730 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00)
4731 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100)
4732 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200)
4733 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400)
4734 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800)
4736 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000)
4737 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000)
4738 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000)
4739 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000)
4740 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000)
4742 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000)
4743 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000)
4744 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000)
4745 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000)
4746 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000)
4748 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000)
4749 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000)
4750 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000)
4751 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000)
4752 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000)
4754 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000)
4755 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000)
4756 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000)
4758 /******************* Bit definition for FSMC_BTR3 register *******************/
4759 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F)
4760 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001)
4761 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002)
4762 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004)
4763 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008)
4765 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0)
4766 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010)
4767 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020)
4768 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040)
4769 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080)
4771 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00)
4772 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100)
4773 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200)
4774 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400)
4775 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800)
4777 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000)
4778 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000)
4779 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000)
4780 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000)
4781 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000)
4783 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000)
4784 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000)
4785 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000)
4786 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000)
4787 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000)
4789 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000)
4790 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000)
4791 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000)
4792 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000)
4793 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000)
4795 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000)
4796 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000)
4797 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000)
4799 /****************** Bit definition for FSMC_BTR4 register *******************/
4800 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F)
4801 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001)
4802 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002)
4803 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004)
4804 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008)
4806 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0)
4807 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010)
4808 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020)
4809 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040)
4810 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080)
4812 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00)
4813 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100)
4814 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200)
4815 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400)
4816 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800)
4818 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000)
4819 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000)
4820 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000)
4821 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000)
4822 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000)
4824 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000)
4825 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000)
4826 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000)
4827 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000)
4828 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000)
4830 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000)
4831 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000)
4832 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000)
4833 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000)
4834 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000)
4836 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000)
4837 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000)
4838 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000)
4840 /****************** Bit definition for FSMC_BWTR1 register ******************/
4841 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F)
4842 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001)
4843 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002)
4844 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004)
4845 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008)
4847 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0)
4848 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010)
4849 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020)
4850 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040)
4851 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080)
4853 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00)
4854 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100)
4855 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200)
4856 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400)
4857 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800)
4859 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000)
4860 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000)
4861 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000)
4862 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000)
4863 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000)
4865 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000)
4866 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000)
4867 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000)
4868 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000)
4869 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000)
4871 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000)
4872 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000)
4873 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000)
4875 /****************** Bit definition for FSMC_BWTR2 register ******************/
4876 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F)
4877 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001)
4878 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002)
4879 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004)
4880 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008)
4882 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0)
4883 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010)
4884 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020)
4885 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040)
4886 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080)
4888 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00)
4889 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100)
4890 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200)
4891 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400)
4892 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800)
4894 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000)
4895 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000)
4896 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000)
4897 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000)
4898 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000)
4900 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000)
4901 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000)
4902 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000)
4903 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000)
4904 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000)
4906 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000)
4907 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000)
4908 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000)
4910 /****************** Bit definition for FSMC_BWTR3 register ******************/
4911 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F)
4912 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001)
4913 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002)
4914 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004)
4915 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008)
4917 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0)
4918 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010)
4919 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020)