stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32F4xx_HAL_TIM_H
22 #define STM32F4xx_HAL_TIM_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f4xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
47 typedef struct
48 {
49  uint32_t Prescaler;
52  uint32_t CounterMode;
55  uint32_t Period;
59  uint32_t ClockDivision;
62  uint32_t RepetitionCounter;
71  uint32_t AutoReloadPreload;
73 } TIM_Base_InitTypeDef;
74 
78 typedef struct
79 {
80  uint32_t OCMode;
83  uint32_t Pulse;
86  uint32_t OCPolarity;
89  uint32_t OCNPolarity;
93  uint32_t OCFastMode;
98  uint32_t OCIdleState;
102  uint32_t OCNIdleState;
105 } TIM_OC_InitTypeDef;
106 
110 typedef struct
111 {
112  uint32_t OCMode;
115  uint32_t Pulse;
118  uint32_t OCPolarity;
121  uint32_t OCNPolarity;
125  uint32_t OCIdleState;
129  uint32_t OCNIdleState;
133  uint32_t ICPolarity;
136  uint32_t ICSelection;
139  uint32_t ICFilter;
141 } TIM_OnePulse_InitTypeDef;
142 
146 typedef struct
147 {
148  uint32_t ICPolarity;
151  uint32_t ICSelection;
154  uint32_t ICPrescaler;
157  uint32_t ICFilter;
159 } TIM_IC_InitTypeDef;
160 
164 typedef struct
165 {
166  uint32_t EncoderMode;
169  uint32_t IC1Polarity;
172  uint32_t IC1Selection;
175  uint32_t IC1Prescaler;
178  uint32_t IC1Filter;
181  uint32_t IC2Polarity;
184  uint32_t IC2Selection;
187  uint32_t IC2Prescaler;
190  uint32_t IC2Filter;
192 } TIM_Encoder_InitTypeDef;
193 
197 typedef struct
198 {
199  uint32_t ClockSource;
201  uint32_t ClockPolarity;
203  uint32_t ClockPrescaler;
205  uint32_t ClockFilter;
207 } TIM_ClockConfigTypeDef;
208 
212 typedef struct
213 {
214  uint32_t ClearInputState;
216  uint32_t ClearInputSource;
218  uint32_t ClearInputPolarity;
220  uint32_t ClearInputPrescaler;
222  uint32_t ClearInputFilter;
224 } TIM_ClearInputConfigTypeDef;
225 
229 typedef struct
230 {
231  uint32_t MasterOutputTrigger;
233  uint32_t MasterSlaveMode;
240 } TIM_MasterConfigTypeDef;
241 
245 typedef struct
246 {
247  uint32_t SlaveMode;
249  uint32_t InputTrigger;
251  uint32_t TriggerPolarity;
253  uint32_t TriggerPrescaler;
255  uint32_t TriggerFilter;
258 } TIM_SlaveConfigTypeDef;
259 
265 typedef struct
266 {
267  uint32_t OffStateRunMode;
269  uint32_t OffStateIDLEMode;
271  uint32_t LockLevel;
273  uint32_t DeadTime;
275  uint32_t BreakState;
277  uint32_t BreakPolarity;
279  uint32_t BreakFilter;
281  uint32_t AutomaticOutput;
283 } TIM_BreakDeadTimeConfigTypeDef;
284 
288 typedef enum
289 {
290  HAL_TIM_STATE_RESET = 0x00U,
291  HAL_TIM_STATE_READY = 0x01U,
292  HAL_TIM_STATE_BUSY = 0x02U,
293  HAL_TIM_STATE_TIMEOUT = 0x03U,
294  HAL_TIM_STATE_ERROR = 0x04U
295 } HAL_TIM_StateTypeDef;
296 
300 typedef enum
301 {
302  HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
303  HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
304  HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
305  HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
306  HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
307 } HAL_TIM_ActiveChannel;
308 
312 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
313 typedef struct __TIM_HandleTypeDef
314 #else
315 typedef struct
316 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
317 {
318  TIM_TypeDef *Instance;
319  TIM_Base_InitTypeDef Init;
320  HAL_TIM_ActiveChannel Channel;
321  DMA_HandleTypeDef *hdma[7];
323  HAL_LockTypeDef Lock;
324  __IO HAL_TIM_StateTypeDef State;
326 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
327  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
328  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
329  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
330  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
331  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
332  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
333  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
334  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
335  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
336  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
337  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
338  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
339  void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
340  void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
341  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);
342  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
343  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);
344  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
345  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);
346  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
347  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);
348  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);
349  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
350  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);
351  void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);
352  void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
353  void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);
354 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
355 } TIM_HandleTypeDef;
356 
357 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
358 
361 typedef enum
362 {
363  HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U
364  ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U
365  ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U
366  ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U
367  ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U
368  ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U
369  ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U
370  ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U
371  ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U
372  ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U
373  ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU
374  ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU
375  ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU
376  ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU
377  ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU
378  ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU
379  ,HAL_TIM_TRIGGER_CB_ID = 0x10U
380  ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U
382  ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U
383  ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U
384  ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U
385  ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U
386  ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U
387  ,HAL_TIM_ERROR_CB_ID = 0x17U
388  ,HAL_TIM_COMMUTATION_CB_ID = 0x18U
389  ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U
390  ,HAL_TIM_BREAK_CB_ID = 0x1AU
391 } HAL_TIM_CallbackIDTypeDef;
392 
396 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);
398 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
399 
403 /* End of exported types -----------------------------------------------------*/
404 
405 /* Exported constants --------------------------------------------------------*/
413 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U
414 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U
422 #define TIM_DMABASE_CR1 0x00000000U
423 #define TIM_DMABASE_CR2 0x00000001U
424 #define TIM_DMABASE_SMCR 0x00000002U
425 #define TIM_DMABASE_DIER 0x00000003U
426 #define TIM_DMABASE_SR 0x00000004U
427 #define TIM_DMABASE_EGR 0x00000005U
428 #define TIM_DMABASE_CCMR1 0x00000006U
429 #define TIM_DMABASE_CCMR2 0x00000007U
430 #define TIM_DMABASE_CCER 0x00000008U
431 #define TIM_DMABASE_CNT 0x00000009U
432 #define TIM_DMABASE_PSC 0x0000000AU
433 #define TIM_DMABASE_ARR 0x0000000BU
434 #define TIM_DMABASE_RCR 0x0000000CU
435 #define TIM_DMABASE_CCR1 0x0000000DU
436 #define TIM_DMABASE_CCR2 0x0000000EU
437 #define TIM_DMABASE_CCR3 0x0000000FU
438 #define TIM_DMABASE_CCR4 0x00000010U
439 #define TIM_DMABASE_BDTR 0x00000011U
440 #define TIM_DMABASE_DCR 0x00000012U
441 #define TIM_DMABASE_DMAR 0x00000013U
442 
449 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
450 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
451 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
452 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
453 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
454 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
455 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
456 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
464 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U
465 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P
466 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
474 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP
475 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U
483 #define TIM_ETRPRESCALER_DIV1 0x00000000U
484 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0
485 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1
486 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS
494 #define TIM_COUNTERMODE_UP 0x00000000U
495 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
496 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
497 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
498 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
506 #define TIM_CLOCKDIVISION_DIV1 0x00000000U
507 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
508 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1
516 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U
517 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E
525 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U
526 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE
535 #define TIM_OCFAST_DISABLE 0x00000000U
536 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE
544 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U
545 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE
553 #define TIM_OCPOLARITY_HIGH 0x00000000U
554 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P
562 #define TIM_OCNPOLARITY_HIGH 0x00000000U
563 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP
571 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1
572 #define TIM_OCIDLESTATE_RESET 0x00000000U
580 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N
581 #define TIM_OCNIDLESTATE_RESET 0x00000000U
589 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
590 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
591 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
599 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
600 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
608 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0
610 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1
612 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S
620 #define TIM_ICPSC_DIV1 0x00000000U
621 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0
622 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1
623 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC
631 #define TIM_OPMODE_SINGLE TIM_CR1_OPM
632 #define TIM_OPMODE_REPETITIVE 0x00000000U
640 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0
641 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1
642 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
650 #define TIM_IT_UPDATE TIM_DIER_UIE
651 #define TIM_IT_CC1 TIM_DIER_CC1IE
652 #define TIM_IT_CC2 TIM_DIER_CC2IE
653 #define TIM_IT_CC3 TIM_DIER_CC3IE
654 #define TIM_IT_CC4 TIM_DIER_CC4IE
655 #define TIM_IT_COM TIM_DIER_COMIE
656 #define TIM_IT_TRIGGER TIM_DIER_TIE
657 #define TIM_IT_BREAK TIM_DIER_BIE
665 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS
666 #define TIM_COMMUTATION_SOFTWARE 0x00000000U
674 #define TIM_DMA_UPDATE TIM_DIER_UDE
675 #define TIM_DMA_CC1 TIM_DIER_CC1DE
676 #define TIM_DMA_CC2 TIM_DIER_CC2DE
677 #define TIM_DMA_CC3 TIM_DIER_CC3DE
678 #define TIM_DMA_CC4 TIM_DIER_CC4DE
679 #define TIM_DMA_COM TIM_DIER_COMDE
680 #define TIM_DMA_TRIGGER TIM_DIER_TDE
688 #define TIM_FLAG_UPDATE TIM_SR_UIF
689 #define TIM_FLAG_CC1 TIM_SR_CC1IF
690 #define TIM_FLAG_CC2 TIM_SR_CC2IF
691 #define TIM_FLAG_CC3 TIM_SR_CC3IF
692 #define TIM_FLAG_CC4 TIM_SR_CC4IF
693 #define TIM_FLAG_COM TIM_SR_COMIF
694 #define TIM_FLAG_TRIGGER TIM_SR_TIF
695 #define TIM_FLAG_BREAK TIM_SR_BIF
696 #define TIM_FLAG_CC1OF TIM_SR_CC1OF
697 #define TIM_FLAG_CC2OF TIM_SR_CC2OF
698 #define TIM_FLAG_CC3OF TIM_SR_CC3OF
699 #define TIM_FLAG_CC4OF TIM_SR_CC4OF
707 #define TIM_CHANNEL_1 0x00000000U
708 #define TIM_CHANNEL_2 0x00000004U
709 #define TIM_CHANNEL_3 0x00000008U
710 #define TIM_CHANNEL_4 0x0000000CU
711 #define TIM_CHANNEL_ALL 0x0000003CU
719 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1
720 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0
721 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0
722 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1
723 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2
724 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3
725 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED
726 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1
727 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2
728 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF
736 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
737 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
738 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
739 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
740 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
748 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
749 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
750 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
751 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
759 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
760 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
768 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
769 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
770 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
771 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
779 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR
780 #define TIM_OSSR_DISABLE 0x00000000U
788 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI
789 #define TIM_OSSI_DISABLE 0x00000000U
796 #define TIM_LOCKLEVEL_OFF 0x00000000U
797 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
798 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
799 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK
807 #define TIM_BREAK_ENABLE TIM_BDTR_BKE
808 #define TIM_BREAK_DISABLE 0x00000000U
816 #define TIM_BREAKPOLARITY_LOW 0x00000000U
817 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP
825 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
826 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE
835 #define TIM_TRGO_RESET 0x00000000U
836 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0
837 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1
838 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
839 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2
840 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
841 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
842 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
850 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM
851 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
859 #define TIM_SLAVEMODE_DISABLE 0x00000000U
860 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
861 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
862 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
863 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
871 #define TIM_OCMODE_TIMING 0x00000000U
872 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
873 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
874 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
875 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
876 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
877 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
878 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
886 #define TIM_TS_ITR0 0x00000000U
887 #define TIM_TS_ITR1 TIM_SMCR_TS_0
888 #define TIM_TS_ITR2 TIM_SMCR_TS_1
889 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
890 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2
891 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
892 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
893 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
894 #define TIM_TS_NONE 0x0000FFFFU
902 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
903 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
904 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
905 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
906 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
914 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
915 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
916 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
917 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
925 #define TIM_TI1SELECTION_CH1 0x00000000U
926 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S
934 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
935 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
936 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
937 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
938 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
939 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
940 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
941 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
942 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
943 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
944 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
945 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
946 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
947 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
948 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
949 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
950 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
951 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
959 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)
960 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001)
961 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002)
962 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003)
963 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004)
964 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005)
965 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)
973 #define TIM_CCx_ENABLE 0x00000001U
974 #define TIM_CCx_DISABLE 0x00000000U
975 #define TIM_CCxN_ENABLE 0x00000004U
976 #define TIM_CCxN_DISABLE 0x00000000U
984 /* End of exported constants -------------------------------------------------*/
985 
986 /* Exported macros -----------------------------------------------------------*/
995 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
996 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
997  (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
998  (__HANDLE__)->Base_MspInitCallback = NULL; \
999  (__HANDLE__)->Base_MspDeInitCallback = NULL; \
1000  (__HANDLE__)->IC_MspInitCallback = NULL; \
1001  (__HANDLE__)->IC_MspDeInitCallback = NULL; \
1002  (__HANDLE__)->OC_MspInitCallback = NULL; \
1003  (__HANDLE__)->OC_MspDeInitCallback = NULL; \
1004  (__HANDLE__)->PWM_MspInitCallback = NULL; \
1005  (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
1006  (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
1007  (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
1008  (__HANDLE__)->Encoder_MspInitCallback = NULL; \
1009  (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
1010  (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
1011  (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
1012  } while(0)
1013 #else
1014 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
1015 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1016 
1022 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1023 
1029 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
1030 
1036 #define __HAL_TIM_DISABLE(__HANDLE__) \
1037  do { \
1038  if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1039  { \
1040  if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1041  { \
1042  (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1043  } \
1044  } \
1045  } while(0)
1046 
1053 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
1054  do { \
1055  if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1056  { \
1057  if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1058  { \
1059  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
1060  } \
1061  } \
1062  } while(0)
1063 
1070 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
1071 
1086 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1087 
1102 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1103 
1117 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
1118 
1132 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1133 
1152 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1153 
1172 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1173 
1189 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
1190  == (__INTERRUPT__)) ? SET : RESET)
1191 
1206 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1207 
1215 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
1216 
1223 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1224 
1231 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1232 
1238 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
1239 
1246 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1247  do{ \
1248  (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1249  (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1250  } while(0)
1251 
1257 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
1258 
1269 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1270  do{ \
1271  (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
1272  (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1273  (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1274  } while(0)
1275 
1284 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1285 
1303 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1304  do{ \
1305  TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
1306  TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1307  } while(0)
1308 
1324 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
1325  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1326  ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
1327  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1328  (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
1329 
1342 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
1343  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
1344  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
1345  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
1346  ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
1347 
1359 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
1360  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
1361  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
1362  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
1363  ((__HANDLE__)->Instance->CCR4))
1364 
1376 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1377  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
1378  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
1379  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
1380  ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
1381 
1393 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1394  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
1395  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
1396  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
1397  ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
1398 
1414 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
1415  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
1416  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
1417  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
1418  ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
1419 
1435 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
1436  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
1437  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
1438  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
1439  ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
1440 
1449 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
1450 
1462 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
1463 
1479 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1480  do{ \
1481  TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
1482  TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1483  }while(0)
1484 
1488 /* End of exported macros ----------------------------------------------------*/
1489 
1490 /* Private constants ---------------------------------------------------------*/
1494 /* The counter of a timer instance is disabled only if all the CCx and CCxN
1495  channels have been disabled */
1496 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1497 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
1498 
1501 /* End of private constants --------------------------------------------------*/
1502 
1503 /* Private macros ------------------------------------------------------------*/
1507 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
1508  ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
1509 
1510 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
1511  ((__BASE__) == TIM_DMABASE_CR2) || \
1512  ((__BASE__) == TIM_DMABASE_SMCR) || \
1513  ((__BASE__) == TIM_DMABASE_DIER) || \
1514  ((__BASE__) == TIM_DMABASE_SR) || \
1515  ((__BASE__) == TIM_DMABASE_EGR) || \
1516  ((__BASE__) == TIM_DMABASE_CCMR1) || \
1517  ((__BASE__) == TIM_DMABASE_CCMR2) || \
1518  ((__BASE__) == TIM_DMABASE_CCER) || \
1519  ((__BASE__) == TIM_DMABASE_CNT) || \
1520  ((__BASE__) == TIM_DMABASE_PSC) || \
1521  ((__BASE__) == TIM_DMABASE_ARR) || \
1522  ((__BASE__) == TIM_DMABASE_RCR) || \
1523  ((__BASE__) == TIM_DMABASE_CCR1) || \
1524  ((__BASE__) == TIM_DMABASE_CCR2) || \
1525  ((__BASE__) == TIM_DMABASE_CCR3) || \
1526  ((__BASE__) == TIM_DMABASE_CCR4) || \
1527  ((__BASE__) == TIM_DMABASE_BDTR))
1528 
1529 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1530 
1531 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
1532  ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
1533  ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
1534  ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
1535  ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
1536 
1537 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
1538  ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
1539  ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
1540 
1541 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
1542  ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
1543 
1544 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
1545  ((__STATE__) == TIM_OCFAST_ENABLE))
1546 
1547 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
1548  ((__POLARITY__) == TIM_OCPOLARITY_LOW))
1549 
1550 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
1551  ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
1552 
1553 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
1554  ((__STATE__) == TIM_OCIDLESTATE_RESET))
1555 
1556 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
1557  ((__STATE__) == TIM_OCNIDLESTATE_RESET))
1558 
1559 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
1560  ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
1561 
1562 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
1563  ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
1564  ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
1565 
1566 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
1567  ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
1568  ((__SELECTION__) == TIM_ICSELECTION_TRC))
1569 
1570 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
1571  ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
1572  ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
1573  ((__PRESCALER__) == TIM_ICPSC_DIV8))
1574 
1575 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
1576  ((__MODE__) == TIM_OPMODE_REPETITIVE))
1577 
1578 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
1579  ((__MODE__) == TIM_ENCODERMODE_TI2) || \
1580  ((__MODE__) == TIM_ENCODERMODE_TI12))
1581 
1582 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1583 
1584 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1585  ((__CHANNEL__) == TIM_CHANNEL_2) || \
1586  ((__CHANNEL__) == TIM_CHANNEL_3) || \
1587  ((__CHANNEL__) == TIM_CHANNEL_4) || \
1588  ((__CHANNEL__) == TIM_CHANNEL_ALL))
1589 
1590 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1591  ((__CHANNEL__) == TIM_CHANNEL_2))
1592 
1593 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1594  ((__CHANNEL__) == TIM_CHANNEL_2) || \
1595  ((__CHANNEL__) == TIM_CHANNEL_3))
1596 
1597 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
1598  ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
1599  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
1600  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
1601  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
1602  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
1603  ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
1604  ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
1605  ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
1606  ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
1607 
1608 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
1609  ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
1610  ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
1611  ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
1612  ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
1613 
1614 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
1615  ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
1616  ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
1617  ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
1618 
1619 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1620 
1621 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
1622  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
1623 
1624 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
1625  ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
1626  ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
1627  ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
1628 
1629 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1630 
1631 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
1632  ((__STATE__) == TIM_OSSR_DISABLE))
1633 
1634 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
1635  ((__STATE__) == TIM_OSSI_DISABLE))
1636 
1637 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
1638  ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
1639  ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
1640  ((__LEVEL__) == TIM_LOCKLEVEL_3))
1641 
1642 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
1643 
1644 
1645 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
1646  ((__STATE__) == TIM_BREAK_DISABLE))
1647 
1648 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
1649  ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
1650 
1651 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
1652  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
1653 
1654 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
1655  ((__SOURCE__) == TIM_TRGO_ENABLE) || \
1656  ((__SOURCE__) == TIM_TRGO_UPDATE) || \
1657  ((__SOURCE__) == TIM_TRGO_OC1) || \
1658  ((__SOURCE__) == TIM_TRGO_OC1REF) || \
1659  ((__SOURCE__) == TIM_TRGO_OC2REF) || \
1660  ((__SOURCE__) == TIM_TRGO_OC3REF) || \
1661  ((__SOURCE__) == TIM_TRGO_OC4REF))
1662 
1663 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
1664  ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
1665 
1666 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
1667  ((__MODE__) == TIM_SLAVEMODE_RESET) || \
1668  ((__MODE__) == TIM_SLAVEMODE_GATED) || \
1669  ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
1670  ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
1671 
1672 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
1673  ((__MODE__) == TIM_OCMODE_PWM2))
1674 
1675 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
1676  ((__MODE__) == TIM_OCMODE_ACTIVE) || \
1677  ((__MODE__) == TIM_OCMODE_INACTIVE) || \
1678  ((__MODE__) == TIM_OCMODE_TOGGLE) || \
1679  ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
1680  ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
1681 
1682 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1683  ((__SELECTION__) == TIM_TS_ITR1) || \
1684  ((__SELECTION__) == TIM_TS_ITR2) || \
1685  ((__SELECTION__) == TIM_TS_ITR3) || \
1686  ((__SELECTION__) == TIM_TS_TI1F_ED) || \
1687  ((__SELECTION__) == TIM_TS_TI1FP1) || \
1688  ((__SELECTION__) == TIM_TS_TI2FP2) || \
1689  ((__SELECTION__) == TIM_TS_ETRF))
1690 
1691 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1692  ((__SELECTION__) == TIM_TS_ITR1) || \
1693  ((__SELECTION__) == TIM_TS_ITR2) || \
1694  ((__SELECTION__) == TIM_TS_ITR3) || \
1695  ((__SELECTION__) == TIM_TS_NONE))
1696 
1697 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
1698  ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
1699  ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
1700  ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
1701  ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
1702 
1703 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
1704  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
1705  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
1706  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
1707 
1708 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1709 
1710 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
1711  ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
1712 
1713 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
1714  ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
1715  ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
1716  ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
1717  ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
1718  ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
1719  ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
1720  ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
1721  ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
1722  ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
1723  ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
1724  ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
1725  ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
1726  ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
1727  ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
1728  ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
1729  ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
1730  ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
1731 
1732 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1733 
1734 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
1735 
1736 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
1737 
1738 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
1739  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
1740  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
1741  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
1742  ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
1743 
1744 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
1745  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
1746  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
1747  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
1748  ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
1749 
1750 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1751  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
1752  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
1753  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
1754  ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
1755 
1756 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
1757  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
1758  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
1759  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
1760  ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
1761 
1765 /* End of private macros -----------------------------------------------------*/
1766 
1767 /* Include TIM HAL Extended module */
1768 #include "stm32f4xx_hal_tim_ex.h"
1769 
1770 /* Exported functions --------------------------------------------------------*/
1779 /* Time Base functions ********************************************************/
1780 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
1781 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
1782 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
1783 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
1784 /* Blocking mode: Polling */
1785 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
1786 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
1787 /* Non-Blocking mode: Interrupt */
1788 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
1789 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
1790 /* Non-Blocking mode: DMA */
1791 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
1792 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
1801 /* Timer Output Compare functions *********************************************/
1802 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
1803 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
1804 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
1805 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
1806 /* Blocking mode: Polling */
1807 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1808 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1809 /* Non-Blocking mode: Interrupt */
1810 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1811 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1812 /* Non-Blocking mode: DMA */
1813 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1814 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1823 /* Timer PWM functions ********************************************************/
1824 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
1825 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
1826 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
1827 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
1828 /* Blocking mode: Polling */
1829 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1830 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1831 /* Non-Blocking mode: Interrupt */
1832 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1833 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1834 /* Non-Blocking mode: DMA */
1835 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1836 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1845 /* Timer Input Capture functions **********************************************/
1846 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
1847 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
1848 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
1849 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
1850 /* Blocking mode: Polling */
1851 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1852 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1853 /* Non-Blocking mode: Interrupt */
1854 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1855 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1856 /* Non-Blocking mode: DMA */
1857 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1858 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1867 /* Timer One Pulse functions **************************************************/
1868 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
1869 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
1870 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
1871 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
1872 /* Blocking mode: Polling */
1873 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1874 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1875 /* Non-Blocking mode: Interrupt */
1876 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1877 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1886 /* Timer Encoder functions ****************************************************/
1887 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
1888 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
1889 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
1890 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
1891 /* Blocking mode: Polling */
1892 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1893 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1894 /* Non-Blocking mode: Interrupt */
1895 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1896 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1897 /* Non-Blocking mode: DMA */
1898 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
1899  uint32_t *pData2, uint16_t Length);
1900 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1909 /* Interrupt Handler functions ***********************************************/
1910 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
1919 /* Control functions *********************************************************/
1920 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
1921 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
1922 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
1923 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
1924  uint32_t OutputChannel, uint32_t InputChannel);
1925 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
1926  uint32_t Channel);
1927 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
1928 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
1929 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
1930 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
1931 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
1932  uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
1933 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1934 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
1935  uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
1936 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1937 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
1938 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
1947 /* Callback in non blocking modes (Interrupt and DMA) *************************/
1948 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
1949 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
1950 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
1951 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
1952 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
1953 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
1954 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
1955 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
1956 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
1957 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
1958 
1959 /* Callbacks Register/UnRegister functions ***********************************/
1960 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1961 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
1962  pTIM_CallbackTypeDef pCallback);
1963 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
1964 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1965 
1974 /* Peripheral State functions ************************************************/
1975 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
1976 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
1977 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
1978 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
1979 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
1980 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
1988 /* End of exported functions -------------------------------------------------*/
1989 
1990 /* Private functions----------------------------------------------------------*/
1994 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
1995 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
1996 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1997 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
1998  uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
1999 
2000 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
2001 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
2002 void TIM_DMAError(DMA_HandleTypeDef *hdma);
2003 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
2004 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
2005 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
2006 
2007 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2008 void TIM_ResetCallback(TIM_HandleTypeDef *htim);
2009 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2010 
2014 /* End of private functions --------------------------------------------------*/
2015 
2024 #ifdef __cplusplus
2025 }
2026 #endif
2027 
2028 #endif /* STM32F4xx_HAL_TIM_H */
2029 
2030 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_TIM_TriggerHalfCpltCallback
void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
HAL_TIM_STATE_TIMEOUT
@ HAL_TIM_STATE_TIMEOUT
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:293
TIM_SlaveConfigTypeDef::SlaveMode
uint32_t SlaveMode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:247
TIM_IC_InitTypeDef::ICPrescaler
uint32_t ICPrescaler
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:154
TIM_OC_InitTypeDef::Pulse
uint32_t Pulse
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:83
TIM_OC_InitTypeDef::OCFastMode
uint32_t OCFastMode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:93
HAL_TIM_IC_Start_DMA
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
TIM_MasterConfigTypeDef::MasterOutputTrigger
uint32_t MasterOutputTrigger
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:231
TIM_OC_InitTypeDef::OCMode
uint32_t OCMode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:80
TIM_DMACaptureHalfCplt
void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
HAL_TIM_Encoder_Init
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
TIM_SlaveConfigTypeDef::TriggerPrescaler
uint32_t TriggerPrescaler
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:253
TIM_BreakDeadTimeConfigTypeDef::BreakState
uint32_t BreakState
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:275
HAL_TIM_ActiveChannel
HAL_TIM_ActiveChannel
HAL Active channel structures definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:300
HAL_TIM_Base_Stop_IT
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:139
TIM_CCxChannelCmd
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
HAL_TIM_OC_GetState
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
HAL_TIM_PWM_PulseFinishedHalfCpltCallback
void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
TIM_ClearInputConfigTypeDef::ClearInputPrescaler
uint32_t ClearInputPrescaler
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:220
HAL_TIM_IRQHandler
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
HAL_TIM_ConfigTI1Input
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
HAL_TIM_PWM_ConfigChannel
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
TIM_IC_InitTypeDef::ICPolarity
uint32_t ICPolarity
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:148
HAL_TIM_OnePulse_Stop
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
HAL_TIM_OnePulse_Stop_IT
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
TIM_Encoder_InitTypeDef::IC2Polarity
uint32_t IC2Polarity
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:181
HAL_TIM_IC_GetState
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
TIM_Base_InitTypeDef::CounterMode
uint32_t CounterMode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:52
TIM_IC_InitTypeDef::ICFilter
uint32_t ICFilter
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:157
HAL_TIM_OC_Stop_DMA
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
TIM_ETR_SetConfig
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
HAL_TIM_ReadCapturedValue
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
TIM_Encoder_InitTypeDef::IC2Selection
uint32_t IC2Selection
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:184
TIM_OC_InitTypeDef::OCNPolarity
uint32_t OCNPolarity
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:89
HAL_TIM_OnePulse_Start
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
TIM_OnePulse_InitTypeDef::OCPolarity
uint32_t OCPolarity
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:118
TIM_Encoder_InitTypeDef::IC2Prescaler
uint32_t IC2Prescaler
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:187
HAL_TIM_ACTIVE_CHANNEL_3
@ HAL_TIM_ACTIVE_CHANNEL_3
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:304
TIM_OC_InitTypeDef::OCIdleState
uint32_t OCIdleState
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:98
HAL_TIM_IC_MspDeInit
void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
HAL_TIM_OC_ConfigChannel
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
TIM_DMAError
void TIM_DMAError(DMA_HandleTypeDef *hdma)
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:51
TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:164
HAL_TIM_TriggerCallback
void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
TIM_MasterConfigTypeDef::MasterSlaveMode
uint32_t MasterSlaveMode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:233
HAL_TIM_IC_Start_IT
HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
TIM_Base_InitTypeDef::ClockDivision
uint32_t ClockDivision
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:59
HAL_TIM_OnePulse_MspInit
void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
HAL_TIM_PeriodElapsedHalfCpltCallback
void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
TIM_ClockConfigTypeDef::ClockPolarity
uint32_t ClockPolarity
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:201
TIM_OnePulse_InitTypeDef::Pulse
uint32_t Pulse
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:115
HAL_TIM_Base_Start
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
TIM_Encoder_InitTypeDef::IC1Prescaler
uint32_t IC1Prescaler
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:175
HAL_TIM_DMABurst_ReadStart
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
TIM_Base_InitTypeDef::Period
uint32_t Period
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:55
HAL_TIM_ErrorCallback
void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
HAL_TIM_Base_Init
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
TIM_ClockConfigTypeDef::ClockPrescaler
uint32_t ClockPrescaler
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:203
TIM_Encoder_InitTypeDef::EncoderMode
uint32_t EncoderMode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:166
TIM_IC_InitTypeDef::ICSelection
uint32_t ICSelection
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:151
TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:146
HAL_TIM_SlaveConfigSynchro_IT
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
HAL_TIM_PeriodElapsedCallback
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
TIM_ClearInputConfigTypeDef::ClearInputPolarity
uint32_t ClearInputPolarity
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:218
TIM_Encoder_InitTypeDef::IC1Filter
uint32_t IC1Filter
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:178
TIM_TypeDef
TIM.
Definition: stm32f407xx.h:729
HAL_TIM_OC_DelayElapsedCallback
void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput
uint32_t AutomaticOutput
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:281
HAL_TIM_OC_Stop_IT
HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:47
TIM_HandleTypeDef::Instance
TIM_TypeDef * Instance
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:318
HAL_TIM_IC_Init
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
TIM_SlaveConfigTypeDef::TriggerFilter
uint32_t TriggerFilter
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:255
HAL_TIM_Encoder_Stop
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_PWM_Start
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
TIM_ClockConfigTypeDef::ClockSource
uint32_t ClockSource
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:199
HAL_TIM_ACTIVE_CHANNEL_2
@ HAL_TIM_ACTIVE_CHANNEL_2
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:303
HAL_TIM_OnePulse_DeInit
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
HAL_TIM_Encoder_Start_IT
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_STATE_RESET
@ HAL_TIM_STATE_RESET
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:290
TIM_DMADelayPulseCplt
void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
HAL_TIM_Base_MspInit
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
TIM_OnePulse_InitTypeDef::OCNPolarity
uint32_t OCNPolarity
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:121
HAL_TIM_Base_GetState
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
HAL_TIM_Encoder_DeInit
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
HAL_TIM_IC_Stop_DMA
HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:78
TIM_Encoder_InitTypeDef::IC1Polarity
uint32_t IC1Polarity
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:169
HAL_TIM_OC_Start_DMA
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
TIM_HandleTypeDef
TIM Time Base Handle Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:315
HAL_TIM_GenerateEvent
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
HAL_TIM_Base_Stop
HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode
uint32_t OffStateIDLEMode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:269
TIM_HandleTypeDef::Channel
HAL_TIM_ActiveChannel Channel
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:320
TIM_OnePulse_InitTypeDef::OCNIdleState
uint32_t OCNIdleState
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:129
TIM_OnePulse_InitTypeDef::ICSelection
uint32_t ICSelection
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:136
HAL_TIM_PWM_PulseFinishedCallback
void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
HAL_TIM_PWM_MspDeInit
void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:197
HAL_TIM_OC_Stop
HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
TIM_ClearInputConfigTypeDef::ClearInputSource
uint32_t ClearInputSource
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:216
HAL_TIM_IC_Stop_IT
HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
TIM_ClearInputConfigTypeDef::ClearInputState
uint32_t ClearInputState
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:214
HAL_TIM_OnePulse_ConfigChannel
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
HAL_TIM_Encoder_MspDeInit
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
TIM_Base_InitTypeDef::AutoReloadPreload
uint32_t AutoReloadPreload
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:71
HAL_TIM_StateTypeDef
HAL_TIM_StateTypeDef
HAL State structures definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:288
HAL_TIM_Encoder_Stop_IT
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_ConfigClockSource
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
TIM_SlaveConfigTypeDef::InputTrigger
uint32_t InputTrigger
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:249
TIM_OnePulse_InitTypeDef::ICFilter
uint32_t ICFilter
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:139
TIM_BreakDeadTimeConfigTypeDef::DeadTime
uint32_t DeadTime
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:273
HAL_TIM_PWM_Init
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
TIM_Base_InitTypeDef::Prescaler
uint32_t Prescaler
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:49
TIM_Base_SetConfig
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
HAL_TIM_ACTIVE_CHANNEL_CLEARED
@ HAL_TIM_ACTIVE_CHANNEL_CLEARED
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:306
HAL_TIM_IC_Stop
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_IC_DeInit
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
HAL_TIM_IC_ConfigChannel
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
HAL_TIM_STATE_ERROR
@ HAL_TIM_STATE_ERROR
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:294
HAL_TIM_Encoder_MspInit
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
HAL_TIM_OC_Init
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
TIM_ClearInputConfigTypeDef::ClearInputFilter
uint32_t ClearInputFilter
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:222
HAL_TIM_IC_CaptureCallback
void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
TIM_OC2_SetConfig
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM_Encoder_InitTypeDef::IC2Filter
uint32_t IC2Filter
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:190
TIM_SlaveConfigTypeDef::TriggerPolarity
uint32_t TriggerPolarity
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:251
TIM_DMADelayPulseHalfCplt
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
HAL_TIM_OC_MspDeInit
void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
HAL_TIM_PWM_Stop
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_OC_Start
HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_Encoder_Stop_DMA
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_SlaveConfigSynchro
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
TIM_MasterConfigTypeDef
TIM Master configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:229
HAL_TIM_PWM_Start_IT
HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_OnePulse_Start_IT
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
HAL_TIM_PWM_Stop_DMA
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_Encoder_Start
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
TIM_OnePulse_InitTypeDef::OCIdleState
uint32_t OCIdleState
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:125
stm32f4xx_hal_tim_ex.h
Header file of TIM HAL Extended module.
HAL_TIM_Base_MspDeInit
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
HAL_TIM_STATE_BUSY
@ HAL_TIM_STATE_BUSY
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:292
TIM_ClockConfigTypeDef::ClockFilter
uint32_t ClockFilter
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:205
TIM_OnePulse_InitTypeDef::ICPolarity
uint32_t ICPolarity
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:133
HAL_TIM_IC_Start
HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_Encoder_Start_DMA
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
TIM_BreakDeadTimeConfigTypeDef::BreakPolarity
uint32_t BreakPolarity
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:277
TIM_Base_InitTypeDef::RepetitionCounter
uint32_t RepetitionCounter
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:62
TIM_OnePulse_InitTypeDef::OCMode
uint32_t OCMode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:112
TIM_HandleTypeDef::Init
TIM_Base_InitTypeDef Init
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:319
TIM_DMACaptureCplt
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
TIM_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:323
HAL_TIM_PWM_MspInit
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
HAL_TIM_OC_Start_IT
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_DMABurst_WriteStart
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
HAL_TIM_OnePulse_MspDeInit
void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
HAL_TIM_DMABurst_WriteStop
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
HAL_TIM_OC_MspInit
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
HAL_TIM_ConfigOCrefClear
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
HAL_TIM_Encoder_GetState
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
HAL_TIM_PWM_Stop_IT
HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
TIM_ClearInputConfigTypeDef
TIM Clear Input Configuration Handle Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:212
TIM_BreakDeadTimeConfigTypeDef::LockLevel
uint32_t LockLevel
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:271
TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode
uint32_t OffStateRunMode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:267
TIM_OC_InitTypeDef::OCNIdleState
uint32_t OCNIdleState
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:102
HAL_TIM_OnePulse_Init
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:110
HAL_TIM_OnePulse_GetState
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
HAL_TIM_PWM_Start_DMA
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
TIM_BreakDeadTimeConfigTypeDef::BreakFilter
uint32_t BreakFilter
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:279
HAL_TIM_OC_DeInit
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
HAL_TIM_DMABurst_ReadStop
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
HAL_TIM_IC_CaptureHalfCpltCallback
void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
HAL_TIM_IC_MspInit
void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
HAL_TIM_Base_Start_DMA
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
HAL_TIM_PWM_DeInit
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
TIM_Encoder_InitTypeDef::IC1Selection
uint32_t IC1Selection
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:172
TIM_HandleTypeDef::State
__IO HAL_TIM_StateTypeDef State
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:324
TIM_OC_InitTypeDef::OCPolarity
uint32_t OCPolarity
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:86
TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:265
HAL_TIM_Base_Stop_DMA
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
HAL_TIM_Base_Start_IT
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
HAL_TIM_STATE_READY
@ HAL_TIM_STATE_READY
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:291
HAL_TIM_PWM_GetState
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
HAL_TIM_ACTIVE_CHANNEL_4
@ HAL_TIM_ACTIVE_CHANNEL_4
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:305
TIM_TI1_SetConfig
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
HAL_TIM_ACTIVE_CHANNEL_1
@ HAL_TIM_ACTIVE_CHANNEL_1
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:302
TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:245
HAL_TIM_Base_DeInit
HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)

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autogenerated on Fri Apr 1 2022 02:14:52