stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F4xx_HAL_DMA_H
22 #define __STM32F4xx_HAL_DMA_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f4xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
40 
49 typedef struct
50 {
51  uint32_t Channel;
54  uint32_t Direction;
58  uint32_t PeriphInc;
61  uint32_t MemInc;
64  uint32_t PeriphDataAlignment;
67  uint32_t MemDataAlignment;
70  uint32_t Mode;
75  uint32_t Priority;
78  uint32_t FIFOMode;
83  uint32_t FIFOThreshold;
86  uint32_t MemBurst;
92  uint32_t PeriphBurst;
97 }DMA_InitTypeDef;
98 
99 
103 typedef enum
104 {
105  HAL_DMA_STATE_RESET = 0x00U,
106  HAL_DMA_STATE_READY = 0x01U,
107  HAL_DMA_STATE_BUSY = 0x02U,
108  HAL_DMA_STATE_TIMEOUT = 0x03U,
109  HAL_DMA_STATE_ERROR = 0x04U,
110  HAL_DMA_STATE_ABORT = 0x05U,
111 }HAL_DMA_StateTypeDef;
112 
116 typedef enum
117 {
118  HAL_DMA_FULL_TRANSFER = 0x00U,
119  HAL_DMA_HALF_TRANSFER = 0x01U
120 }HAL_DMA_LevelCompleteTypeDef;
121 
125 typedef enum
126 {
127  HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
128  HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
129  HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
130  HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
131  HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
132  HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
133  HAL_DMA_XFER_ALL_CB_ID = 0x06U
134 }HAL_DMA_CallbackIDTypeDef;
135 
139 typedef struct __DMA_HandleTypeDef
140 {
141  DMA_Stream_TypeDef *Instance;
143  DMA_InitTypeDef Init;
145  HAL_LockTypeDef Lock;
147  __IO HAL_DMA_StateTypeDef State;
149  void *Parent;
151  void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);
153  void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);
155  void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);
157  void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);
159  void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);
161  void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);
163  __IO uint32_t ErrorCode;
165  uint32_t StreamBaseAddress;
167  uint32_t StreamIndex;
169 }DMA_HandleTypeDef;
170 
175 /* Exported constants --------------------------------------------------------*/
176 
186 #define HAL_DMA_ERROR_NONE 0x00000000U
187 #define HAL_DMA_ERROR_TE 0x00000001U
188 #define HAL_DMA_ERROR_FE 0x00000002U
189 #define HAL_DMA_ERROR_DME 0x00000004U
190 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U
191 #define HAL_DMA_ERROR_PARAM 0x00000040U
192 #define HAL_DMA_ERROR_NO_XFER 0x00000080U
193 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U
202 #define DMA_CHANNEL_0 0x00000000U
203 #define DMA_CHANNEL_1 0x02000000U
204 #define DMA_CHANNEL_2 0x04000000U
205 #define DMA_CHANNEL_3 0x06000000U
206 #define DMA_CHANNEL_4 0x08000000U
207 #define DMA_CHANNEL_5 0x0A000000U
208 #define DMA_CHANNEL_6 0x0C000000U
209 #define DMA_CHANNEL_7 0x0E000000U
210 #if defined (DMA_SxCR_CHSEL_3)
211 #define DMA_CHANNEL_8 0x10000000U
212 #define DMA_CHANNEL_9 0x12000000U
213 #define DMA_CHANNEL_10 0x14000000U
214 #define DMA_CHANNEL_11 0x16000000U
215 #define DMA_CHANNEL_12 0x18000000U
216 #define DMA_CHANNEL_13 0x1A000000U
217 #define DMA_CHANNEL_14 0x1C000000U
218 #define DMA_CHANNEL_15 0x1E000000U
219 #endif /* DMA_SxCR_CHSEL_3 */
220 
228 #define DMA_PERIPH_TO_MEMORY 0x00000000U
229 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)
230 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)
239 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)
240 #define DMA_PINC_DISABLE 0x00000000U
249 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)
250 #define DMA_MINC_DISABLE 0x00000000U
259 #define DMA_PDATAALIGN_BYTE 0x00000000U
260 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)
261 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)
270 #define DMA_MDATAALIGN_BYTE 0x00000000U
271 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)
272 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)
281 #define DMA_NORMAL 0x00000000U
282 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)
283 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)
292 #define DMA_PRIORITY_LOW 0x00000000U
293 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)
294 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)
295 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)
304 #define DMA_FIFOMODE_DISABLE 0x00000000U
305 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)
314 #define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U
315 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)
316 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)
317 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)
326 #define DMA_MBURST_SINGLE 0x00000000U
327 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
328 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
329 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
330 
338 #define DMA_PBURST_SINGLE 0x00000000U
339 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
340 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
341 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
342 
350 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
351 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
352 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
353 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
354 #define DMA_IT_FE 0x00000080U
355 
363 #define DMA_FLAG_FEIF0_4 0x00000001U
364 #define DMA_FLAG_DMEIF0_4 0x00000004U
365 #define DMA_FLAG_TEIF0_4 0x00000008U
366 #define DMA_FLAG_HTIF0_4 0x00000010U
367 #define DMA_FLAG_TCIF0_4 0x00000020U
368 #define DMA_FLAG_FEIF1_5 0x00000040U
369 #define DMA_FLAG_DMEIF1_5 0x00000100U
370 #define DMA_FLAG_TEIF1_5 0x00000200U
371 #define DMA_FLAG_HTIF1_5 0x00000400U
372 #define DMA_FLAG_TCIF1_5 0x00000800U
373 #define DMA_FLAG_FEIF2_6 0x00010000U
374 #define DMA_FLAG_DMEIF2_6 0x00040000U
375 #define DMA_FLAG_TEIF2_6 0x00080000U
376 #define DMA_FLAG_HTIF2_6 0x00100000U
377 #define DMA_FLAG_TCIF2_6 0x00200000U
378 #define DMA_FLAG_FEIF3_7 0x00400000U
379 #define DMA_FLAG_DMEIF3_7 0x01000000U
380 #define DMA_FLAG_TEIF3_7 0x02000000U
381 #define DMA_FLAG_HTIF3_7 0x04000000U
382 #define DMA_FLAG_TCIF3_7 0x08000000U
383 
391 /* Exported macro ------------------------------------------------------------*/
392 
397 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
398 
411 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
412 
418 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
419 
425 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
426 
427 /* Interrupt & Flag management */
428 
434 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
435 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
436  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
437  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
438  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
439  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
440  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
441  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
442  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
443  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
444  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
445  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
446  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
447  DMA_FLAG_TCIF3_7)
448 
454 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
455 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
456  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
457  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
458  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
459  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
460  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
461  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
462  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
463  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
464  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
465  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
466  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
467  DMA_FLAG_HTIF3_7)
468 
474 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
475 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
476  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
477  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
478  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
479  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
480  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
481  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
482  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
483  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
484  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
485  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
486  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
487  DMA_FLAG_TEIF3_7)
488 
494 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
495 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
496  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
497  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
498  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
499  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
500  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
501  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
502  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
503  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
504  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
505  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
506  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
507  DMA_FLAG_FEIF3_7)
508 
514 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
515 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
516  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
517  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
518  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
519  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
520  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
521  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
522  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
523  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
524  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
525  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
526  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
527  DMA_FLAG_DMEIF3_7)
528 
542 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
543 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
544  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
545  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
546 
560 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
561 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
562  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
563  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
564 
577 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
578 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
579 
592 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
593 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
594 
607 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
608  ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
609  ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
610 
628 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
629 
636 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
637 
638 
639 /* Include DMA HAL Extension module */
640 #include "stm32f4xx_hal_dma_ex.h"
641 
642 /* Exported functions --------------------------------------------------------*/
643 
653 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
654 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
663 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
664 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
665 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
666 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
667 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
668 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
669 HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
670 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
671 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
672 
681 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
682 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
689 /* Private Constants -------------------------------------------------------------*/
698 /* Private macros ------------------------------------------------------------*/
703 #if defined (DMA_SxCR_CHSEL_3)
704 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
705  ((CHANNEL) == DMA_CHANNEL_1) || \
706  ((CHANNEL) == DMA_CHANNEL_2) || \
707  ((CHANNEL) == DMA_CHANNEL_3) || \
708  ((CHANNEL) == DMA_CHANNEL_4) || \
709  ((CHANNEL) == DMA_CHANNEL_5) || \
710  ((CHANNEL) == DMA_CHANNEL_6) || \
711  ((CHANNEL) == DMA_CHANNEL_7) || \
712  ((CHANNEL) == DMA_CHANNEL_8) || \
713  ((CHANNEL) == DMA_CHANNEL_9) || \
714  ((CHANNEL) == DMA_CHANNEL_10)|| \
715  ((CHANNEL) == DMA_CHANNEL_11)|| \
716  ((CHANNEL) == DMA_CHANNEL_12)|| \
717  ((CHANNEL) == DMA_CHANNEL_13)|| \
718  ((CHANNEL) == DMA_CHANNEL_14)|| \
719  ((CHANNEL) == DMA_CHANNEL_15))
720 #else
721 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
722  ((CHANNEL) == DMA_CHANNEL_1) || \
723  ((CHANNEL) == DMA_CHANNEL_2) || \
724  ((CHANNEL) == DMA_CHANNEL_3) || \
725  ((CHANNEL) == DMA_CHANNEL_4) || \
726  ((CHANNEL) == DMA_CHANNEL_5) || \
727  ((CHANNEL) == DMA_CHANNEL_6) || \
728  ((CHANNEL) == DMA_CHANNEL_7))
729 #endif /* DMA_SxCR_CHSEL_3 */
730 
731 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
732  ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
733  ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
734 
735 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
736 
737 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
738  ((STATE) == DMA_PINC_DISABLE))
739 
740 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
741  ((STATE) == DMA_MINC_DISABLE))
742 
743 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
744  ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
745  ((SIZE) == DMA_PDATAALIGN_WORD))
746 
747 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
748  ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
749  ((SIZE) == DMA_MDATAALIGN_WORD ))
750 
751 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
752  ((MODE) == DMA_CIRCULAR) || \
753  ((MODE) == DMA_PFCTRL))
754 
755 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
756  ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
757  ((PRIORITY) == DMA_PRIORITY_HIGH) || \
758  ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
759 
760 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
761  ((STATE) == DMA_FIFOMODE_ENABLE))
762 
763 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
764  ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
765  ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
766  ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
767 
768 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
769  ((BURST) == DMA_MBURST_INC4) || \
770  ((BURST) == DMA_MBURST_INC8) || \
771  ((BURST) == DMA_MBURST_INC16))
772 
773 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
774  ((BURST) == DMA_PBURST_INC4) || \
775  ((BURST) == DMA_PBURST_INC8) || \
776  ((BURST) == DMA_PBURST_INC16))
777 
781 /* Private functions ---------------------------------------------------------*/
798 #ifdef __cplusplus
799 }
800 #endif
801 
802 #endif /* __STM32F4xx_HAL_DMA_H */
803 
804 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
DMA_InitTypeDef::Channel
uint32_t Channel
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:51
HAL_DMA_STATE_BUSY
@ HAL_DMA_STATE_BUSY
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:107
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
stm32f4xx_hal_dma_ex.h
Header file of DMA HAL extension module.
HAL_DMA_XFER_ERROR_CB_ID
@ HAL_DMA_XFER_ERROR_CB_ID
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:131
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f407xx.h:346
__DMA_HandleTypeDef::XferHalfCpltCallback
void(* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:153
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:139
__DMA_HandleTypeDef::StreamIndex
uint32_t StreamIndex
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:167
DMA_InitTypeDef::Priority
uint32_t Priority
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:75
__DMA_HandleTypeDef::StreamBaseAddress
uint32_t StreamBaseAddress
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:165
DMA_InitTypeDef::PeriphInc
uint32_t PeriphInc
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:58
__DMA_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:163
DMA_InitTypeDef
DMA Configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:49
HAL_DMA_Abort_IT
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
__DMA_HandleTypeDef::XferM1CpltCallback
void(* XferM1CpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:155
HAL_DMA_STATE_ERROR
@ HAL_DMA_STATE_ERROR
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:109
__DMA_HandleTypeDef::XferAbortCallback
void(* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:161
__DMA_HandleTypeDef::Init
DMA_InitTypeDef Init
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:143
HAL_DMA_STATE_ABORT
@ HAL_DMA_STATE_ABORT
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:110
__DMA_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:145
DMA_InitTypeDef::FIFOThreshold
uint32_t FIFOThreshold
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:83
HAL_DMA_STATE_TIMEOUT
@ HAL_DMA_STATE_TIMEOUT
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:108
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:51
DMA_InitTypeDef::PeriphDataAlignment
uint32_t PeriphDataAlignment
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:64
__DMA_HandleTypeDef::State
__IO HAL_DMA_StateTypeDef State
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:147
HAL_DMA_XFER_ABORT_CB_ID
@ HAL_DMA_XFER_ABORT_CB_ID
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:132
HAL_DMA_XFER_M1HALFCPLT_CB_ID
@ HAL_DMA_XFER_M1HALFCPLT_CB_ID
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:130
DMA_InitTypeDef::MemInc
uint32_t MemInc
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:61
HAL_DMA_FULL_TRANSFER
@ HAL_DMA_FULL_TRANSFER
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:118
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_DMA_UnRegisterCallback
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
HAL_DMA_XFER_ALL_CB_ID
@ HAL_DMA_XFER_ALL_CB_ID
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:133
HAL_DMA_PollForTransfer
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
DMA_InitTypeDef::PeriphBurst
uint32_t PeriphBurst
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:92
HAL_DMA_GetState
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
__DMA_HandleTypeDef::Instance
DMA_Stream_TypeDef * Instance
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:141
DMA_InitTypeDef::MemDataAlignment
uint32_t MemDataAlignment
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:67
HAL_DMA_CallbackIDTypeDef
HAL_DMA_CallbackIDTypeDef
HAL DMA Error Code structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:125
DMA_HandleTypeDef
struct __DMA_HandleTypeDef DMA_HandleTypeDef
DMA handle Structure definition.
HAL_DMA_Start_IT
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
HAL_DMA_XFER_M1CPLT_CB_ID
@ HAL_DMA_XFER_M1CPLT_CB_ID
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:129
HAL_DMA_Abort
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
HAL_DMA_XFER_CPLT_CB_ID
@ HAL_DMA_XFER_CPLT_CB_ID
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:127
DMA_InitTypeDef::MemBurst
uint32_t MemBurst
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:86
HAL_DMA_CleanCallbacks
HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma)
HAL_DMA_STATE_RESET
@ HAL_DMA_STATE_RESET
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:105
DMA_InitTypeDef::FIFOMode
uint32_t FIFOMode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:78
__DMA_HandleTypeDef::Parent
void * Parent
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:149
__DMA_HandleTypeDef::XferCpltCallback
void(* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:151
HAL_DMA_Init
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
HAL_DMA_HALF_TRANSFER
@ HAL_DMA_HALF_TRANSFER
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:119
DMA_InitTypeDef::Direction
uint32_t Direction
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:54
HAL_DMA_DeInit
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
HAL_DMA_XFER_HALFCPLT_CB_ID
@ HAL_DMA_XFER_HALFCPLT_CB_ID
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:128
__DMA_HandleTypeDef::XferM1HalfCpltCallback
void(* XferM1HalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:157
HAL_DMA_GetError
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
DMA_InitTypeDef::Mode
uint32_t Mode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:70
HAL_DMA_Start
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
HAL_DMA_StateTypeDef
HAL_DMA_StateTypeDef
HAL DMA State structures definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:103
HAL_DMA_LevelCompleteTypeDef
HAL_DMA_LevelCompleteTypeDef
HAL DMA Error Code structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:116
HAL_DMA_IRQHandler
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__DMA_HandleTypeDef::XferErrorCallback
void(* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:159
HAL_DMA_RegisterCallback
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
HAL_DMA_STATE_READY
@ HAL_DMA_STATE_READY
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:106

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autogenerated on Fri Apr 1 2022 02:14:52