TIM Exported Types

Collaboration diagram for TIM Exported Types:

Classes
struct	TIM_Base_InitTypeDef
	TIM Time base Configuration Structure definition. More...
struct	TIM_BreakDeadTimeConfigTypeDef
	TIM Break input(s) and Dead time configuration Structure definition. More...
struct	TIM_ClearInputConfigTypeDef
	TIM Clear Input Configuration Handle Structure definition. More...
struct	TIM_ClockConfigTypeDef
	Clock Configuration Handle Structure definition. More...
struct	TIM_Encoder_InitTypeDef
	TIM Encoder Configuration Structure definition. More...
struct	TIM_HandleTypeDef
	TIM Time Base Handle Structure definition. More...
struct	TIM_IC_InitTypeDef
	TIM Input Capture Configuration Structure definition. More...
struct	TIM_MasterConfigTypeDef
	TIM Master configuration Structure definition. More...
struct	TIM_OC_InitTypeDef
	TIM Output Compare Configuration Structure definition. More...
struct	TIM_OnePulse_InitTypeDef
	TIM One Pulse Mode Configuration Structure definition. More...
struct	TIM_SlaveConfigTypeDef
	TIM Slave configuration Structure definition. More...

Enumerations
enum	HAL_TIM_ActiveChannel {   HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,   HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U, HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,   HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U, HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,   HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,   HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U, HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,   HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,   HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,   HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U }
	HAL Active channel structures definition. More...
enum	HAL_TIM_ActiveChannel {   HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,   HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U, HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,   HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U, HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,   HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,   HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U, HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,   HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,   HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,   HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U }
	HAL Active channel structures definition. More...
enum	HAL_TIM_ActiveChannel {   HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,   HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U, HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,   HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U, HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,   HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,   HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U, HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,   HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,   HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,   HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U }
	HAL Active channel structures definition. More...
enum	HAL_TIM_ActiveChannel {   HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,   HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U, HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,   HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U, HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,   HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,   HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U, HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,   HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,   HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,   HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U }
	HAL Active channel structures definition. More...
enum	HAL_TIM_ActiveChannel {   HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,   HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U, HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,   HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U, HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,   HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,   HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U, HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,   HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,   HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,   HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U }
	HAL Active channel structures definition. More...
enum	HAL_TIM_ChannelStateTypeDef {   HAL_TIM_CHANNEL_STATE_RESET = 0x00U, HAL_TIM_CHANNEL_STATE_READY = 0x01U, HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, HAL_TIM_CHANNEL_STATE_RESET = 0x00U,   HAL_TIM_CHANNEL_STATE_READY = 0x01U, HAL_TIM_CHANNEL_STATE_BUSY = 0x02U }
	TIM Channel States definition. More...
enum	HAL_TIM_ChannelStateTypeDef {   HAL_TIM_CHANNEL_STATE_RESET = 0x00U, HAL_TIM_CHANNEL_STATE_READY = 0x01U, HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, HAL_TIM_CHANNEL_STATE_RESET = 0x00U,   HAL_TIM_CHANNEL_STATE_READY = 0x01U, HAL_TIM_CHANNEL_STATE_BUSY = 0x02U }
	TIM Channel States definition. More...
enum	HAL_TIM_DMABurstStateTypeDef {   HAL_DMA_BURST_STATE_RESET = 0x00U, HAL_DMA_BURST_STATE_READY = 0x01U, HAL_DMA_BURST_STATE_BUSY = 0x02U, HAL_DMA_BURST_STATE_RESET = 0x00U,   HAL_DMA_BURST_STATE_READY = 0x01U, HAL_DMA_BURST_STATE_BUSY = 0x02U }
	DMA Burst States definition. More...
enum	HAL_TIM_DMABurstStateTypeDef {   HAL_DMA_BURST_STATE_RESET = 0x00U, HAL_DMA_BURST_STATE_READY = 0x01U, HAL_DMA_BURST_STATE_BUSY = 0x02U, HAL_DMA_BURST_STATE_RESET = 0x00U,   HAL_DMA_BURST_STATE_READY = 0x01U, HAL_DMA_BURST_STATE_BUSY = 0x02U }
	DMA Burst States definition. More...
enum	HAL_TIM_StateTypeDef {   HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,   HAL_TIM_STATE_ERROR = 0x04U, HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U,   HAL_TIM_STATE_TIMEOUT = 0x03U, HAL_TIM_STATE_ERROR = 0x04U, HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U,   HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U, HAL_TIM_STATE_ERROR = 0x04U, HAL_TIM_STATE_RESET = 0x00U,   HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U, HAL_TIM_STATE_ERROR = 0x04U,   HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,   HAL_TIM_STATE_ERROR = 0x04U }
	HAL State structures definition. More...
enum	HAL_TIM_StateTypeDef {   HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,   HAL_TIM_STATE_ERROR = 0x04U, HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U,   HAL_TIM_STATE_TIMEOUT = 0x03U, HAL_TIM_STATE_ERROR = 0x04U, HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U,   HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U, HAL_TIM_STATE_ERROR = 0x04U, HAL_TIM_STATE_RESET = 0x00U,   HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U, HAL_TIM_STATE_ERROR = 0x04U,   HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,   HAL_TIM_STATE_ERROR = 0x04U }
	HAL State structures definition. More...
enum	HAL_TIM_StateTypeDef {   HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,   HAL_TIM_STATE_ERROR = 0x04U, HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U,   HAL_TIM_STATE_TIMEOUT = 0x03U, HAL_TIM_STATE_ERROR = 0x04U, HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U,   HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U, HAL_TIM_STATE_ERROR = 0x04U, HAL_TIM_STATE_RESET = 0x00U,   HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U, HAL_TIM_STATE_ERROR = 0x04U,   HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,   HAL_TIM_STATE_ERROR = 0x04U }
	HAL State structures definition. More...
enum	HAL_TIM_StateTypeDef {   HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,   HAL_TIM_STATE_ERROR = 0x04U, HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U,   HAL_TIM_STATE_TIMEOUT = 0x03U, HAL_TIM_STATE_ERROR = 0x04U, HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U,   HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U, HAL_TIM_STATE_ERROR = 0x04U, HAL_TIM_STATE_RESET = 0x00U,   HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U, HAL_TIM_STATE_ERROR = 0x04U,   HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,   HAL_TIM_STATE_ERROR = 0x04U }
	HAL State structures definition. More...
enum	HAL_TIM_StateTypeDef {   HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,   HAL_TIM_STATE_ERROR = 0x04U, HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U,   HAL_TIM_STATE_TIMEOUT = 0x03U, HAL_TIM_STATE_ERROR = 0x04U, HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U,   HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U, HAL_TIM_STATE_ERROR = 0x04U, HAL_TIM_STATE_RESET = 0x00U,   HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U, HAL_TIM_STATE_ERROR = 0x04U,   HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,   HAL_TIM_STATE_ERROR = 0x04U }
	HAL State structures definition. More...

Detailed Description

Enumeration Type Documentation

HAL_TIM_ActiveChannel [1/5]

enum HAL_TIM_ActiveChannel

HAL Active channel structures definition.

Enumerator
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_5	The active channel is 5
HAL_TIM_ACTIVE_CHANNEL_6	The active channel is 6
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_5	The active channel is 5
HAL_TIM_ACTIVE_CHANNEL_6	The active channel is 6
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_5	The active channel is 5
HAL_TIM_ACTIVE_CHANNEL_6	The active channel is 6
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared

Definition at line 300 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h.

HAL_TIM_ActiveChannel [2/5]

enum HAL_TIM_ActiveChannel

HAL Active channel structures definition.

Enumerator
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_5	The active channel is 5
HAL_TIM_ACTIVE_CHANNEL_6	The active channel is 6
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_5	The active channel is 5
HAL_TIM_ACTIVE_CHANNEL_6	The active channel is 6
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_5	The active channel is 5
HAL_TIM_ACTIVE_CHANNEL_6	The active channel is 6
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared

Definition at line 300 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h.

HAL_TIM_ActiveChannel [3/5]

enum HAL_TIM_ActiveChannel

HAL Active channel structures definition.

Enumerator
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_5	The active channel is 5
HAL_TIM_ACTIVE_CHANNEL_6	The active channel is 6
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_5	The active channel is 5
HAL_TIM_ACTIVE_CHANNEL_6	The active channel is 6
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_5	The active channel is 5
HAL_TIM_ACTIVE_CHANNEL_6	The active channel is 6
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared

Definition at line 310 of file stm32f7xx_hal_tim.h.

HAL_TIM_ActiveChannel [4/5]

enum HAL_TIM_ActiveChannel

HAL Active channel structures definition.

Enumerator
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_5	The active channel is 5
HAL_TIM_ACTIVE_CHANNEL_6	The active channel is 6
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_5	The active channel is 5
HAL_TIM_ACTIVE_CHANNEL_6	The active channel is 6
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_5	The active channel is 5
HAL_TIM_ACTIVE_CHANNEL_6	The active channel is 6
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared

Definition at line 330 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h.

HAL_TIM_ActiveChannel [5/5]

enum HAL_TIM_ActiveChannel

HAL Active channel structures definition.

Enumerator
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_5	The active channel is 5
HAL_TIM_ACTIVE_CHANNEL_6	The active channel is 6
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_5	The active channel is 5
HAL_TIM_ACTIVE_CHANNEL_6	The active channel is 6
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared
HAL_TIM_ACTIVE_CHANNEL_1	The active channel is 1
HAL_TIM_ACTIVE_CHANNEL_2	The active channel is 2
HAL_TIM_ACTIVE_CHANNEL_3	The active channel is 3
HAL_TIM_ACTIVE_CHANNEL_4	The active channel is 4
HAL_TIM_ACTIVE_CHANNEL_5	The active channel is 5
HAL_TIM_ACTIVE_CHANNEL_6	The active channel is 6
HAL_TIM_ACTIVE_CHANNEL_CLEARED	All active channels cleared

Definition at line 330 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h.

HAL_TIM_ChannelStateTypeDef [1/2]

enum HAL_TIM_ChannelStateTypeDef

TIM Channel States definition.

Enumerator
HAL_TIM_CHANNEL_STATE_RESET	TIM Channel initial state
HAL_TIM_CHANNEL_STATE_READY	TIM Channel ready for use
HAL_TIM_CHANNEL_STATE_BUSY	An internal process is ongoing on the TIM channel
HAL_TIM_CHANNEL_STATE_RESET	TIM Channel initial state
HAL_TIM_CHANNEL_STATE_READY	TIM Channel ready for use
HAL_TIM_CHANNEL_STATE_BUSY	An internal process is ongoing on the TIM channel

Definition at line 310 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h.

HAL_TIM_ChannelStateTypeDef [2/2]

enum HAL_TIM_ChannelStateTypeDef

TIM Channel States definition.

Enumerator
HAL_TIM_CHANNEL_STATE_RESET	TIM Channel initial state
HAL_TIM_CHANNEL_STATE_READY	TIM Channel ready for use
HAL_TIM_CHANNEL_STATE_BUSY	An internal process is ongoing on the TIM channel
HAL_TIM_CHANNEL_STATE_RESET	TIM Channel initial state
HAL_TIM_CHANNEL_STATE_READY	TIM Channel ready for use
HAL_TIM_CHANNEL_STATE_BUSY	An internal process is ongoing on the TIM channel

Definition at line 310 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h.

HAL_TIM_DMABurstStateTypeDef [1/2]

enum HAL_TIM_DMABurstStateTypeDef

DMA Burst States definition.

Enumerator
HAL_DMA_BURST_STATE_RESET	DMA Burst initial state
HAL_DMA_BURST_STATE_READY	DMA Burst ready for use
HAL_DMA_BURST_STATE_BUSY	Ongoing DMA Burst
HAL_DMA_BURST_STATE_RESET	DMA Burst initial state
HAL_DMA_BURST_STATE_READY	DMA Burst ready for use
HAL_DMA_BURST_STATE_BUSY	Ongoing DMA Burst

Definition at line 320 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h.

HAL_TIM_DMABurstStateTypeDef [2/2]

enum HAL_TIM_DMABurstStateTypeDef

DMA Burst States definition.

Enumerator
HAL_DMA_BURST_STATE_RESET	DMA Burst initial state
HAL_DMA_BURST_STATE_READY	DMA Burst ready for use
HAL_DMA_BURST_STATE_BUSY	Ongoing DMA Burst
HAL_DMA_BURST_STATE_RESET	DMA Burst initial state
HAL_DMA_BURST_STATE_READY	DMA Burst ready for use
HAL_DMA_BURST_STATE_BUSY	Ongoing DMA Burst

Definition at line 320 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h.

HAL_TIM_StateTypeDef [1/5]

enum HAL_TIM_StateTypeDef

HAL State structures definition.

Enumerator
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing

Definition at line 288 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h.

HAL_TIM_StateTypeDef [2/5]

enum HAL_TIM_StateTypeDef

HAL State structures definition.

Enumerator
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing

Definition at line 288 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h.

HAL_TIM_StateTypeDef [3/5]

enum HAL_TIM_StateTypeDef

HAL State structures definition.

Enumerator
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing

Definition at line 298 of file stm32f7xx_hal_tim.h.

HAL_TIM_StateTypeDef [4/5]

enum HAL_TIM_StateTypeDef

HAL State structures definition.

Enumerator
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing

Definition at line 298 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h.

HAL_TIM_StateTypeDef [5/5]

enum HAL_TIM_StateTypeDef

HAL State structures definition.

Enumerator
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing
HAL_TIM_STATE_RESET	Peripheral not yet initialized or disabled
HAL_TIM_STATE_READY	Peripheral Initialized and ready for use
HAL_TIM_STATE_BUSY	An internal process is ongoing
HAL_TIM_STATE_TIMEOUT	Timeout state
HAL_TIM_STATE_ERROR	Reception process is ongoing

Definition at line 298 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h.