clock_config.c
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1 /*
2  * Copyright 2017-2020 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 /*
8  * How to setup clock using clock driver functions:
9  *
10  * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
11  *
12  * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
13  *
14  * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
15  *
16  * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
17  *
18  * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
19  *
20  */
21 
22 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
23 !!GlobalInfo
24 product: Clocks v7.0
25 processor: MIMXRT1052xxxxB
26 package_id: MIMXRT1052DVL6B
27 mcu_data: ksdk2_0
28 processor_version: 0.7.9
29 board: IMXRT1050-EVKB
30  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
31 
32 #include "clock_config.h"
33 #include "fsl_iomuxc.h"
34 
35 /*******************************************************************************
36  * Definitions
37  ******************************************************************************/
38 
39 /*******************************************************************************
40  * Variables
41  ******************************************************************************/
42 /* System clock frequency. */
43 extern uint32_t SystemCoreClock;
44 
45 /*******************************************************************************
46  ************************ BOARD_InitBootClocks function ************************
47  ******************************************************************************/
48 void BOARD_InitBootClocks(void)
49 {
50  BOARD_BootClockRUN();
51 }
52 
53 /*******************************************************************************
54  ********************** Configuration BOARD_BootClockRUN ***********************
55  ******************************************************************************/
56 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
57 !!Configuration
58 name: BOARD_BootClockRUN
59 called_from_default_init: true
60 outputs:
61 - {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
62 - {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
63 - {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
64 - {id: CLK_1M.outFreq, value: 1 MHz}
65 - {id: CLK_24M.outFreq, value: 24 MHz}
66 - {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
67 - {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
68 - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
69 - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
70 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
71 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
72 - {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
73 - {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
74 - {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
75 - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
76 - {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
77 - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
78 - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
79 - {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
80 - {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
81 - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
82 - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
83 - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
84 - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
85 - {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
86 - {id: SAI1_MCLK3.outFreq, value: 30 MHz}
87 - {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
88 - {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
89 - {id: SAI2_MCLK3.outFreq, value: 30 MHz}
90 - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
91 - {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
92 - {id: SAI3_MCLK3.outFreq, value: 30 MHz}
93 - {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
94 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
95 - {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
96 - {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
97 - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
98 - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
99 settings:
100 - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
101 - {id: CCM.ARM_PODF.scale, value: '2', locked: true}
102 - {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
103 - {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
104 - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
105 - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
106 - {id: CCM.SEMC_PODF.scale, value: '8'}
107 - {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
108 - {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
109 - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
110 - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
111 - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
112 - {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
113 - {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
114 - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
115 - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
116 - {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
117 - {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
118 - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
119 - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
120 - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
121 - {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
122 - {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
123 - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
124 - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
125 - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
126 - {id: CCM_ANALOG.PLL4.denom, value: '50'}
127 - {id: CCM_ANALOG.PLL4.div, value: '47'}
128 - {id: CCM_ANALOG.PLL5.denom, value: '1'}
129 - {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
130 - {id: CCM_ANALOG.PLL5.num, value: '0'}
131 - {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
132 - {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
133 - {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
134 - {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
135 - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
136 - {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
137 sources:
138 - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
139  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
140 
141 /*******************************************************************************
142  * Variables for BOARD_BootClockRUN configuration
143  ******************************************************************************/
144 const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
145  {
146  .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
147  .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
148  };
149 const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
150  {
151  .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
152  .numerator = 0, /* 30 bit numerator of fractional loop divider */
153  .denominator = 1, /* 30 bit denominator of fractional loop divider */
154  .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
155  };
156 const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
157  {
158  .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
159  .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
160  };
161 const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
162  {
163  .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
164  .postDivider = 8, /* Divider after PLL */
165  .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
166  .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
167  .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
168  };
169 /*******************************************************************************
170  * Code for BOARD_BootClockRUN configuration
171  ******************************************************************************/
172 void BOARD_BootClockRUN(void)
173 {
174  /* Init RTC OSC clock frequency. */
175  CLOCK_SetRtcXtalFreq(32768U);
176  /* Enable 1MHz clock output. */
177  XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
178  /* Use free 1MHz clock output. */
179  XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
180  /* Set XTAL 24MHz clock frequency. */
181  CLOCK_SetXtalFreq(24000000U);
182  /* Enable XTAL 24MHz clock source. */
183  CLOCK_InitExternalClk(0);
184  /* Enable internal RC. */
185  CLOCK_InitRcOsc24M();
186  /* Switch clock source to external OSC. */
187  CLOCK_SwitchOsc(kCLOCK_XtalOsc);
188  /* Set Oscillator ready counter value. */
189  CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
190  /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
191  CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
192  CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
193  /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
194  DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
195  /* Waiting for DCDC_STS_DC_OK bit is asserted */
196  while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
197  {
198  }
199  /* Set AHB_PODF. */
200  CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
201  /* Disable IPG clock gate. */
202  CLOCK_DisableClock(kCLOCK_Adc1);
203  CLOCK_DisableClock(kCLOCK_Adc2);
204  CLOCK_DisableClock(kCLOCK_Xbar1);
205  CLOCK_DisableClock(kCLOCK_Xbar2);
206  CLOCK_DisableClock(kCLOCK_Xbar3);
207  /* Set IPG_PODF. */
208  CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
209  /* Set ARM_PODF. */
210  CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
211  /* Set PERIPH_CLK2_PODF. */
212  CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
213  /* Disable PERCLK clock gate. */
214  CLOCK_DisableClock(kCLOCK_Gpt1);
215  CLOCK_DisableClock(kCLOCK_Gpt1S);
216  CLOCK_DisableClock(kCLOCK_Gpt2);
217  CLOCK_DisableClock(kCLOCK_Gpt2S);
218  CLOCK_DisableClock(kCLOCK_Pit);
219  /* Set PERCLK_PODF. */
220  CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
221  /* Disable USDHC1 clock gate. */
222  CLOCK_DisableClock(kCLOCK_Usdhc1);
223  /* Set USDHC1_PODF. */
224  CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
225  /* Set Usdhc1 clock source. */
226  CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
227  /* Disable USDHC2 clock gate. */
228  CLOCK_DisableClock(kCLOCK_Usdhc2);
229  /* Set USDHC2_PODF. */
230  CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
231  /* Set Usdhc2 clock source. */
232  CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
233  /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
234  * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
235  * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
236 #ifndef SKIP_SYSCLK_INIT
237  /* Disable Semc clock gate. */
238  CLOCK_DisableClock(kCLOCK_Semc);
239  /* Set SEMC_PODF. */
240  CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
241  /* Set Semc alt clock source. */
242  CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
243  /* Set Semc clock source. */
244  CLOCK_SetMux(kCLOCK_SemcMux, 0);
245 #endif
246  /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
247  * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
248  * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
249 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
250  /* Disable Flexspi clock gate. */
251  CLOCK_DisableClock(kCLOCK_FlexSpi);
252  /* Set FLEXSPI_PODF. */
253  CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
254  /* Set Flexspi clock source. */
255  CLOCK_SetMux(kCLOCK_FlexspiMux, 1);
256 #endif
257  /* Disable CSI clock gate. */
258  CLOCK_DisableClock(kCLOCK_Csi);
259  /* Set CSI_PODF. */
260  CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
261  /* Set Csi clock source. */
262  CLOCK_SetMux(kCLOCK_CsiMux, 0);
263  /* Disable LPSPI clock gate. */
264  CLOCK_DisableClock(kCLOCK_Lpspi1);
265  CLOCK_DisableClock(kCLOCK_Lpspi2);
266  CLOCK_DisableClock(kCLOCK_Lpspi3);
267  CLOCK_DisableClock(kCLOCK_Lpspi4);
268  /* Set LPSPI_PODF. */
269  CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
270  /* Set Lpspi clock source. */
271  CLOCK_SetMux(kCLOCK_LpspiMux, 2);
272  /* Disable TRACE clock gate. */
273  CLOCK_DisableClock(kCLOCK_Trace);
274  /* Set TRACE_PODF. */
275  CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
276  /* Set Trace clock source. */
277  CLOCK_SetMux(kCLOCK_TraceMux, 0);
278  /* Disable SAI1 clock gate. */
279  CLOCK_DisableClock(kCLOCK_Sai1);
280  /* Set SAI1_CLK_PRED. */
281  CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
282  /* Set SAI1_CLK_PODF. */
283  CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
284  /* Set Sai1 clock source. */
285  CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
286  /* Disable SAI2 clock gate. */
287  CLOCK_DisableClock(kCLOCK_Sai2);
288  /* Set SAI2_CLK_PRED. */
289  CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
290  /* Set SAI2_CLK_PODF. */
291  CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
292  /* Set Sai2 clock source. */
293  CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
294  /* Disable SAI3 clock gate. */
295  CLOCK_DisableClock(kCLOCK_Sai3);
296  /* Set SAI3_CLK_PRED. */
297  CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
298  /* Set SAI3_CLK_PODF. */
299  CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
300  /* Set Sai3 clock source. */
301  CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
302  /* Disable Lpi2c clock gate. */
303  CLOCK_DisableClock(kCLOCK_Lpi2c1);
304  CLOCK_DisableClock(kCLOCK_Lpi2c2);
305  CLOCK_DisableClock(kCLOCK_Lpi2c3);
306  /* Set LPI2C_CLK_PODF. */
307  CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
308  /* Set Lpi2c clock source. */
309  CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
310  /* Disable CAN clock gate. */
311  CLOCK_DisableClock(kCLOCK_Can1);
312  CLOCK_DisableClock(kCLOCK_Can2);
313  CLOCK_DisableClock(kCLOCK_Can1S);
314  CLOCK_DisableClock(kCLOCK_Can2S);
315  /* Set CAN_CLK_PODF. */
316  CLOCK_SetDiv(kCLOCK_CanDiv, 1);
317  /* Set Can clock source. */
318  CLOCK_SetMux(kCLOCK_CanMux, 2);
319  /* Disable UART clock gate. */
320  CLOCK_DisableClock(kCLOCK_Lpuart1);
321  CLOCK_DisableClock(kCLOCK_Lpuart2);
322  CLOCK_DisableClock(kCLOCK_Lpuart3);
323  CLOCK_DisableClock(kCLOCK_Lpuart4);
324  CLOCK_DisableClock(kCLOCK_Lpuart5);
325  CLOCK_DisableClock(kCLOCK_Lpuart6);
326  CLOCK_DisableClock(kCLOCK_Lpuart7);
327  CLOCK_DisableClock(kCLOCK_Lpuart8);
328  /* Set UART_CLK_PODF. */
329  CLOCK_SetDiv(kCLOCK_UartDiv, 0);
330  /* Set Uart clock source. */
331  CLOCK_SetMux(kCLOCK_UartMux, 0);
332  /* Disable LCDIF clock gate. */
333  CLOCK_DisableClock(kCLOCK_LcdPixel);
334  /* Set LCDIF_PRED. */
335  CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
336  /* Set LCDIF_CLK_PODF. */
337  CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
338  /* Set Lcdif pre clock source. */
339  CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
340  /* Disable SPDIF clock gate. */
341  CLOCK_DisableClock(kCLOCK_Spdif);
342  /* Set SPDIF0_CLK_PRED. */
343  CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
344  /* Set SPDIF0_CLK_PODF. */
345  CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
346  /* Set Spdif clock source. */
347  CLOCK_SetMux(kCLOCK_SpdifMux, 3);
348  /* Disable Flexio1 clock gate. */
349  CLOCK_DisableClock(kCLOCK_Flexio1);
350  /* Set FLEXIO1_CLK_PRED. */
351  CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
352  /* Set FLEXIO1_CLK_PODF. */
353  CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
354  /* Set Flexio1 clock source. */
355  CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
356  /* Disable Flexio2 clock gate. */
357  CLOCK_DisableClock(kCLOCK_Flexio2);
358  /* Set FLEXIO2_CLK_PRED. */
359  CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
360  /* Set FLEXIO2_CLK_PODF. */
361  CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
362  /* Set Flexio2 clock source. */
363  CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
364  /* Set Pll3 sw clock source. */
365  CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
366  /* Init ARM PLL. */
367  CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
368  /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
369  * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
370  * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
371 #ifndef SKIP_SYSCLK_INIT
372 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
373  #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
374 #endif
375  /* Init System PLL. */
376  CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
377  /* Init System pfd0. */
378  CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
379  /* Init System pfd1. */
380  CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
381  /* Init System pfd2. */
382  CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
383  /* Init System pfd3. */
384  CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
385  /* Disable pfd offset. */
386  CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK;
387 #endif
388  /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
389  * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
390  * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
391 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
392  /* Init Usb1 PLL. */
393  CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
394  /* Init Usb1 pfd0. */
395  CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
396  /* Init Usb1 pfd1. */
397  CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
398  /* Init Usb1 pfd2. */
399  CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
400  /* Init Usb1 pfd3. */
401  CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
402  /* Disable Usb1 PLL output for USBPHY1. */
403  CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
404 #endif
405  /* DeInit Audio PLL. */
406  CLOCK_DeinitAudioPll();
407  /* Bypass Audio PLL. */
408  CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
409  /* Set divider for Audio PLL. */
410  CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
411  CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
412  /* Enable Audio PLL output. */
413  CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
414  /* Init Video PLL. */
415  uint32_t pllVideo;
416  /* Disable Video PLL output before initial Video PLL. */
417  CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
418  /* Bypass PLL first */
419  CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
420  CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
421  CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
422  CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
423  pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
424  CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
425  pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
426  CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
427  CCM_ANALOG->PLL_VIDEO = pllVideo;
428  while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
429  {
430  }
431  /* Disable pfd offset. */
432  CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK;
433  /* Disable bypass for Video PLL. */
434  CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
435  /* DeInit Enet PLL. */
436  CLOCK_DeinitEnetPll();
437  /* Bypass Enet PLL. */
438  CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
439  /* Set Enet output divider. */
440  CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
441  /* Enable Enet output. */
442  CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
443  /* Enable Enet25M output. */
444  CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
445  /* DeInit Usb2 PLL. */
446  CLOCK_DeinitUsb2Pll();
447  /* Bypass Usb2 PLL. */
448  CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
449  /* Enable Usb2 PLL output. */
450  CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
451  /* Set preperiph clock source. */
452  CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
453  /* Set periph clock source. */
454  CLOCK_SetMux(kCLOCK_PeriphMux, 0);
455  /* Set periph clock2 clock source. */
456  CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
457  /* Set per clock source. */
458  CLOCK_SetMux(kCLOCK_PerclkMux, 0);
459  /* Set lvds1 clock source. */
460  CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
461  /* Set clock out1 divider. */
462  CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
463  /* Set clock out1 source. */
464  CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
465  /* Set clock out2 divider. */
466  CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
467  /* Set clock out2 source. */
468  CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
469  /* Set clock out1 drives clock out1. */
470  CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
471  /* Disable clock out1. */
472  CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
473  /* Disable clock out2. */
474  CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
475  /* Set SAI1 MCLK1 clock source. */
476  IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
477  /* Set SAI1 MCLK2 clock source. */
478  IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
479  /* Set SAI1 MCLK3 clock source. */
480  IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
481  /* Set SAI2 MCLK3 clock source. */
482  IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
483  /* Set SAI3 MCLK3 clock source. */
484  IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
485  /* Set MQS configuration. */
486  IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
487  /* Set ENET Tx clock source. */
488  IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
489  /* Set GPT1 High frequency reference clock source. */
490  IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
491  /* Set GPT2 High frequency reference clock source. */
492  IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
493  /* Set SystemCoreClock variable. */
494  SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
495 }
496 
XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK
#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK
Definition: MIMXRT1052.h:46024
kCLOCK_Usdhc2Div
@ kCLOCK_Usdhc2Div
Definition: fsl_clock.h:763
CCM_CCOSR_CLKO2_DIV
#define CCM_CCOSR_CLKO2_DIV(x)
Definition: MIMXRT1052.h:5578
kCLOCK_Sai2
@ kCLOCK_Sai2
Definition: fsl_clock.h:548
kCLOCK_Flexio2PreDiv
@ kCLOCK_Flexio2PreDiv
Definition: fsl_clock.h:788
kCLOCK_SpdifMux
@ kCLOCK_SpdifMux
Definition: fsl_clock.h:686
_clock_video_pll_config
PLL configuration for AUDIO and VIDEO.
Definition: fsl_clock.h:904
kCLOCK_Usdhc2
@ kCLOCK_Usdhc2
Definition: fsl_clock.h:558
kCLOCK_PllEnet
@ kCLOCK_PllEnet
Definition: fsl_clock.h:938
CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT
#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x)
Definition: MIMXRT1052.h:6882
CCM_ANALOG
#define CCM_ANALOG
Definition: MIMXRT1052.h:8520
videoPllConfig_BOARD_BootClockRUN
const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN
Video PLL set for BOARD_BootClockRUN configuration.
Definition: clock_config.c:161
kCLOCK_PeriphMux
@ kCLOCK_PeriphMux
Definition: fsl_clock.h:613
clock_config.h
kIOMUXC_MqsPwmOverSampleRate32
@ kIOMUXC_MqsPwmOverSampleRate32
Definition: fsl_iomuxc.h:1061
kCLOCK_PeriphClk2Mux
@ kCLOCK_PeriphClk2Mux
Definition: fsl_clock.h:634
kCLOCK_Usdhc1Div
@ kCLOCK_Usdhc1Div
Definition: fsl_clock.h:767
kCLOCK_Lpuart4
@ kCLOCK_Lpuart4
Definition: fsl_clock.h:479
kCLOCK_Lpuart5
@ kCLOCK_Lpuart5
Definition: fsl_clock.h:504
CCM_CCOSR_CLKO1_DIV
#define CCM_CCOSR_CLKO1_DIV(x)
Definition: MIMXRT1052.h:5532
CCM_CCOSR_CLKO2_EN_MASK
#define CCM_CCOSR_CLKO2_EN_MASK
Definition: MIMXRT1052.h:5579
CLOCK_DeinitAudioPll
void CLOCK_DeinitAudioPll(void)
De-initialize the Audio PLL.
Definition: fsl_clock.c:711
CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC
#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x)
Definition: MIMXRT1052.h:6867
CLOCK_SetPllBypass
static void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass)
PLL bypass setting.
Definition: fsl_clock.h:1268
kCLOCK_PllVideo
@ kCLOCK_PllVideo
Definition: fsl_clock.h:936
kCLOCK_Spdif0Div
@ kCLOCK_Spdif0Div
Definition: fsl_clock.h:814
kCLOCK_UartMux
@ kCLOCK_UartMux
Definition: fsl_clock.h:681
DCDC_REG3_TRG_MASK
#define DCDC_REG3_TRG_MASK
Definition: MIMXRT1052.h:10216
IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK
Definition: MIMXRT1052.h:21588
CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK
#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK
Definition: MIMXRT1052.h:6853
kCLOCK_Lpspi1
@ kCLOCK_Lpspi1
Definition: fsl_clock.h:467
kCLOCK_Flexio1Div
@ kCLOCK_Flexio1Div
Definition: fsl_clock.h:822
kIOMUXC_GPR_SAI1MClk1Sel
@ kIOMUXC_GPR_SAI1MClk1Sel
Definition: fsl_iomuxc.h:1052
kCLOCK_Pll3SwMux
@ kCLOCK_Pll3SwMux
Definition: fsl_clock.h:608
CCM_ANALOG_MISC2_VIDEO_DIV_MASK
#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK
Definition: MIMXRT1052.h:8154
kCLOCK_LcdPixel
@ kCLOCK_LcdPixel
Definition: fsl_clock.h:508
kCLOCK_CanDiv
@ kCLOCK_CanDiv
Definition: fsl_clock.h:754
kCLOCK_Lpspi2
@ kCLOCK_Lpspi2
Definition: fsl_clock.h:468
kCLOCK_Sai3Div
@ kCLOCK_Sai3Div
Definition: fsl_clock.h:784
kCLOCK_Lpuart1
@ kCLOCK_Lpuart1
Definition: fsl_clock.h:550
kCLOCK_FlexspiDiv
@ kCLOCK_FlexspiDiv
Definition: fsl_clock.h:745
kCLOCK_TraceMux
@ kCLOCK_TraceMux
Definition: fsl_clock.h:630
kCLOCK_Flexio2Div
@ kCLOCK_Flexio2Div
Definition: fsl_clock.h:776
kCLOCK_Xbar1
@ kCLOCK_Xbar1
Definition: fsl_clock.h:496
CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK
#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK
Definition: MIMXRT1052.h:8120
CCM_ANALOG_PLL_VIDEO_NUM_A
#define CCM_ANALOG_PLL_VIDEO_NUM_A(x)
Definition: MIMXRT1052.h:7012
kCLOCK_Flexio1
@ kCLOCK_Flexio1
Definition: fsl_clock.h:539
kCLOCK_Lpuart7
@ kCLOCK_Lpuart7
Definition: fsl_clock.h:551
CCM_CCOSR_CLKO1_SEL_MASK
#define CCM_CCOSR_CLKO1_SEL_MASK
Definition: MIMXRT1052.h:5504
CCM_ANALOG_MISC1_LVDS1_CLK_SEL
#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x)
Definition: MIMXRT1052.h:7864
kCLOCK_Xbar2
@ kCLOCK_Xbar2
Definition: fsl_clock.h:497
IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK
Definition: MIMXRT1052.h:21595
CCM_ANALOG_PLL_VIDEO_ENABLE_MASK
#define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK
Definition: MIMXRT1052.h:6856
kCLOCK_CanMux
@ kCLOCK_CanMux
Definition: fsl_clock.h:676
CCM_CCOSR_CLKO2_DIV_MASK
#define CCM_CCOSR_CLKO2_DIV_MASK
Definition: MIMXRT1052.h:5566
kCLOCK_Pfd3
@ kCLOCK_Pfd3
Definition: fsl_clock.h:952
kCLOCK_Sai1Div
@ kCLOCK_Sai1Div
Definition: fsl_clock.h:796
CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK
#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK
Definition: MIMXRT1052.h:6871
BOARD_BOOTCLOCKRUN_CORE_CLOCK
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK
Definition: clock_config.h:42
IOMUXC_MQSConfig
static void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider)
Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk.
Definition: fsl_iomuxc.h:1228
kCLOCK_Lpspi4
@ kCLOCK_Lpspi4
Definition: fsl_clock.h:470
kIOMUXC_GPR_SAI2MClk3Sel
@ kIOMUXC_GPR_SAI2MClk3Sel
Definition: fsl_iomuxc.h:1055
kCLOCK_Lpuart6
@ kCLOCK_Lpuart6
Definition: fsl_clock.h:506
_clock_video_pll_config::loopDivider
uint8_t loopDivider
Definition: fsl_clock.h:906
kCLOCK_Spdif0PreDiv
@ kCLOCK_Spdif0PreDiv
Definition: fsl_clock.h:810
DCDC_REG0_STS_DC_OK_MASK
#define DCDC_REG0_STS_DC_OK_MASK
Definition: MIMXRT1052.h:10159
_clock_sys_pll_config::loopDivider
uint8_t loopDivider
Definition: fsl_clock.h:881
IOMUXC_SetSaiMClkClockSource
static void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gpr_saimclk_t mclk, uint8_t clkSrc)
Sets IOMUXC general configuration for SAI MCLK selection.
Definition: fsl_iomuxc.h:1168
CLOCK_InitUsb1Pfd
void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac)
Initialize the USB1 PLL PFD.
Definition: fsl_clock.c:1113
CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK
#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK
Definition: MIMXRT1052.h:7844
kCLOCK_Lpi2c3
@ kCLOCK_Lpi2c3
Definition: fsl_clock.h:490
kCLOCK_Can1
@ kCLOCK_Can1
Definition: fsl_clock.h:456
kCLOCK_XtalOsc
@ kCLOCK_XtalOsc
Definition: fsl_clock.h:579
_clock_arm_pll_config
PLL configuration for ARM.
Definition: fsl_clock.h:862
kCLOCK_TraceDiv
@ kCLOCK_TraceDiv
Definition: fsl_clock.h:759
CLOCK_DeinitUsb2Pll
void CLOCK_DeinitUsb2Pll(void)
Deinitialize the USB2 PLL.
Definition: fsl_clock.c:624
CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK
#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK
Definition: MIMXRT1052.h:7024
CCM_ANALOG_PLL_VIDEO_LOCK_MASK
#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK
Definition: MIMXRT1052.h:6883
armPllConfig_BOARD_BootClockRUN
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN
Arm PLL set for BOARD_BootClockRUN configuration.
Definition: clock_config.c:144
CCM_ANALOG_PLL_ENET_DIV_SELECT
#define CCM_ANALOG_PLL_ENET_DIV_SELECT(x)
Definition: MIMXRT1052.h:7026
CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK
#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK
Definition: MIMXRT1052.h:6850
kCLOCK_Flexio1PreDiv
@ kCLOCK_Flexio1PreDiv
Definition: fsl_clock.h:818
CCM_CCOSR_CLKO1_EN_MASK
#define CCM_CCOSR_CLKO1_EN_MASK
Definition: MIMXRT1052.h:5533
kCLOCK_Can1S
@ kCLOCK_Can1S
Definition: fsl_clock.h:457
kCLOCK_PllUsb2
@ kCLOCK_PllUsb2
Definition: fsl_clock.h:942
CCM_ANALOG_PLL_USB2_ENABLE_MASK
#define CCM_ANALOG_PLL_USB2_ENABLE_MASK
Definition: MIMXRT1052.h:6414
kCLOCK_Sai3PreDiv
@ kCLOCK_Sai3PreDiv
Definition: fsl_clock.h:780
kCLOCK_SemcAltMux
@ kCLOCK_SemcAltMux
Definition: fsl_clock.h:617
kCLOCK_Pfd0
@ kCLOCK_Pfd0
Definition: fsl_clock.h:949
kCLOCK_FlexspiMux
@ kCLOCK_FlexspiMux
Definition: fsl_clock.h:643
kCLOCK_IpgDiv
@ kCLOCK_IpgDiv
Definition: fsl_clock.h:737
kIOMUXC_GPR_SAI1MClk2Sel
@ kIOMUXC_GPR_SAI1MClk2Sel
Definition: fsl_iomuxc.h:1053
IOMUXC_GPR
#define IOMUXC_GPR
Definition: MIMXRT1052.h:22774
kCLOCK_PeriphClk2Div
@ kCLOCK_PeriphClk2Div
Definition: fsl_clock.h:725
CCM_ANALOG_PLL_AUDIO_ENABLE_MASK
#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK
Definition: MIMXRT1052.h:6682
CLOCK_SetRtcXtalFreq
static void CLOCK_SetRtcXtalFreq(uint32_t freq)
Set the RTC XTAL (32K OSC) frequency based on board setting.
Definition: fsl_clock.h:1211
kCLOCK_Sai1
@ kCLOCK_Sai1
Definition: fsl_clock.h:547
BOARD_InitBootClocks
void BOARD_InitBootClocks(void)
This function executes default configuration of clocks.
Definition: clock_config.c:48
CLOCK_InitSysPfd
void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac)
Initialize the System PLL PFD.
Definition: fsl_clock.c:1075
SystemCoreClock
uint32_t SystemCoreClock
Definition: system_MIMXRT1052.c:69
CCM
#define CCM
Definition: MIMXRT1052.h:6049
kCLOCK_LcdifDiv
@ kCLOCK_LcdifDiv
Definition: fsl_clock.h:742
CLOCK_InitRcOsc24M
void CLOCK_InitRcOsc24M(void)
Initialize the RC oscillator 24MHz clock.
Definition: fsl_clock.c:209
CLOCK_SetMux
static void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
Set CCM MUX node to certain value.
Definition: fsl_clock.h:969
CCM_ANALOG_PLL_VIDEO_BYPASS_MASK
#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK
Definition: MIMXRT1052.h:6868
kCLOCK_Csi
@ kCLOCK_Csi
Definition: fsl_clock.h:486
kCLOCK_PerclkMux
@ kCLOCK_PerclkMux
Definition: fsl_clock.h:667
kCLOCK_Sai2PreDiv
@ kCLOCK_Sai2PreDiv
Definition: fsl_clock.h:801
kCLOCK_LpspiDiv
@ kCLOCK_LpspiDiv
Definition: fsl_clock.h:740
CCM_CCR_OSCNT
#define CCM_CCR_OSCNT(x)
Definition: MIMXRT1052.h:4209
CCM_ANALOG_PLL_ENET_ENABLE_MASK
#define CCM_ANALOG_PLL_ENET_ENABLE_MASK
Definition: MIMXRT1052.h:7030
kCLOCK_Semc
@ kCLOCK_Semc
Definition: fsl_clock.h:505
DCDC_REG3_TRG
#define DCDC_REG3_TRG(x)
Definition: MIMXRT1052.h:10218
kCLOCK_ArmDiv
@ kCLOCK_ArmDiv
Definition: fsl_clock.h:720
kCLOCK_Trace
@ kCLOCK_Trace
Definition: fsl_clock.h:460
kCLOCK_Flexio2
@ kCLOCK_Flexio2
Definition: fsl_clock.h:503
_clock_arm_pll_config::loopDivider
uint32_t loopDivider
Definition: fsl_clock.h:864
_clock_usb_pll_config
PLL configuration for USB.
Definition: fsl_clock.h:869
CLOCK_InitUsb1Pll
void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config)
Initialize the USB1 PLL.
Definition: fsl_clock.c:570
kCLOCK_PllAudio
@ kCLOCK_PllAudio
Definition: fsl_clock.h:935
kCLOCK_Gpt1
@ kCLOCK_Gpt1
Definition: fsl_clock.h:477
kCLOCK_PrePeriphMux
@ kCLOCK_PrePeriphMux
Definition: fsl_clock.h:626
XTALOSC24M
#define XTALOSC24M
Definition: MIMXRT1052.h:46093
kCLOCK_AhbDiv
@ kCLOCK_AhbDiv
Definition: fsl_clock.h:733
kCLOCK_Sai2Mux
@ kCLOCK_Sai2Mux
Definition: fsl_clock.h:659
kCLOCK_Sai1Mux
@ kCLOCK_Sai1Mux
Definition: fsl_clock.h:663
kCLOCK_Usdhc2Mux
@ kCLOCK_Usdhc2Mux
Definition: fsl_clock.h:647
CLOCK_SetDiv
static void CLOCK_SetDiv(clock_div_t divider, uint32_t value)
Set CCM DIV node to certain value.
Definition: fsl_clock.h:1006
kCLOCK_Usdhc1
@ kCLOCK_Usdhc1
Definition: fsl_clock.h:557
kCLOCK_Lpuart2
@ kCLOCK_Lpuart2
Definition: fsl_clock.h:463
kCLOCK_Can2
@ kCLOCK_Can2
Definition: fsl_clock.h:458
CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK
#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK
Definition: MIMXRT1052.h:6276
kCLOCK_Pfd1
@ kCLOCK_Pfd1
Definition: fsl_clock.h:950
_clock_usb_pll_config::loopDivider
uint8_t loopDivider
Definition: fsl_clock.h:871
CLOCK_SwitchOsc
void CLOCK_SwitchOsc(clock_osc_t osc)
Switch the OSC.
Definition: fsl_clock.c:194
kCLOCK_SemcMux
@ kCLOCK_SemcMux
Definition: fsl_clock.h:621
kCLOCK_Spdif
@ kCLOCK_Spdif
Definition: fsl_clock.h:545
CCM_ANALOG_MISC2_VIDEO_DIV
#define CCM_ANALOG_MISC2_VIDEO_DIV(x)
Definition: MIMXRT1052.h:8162
CLOCK_InitSysPll
void CLOCK_InitSysPll(const clock_sys_pll_config_t *config)
Initialize the System PLL.
Definition: fsl_clock.c:528
CLOCK_DeinitEnetPll
void CLOCK_DeinitEnetPll(void)
Deinitialize the ENET PLL.
Definition: fsl_clock.c:844
kCLOCK_LcdifPreMux
@ kCLOCK_LcdifPreMux
Definition: fsl_clock.h:699
CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK
#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK
Definition: MIMXRT1052.h:6548
kCLOCK_Lpi2c1
@ kCLOCK_Lpi2c1
Definition: fsl_clock.h:488
CCM_CCOSR_CLK_OUT_SEL_MASK
#define CCM_CCOSR_CLK_OUT_SEL_MASK
Definition: MIMXRT1052.h:5540
kCLOCK_LpspiMux
@ kCLOCK_LpspiMux
Definition: fsl_clock.h:638
CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK
#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK
Definition: MIMXRT1052.h:7048
kCLOCK_Lpi2cMux
@ kCLOCK_Lpi2cMux
Definition: fsl_clock.h:695
kCLOCK_Usdhc1Mux
@ kCLOCK_Usdhc1Mux
Definition: fsl_clock.h:651
kCLOCK_UartDiv
@ kCLOCK_UartDiv
Definition: fsl_clock.h:771
kCLOCK_Pfd2
@ kCLOCK_Pfd2
Definition: fsl_clock.h:951
kCLOCK_Gpt1S
@ kCLOCK_Gpt1S
Definition: fsl_clock.h:478
kCLOCK_Lpspi3
@ kCLOCK_Lpspi3
Definition: fsl_clock.h:469
kCLOCK_PerclkDiv
@ kCLOCK_PerclkDiv
Definition: fsl_clock.h:749
CLOCK_DisableClock
static void CLOCK_DisableClock(clock_ip_name_t name)
Disable the clock for specific IP.
Definition: fsl_clock.h:1069
CCM_CCR_OSCNT_MASK
#define CCM_CCR_OSCNT_MASK
Definition: MIMXRT1052.h:4201
CCM_ANALOG_PLL_VIDEO_DENOM_B
#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x)
Definition: MIMXRT1052.h:7019
CCM_CCOSR_CLKO1_DIV_MASK
#define CCM_CCOSR_CLKO1_DIV_MASK
Definition: MIMXRT1052.h:5520
kCLOCK_Lpi2cDiv
@ kCLOCK_Lpi2cDiv
Definition: fsl_clock.h:827
kCLOCK_FlexSpi
@ kCLOCK_FlexSpi
Definition: fsl_clock.h:561
kCLOCK_Pit
@ kCLOCK_Pit
Definition: fsl_clock.h:473
CLOCK_InitExternalClk
void CLOCK_InitExternalClk(bool bypassXtalOsc)
Initialize the external 24MHz clock.
Definition: fsl_clock.c:158
kIOMUXC_GPR_SAI1MClk3Sel
@ kIOMUXC_GPR_SAI1MClk3Sel
Definition: fsl_iomuxc.h:1054
CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK
#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK
Definition: MIMXRT1052.h:8097
kCLOCK_Adc2
@ kCLOCK_Adc2
Definition: fsl_clock.h:471
kCLOCK_Flexio2Mux
@ kCLOCK_Flexio2Mux
Definition: fsl_clock.h:672
kCLOCK_Lpuart8
@ kCLOCK_Lpuart8
Definition: fsl_clock.h:563
CLOCK_SetXtalFreq
static void CLOCK_SetXtalFreq(uint32_t freq)
Set the XTAL (24M OSC) frequency based on board setting.
Definition: fsl_clock.h:1201
kCLOCK_Sai2Div
@ kCLOCK_Sai2Div
Definition: fsl_clock.h:805
fsl_iomuxc.h
CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK
#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK
Definition: MIMXRT1052.h:6859
BOARD_BootClockRUN
void BOARD_BootClockRUN(void)
This function executes configuration of clocks.
Definition: clock_config.c:172
kCLOCK_Lpi2c2
@ kCLOCK_Lpi2c2
Definition: fsl_clock.h:489
CLOCK_InitArmPll
void CLOCK_InitArmPll(const clock_arm_pll_config_t *config)
Initialize the ARM PLL.
Definition: fsl_clock.c:495
CCM_CCOSR_CLKO2_SEL
#define CCM_CCOSR_CLKO2_SEL(x)
Definition: MIMXRT1052.h:5565
kCLOCK_Lpuart3
@ kCLOCK_Lpuart3
Definition: fsl_clock.h:455
kCLOCK_Can2S
@ kCLOCK_Can2S
Definition: fsl_clock.h:459
kCLOCK_CsiDiv
@ kCLOCK_CsiDiv
Definition: fsl_clock.h:836
DCDC
#define DCDC
Definition: MIMXRT1052.h:10246
CCM_CCOSR_CLKO2_SEL_MASK
#define CCM_CCOSR_CLKO2_SEL_MASK
Definition: MIMXRT1052.h:5547
kCLOCK_LcdifPreDiv
@ kCLOCK_LcdifPreDiv
Definition: fsl_clock.h:831
kCLOCK_Sai3Mux
@ kCLOCK_Sai3Mux
Definition: fsl_clock.h:655
XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK
#define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK
Definition: MIMXRT1052.h:46027
kCLOCK_Sai1PreDiv
@ kCLOCK_Sai1PreDiv
Definition: fsl_clock.h:792
kCLOCK_Adc1
@ kCLOCK_Adc1
Definition: fsl_clock.h:475
_clock_sys_pll_config
PLL configuration for System.
Definition: fsl_clock.h:879
CCM_CCOSR_CLKO1_SEL
#define CCM_CCOSR_CLKO1_SEL(x)
Definition: MIMXRT1052.h:5519
kCLOCK_Sai3
@ kCLOCK_Sai3
Definition: fsl_clock.h:549
kCLOCK_Flexio1Mux
@ kCLOCK_Flexio1Mux
Definition: fsl_clock.h:690
IOMUXC_EnableMode
static void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable)
Sets IOMUXC general configuration for some mode.
Definition: fsl_iomuxc.h:1145
kIOMUXC_GPR_SAI3MClk3Sel
@ kIOMUXC_GPR_SAI3MClk3Sel
Definition: fsl_iomuxc.h:1056
kCLOCK_Gpt2S
@ kCLOCK_Gpt2S
Definition: fsl_clock.h:462
usb1PllConfig_BOARD_BootClockRUN
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN
Usb1 PLL set for BOARD_BootClockRUN configuration.
Definition: clock_config.c:156
CCM_ANALOG_PLL_VIDEO_DIV_SELECT
#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x)
Definition: MIMXRT1052.h:6852
kCLOCK_Gpt2
@ kCLOCK_Gpt2
Definition: fsl_clock.h:461
kCLOCK_SemcDiv
@ kCLOCK_SemcDiv
Definition: fsl_clock.h:729
kCLOCK_Xbar3
@ kCLOCK_Xbar3
Definition: fsl_clock.h:492
sysPllConfig_BOARD_BootClockRUN
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN
Sys PLL for BOARD_BootClockRUN configuration.
Definition: clock_config.c:149
kIOMUXC_GPR_ENET1RefClkMode
@ kIOMUXC_GPR_ENET1RefClkMode
Definition: fsl_iomuxc.h:1039
kCLOCK_CsiMux
@ kCLOCK_CsiMux
Definition: fsl_clock.h:704

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:13:47