fsl_clock.h

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/*
 * Copyright 2017 - 2020, NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
 
#ifndef _FSL_CLOCK_H_
#define _FSL_CLOCK_H_
 
#include "fsl_common.h"
 
/*******************************************************************************
 * Configurations
 ******************************************************************************/
 
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
#endif
 
/*******************************************************************************
 * Definitions
 ******************************************************************************/
 
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
 
/* Definition for delay API in clock driver, users can redefine it to the real application. */
#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL)
#endif
 
/* analog pll definition */
#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
 
#define CCSR_OFFSET 0x0C
#define CBCDR_OFFSET 0x14
#define CBCMR_OFFSET 0x18
#define CSCMR1_OFFSET 0x1C
#define CSCMR2_OFFSET 0x20
#define CSCDR1_OFFSET 0x24
#define CDCDR_OFFSET 0x30
#define CSCDR2_OFFSET 0x38
#define CSCDR3_OFFSET 0x3C
#define CACRR_OFFSET 0x10
#define CS1CDR_OFFSET 0x28
#define CS2CDR_OFFSET 0x2C
 
#define PLL_ARM_OFFSET 0x00
#define PLL_SYS_OFFSET 0x30
#define PLL_USB1_OFFSET 0x10
#define PLL_AUDIO_OFFSET 0x70
#define PLL_VIDEO_OFFSET 0xA0
#define PLL_ENET_OFFSET 0xE0
#define PLL_USB2_OFFSET 0x20
 
#define CCM_TUPLE(reg, shift, mask, busyShift) \
    (int)(((reg)&0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFU))))
#define CCM_TUPLE_SHIFT(tuple) ((((uint32_t)tuple) >> 8U) & 0x1FU)
#define CCM_TUPLE_MASK(tuple) \
    ((uint32_t)((((uint32_t)(tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU))))
#define CCM_TUPLE_BUSY_SHIFT(tuple) ((((uint32_t)tuple) >> 26U) & 0x3FU)
 
#define CCM_NO_BUSY_WAIT (0x20U)
 
#define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFU) << 16U) | (shift))
#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU)
#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
    (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off))))
#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
 
/* Definition for ERRATA 50235 check */
#if (defined(FSL_FEATURE_CCM_HAS_ERRATA_50235) && FSL_FEATURE_CCM_HAS_ERRATA_50235)
#define CAN_CLOCK_CHECK_NO_AFFECTS                                                  \
    ((CCM_CSCMR2_CAN_CLK_SEL(2U) != (CCM->CSCMR2 & CCM_CSCMR2_CAN_CLK_SEL_MASK)) || \
     (CCM_CCGR5_CG12(0) != (CCM->CCGR5 & CCM_CCGR5_CG12_MASK)))
#endif /* FSL_FEATURE_CCM_HAS_ERRATA_50235 */
 
#define CLKPN_FREQ 0U
 
extern volatile uint32_t g_xtalFreq;
 
extern volatile uint32_t g_rtcXtalFreq;
 
/* For compatible with other platforms */
#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq
#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq
 
#define ADC_CLOCKS                                 \
    {                                              \
        kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \
    }
 
#define AOI_CLOCKS                                 \
    {                                              \
        kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \
    }
 
#define BEE_CLOCKS \
    {              \
        kCLOCK_Bee \
    }
 
#define CMP_CLOCKS                                                               \
    {                                                                            \
        kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \
    }
 
#define CSI_CLOCKS \
    {              \
        kCLOCK_Csi \
    }
 
#define DCDC_CLOCKS \
    {               \
        kCLOCK_Dcdc \
    }
 
#define DCP_CLOCKS \
    {              \
        kCLOCK_Dcp \
    }
 
#define DMAMUX_CLOCKS \
    {                 \
        kCLOCK_Dma    \
    }
 
#define EDMA_CLOCKS \
    {               \
        kCLOCK_Dma  \
    }
 
#define ENC_CLOCKS                                                           \
    {                                                                        \
        kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \
    }
 
#define ENET_CLOCKS \
    {               \
        kCLOCK_Enet \
    }
 
#define EWM_CLOCKS  \
    {               \
        kCLOCK_Ewm0 \
    }
 
#define FLEXCAN_CLOCKS                             \
    {                                              \
        kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \
    }
 
#define FLEXCAN_PERIPH_CLOCKS                        \
    {                                                \
        kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \
    }
 
#define FLEXIO_CLOCKS                                    \
    {                                                    \
        kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \
    }
 
#define FLEXRAM_CLOCKS \
    {                  \
        kCLOCK_FlexRam \
    }
 
#define FLEXSPI_CLOCKS \
    {                  \
        kCLOCK_FlexSpi \
    }
 
#define FLEXSPI_EXSC_CLOCKS \
    {                       \
        kCLOCK_FlexSpiExsc  \
    }
 
#define GPIO_CLOCKS                                                                            \
    {                                                                                          \
        kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
    }
 
#define GPT_CLOCKS                                 \
    {                                              \
        kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \
    }
 
#define KPP_CLOCKS \
    {              \
        kCLOCK_Kpp \
    }
 
#define LCDIF_CLOCKS \
    {                \
        kCLOCK_Lcd   \
    }
 
#define LCDIF_PERIPH_CLOCKS \
    {                       \
        kCLOCK_LcdPixel     \
    }
 
#define LPI2C_CLOCKS                                                                 \
    {                                                                                \
        kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \
    }
 
#define LPSPI_CLOCKS                                                                 \
    {                                                                                \
        kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \
    }
 
#define LPUART_CLOCKS                                                                                     \
    {                                                                                                     \
        kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \
            kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8                                                \
    }
 
#define MQS_CLOCKS \
    {              \
        kCLOCK_Mqs \
    }
 
#define OCRAM_EXSC_CLOCKS \
    {                     \
        kCLOCK_OcramExsc  \
    }
 
#define PIT_CLOCKS \
    {              \
        kCLOCK_Pit \
    }
 
#define PWM_CLOCKS                                                                \
    {                                                                             \
        {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
            {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1},                 \
            {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2},                 \
            {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3},                 \
        {                                                                         \
            kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4                    \
        }                                                                         \
    }
 
#define PXP_CLOCKS \
    {              \
        kCLOCK_Pxp \
    }
 
#define RTWDOG_CLOCKS \
    {                 \
        kCLOCK_Wdog3  \
    }
 
#define SAI_CLOCKS                                              \
    {                                                           \
        kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \
    }
 
#define SEMC_CLOCKS \
    {               \
        kCLOCK_Semc \
    }
 
#define SEMC_EXSC_CLOCKS \
    {                    \
        kCLOCK_SemcExsc  \
    }
 
#define TMR_CLOCKS                                                                   \
    {                                                                                \
        kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
    }
 
#define TRNG_CLOCKS \
    {               \
        kCLOCK_Trng \
    }
 
#define TSC_CLOCKS \
    {              \
        kCLOCK_Tsc \
    }
 
#define WDOG_CLOCKS                                  \
    {                                                \
        kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \
    }
 
#define USDHC_CLOCKS                                   \
    {                                                  \
        kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
    }
 
#define SPDIF_CLOCKS \
    {                \
        kCLOCK_Spdif \
    }
 
#define XBARA_CLOCKS \
    {                \
        kCLOCK_Xbar1 \
    }
 
#define XBARB_CLOCKS                                                   \
    {                                                                  \
        kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \
    }
 
typedef enum _clock_name
{
    kCLOCK_CpuClk  = 0x0U, 
    kCLOCK_AhbClk  = 0x1U, 
    kCLOCK_SemcClk = 0x2U, 
    kCLOCK_IpgClk  = 0x3U, 
    kCLOCK_PerClk  = 0x4U, 
    kCLOCK_OscClk = 0x5U, 
    kCLOCK_RtcClk = 0x6U, 
    kCLOCK_ArmPllClk = 0x7U, 
    kCLOCK_Usb1PllClk     = 0x8U, 
    kCLOCK_Usb1PllPfd0Clk = 0x9U, 
    kCLOCK_Usb1PllPfd1Clk = 0xAU, 
    kCLOCK_Usb1PllPfd2Clk = 0xBU, 
    kCLOCK_Usb1PllPfd3Clk = 0xCU, 
    kCLOCK_Usb2PllClk = 0xDU, 
    kCLOCK_SysPllClk     = 0xEU,  
    kCLOCK_SysPllPfd0Clk = 0xFU,  
    kCLOCK_SysPllPfd1Clk = 0x10U, 
    kCLOCK_SysPllPfd2Clk = 0x11U, 
    kCLOCK_SysPllPfd3Clk = 0x12U, 
    kCLOCK_EnetPll0Clk = 0x13U, 
    kCLOCK_EnetPll1Clk = 0x14U, 
    kCLOCK_AudioPllClk = 0x15U, 
    kCLOCK_VideoPllClk = 0x16U, 
} clock_name_t;
 
#define kCLOCK_CoreSysClk kCLOCK_CpuClk             
#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq 
typedef enum _clock_ip_name
{
    kCLOCK_IpInvalid = -1,
 
    /* CCM CCGR0 */
    kCLOCK_Aips_tz1    = (0U << 8U) | CCM_CCGR0_CG0_SHIFT,  
    kCLOCK_Aips_tz2    = (0U << 8U) | CCM_CCGR0_CG1_SHIFT,  
    kCLOCK_Mqs         = (0U << 8U) | CCM_CCGR0_CG2_SHIFT,  
    kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT,  
    kCLOCK_Sim_M_Main  = (0U << 8U) | CCM_CCGR0_CG4_SHIFT,  
    kCLOCK_Dcp         = (0U << 8U) | CCM_CCGR0_CG5_SHIFT,  
    kCLOCK_Lpuart3     = (0U << 8U) | CCM_CCGR0_CG6_SHIFT,  
    kCLOCK_Can1        = (0U << 8U) | CCM_CCGR0_CG7_SHIFT,  
    kCLOCK_Can1S       = (0U << 8U) | CCM_CCGR0_CG8_SHIFT,  
    kCLOCK_Can2        = (0U << 8U) | CCM_CCGR0_CG9_SHIFT,  
    kCLOCK_Can2S       = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, 
    kCLOCK_Trace       = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, 
    kCLOCK_Gpt2        = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, 
    kCLOCK_Gpt2S       = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, 
    kCLOCK_Lpuart2     = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, 
    kCLOCK_Gpio2       = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, 
    /* CCM CCGR1 */
    kCLOCK_Lpspi1   = (1U << 8U) | CCM_CCGR1_CG0_SHIFT,  
    kCLOCK_Lpspi2   = (1U << 8U) | CCM_CCGR1_CG1_SHIFT,  
    kCLOCK_Lpspi3   = (1U << 8U) | CCM_CCGR1_CG2_SHIFT,  
    kCLOCK_Lpspi4   = (1U << 8U) | CCM_CCGR1_CG3_SHIFT,  
    kCLOCK_Adc2     = (1U << 8U) | CCM_CCGR1_CG4_SHIFT,  
    kCLOCK_Enet     = (1U << 8U) | CCM_CCGR1_CG5_SHIFT,  
    kCLOCK_Pit      = (1U << 8U) | CCM_CCGR1_CG6_SHIFT,  
    kCLOCK_Aoi2     = (1U << 8U) | CCM_CCGR1_CG7_SHIFT,  
    kCLOCK_Adc1     = (1U << 8U) | CCM_CCGR1_CG8_SHIFT,  
    kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT,  
    kCLOCK_Gpt1     = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, 
    kCLOCK_Gpt1S    = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, 
    kCLOCK_Lpuart4  = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, 
    kCLOCK_Gpio1    = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, 
    kCLOCK_Csu      = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, 
    kCLOCK_Gpio5    = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, 
    /* CCM CCGR2 */
    kCLOCK_OcramExsc  = (2U << 8U) | CCM_CCGR2_CG0_SHIFT,  
    kCLOCK_Csi        = (2U << 8U) | CCM_CCGR2_CG1_SHIFT,  
    kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT,  
    kCLOCK_Lpi2c1     = (2U << 8U) | CCM_CCGR2_CG3_SHIFT,  
    kCLOCK_Lpi2c2     = (2U << 8U) | CCM_CCGR2_CG4_SHIFT,  
    kCLOCK_Lpi2c3     = (2U << 8U) | CCM_CCGR2_CG5_SHIFT,  
    kCLOCK_Ocotp      = (2U << 8U) | CCM_CCGR2_CG6_SHIFT,  
    kCLOCK_Xbar3      = (2U << 8U) | CCM_CCGR2_CG7_SHIFT,  
    kCLOCK_Ipmux1     = (2U << 8U) | CCM_CCGR2_CG8_SHIFT,  
    kCLOCK_Ipmux2     = (2U << 8U) | CCM_CCGR2_CG9_SHIFT,  
    kCLOCK_Ipmux3     = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, 
    kCLOCK_Xbar1      = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, 
    kCLOCK_Xbar2      = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, 
    kCLOCK_Gpio3      = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, 
    kCLOCK_Lcd        = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, 
    kCLOCK_Pxp        = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, 
    /* CCM CCGR3 */
    kCLOCK_Flexio2       = (3U << 8U) | CCM_CCGR3_CG0_SHIFT,  
    kCLOCK_Lpuart5       = (3U << 8U) | CCM_CCGR3_CG1_SHIFT,  
    kCLOCK_Semc          = (3U << 8U) | CCM_CCGR3_CG2_SHIFT,  
    kCLOCK_Lpuart6       = (3U << 8U) | CCM_CCGR3_CG3_SHIFT,  
    kCLOCK_Aoi1          = (3U << 8U) | CCM_CCGR3_CG4_SHIFT,  
    kCLOCK_LcdPixel      = (3U << 8U) | CCM_CCGR3_CG5_SHIFT,  
    kCLOCK_Gpio4         = (3U << 8U) | CCM_CCGR3_CG6_SHIFT,  
    kCLOCK_Ewm0          = (3U << 8U) | CCM_CCGR3_CG7_SHIFT,  
    kCLOCK_Wdog1         = (3U << 8U) | CCM_CCGR3_CG8_SHIFT,  
    kCLOCK_FlexRam       = (3U << 8U) | CCM_CCGR3_CG9_SHIFT,  
    kCLOCK_Acmp1         = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, 
    kCLOCK_Acmp2         = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, 
    kCLOCK_Acmp3         = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, 
    kCLOCK_Acmp4         = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, 
    kCLOCK_Ocram         = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, 
    kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, 
    /* CCM CCGR4 */
    kCLOCK_Iomuxc    = (4U << 8U) | CCM_CCGR4_CG1_SHIFT,  
    kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT,  
    kCLOCK_Bee       = (4U << 8U) | CCM_CCGR4_CG3_SHIFT,  
    kCLOCK_SimM7     = (4U << 8U) | CCM_CCGR4_CG4_SHIFT,  
    kCLOCK_Tsc       = (4U << 8U) | CCM_CCGR4_CG5_SHIFT,  
    kCLOCK_SimM      = (4U << 8U) | CCM_CCGR4_CG6_SHIFT,  
    kCLOCK_SimEms    = (4U << 8U) | CCM_CCGR4_CG7_SHIFT,  
    kCLOCK_Pwm1      = (4U << 8U) | CCM_CCGR4_CG8_SHIFT,  
    kCLOCK_Pwm2      = (4U << 8U) | CCM_CCGR4_CG9_SHIFT,  
    kCLOCK_Pwm3      = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, 
    kCLOCK_Pwm4      = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, 
    kCLOCK_Enc1      = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, 
    kCLOCK_Enc2      = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, 
    kCLOCK_Enc3      = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, 
    kCLOCK_Enc4      = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, 
    /* CCM CCGR5 */
    kCLOCK_Rom      = (5U << 8U) | CCM_CCGR5_CG0_SHIFT,  
    kCLOCK_Flexio1  = (5U << 8U) | CCM_CCGR5_CG1_SHIFT,  
    kCLOCK_Wdog3    = (5U << 8U) | CCM_CCGR5_CG2_SHIFT,  
    kCLOCK_Dma      = (5U << 8U) | CCM_CCGR5_CG3_SHIFT,  
    kCLOCK_Kpp      = (5U << 8U) | CCM_CCGR5_CG4_SHIFT,  
    kCLOCK_Wdog2    = (5U << 8U) | CCM_CCGR5_CG5_SHIFT,  
    kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT,  
    kCLOCK_Spdif    = (5U << 8U) | CCM_CCGR5_CG7_SHIFT,  
    kCLOCK_SimMain  = (5U << 8U) | CCM_CCGR5_CG8_SHIFT,  
    kCLOCK_Sai1     = (5U << 8U) | CCM_CCGR5_CG9_SHIFT,  
    kCLOCK_Sai2     = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, 
    kCLOCK_Sai3     = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, 
    kCLOCK_Lpuart1  = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, 
    kCLOCK_Lpuart7  = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, 
    kCLOCK_SnvsHp   = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, 
    kCLOCK_SnvsLp   = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, 
    /* CCM CCGR6 */
    kCLOCK_UsbOh3   = (6U << 8U) | CCM_CCGR6_CG0_SHIFT,  
    kCLOCK_Usdhc1   = (6U << 8U) | CCM_CCGR6_CG1_SHIFT,  
    kCLOCK_Usdhc2   = (6U << 8U) | CCM_CCGR6_CG2_SHIFT,  
    kCLOCK_Dcdc     = (6U << 8U) | CCM_CCGR6_CG3_SHIFT,  
    kCLOCK_Ipmux4   = (6U << 8U) | CCM_CCGR6_CG4_SHIFT,  
    kCLOCK_FlexSpi  = (6U << 8U) | CCM_CCGR6_CG5_SHIFT,  
    kCLOCK_Trng     = (6U << 8U) | CCM_CCGR6_CG6_SHIFT,  
    kCLOCK_Lpuart8  = (6U << 8U) | CCM_CCGR6_CG7_SHIFT,  
    kCLOCK_Timer4   = (6U << 8U) | CCM_CCGR6_CG8_SHIFT,  
    kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT,  
    kCLOCK_SimPer   = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, 
    kCLOCK_Anadig   = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, 
    kCLOCK_Lpi2c4   = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, 
    kCLOCK_Timer1   = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, 
    kCLOCK_Timer2   = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, 
    kCLOCK_Timer3   = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, 
} clock_ip_name_t;
 
typedef enum _clock_osc
{
    kCLOCK_RcOsc   = 0U, 
    kCLOCK_XtalOsc = 1U, 
} clock_osc_t;
 
typedef enum _clock_gate_value
{
    kCLOCK_ClockNotNeeded     = 0U, 
    kCLOCK_ClockNeededRun     = 1U, 
    kCLOCK_ClockNeededRunWait = 3U, 
} clock_gate_value_t;
 
typedef enum _clock_mode_t
{
    kCLOCK_ModeRun  = 0U, 
    kCLOCK_ModeWait = 1U, 
    kCLOCK_ModeStop = 2U, 
} clock_mode_t;
 
typedef enum _clock_mux
{
    kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET,
                                 CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT,
                                 CCM_CCSR_PLL3_SW_CLK_SEL_MASK,
                                 CCM_NO_BUSY_WAIT), 
    kCLOCK_PeriphMux  = CCM_TUPLE(CBCDR_OFFSET,
                                 CCM_CBCDR_PERIPH_CLK_SEL_SHIFT,
                                 CCM_CBCDR_PERIPH_CLK_SEL_MASK,
                                 CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), 
    kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET,
                                  CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT,
                                  CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK,
                                  CCM_NO_BUSY_WAIT), 
    kCLOCK_SemcMux    = CCM_TUPLE(CBCDR_OFFSET,
                               CCM_CBCDR_SEMC_CLK_SEL_SHIFT,
                               CCM_CBCDR_SEMC_CLK_SEL_MASK,
                               CCM_NO_BUSY_WAIT), 
    kCLOCK_PrePeriphMux  = CCM_TUPLE(CBCMR_OFFSET,
                                    CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT,
                                    CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK,
                                    CCM_NO_BUSY_WAIT), 
    kCLOCK_TraceMux      = CCM_TUPLE(CBCMR_OFFSET,
                                CCM_CBCMR_TRACE_CLK_SEL_SHIFT,
                                CCM_CBCMR_TRACE_CLK_SEL_MASK,
                                CCM_NO_BUSY_WAIT), 
    kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
                                     CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT,
                                     CCM_CBCMR_PERIPH_CLK2_SEL_MASK,
                                     CCM_NO_BUSY_WAIT), 
    kCLOCK_LpspiMux      = CCM_TUPLE(CBCMR_OFFSET,
                                CCM_CBCMR_LPSPI_CLK_SEL_SHIFT,
                                CCM_CBCMR_LPSPI_CLK_SEL_MASK,
                                CCM_NO_BUSY_WAIT), 
    kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET,
                                  CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT,
                                  CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK,
                                  CCM_NO_BUSY_WAIT), 
    kCLOCK_Usdhc2Mux  = CCM_TUPLE(CSCMR1_OFFSET,
                                 CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT,
                                 CCM_CSCMR1_USDHC2_CLK_SEL_MASK,
                                 CCM_NO_BUSY_WAIT), 
    kCLOCK_Usdhc1Mux  = CCM_TUPLE(CSCMR1_OFFSET,
                                 CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT,
                                 CCM_CSCMR1_USDHC1_CLK_SEL_MASK,
                                 CCM_NO_BUSY_WAIT), 
    kCLOCK_Sai3Mux    = CCM_TUPLE(CSCMR1_OFFSET,
                               CCM_CSCMR1_SAI3_CLK_SEL_SHIFT,
                               CCM_CSCMR1_SAI3_CLK_SEL_MASK,
                               CCM_NO_BUSY_WAIT), 
    kCLOCK_Sai2Mux    = CCM_TUPLE(CSCMR1_OFFSET,
                               CCM_CSCMR1_SAI2_CLK_SEL_SHIFT,
                               CCM_CSCMR1_SAI2_CLK_SEL_MASK,
                               CCM_NO_BUSY_WAIT), 
    kCLOCK_Sai1Mux    = CCM_TUPLE(CSCMR1_OFFSET,
                               CCM_CSCMR1_SAI1_CLK_SEL_SHIFT,
                               CCM_CSCMR1_SAI1_CLK_SEL_MASK,
                               CCM_NO_BUSY_WAIT), 
    kCLOCK_PerclkMux  = CCM_TUPLE(CSCMR1_OFFSET,
                                 CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT,
                                 CCM_CSCMR1_PERCLK_CLK_SEL_MASK,
                                 CCM_NO_BUSY_WAIT), 
    kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2_OFFSET,
                                  CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT,
                                  CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK,
                                  CCM_NO_BUSY_WAIT), 
    kCLOCK_CanMux     = CCM_TUPLE(CSCMR2_OFFSET,
                              CCM_CSCMR2_CAN_CLK_SEL_SHIFT,
                              CCM_CSCMR2_CAN_CLK_SEL_MASK,
                              CCM_NO_BUSY_WAIT), 
    kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET,
                               CCM_CSCDR1_UART_CLK_SEL_SHIFT,
                               CCM_CSCDR1_UART_CLK_SEL_MASK,
                               CCM_NO_BUSY_WAIT), 
    kCLOCK_SpdifMux   = CCM_TUPLE(CDCDR_OFFSET,
                                CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT,
                                CCM_CDCDR_SPDIF0_CLK_SEL_MASK,
                                CCM_NO_BUSY_WAIT), 
    kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR_OFFSET,
                                  CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT,
                                  CCM_CDCDR_FLEXIO1_CLK_SEL_MASK,
                                  CCM_NO_BUSY_WAIT), 
    kCLOCK_Lpi2cMux    = CCM_TUPLE(CSCDR2_OFFSET,
                                CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT,
                                CCM_CSCDR2_LPI2C_CLK_SEL_MASK,
                                CCM_NO_BUSY_WAIT), 
    kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2_OFFSET,
                                   CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT,
                                   CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK,
                                   CCM_NO_BUSY_WAIT), 
    kCLOCK_CsiMux = CCM_TUPLE(CSCDR3_OFFSET,
                              CCM_CSCDR3_CSI_CLK_SEL_SHIFT,
                              CCM_CSCDR3_CSI_CLK_SEL_MASK,
                              CCM_NO_BUSY_WAIT), 
} clock_mux_t;
 
typedef enum _clock_div
{
    kCLOCK_ArmDiv = CCM_TUPLE(CACRR_OFFSET,
                              CCM_CACRR_ARM_PODF_SHIFT,
                              CCM_CACRR_ARM_PODF_MASK,
                              CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), 
    kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET,
                                     CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT,
                                     CCM_CBCDR_PERIPH_CLK2_PODF_MASK,
                                     CCM_NO_BUSY_WAIT), 
    kCLOCK_SemcDiv       = CCM_TUPLE(CBCDR_OFFSET,
                               CCM_CBCDR_SEMC_PODF_SHIFT,
                               CCM_CBCDR_SEMC_PODF_MASK,
                               CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), 
    kCLOCK_AhbDiv        = CCM_TUPLE(CBCDR_OFFSET,
                              CCM_CBCDR_AHB_PODF_SHIFT,
                              CCM_CBCDR_AHB_PODF_MASK,
                              CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), 
    kCLOCK_IpgDiv        = CCM_TUPLE(
        CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), 
    kCLOCK_LpspiDiv = CCM_TUPLE(
        CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), 
    kCLOCK_LcdifDiv = CCM_TUPLE(
        CBCMR_OFFSET, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), 
    kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET,
                                  CCM_CSCMR1_FLEXSPI_PODF_SHIFT,
                                  CCM_CSCMR1_FLEXSPI_PODF_MASK,
                                  CCM_NO_BUSY_WAIT), 
    kCLOCK_PerclkDiv  = CCM_TUPLE(CSCMR1_OFFSET,
                                 CCM_CSCMR1_PERCLK_PODF_SHIFT,
                                 CCM_CSCMR1_PERCLK_PODF_MASK,
                                 CCM_NO_BUSY_WAIT), 
    kCLOCK_CanDiv = CCM_TUPLE(CSCMR2_OFFSET,
                              CCM_CSCMR2_CAN_CLK_PODF_SHIFT,
                              CCM_CSCMR2_CAN_CLK_PODF_MASK,
                              CCM_NO_BUSY_WAIT), 
    kCLOCK_TraceDiv  = CCM_TUPLE(CSCDR1_OFFSET,
                                CCM_CSCDR1_TRACE_PODF_SHIFT,
                                CCM_CSCDR1_TRACE_PODF_MASK,
                                CCM_NO_BUSY_WAIT), 
    kCLOCK_Usdhc2Div = CCM_TUPLE(CSCDR1_OFFSET,
                                 CCM_CSCDR1_USDHC2_PODF_SHIFT,
                                 CCM_CSCDR1_USDHC2_PODF_MASK,
                                 CCM_NO_BUSY_WAIT), 
    kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1_OFFSET,
                                 CCM_CSCDR1_USDHC1_PODF_SHIFT,
                                 CCM_CSCDR1_USDHC1_PODF_MASK,
                                 CCM_NO_BUSY_WAIT), 
    kCLOCK_UartDiv   = CCM_TUPLE(CSCDR1_OFFSET,
                               CCM_CSCDR1_UART_CLK_PODF_SHIFT,
                               CCM_CSCDR1_UART_CLK_PODF_MASK,
                               CCM_NO_BUSY_WAIT), 
    kCLOCK_Flexio2Div    = CCM_TUPLE(CS1CDR_OFFSET,
                                  CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT,
                                  CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK,
                                  CCM_NO_BUSY_WAIT), 
    kCLOCK_Sai3PreDiv    = CCM_TUPLE(CS1CDR_OFFSET,
                                  CCM_CS1CDR_SAI3_CLK_PRED_SHIFT,
                                  CCM_CS1CDR_SAI3_CLK_PRED_MASK,
                                  CCM_NO_BUSY_WAIT), 
    kCLOCK_Sai3Div       = CCM_TUPLE(CS1CDR_OFFSET,
                               CCM_CS1CDR_SAI3_CLK_PODF_SHIFT,
                               CCM_CS1CDR_SAI3_CLK_PODF_MASK,
                               CCM_NO_BUSY_WAIT), 
    kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
                                     CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT,
                                     CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK,
                                     CCM_NO_BUSY_WAIT), 
    kCLOCK_Sai1PreDiv    = CCM_TUPLE(CS1CDR_OFFSET,
                                  CCM_CS1CDR_SAI1_CLK_PRED_SHIFT,
                                  CCM_CS1CDR_SAI1_CLK_PRED_MASK,
                                  CCM_NO_BUSY_WAIT), 
    kCLOCK_Sai1Div       = CCM_TUPLE(CS1CDR_OFFSET,
                               CCM_CS1CDR_SAI1_CLK_PODF_SHIFT,
                               CCM_CS1CDR_SAI1_CLK_PODF_MASK,
                               CCM_NO_BUSY_WAIT), 
    kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET,
                                  CCM_CS2CDR_SAI2_CLK_PRED_SHIFT,
                                  CCM_CS2CDR_SAI2_CLK_PRED_MASK,
                                  CCM_NO_BUSY_WAIT), 
    kCLOCK_Sai2Div    = CCM_TUPLE(CS2CDR_OFFSET,
                               CCM_CS2CDR_SAI2_CLK_PODF_SHIFT,
                               CCM_CS2CDR_SAI2_CLK_PODF_MASK,
                               CCM_NO_BUSY_WAIT), 
    kCLOCK_Spdif0PreDiv  = CCM_TUPLE(CDCDR_OFFSET,
                                    CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT,
                                    CCM_CDCDR_SPDIF0_CLK_PRED_MASK,
                                    CCM_NO_BUSY_WAIT), 
    kCLOCK_Spdif0Div     = CCM_TUPLE(CDCDR_OFFSET,
                                 CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT,
                                 CCM_CDCDR_SPDIF0_CLK_PODF_MASK,
                                 CCM_NO_BUSY_WAIT), 
    kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR_OFFSET,
                                     CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT,
                                     CCM_CDCDR_FLEXIO1_CLK_PRED_MASK,
                                     CCM_NO_BUSY_WAIT), 
    kCLOCK_Flexio1Div    = CCM_TUPLE(CDCDR_OFFSET,
                                  CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT,
                                  CCM_CDCDR_FLEXIO1_CLK_PODF_MASK,
                                  CCM_NO_BUSY_WAIT), 
    kCLOCK_Lpi2cDiv    = CCM_TUPLE(CSCDR2_OFFSET,
                                CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT,
                                CCM_CSCDR2_LPI2C_CLK_PODF_MASK,
                                CCM_NO_BUSY_WAIT), 
    kCLOCK_LcdifPreDiv = CCM_TUPLE(CSCDR2_OFFSET,
                                   CCM_CSCDR2_LCDIF_PRED_SHIFT,
                                   CCM_CSCDR2_LCDIF_PRED_MASK,
                                   CCM_NO_BUSY_WAIT), 
    kCLOCK_CsiDiv = CCM_TUPLE(
        CSCDR3_OFFSET, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), 
} clock_div_t;
 
typedef enum _clock_usb_src
{
    kCLOCK_Usb480M      = 0,                
    kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, 
} clock_usb_src_t;
 
typedef enum _clock_usb_phy_src
{
    kCLOCK_Usbphy480M = 0, 
} clock_usb_phy_src_t;
 
enum _clock_pll_clk_src
{
    kCLOCK_PllClkSrc24M = 0U, 
    kCLOCK_PllSrcClkPN  = 1U, 
};
 
typedef struct _clock_arm_pll_config
{
    uint32_t loopDivider; 
    uint8_t src;          
} clock_arm_pll_config_t;
 
typedef struct _clock_usb_pll_config
{
    uint8_t loopDivider; 
    uint8_t src;         
} clock_usb_pll_config_t;
 
typedef struct _clock_sys_pll_config
{
    uint8_t loopDivider;  
    uint32_t numerator;   
    uint32_t denominator; 
    uint8_t src;          
    uint16_t ss_stop;     
    uint8_t ss_enable;    
    uint16_t ss_step;     
} clock_sys_pll_config_t;
 
typedef struct _clock_audio_pll_config
{
    uint8_t loopDivider;  
    uint8_t postDivider;  
    uint32_t numerator;   
    uint32_t denominator; 
    uint8_t src;          
} clock_audio_pll_config_t;
 
typedef struct _clock_video_pll_config
{
    uint8_t loopDivider;  
    uint8_t postDivider;  
    uint32_t numerator;   
    uint32_t denominator; 
    uint8_t src;          
} clock_video_pll_config_t;
 
typedef struct _clock_enet_pll_config
{
    bool enableClkOutput; 
    bool enableClkOutput25M; 
    uint8_t loopDivider;     
    uint8_t src;             
} clock_enet_pll_config_t;
 
typedef enum _clock_pll
{
    kCLOCK_PllArm   = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT),     
    kCLOCK_PllSys   = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT),     
    kCLOCK_PllUsb1  = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT),   
    kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), 
    kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), 
    kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), 
    kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), 
    kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2_OFFSET, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), 
} clock_pll_t;
 
typedef enum _clock_pfd
{
    kCLOCK_Pfd0 = 0U, 
    kCLOCK_Pfd1 = 1U, 
    kCLOCK_Pfd2 = 2U, 
    kCLOCK_Pfd3 = 3U, 
} clock_pfd_t;
 
/*******************************************************************************
 * API
 ******************************************************************************/
 
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
 
static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
{
    uint32_t busyShift;
 
    busyShift               = (uint32_t)CCM_TUPLE_BUSY_SHIFT(mux);
    CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) |
                              (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux));
 
    assert(busyShift <= CCM_NO_BUSY_WAIT);
 
    /* Clock switch need Handshake? */
    if (CCM_NO_BUSY_WAIT != busyShift)
    {
        /* Wait until CCM internal handshake finish. */
        while ((CCM->CDHIPR & ((1UL << busyShift))) != 0UL)
        {
        }
    }
}
 
static inline uint32_t CLOCK_GetMux(clock_mux_t mux)
{
    return (((uint32_t)(CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux))) >> CCM_TUPLE_SHIFT(mux));
}
 
static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value)
{
    uint32_t busyShift;
 
    busyShift                   = CCM_TUPLE_BUSY_SHIFT(divider);
    CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) |
                                  (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider));
 
    assert(busyShift <= CCM_NO_BUSY_WAIT);
 
    /* Clock switch need Handshake? */
    if (CCM_NO_BUSY_WAIT != busyShift)
    {
        /* Wait until CCM internal handshake finish. */
        while ((CCM->CDHIPR & ((uint32_t)(1UL << busyShift))) != 0UL)
        {
        }
    }
}
 
static inline uint32_t CLOCK_GetDiv(clock_div_t divider)
{
    return ((uint32_t)(CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider));
}
 
static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value)
{
    uint32_t index = ((uint32_t)name) >> 8U;
    uint32_t shift = ((uint32_t)name) & 0x1FU;
    volatile uint32_t *reg;
 
    assert(index <= 6UL);
 
    reg  = (volatile uint32_t *)(&(((volatile uint32_t *)&CCM->CCGR0)[index]));
    *reg = ((*reg) & ~((uint32_t)(3UL << shift))) | (((uint32_t)value) << shift);
}
 
static inline void CLOCK_EnableClock(clock_ip_name_t name)
{
    CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait);
}
 
static inline void CLOCK_DisableClock(clock_ip_name_t name)
{
    CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded);
}
 
static inline void CLOCK_SetMode(clock_mode_t mode)
{
    CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode);
}
 
static inline uint32_t CLOCK_GetOscFreq(void)
{
    return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_xtalFreq;
}
 
uint32_t CLOCK_GetAhbFreq(void);
 
uint32_t CLOCK_GetSemcFreq(void);
 
uint32_t CLOCK_GetIpgFreq(void);
 
uint32_t CLOCK_GetPerClkFreq(void);
 
uint32_t CLOCK_GetFreq(clock_name_t name);
 
static inline uint32_t CLOCK_GetCpuClkFreq(void)
{
    return CLOCK_GetFreq(kCLOCK_CpuClk);
}
 
void CLOCK_InitExternalClk(bool bypassXtalOsc);
 
void CLOCK_DeinitExternalClk(void);
 
void CLOCK_SwitchOsc(clock_osc_t osc);
 
static inline uint32_t CLOCK_GetRtcFreq(void)
{
    return 32768U;
}
 
static inline void CLOCK_SetXtalFreq(uint32_t freq)
{
    g_xtalFreq = freq;
}
 
static inline void CLOCK_SetRtcXtalFreq(uint32_t freq)
{
    g_rtcXtalFreq = freq;
}
 
void CLOCK_InitRcOsc24M(void);
 
void CLOCK_DeinitRcOsc24M(void);
/* @} */
 
bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
 
bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq);
 
/* @} */
 
static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass)
{
    if (bypass)
    {
        CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
    }
    else
    {
        CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
    }
}
 
static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll)
{
    return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_PLL_BYPASS_SHIFT));
}
 
static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll)
{
    return ((CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pll))) != 0U);
}
 
static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src)
{
    CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src;
}
 
static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll)
{
    return (((CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK) >>
             CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == (uint32_t)kCLOCK_PllClkSrc24M) ?
               CLOCK_GetOscFreq() :
               CLKPN_FREQ;
}
 
void CLOCK_InitArmPll(const clock_arm_pll_config_t *config);
 
void CLOCK_DeinitArmPll(void);
 
void CLOCK_InitSysPll(const clock_sys_pll_config_t *config);
 
void CLOCK_DeinitSysPll(void);
 
void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config);
 
void CLOCK_DeinitUsb1Pll(void);
 
void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config);
 
void CLOCK_DeinitUsb2Pll(void);
 
void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
 
void CLOCK_DeinitAudioPll(void);
 
void CLOCK_InitVideoPll(const clock_video_pll_config_t *config);
 
void CLOCK_DeinitVideoPll(void);
void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config);
 
void CLOCK_DeinitEnetPll(void);
 
uint32_t CLOCK_GetPllFreq(clock_pll_t pll);
 
void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac);
 
void CLOCK_DeinitSysPfd(clock_pfd_t pfd);
 
void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac);
 
void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd);
 
uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd);
 
uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd);
 
bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
 
void CLOCK_DisableUsbhs0PhyPllClock(void);
 
bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
 
void CLOCK_DisableUsbhs1PhyPllClock(void);
 
/* @} */
 
#if defined(__cplusplus)
}
#endif /* __cplusplus */
 
#endif /* _FSL_CLOCK_H_ */