inertial_sense_ros: sysclk.c Source File

1

33 /*

34 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>

35 */

36

37 #include <sysclk.h>

38

40

41 #ifdef __cplusplus

42 extern "C" {

43 #endif

44

45

52 #if defined(CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)

53

56 uint32_t sysclk_initialized = 0;

57 #endif

58

69 void sysclk_set_prescalers(uint32_t ul_pres)

70 {

71 pmc_mck_set_prescaler(ul_pres);

72 SystemCoreClockUpdate();

73 }

74

81 void sysclk_set_source(uint32_t ul_src)

82 {

83 switch (ul_src) {

84 case SYSCLK_SRC_SLCK_RC:

85 case SYSCLK_SRC_SLCK_XTAL:

86 case SYSCLK_SRC_SLCK_BYPASS:

87 pmc_mck_set_source(PMC_MCKR_CSS_SLOW_CLK);

88 break;

89

90 case SYSCLK_SRC_MAINCK_4M_RC:

91 case SYSCLK_SRC_MAINCK_8M_RC:

92 case SYSCLK_SRC_MAINCK_12M_RC:

93 case SYSCLK_SRC_MAINCK_XTAL:

94 case SYSCLK_SRC_MAINCK_BYPASS:

95 pmc_mck_set_source(PMC_MCKR_CSS_MAIN_CLK);

96 break;

97

98 case SYSCLK_SRC_PLLACK:

99 pmc_mck_set_source(PMC_MCKR_CSS_PLLA_CLK);

100 break;

101

102 case SYSCLK_SRC_UPLLCK:

103 pmc_mck_set_source(PMC_MCKR_CSS_UPLL_CLK);

104 break;

105 }

106

107 SystemCoreClockUpdate();

108 }

109

110 #if defined(CONFIG_USBCLK_SOURCE) || defined(__DOXYGEN__)

111

120 void sysclk_enable_usb(void)

121 {

122 Assert(CONFIG_USBCLK_DIV > 0);

123

124 #ifdef CONFIG_PLL0_SOURCE

125 if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_PLL0) {

126 struct pll_config pllcfg;

127

128 pll_enable_source(CONFIG_PLL0_SOURCE);

129 pll_config_defaults(&pllcfg, 0);

130 pll_enable(&pllcfg, 0);

131 pll_wait_for_lock(0);

132 pmc_switch_udpck_to_pllack(CONFIG_USBCLK_DIV - 1);

133 pmc_enable_udpck();

134 return;

135 }

136 #endif

137

138 if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_UPLL) {

139

140 pmc_enable_upll_clock();

141 pmc_switch_udpck_to_upllck(CONFIG_USBCLK_DIV - 1);

142 pmc_enable_udpck();

143 return;

144 }

145 }

146

152 void sysclk_disable_usb(void)

153 {

154 pmc_disable_udpck();

155 }

156 #endif // CONFIG_USBCLK_SOURCE

157

158 void sysclk_init(void)

159 {

160 struct pll_config pllcfg;

161

162 /* Set flash wait state to max in case the below clock switching. */

163 system_init_flash(CHIP_FREQ_CPU_MAX / 2);

164

165 /* Config system clock setting */

166 if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) {

167 osc_enable(OSC_SLCK_32K_RC);

168 osc_wait_ready(OSC_SLCK_32K_RC);

169 pmc_mck_set_division(CONFIG_SYSCLK_DIV);

170 pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);

171 }

172

173 else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) {

174 osc_enable(OSC_SLCK_32K_XTAL);

175 osc_wait_ready(OSC_SLCK_32K_XTAL);

176 pmc_mck_set_division(CONFIG_SYSCLK_DIV);

177 pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);

178 }

179

180 else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) {

181 osc_enable(OSC_SLCK_32K_BYPASS);

182 osc_wait_ready(OSC_SLCK_32K_BYPASS);

183 pmc_mck_set_division(CONFIG_SYSCLK_DIV);

184 pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);

185 }

186

187 else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) {

188 /* Already running from SYSCLK_SRC_MAINCK_4M_RC */

189 }

190

191 else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) {

192 osc_enable(OSC_MAINCK_8M_RC);

193 osc_wait_ready(OSC_MAINCK_8M_RC);

194 pmc_mck_set_division(CONFIG_SYSCLK_DIV);

195 pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);

196 }

197

198 else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) {

199 osc_enable(OSC_MAINCK_12M_RC);

200 osc_wait_ready(OSC_MAINCK_12M_RC);

201 pmc_mck_set_division(CONFIG_SYSCLK_DIV);

202 pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);

203 }

204

205 else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) {

206 osc_enable(OSC_MAINCK_XTAL);

207 osc_wait_ready(OSC_MAINCK_XTAL);

208 pmc_mck_set_division(CONFIG_SYSCLK_DIV);

209 pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);

210 }

211

212 else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) {

213 osc_enable(OSC_MAINCK_BYPASS);

214 osc_wait_ready(OSC_MAINCK_BYPASS);

215 pmc_mck_set_division(CONFIG_SYSCLK_DIV);

216 pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);

217 }

218

219 #ifdef CONFIG_PLL0_SOURCE

220 else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) {

221 pll_enable_source(CONFIG_PLL0_SOURCE);

222 pll_config_defaults(&pllcfg, 0);

223 pll_enable(&pllcfg, 0);

224 pll_wait_for_lock(0);

225 pmc_mck_set_division(CONFIG_SYSCLK_DIV);

226 pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES);

227 }

228 #endif

229

230 else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_UPLLCK) {

231 pll_enable_source(CONFIG_PLL1_SOURCE);

232 pll_config_defaults(&pllcfg, 1);

233 pll_enable(&pllcfg, 1);

234 pll_wait_for_lock(1);

235 pmc_mck_set_division(CONFIG_SYSCLK_DIV);

236 pmc_switch_mck_to_upllck(CONFIG_SYSCLK_PRES);

237 }

238 /* Update the SystemFrequency variable */

239 SystemCoreClockUpdate();

240

241 /* Set a flash wait state depending on the master clock frequency */

242 system_init_flash(sysclk_get_cpu_hz() / CONFIG_SYSCLK_DIV);

243

244 #if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)

245 /* Signal that the internal frequencies are setup */

246 sysclk_initialized = 1;

247 #endif

248 }

249

251

253

254 #ifdef __cplusplus

255 }

256 #endif

257

258

sysclk.h

Chip-specific system clock management functions.

osc_wait_ready

static void osc_wait_ready(uint8_t id)

Wait until the oscillator identified by id is ready.

Definition: osc.h:162

CONFIG_PLL1_SOURCE

#define CONFIG_PLL1_SOURCE

Definition: same70/pll.h:97

OSC_SLCK_32K_RC

#define OSC_SLCK_32K_RC

Internal 32kHz RC oscillator.

Definition: same70/osc.h:87

CHIP_FREQ_CPU_MAX

#define CHIP_FREQ_CPU_MAX

Definition: same70j19.h:592

USBCLK_SRC_UPLL

#define USBCLK_SRC_UPLL

Use UPLL.

Definition: same70/sysclk.h:270

PMC_MCKR_CSS_SLOW_CLK

#define PMC_MCKR_CSS_SLOW_CLK

(PMC_MCKR) Slow Clock is selected

Definition: utils/cmsis/same70/include/component/pmc.h:253

pmc_switch_mck_to_pllack

uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres)

Switch master clock source selection to PLLA clock.

Definition: pmc.c:218

OSC_SLCK_32K_BYPASS

#define OSC_SLCK_32K_BYPASS

External 32kHz bypass oscillator.

Definition: same70/osc.h:89

sysclk_get_cpu_hz

static uint32_t sysclk_get_cpu_hz(void)

Return the current rate in Hz of the CPU clock.

Definition: same70/sysclk.h:378

OSC_MAINCK_12M_RC

#define OSC_MAINCK_12M_RC

Internal 12MHz RC oscillator.

Definition: same70/osc.h:92

CONFIG_SYSCLK_SOURCE

#define CONFIG_SYSCLK_SOURCE

Initial/static main system clock source.

Definition: same70/sysclk.h:215

SYSCLK_SRC_MAINCK_12M_RC

#define SYSCLK_SRC_MAINCK_12M_RC

Internal 12MHz RC oscillator as master source clock.

Definition: same70/sysclk.h:240

pmc_mck_set_prescaler

void pmc_mck_set_prescaler(uint32_t ul_pres)

Set the prescaler of the MCK.

Definition: pmc.c:96

pmc_switch_mck_to_sclk

uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres)

Switch master clock source selection to slow clock.

Definition: pmc.c:154

SystemCoreClockUpdate

void SystemCoreClockUpdate(void)

Updates the SystemCoreClock with current core Clock retrieved from cpu registers. ...

Definition: system_same70.c:108

SYSCLK_SRC_PLLACK

#define SYSCLK_SRC_PLLACK

Use PLLACK as master source clock.

Definition: same70/sysclk.h:243

SYSCLK_SRC_MAINCK_8M_RC

#define SYSCLK_SRC_MAINCK_8M_RC

Internal 8MHz RC oscillator as master source clock.

Definition: same70/sysclk.h:239

pll_enable_source

static void pll_enable_source(enum pll_source e_src)

Enable the source of the pll. The source is enabled, if the source is not already running...

Definition: same70/pll.h:197

SYSCLK_SRC_SLCK_XTAL

#define SYSCLK_SRC_SLCK_XTAL

External 32kHz crystal oscillator as master source clock.

Definition: same70/sysclk.h:236

SYSCLK_SRC_SLCK_RC

#define SYSCLK_SRC_SLCK_RC

Internal 32kHz RC oscillator as master source clock.

Definition: same70/sysclk.h:235

PMC_MCKR_CSS_MAIN_CLK

#define PMC_MCKR_CSS_MAIN_CLK

(PMC_MCKR) Main Clock is selected

Definition: utils/cmsis/same70/include/component/pmc.h:254

pll_enable

static void pll_enable(const struct pll_config *p_cfg, uint32_t ul_pll_id)

Definition: same70/pll.h:160

sysclk_set_prescalers

void sysclk_set_prescalers(uint32_t ul_pres)

Set system clock prescaler configuration.

Definition: sysclk.c:69

osc_enable

static void osc_enable(uint32_t ul_id)

Definition: same70/osc.h:109

sysclk_init

void sysclk_init(void)

Initialize the synchronous clock system.

Definition: sysclk.c:158

CONFIG_PLL0_SOURCE

#define CONFIG_PLL0_SOURCE

Definition: conf_clock.h:68

sysclk_enable_usb

void sysclk_enable_usb(void)

SYSCLK_SRC_SLCK_BYPASS

#define SYSCLK_SRC_SLCK_BYPASS

External 32kHz bypass oscillator as master source clock.

Definition: same70/sysclk.h:237

pll_config

Hardware-specific representation of PLL configuration.

Definition: same70/pll.h:78

system_init_flash

void system_init_flash(uint32_t ul_clk)

Definition: system_same70.c:202

pll_config_defaults

#define pll_config_defaults(cfg, pll_id)

Initialize PLL configuration using default parameters.

Definition: same70/pll.h:131

pll_wait_for_lock

static int pll_wait_for_lock(unsigned int pll_id)

Wait for PLL pll_id to become locked.

Definition: pll.h:317

CONFIG_USBCLK_DIV

#define CONFIG_USBCLK_DIV

Configuration symbol for the USB generic clock divider setting.

Definition: conf_clock.h:87

OSC_MAINCK_BYPASS

#define OSC_MAINCK_BYPASS

External bypass oscillator.

Definition: same70/osc.h:94

sysclk_disable_usb

void sysclk_disable_usb(void)

CONFIG_SYSCLK_PRES

#define CONFIG_SYSCLK_PRES

Initial CPU clock divider (mck)

Definition: same70/sysclk.h:228

pmc_mck_set_source

void pmc_mck_set_source(uint32_t ul_source)

Set the source of the MCK.

Definition: pmc.c:139

PMC_MCKR_CSS_PLLA_CLK

#define PMC_MCKR_CSS_PLLA_CLK

(PMC_MCKR) PLLA Clock is selected

Definition: utils/cmsis/same70/include/component/pmc.h:255

pmc_switch_mck_to_mainck

uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres)

Switch master clock source selection to main clock.

Definition: pmc.c:186

OSC_MAINCK_8M_RC

#define OSC_MAINCK_8M_RC

Internal 8MHz RC oscillator.

Definition: same70/osc.h:91

PMC_MCKR_CSS_UPLL_CLK

#define PMC_MCKR_CSS_UPLL_CLK

(PMC_MCKR) Divided UPLL Clock is selected

Definition: utils/cmsis/same70/include/component/pmc.h:256

CONFIG_SYSCLK_DIV

#define CONFIG_SYSCLK_DIV

Definition: conf_clock.h:63

OSC_MAINCK_XTAL

#define OSC_MAINCK_XTAL

External crystal oscillator.

Definition: same70/osc.h:93

USBCLK_SRC_PLL0

#define USBCLK_SRC_PLL0

Use PLLA.

Definition: same70/sysclk.h:269

SYSCLK_SRC_UPLLCK

#define SYSCLK_SRC_UPLLCK

Use UPLLCK as master source clock.

Definition: same70/sysclk.h:244

SYSCLK_SRC_MAINCK_XTAL

#define SYSCLK_SRC_MAINCK_XTAL

External crystal oscillator as master source clock.

Definition: same70/sysclk.h:241

CONFIG_USBCLK_SOURCE

#define CONFIG_USBCLK_SOURCE

Configuration symbol for the USB generic clock source.

Definition: conf_clock.h:86

Assert

#define Assert(expr)

This macro is used to test fatal errors.

Definition: compiler.h:196

SYSCLK_SRC_MAINCK_BYPASS

#define SYSCLK_SRC_MAINCK_BYPASS

External bypass oscillator as master source clock.

Definition: same70/sysclk.h:242

OSC_SLCK_32K_XTAL

#define OSC_SLCK_32K_XTAL

External 32kHz crystal oscillator.

Definition: same70/osc.h:88

SYSCLK_SRC_MAINCK_4M_RC

#define SYSCLK_SRC_MAINCK_4M_RC

Internal 4MHz RC oscillator as master source clock.

Definition: same70/sysclk.h:238

sysclk_set_source

void sysclk_set_source(uint32_t ul_src)

Change the source of the main system clock.

Definition: sysclk.c:81