Collaboration diagram for PLL Management:

Classes
struct	pll_config
	Hardware-specific representation of PLL configuration. More...

Macros
#define	CONFIG_PLL1_DIV 0

#define	CONFIG_PLL1_MUL 0

#define	CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL

#define	PLL_COUNT 0x3fU

#define	PLL_INPUT_MAX_HZ 32000000

#define	PLL_INPUT_MIN_HZ 3000000

#define	PLL_OUTPUT_MAX_HZ 500000000

#define	PLL_OUTPUT_MIN_HZ 160000000

#define	PLL_UPLL_HZ 480000000

#define	PLLA_ID 0

#define	UPLL_ID 1
	USB UTMI PLL. More...

Enumerations
enum	pll_source { PLL_SRC_MAINCK_4M_RC = OSC_MAINCK_4M_RC, PLL_SRC_MAINCK_8M_RC = OSC_MAINCK_8M_RC, PLL_SRC_MAINCK_12M_RC = OSC_MAINCK_12M_RC, PLL_SRC_MAINCK_XTAL = OSC_MAINCK_XTAL, PLL_SRC_MAINCK_BYPASS = OSC_MAINCK_BYPASS, PLL_NR_SOURCES }
	PLL clock source. More...

Functions
static void	pll_config_init (struct pll_config *p_cfg, enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul)

static void	pll_config_read (struct pll_config *p_cfg, uint32_t ul_pll_id)

static void	pll_config_write (const struct pll_config *p_cfg, uint32_t ul_pll_id)

static void	pll_disable (uint32_t ul_pll_id)

static void	pll_enable (const struct pll_config *p_cfg, uint32_t ul_pll_id)

static uint32_t	pll_is_locked (uint32_t ul_pll_id)

Chip-specific PLL characteristics
#define	NR_PLLS 2
	Number of on-chip PLLs. More...

PLL configuration
#define	pll_config_defaults(cfg, pll_id)
	Initialize PLL configuration using default parameters. More...

#define	pll_get_default_rate(pll_id)
	Get the default rate in Hz of pll_id. More...

Interaction with the PLL hardware
static int	pll_wait_for_lock (unsigned int pll_id)
	Wait for PLL pll_id to become locked. More...

static void	pll_enable_source (enum pll_source e_src)
	Enable the source of the pll. The source is enabled, if the source is not already running. More...

static void	pll_enable_config_defaults (unsigned int ul_pll_id)
	Enable the pll with the default configuration. PLL is enabled, if the PLL is not already locked. More...

Detailed Description

This group contains functions and definitions related to configuring and enabling/disabling on-chip PLLs. A PLL will take an input signal (the source), optionally divide the frequency by a configurable divider, and then multiply the frequency by a configurable multiplier.

Some devices don't support input dividers; specifying any other divisor than 1 on these devices will result in an assertion failure. Other devices may have various restrictions to the frequency range of the input and output signals.

Example: Setting up PLL0 with default parameters

The following example shows how to configure and enable PLL0 using the default parameters specified using the configuration symbols listed above.

pll_enable_config_defaults(0);

To configure, enable PLL0 using the default parameters and to disable a specific feature like Wide Bandwidth Mode (a UC3A3-specific PLL option.), you can use this initialization process.

struct pll_config pllcfg;
if (pll_is_locked(pll_id)) {
   return; // Pll already running
}
pll_enable_source(CONFIG_PLL0_SOURCE);
pll_config_defaults(&pllcfg, 0);
pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE);
pll_enable(&pllcfg, 0);
pll_wait_for_lock(0); 

When the last function call returns, PLL0 is ready to be used as the main system clock source.

Configuration Symbols

Each PLL has a set of default parameters determined by the following configuration symbols in the application's configuration file:

CONFIG_PLLn_SOURCE: The default clock source connected to the input of PLL n. Must be one of the values defined by the pll_source enum.
CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL n.
CONFIG_PLLn_DIV: The default input divider of PLL n.

These configuration symbols determine the result of calling pll_config_defaults() and pll_get_default_rate().

Macro Definition Documentation

◆ CONFIG_PLL1_DIV

#define CONFIG_PLL1_DIV 0

Definition at line 99 of file same70/pll.h.

◆ CONFIG_PLL1_MUL

#define CONFIG_PLL1_MUL 0

Definition at line 98 of file same70/pll.h.

◆ CONFIG_PLL1_SOURCE

#define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL

Definition at line 97 of file same70/pll.h.

◆ NR_PLLS

#define NR_PLLS 2

Number of on-chip PLLs.

Definition at line 61 of file same70/pll.h.

◆ pll_config_defaults

#define pll_config_defaults	(	cfg,
		pll_id
	)

Value:

pll_config_init(cfg,                                             \
                        CONFIG_PLL##pll_id##_SOURCE,                     \
                        CONFIG_PLL##pll_id##_DIV,                        \
                        CONFIG_PLL##pll_id##_MUL)

Initialize PLL configuration using default parameters.

After this function returns, cfg will contain a configuration which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV) times the frequency of CONFIG_PLLx_SOURCE.

Parameters

cfg	The PLL configuration to be initialized.
pll_id	Use defaults for this PLL.

Definition at line 131 of file same70/pll.h.

◆ PLL_COUNT

#define PLL_COUNT 0x3fU

Definition at line 67 of file same70/pll.h.

◆ pll_get_default_rate

#define pll_get_default_rate ( pll_id )

Value:

((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE)                      \
                        * CONFIG_PLL##pll_id##_MUL)                      \
                        / CONFIG_PLL##pll_id##_DIV)

Get the default rate in Hz of pll_id.

Definition at line 82 of file same70/pll.h.

◆ PLL_INPUT_MAX_HZ

#define PLL_INPUT_MAX_HZ 32000000

Definition at line 59 of file same70/pll.h.

◆ PLL_INPUT_MIN_HZ

#define PLL_INPUT_MIN_HZ 3000000

Definition at line 58 of file same70/pll.h.

◆ PLL_OUTPUT_MAX_HZ

#define PLL_OUTPUT_MAX_HZ 500000000

Definition at line 56 of file same70/pll.h.

◆ PLL_OUTPUT_MIN_HZ

#define PLL_OUTPUT_MIN_HZ 160000000

Definition at line 55 of file same70/pll.h.

◆ PLL_UPLL_HZ

#define PLL_UPLL_HZ 480000000

Definition at line 65 of file same70/pll.h.

◆ PLLA_ID

#define PLLA_ID 0

Definition at line 62 of file same70/pll.h.

◆ UPLL_ID

#define UPLL_ID 1

USB UTMI PLL.

Definition at line 63 of file same70/pll.h.

Enumeration Type Documentation

◆ pll_source

enum pll_source

PLL clock source.

Enumerator
PLL_SRC_MAINCK_4M_RC	Internal 4MHz RC oscillator.
PLL_SRC_MAINCK_8M_RC	Internal 8MHz RC oscillator.
PLL_SRC_MAINCK_12M_RC	Internal 12MHz RC oscillator.
PLL_SRC_MAINCK_XTAL	External crystal oscillator.
PLL_SRC_MAINCK_BYPASS	External bypass oscillator.
PLL_NR_SOURCES	Number of PLL sources.

Definition at line 69 of file same70/pll.h.

Function Documentation

◆ pll_config_init()

static void pll_config_init	(	struct pll_config *	p_cfg,
		enum pll_source	e_src,
		uint32_t	ul_div,
		uint32_t	ul_mul
	)

inlinestatic

Note: The SAMV71 PLL hardware interprets mul as mul+1. For readability the hardware mul+1 is hidden in this implementation. Use mul as mul effective value.

Definition at line 106 of file same70/pll.h.

◆ pll_config_read()

static void pll_config_read	(	struct pll_config *	p_cfg,
		uint32_t	ul_pll_id
	)

inlinestatic

Definition at line 137 of file same70/pll.h.

◆ pll_config_write()

static void pll_config_write	(	const struct pll_config *	p_cfg,
		uint32_t	ul_pll_id
	)

inlinestatic

Definition at line 148 of file same70/pll.h.

◆ pll_disable()

static void pll_disable ( uint32_t ul_pll_id )

inlinestatic

Note: This will only disable the selected PLL, not the underlying oscillator (mainck).

Definition at line 175 of file same70/pll.h.

◆ pll_enable()

static void pll_enable	(	const struct pll_config *	p_cfg,
		uint32_t	ul_pll_id
	)

inlinestatic

Definition at line 160 of file same70/pll.h.

◆ pll_enable_config_defaults()

void pll_enable_config_defaults ( unsigned int pll_id )

inlinestatic

Enable the pll with the default configuration. PLL is enabled, if the PLL is not already locked.

Parameters

pll_id The ID of the PLL to enable.

Definition at line 215 of file same70/pll.h.

◆ pll_enable_source()

void pll_enable_source ( enum pll_source src )

inlinestatic

Enable the source of the pll. The source is enabled, if the source is not already running.

Parameters

src	The ID of the PLL source to enable.

Definition at line 197 of file same70/pll.h.

◆ pll_is_locked()

static uint32_t pll_is_locked ( uint32_t ul_pll_id )

inlinestatic

Definition at line 186 of file same70/pll.h.

◆ pll_wait_for_lock()

static int pll_wait_for_lock ( unsigned int pll_id )

inlinestatic

Wait for PLL pll_id to become locked.

Todo:: Use a timeout to avoid waiting forever and hanging the system

Parameters

pll_id The ID of the PLL to wait for.

Return values

STATUS_OK	The PLL is now locked.
ERR_TIMEOUT	Timed out waiting for PLL to become locked.

Definition at line 317 of file pll.h.

Classes

Macros

Enumerations

Functions

Chip-specific PLL characteristics

PLL configuration

Interaction with the PLL hardware

Detailed Description

Configuration Symbols

Macro Definition Documentation

◆ CONFIG_PLL1_DIV

◆ CONFIG_PLL1_MUL

◆ CONFIG_PLL1_SOURCE

◆ NR_PLLS

◆ pll_config_defaults

◆ PLL_COUNT

◆ pll_get_default_rate

◆ PLL_INPUT_MAX_HZ

◆ PLL_INPUT_MIN_HZ

◆ PLL_OUTPUT_MAX_HZ

◆ PLL_OUTPUT_MIN_HZ

◆ PLL_UPLL_HZ

◆ PLLA_ID

◆ UPLL_ID

Enumeration Type Documentation

◆ pll_source

Function Documentation

◆ pll_config_init()

◆ pll_config_read()

◆ pll_config_write()

◆ pll_disable()

◆ pll_enable()

◆ pll_enable_config_defaults()

◆ pll_enable_source()

◆ pll_is_locked()

◆ pll_wait_for_lock()