same70/sysclk.h

Go to the documentation of this file.

/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */

#ifndef CHIP_SYSCLK_H_INCLUDED
#define CHIP_SYSCLK_H_INCLUDED

#include <osc.h>
#include <pll.h>


#ifdef __cplusplus
extern "C" {
#endif




#ifndef CONFIG_SYSCLK_SOURCE
# define CONFIG_SYSCLK_SOURCE   SYSCLK_SRC_MAINCK_4M_RC
#endif

#ifndef CONFIG_SYSCLK_PRES
# define CONFIG_SYSCLK_PRES  0
#endif



#define SYSCLK_SRC_SLCK_RC         0 
#define SYSCLK_SRC_SLCK_XTAL       1 
#define SYSCLK_SRC_SLCK_BYPASS     2 
#define SYSCLK_SRC_MAINCK_4M_RC    3 
#define SYSCLK_SRC_MAINCK_8M_RC    4 
#define SYSCLK_SRC_MAINCK_12M_RC   5 
#define SYSCLK_SRC_MAINCK_XTAL     6 
#define SYSCLK_SRC_MAINCK_BYPASS   7 
#define SYSCLK_SRC_PLLACK          8 
#define SYSCLK_SRC_UPLLCK          9       



#define SYSCLK_PRES_1   PMC_MCKR_PRES_CLK_1  
#define SYSCLK_PRES_2   PMC_MCKR_PRES_CLK_2  
#define SYSCLK_PRES_4   PMC_MCKR_PRES_CLK_4  
#define SYSCLK_PRES_8   PMC_MCKR_PRES_CLK_8  
#define SYSCLK_PRES_16  PMC_MCKR_PRES_CLK_16 
#define SYSCLK_PRES_32  PMC_MCKR_PRES_CLK_32 
#define SYSCLK_PRES_64  PMC_MCKR_PRES_CLK_64 
#define SYSCLK_PRES_3   PMC_MCKR_PRES_CLK_3  



#define SYSCLK_DIV_1   PMC_MCKR_MDIV_EQ_PCK  
#define SYSCLK_DIV_2   PMC_MCKR_MDIV_PCK_DIV2  
#define SYSCLK_DIV_4   PMC_MCKR_MDIV_PCK_DIV4  
#define SYSCLK_DIV_3   PMC_MCKR_MDIV_PCK_DIV3  



#define USBCLK_SRC_PLL0       0     
#define USBCLK_SRC_UPLL       1     



#ifdef __DOXYGEN__
# define CONFIG_USBCLK_SOURCE
#endif

#ifdef __DOXYGEN__
# define CONFIG_USBCLK_DIV
#endif


#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
extern uint32_t sysclk_initialized;
#endif
static inline uint32_t sysclk_get_main_hz(void)
{
#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
        if (!sysclk_initialized ) {
                return OSC_MAINCK_4M_RC_HZ;
        }
#endif

        /* Config system clock setting */
        if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) {
                return OSC_SLCK_32K_RC_HZ;
        } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) {
                return OSC_SLCK_32K_XTAL_HZ;
        } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) {
                return OSC_SLCK_32K_BYPASS_HZ;
        } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) {
                return OSC_MAINCK_4M_RC_HZ;
        } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) {
                return OSC_MAINCK_8M_RC_HZ;
        } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) {
                return OSC_MAINCK_12M_RC_HZ;
        } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) {
                return OSC_MAINCK_XTAL_HZ;
        } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) {
                return OSC_MAINCK_BYPASS_HZ;
        }
#ifdef CONFIG_PLL0_SOURCE
        else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) {
                return pll_get_default_rate(0);
        }
#endif

#ifdef CONFIG_PLL1_SOURCE
        else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_UPLLCK) {
                return PLL_UPLL_HZ;
        }
#endif
        else {
                /* unhandled_case(CONFIG_SYSCLK_SOURCE); */
                return 0;
        }
}

static inline uint32_t sysclk_get_cpu_hz(void)
{
        /* CONFIG_SYSCLK_PRES is the register value for setting the expected */
        /* prescaler, not an immediate value. */
        return sysclk_get_main_hz() /
                ((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 :
                        (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos)));
}

static inline uint32_t sysclk_get_peripheral_hz(void)
{
        /* CONFIG_SYSCLK_PRES is the register value for setting the expected */
        /* prescaler, not an immediate value. */
        return sysclk_get_main_hz() /
                (((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 : (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos))) * CONFIG_SYSCLK_DIV);
}

static inline uint32_t sysclk_get_peripheral_bus_hz(const volatile void *module)
{
        UNUSED(module);
        return sysclk_get_peripheral_hz();
}



static inline void sysclk_enable_peripheral_clock(uint32_t ul_id)
{
        pmc_enable_periph_clk(ul_id);
}

static inline void sysclk_disable_peripheral_clock(uint32_t ul_id)
{
        pmc_disable_periph_clk(ul_id);
}




extern void sysclk_set_prescalers(uint32_t ul_pres);
extern void sysclk_set_source(uint32_t ul_src);


extern void sysclk_enable_usb(void);
extern void sysclk_disable_usb(void);

extern void sysclk_init(void);



#ifdef __cplusplus
}
#endif


#endif /* CHIP_SYSCLK_H_INCLUDED */