pmc.c

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/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */

#include "pmc.h"

#if (SAM3N)
# define MAX_PERIPH_ID    31
#elif (SAM3XA)
# define MAX_PERIPH_ID    44
#elif (SAM3U)
# define MAX_PERIPH_ID    29
#elif (SAM3S || SAM4S)
# define MAX_PERIPH_ID    34
#elif (SAM4E)
# define MAX_PERIPH_ID    47
#elif (SAMV71)
# define MAX_PERIPH_ID    63
#elif (SAMV70)
# define MAX_PERIPH_ID    63
#elif (SAME70)
# define MAX_PERIPH_ID    63
#elif (SAMS70)
# define MAX_PERIPH_ID    63
#elif (SAM4N)
# define MAX_PERIPH_ID    31
#elif (SAM4C || SAM4CM || SAM4CP)
# define MAX_PERIPH_ID    43
#elif (SAMG51)
# define MAX_PERIPH_ID    47
#elif (SAMG53)
# define MAX_PERIPH_ID    47
#elif (SAMG54)
# define MAX_PERIPH_ID    47
#elif (SAMG55)
# define MAX_PERIPH_ID    50
#endif


#ifdef __cplusplus
extern "C" {
#endif


void pmc_mck_set_prescaler(uint32_t ul_pres)
{
        PMC->PMC_MCKR =
                        (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
        while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
}

#if SAMV71 || SAMV70 || SAME70 || SAMS70

void pmc_mck_set_division(uint32_t ul_div)
{
        switch (ul_div) {
                case 1:
                        ul_div = PMC_MCKR_MDIV_EQ_PCK;
                        break;
                case 2:
                        ul_div = PMC_MCKR_MDIV_PCK_DIV2;
                        break;
                case 3:
                        ul_div = PMC_MCKR_MDIV_PCK_DIV3;
                        break;
                case 4:
                        ul_div = PMC_MCKR_MDIV_PCK_DIV4;
                        break;
                default:
                        ul_div = PMC_MCKR_MDIV_EQ_PCK;
                        break;
        }
        PMC->PMC_MCKR =
                        (PMC->PMC_MCKR & (~PMC_MCKR_MDIV_Msk)) | ul_div;
        while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
}
#endif

void pmc_mck_set_source(uint32_t ul_source)
{
        PMC->PMC_MCKR =
                        (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | ul_source;
        while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
}

uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres)
{
        uint32_t ul_timeout;

        PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
                        PMC_MCKR_CSS_SLOW_CLK;
        for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
                        --ul_timeout) {
                if (ul_timeout == 0) {
                        return 1;
                }
        }

        PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
        for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
                        --ul_timeout) {
                if (ul_timeout == 0) {
                        return 1;
                }
        }

        return 0;
}

uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres)
{
        uint32_t ul_timeout;

        PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
                        PMC_MCKR_CSS_MAIN_CLK;
        for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
                        --ul_timeout) {
                if (ul_timeout == 0) {
                        return 1;
                }
        }

        PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
        for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
                        --ul_timeout) {
                if (ul_timeout == 0) {
                        return 1;
                }
        }

        return 0;
}

uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres)
{
        uint32_t ul_timeout;

        PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
        for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
                        --ul_timeout) {
                if (ul_timeout == 0) {
                        return 1;
                }
        }

        PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
                        PMC_MCKR_CSS_PLLA_CLK;

        for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
                        --ul_timeout) {
                if (ul_timeout == 0) {
                        return 1;
                }
        }

        return 0;
}

#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)

uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres)
{
        uint32_t ul_timeout;

        PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
        for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
                        --ul_timeout) {
                if (ul_timeout == 0) {
                        return 1;
                }
        }

        PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
                        PMC_MCKR_CSS_PLLB_CLK;
        for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
                        --ul_timeout) {
                if (ul_timeout == 0) {
                        return 1;
                }
        }

        return 0;
}
#endif

#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)

uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres)
{
        uint32_t ul_timeout;

        PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
        for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
                        --ul_timeout) {
                if (ul_timeout == 0) {
                        return 1;
                }
        }

        PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
                        PMC_MCKR_CSS_UPLL_CLK;
        for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
                        --ul_timeout) {
                if (ul_timeout == 0) {
                        return 1;
                }
        }

        return 0;
}
#endif

void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass)
{
        /* Set Bypass mode if required */
        if (ul_bypass == 1) {
                SUPC->SUPC_MR |= SUPC_MR_KEY_PASSWD |
                        SUPC_MR_OSCBYPASS;
        }

        SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL;
}

uint32_t pmc_osc_is_ready_32kxtal(void)
{
        return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL)
                        && (PMC->PMC_SR & PMC_SR_OSCSELS));
}

void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf)
{
        /* Enable Fast RC oscillator but DO NOT switch to RC now */
        PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN);

        /* Wait the Fast RC to stabilize */
        while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));

        /* Change Fast RC oscillator frequency */
        PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |
                        CKGR_MOR_KEY_PASSWD | ul_moscrcf;

        /* Wait the Fast RC to stabilize */
        while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));

        /* Switch to Fast RC */
        PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) |
                        CKGR_MOR_KEY_PASSWD;
}

void pmc_osc_enable_fastrc(uint32_t ul_rc)
{
        /* Enable Fast RC oscillator but DO NOT switch to RC */
        PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN);
        /* Wait the Fast RC to stabilize */
        while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));

        /* Change Fast RC oscillator frequency */
        PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |
                        CKGR_MOR_KEY_PASSWD | ul_rc;
        /* Wait the Fast RC to stabilize */
        while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
}

void pmc_osc_disable_fastrc(void)
{
        /* Disable Fast RC oscillator */
        PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN &
                                        ~CKGR_MOR_MOSCRCF_Msk)
                                | CKGR_MOR_KEY_PASSWD;
}

uint32_t pmc_osc_is_ready_fastrc(void)
{
        return (PMC->PMC_SR & PMC_SR_MOSCRCS);
}

void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time)
{
        uint32_t mor = PMC->CKGR_MOR;
        mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);
        mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN |
                        CKGR_MOR_MOSCXTST(ul_xtal_startup_time);
        PMC->CKGR_MOR = mor;
        /* Wait the main Xtal to stabilize */
        while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
}

void pmc_osc_bypass_main_xtal(void)
{
        uint32_t mor = PMC->CKGR_MOR;
        mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);
        mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY;
        /* Enable Crystal oscillator but DO NOT switch now. Keep MOSCSEL to 0 */
        PMC->CKGR_MOR = mor;
        /* The MOSCXTS in PMC_SR is automatically set */
}

void pmc_osc_disable_main_xtal(void)
{
        uint32_t mor = PMC->CKGR_MOR;
        mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);
        PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;
}

uint32_t pmc_osc_is_bypassed_main_xtal(void)
{
        return (PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY);
}

uint32_t pmc_osc_is_ready_main_xtal(void)
{
        return (PMC->PMC_SR & PMC_SR_MOSCXTS);
}

void pmc_switch_mainck_to_xtal(uint32_t ul_bypass,
                uint32_t ul_xtal_startup_time)
{
        /* Enable Main Xtal oscillator */
        if (ul_bypass) {
                PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
                                CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY |
                                CKGR_MOR_MOSCSEL;
        } else {
                PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
                                CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN |
                                CKGR_MOR_MOSCXTST(ul_xtal_startup_time);
                /* Wait the Xtal to stabilize */
                while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));

                PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL;
        }
}

void pmc_osc_disable_xtal(uint32_t ul_bypass)
{
        /* Disable xtal oscillator */
        if (ul_bypass) {
                PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
                                CKGR_MOR_KEY_PASSWD;
        } else {
                PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
                                CKGR_MOR_KEY_PASSWD;
        }
}

uint32_t pmc_osc_is_ready_mainck(void)
{
        return PMC->PMC_SR & PMC_SR_MOSCSELS;
}

void pmc_mainck_osc_select(uint32_t ul_xtal_rc)
{
        uint32_t mor = PMC->CKGR_MOR;
        if (ul_xtal_rc) {
                mor |=  CKGR_MOR_MOSCSEL;
        } else {
                mor &= ~CKGR_MOR_MOSCSEL;
        }
        PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;
}

void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva)
{
        /* first disable the PLL to unlock the lock */
        pmc_disable_pllack();

#if (SAM4C || SAM4CM || SAM4CP || SAMG)
        PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(diva) |
                        CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula);
#else
        PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(diva) |
                        CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula);
#endif
        while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0);
}

void pmc_disable_pllack(void)
{
#if (SAM4C || SAM4CM || SAM4CP || SAMG)
        PMC->CKGR_PLLAR = CKGR_PLLAR_MULA(0);
#else
        PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0);
#endif
}

uint32_t pmc_is_locked_pllack(void)
{
        return (PMC->PMC_SR & PMC_SR_LOCKA);
}

#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)

void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb)
{
        /* first disable the PLL to unlock the lock */
        pmc_disable_pllbck();

#if SAMG55
        PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(divb) |
                CKGR_PLLAR_PLLACOUNT(pllbcount) | CKGR_PLLAR_MULA(mulb);
#else
        PMC->CKGR_PLLBR =
                        CKGR_PLLBR_DIVB(divb) | CKGR_PLLBR_PLLBCOUNT(pllbcount)
                        | CKGR_PLLBR_MULB(mulb);
#endif
        while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0);
}

void pmc_disable_pllbck(void)
{
        PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0);
}

uint32_t pmc_is_locked_pllbck(void)
{
        return (PMC->PMC_SR & PMC_SR_LOCKB);
}
#endif

#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)

void pmc_enable_upll_clock(void)
{
        PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN;

        /* Wait UTMI PLL Lock Status */
        while (!(PMC->PMC_SR & PMC_SR_LOCKU));
}

void pmc_disable_upll_clock(void)
{
        PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;
}

uint32_t pmc_is_locked_upll(void)
{
        return (PMC->PMC_SR & PMC_SR_LOCKU);
}
#endif

uint32_t pmc_enable_periph_clk(uint32_t ul_id)
{
#if defined(REG_PMC_PCR) && !SAMG55
        uint32_t pcr;
        PMC->PMC_PCR = ul_id & 0x7F;
        pcr = PMC->PMC_PCR | PMC_PCR_EN | PMC_PCR_CMD;
        PMC->PMC_PCR = pcr;
        return 0;
#else
        if (ul_id > MAX_PERIPH_ID) {
                return 1;
        }

        if (ul_id < 32) {
                if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) {
                        PMC->PMC_PCER0 = 1 << ul_id;
                }
#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
        } else {
                ul_id -= 32;
                if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) {
                        PMC->PMC_PCER1 = 1 << ul_id;
                }
#endif
        }

        return 0;
#endif /* defined(REG_PMC_PCR) && !SAMG55 */
}

uint32_t pmc_disable_periph_clk(uint32_t ul_id)
{
#if defined(REG_PMC_PCR) && !SAMG55
        uint32_t pcr;
        PMC->PMC_PCR = ul_id & 0x7F;
        pcr = PMC->PMC_PCR | PMC_PCR_CMD;
        PMC->PMC_PCR = pcr;
        return 0;
#else
        if (ul_id > MAX_PERIPH_ID) {
                return 1;
        }

        if (ul_id < 32) {
                if ((PMC->PMC_PCSR0 & (1u << ul_id)) == (1u << ul_id)) {
                        PMC->PMC_PCDR0 = 1 << ul_id;
                }
#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 \
                || SAMV70 || SAME70 || SAMS70)
        } else {
                ul_id -= 32;
                if ((PMC->PMC_PCSR1 & (1u << ul_id)) == (1u << ul_id)) {
                        PMC->PMC_PCDR1 = 1 << ul_id;
                }
#endif
        }
        return 0;
#endif /* defined(REG_PMC_PCR) && !SAMG55 */
}

void pmc_enable_all_periph_clk(void)
{
        PMC->PMC_PCER0 = PMC_MASK_STATUS0;
        while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != PMC_MASK_STATUS0);

#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71  \
                || SAMV70 || SAME70 || SAMS70)
        PMC->PMC_PCER1 = PMC_MASK_STATUS1;
        while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != PMC_MASK_STATUS1);
#endif

#if defined(REG_PMC_PCR) && !SAMG55
        for (uint32_t id = 64; id <= 0x7F; id ++) {
                pmc_enable_periph_clk(id);
        }
#endif
}

void pmc_disable_all_periph_clk(void)
{
        PMC->PMC_PCDR0 = PMC_MASK_STATUS0;
        while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != 0);

#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
                || SAMV70 || SAME70 || SAMS70)
        PMC->PMC_PCDR1 = PMC_MASK_STATUS1;
        while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != 0);
#endif

#if defined(REG_PMC_PCR) && !SAMG55
        for (uint32_t id = 64; id <= 0x7F; id ++) {
                pmc_disable_periph_clk(id);
        }
#endif
}

uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id)
{
#if defined(REG_PMC_PCR) && !SAMG55
        PMC->PMC_PCR = ul_id & 0x7F;
        return (PMC->PMC_PCR & PMC_PCR_EN) ? 1 : 0;
#else
        if (ul_id > MAX_PERIPH_ID) {
                return 0;
        }

#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
                || SAMV70 || SAME70 || SAMS70)
        if (ul_id < 32) {
#endif
                if ((PMC->PMC_PCSR0 & (1u << ul_id))) {
                        return 1;
                } else {
                        return 0;
                }
#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
                || SAMV70 || SAME70 || SAMS70)
        } else {
                ul_id -= 32;
                if ((PMC->PMC_PCSR1 & (1u << ul_id))) {
                        return 1;
                } else {
                        return 0;
                }
        }
#endif
#endif /* defined(REG_PMC_PCR) && !SAMG55 */
}

void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres)
{
        PMC->PMC_PCK[ul_id] =
                        (PMC->PMC_PCK[ul_id] & ~PMC_PCK_PRES_Msk) | ul_pres;
        while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))
                        && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));
}

void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source)
{
        PMC->PMC_PCK[ul_id] =
                        (PMC->PMC_PCK[ul_id] & ~PMC_PCK_CSS_Msk) | ul_source;
        while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))
                        && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));
}

uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres)
{
        uint32_t ul_timeout;

        PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_SLOW_CLK | ul_pres;
        for (ul_timeout = PMC_TIMEOUT;
        !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
                if (ul_timeout == 0) {
                        return 1;
                }
        }

        return 0;
}

uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres)
{
        uint32_t ul_timeout;

        PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MAIN_CLK | ul_pres;
        for (ul_timeout = PMC_TIMEOUT;
        !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
                if (ul_timeout == 0) {
                        return 1;
                }
        }

        return 0;
}

uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres)
{
        uint32_t ul_timeout;

        PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLA_CLK | ul_pres;
        for (ul_timeout = PMC_TIMEOUT;
        !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
                if (ul_timeout == 0) {
                        return 1;
                }
        }

        return 0;
}

#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)

uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres)
{
        uint32_t ul_timeout;

        PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLB_CLK | ul_pres;
        for (ul_timeout = PMC_TIMEOUT;
                        !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));
                        --ul_timeout) {
                if (ul_timeout == 0) {
                        return 1;
                }
        }

        return 0;
}
#endif

#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)

uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres)
{
        uint32_t ul_timeout;

        PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_UPLL_CLK | ul_pres;
        for (ul_timeout = PMC_TIMEOUT;
                        !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));
                        --ul_timeout) {
                if (ul_timeout == 0) {
                        return 1;
                }
        }

        return 0;
}
#endif

uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres)
{
        uint32_t ul_timeout;

        PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MCK | ul_pres;
        for (ul_timeout = PMC_TIMEOUT;
        !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
                if (ul_timeout == 0) {
                        return 1;
                }
        }

        return 0;
}

void pmc_enable_pck(uint32_t ul_id)
{
        PMC->PMC_SCER = PMC_SCER_PCK0 << ul_id;
}

void pmc_disable_pck(uint32_t ul_id)
{
        PMC->PMC_SCDR = PMC_SCER_PCK0 << ul_id;
}

void pmc_enable_all_pck(void)
{
        PMC->PMC_SCER = PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2;
}

void pmc_disable_all_pck(void)
{
        PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2;
}

uint32_t pmc_is_pck_enabled(uint32_t ul_id)
{
        if (ul_id > 2) {
                return 0;
        }

        return (PMC->PMC_SCSR & (PMC_SCSR_PCK0 << ul_id));
}

#if (SAM4C || SAM4CM || SAM4CP)

void pmc_enable_cpck(void)
{
        PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD;
}

void pmc_disable_cpck(void)
{
        PMC->PMC_SCDR = PMC_SCDR_CPCK | PMC_SCDR_CPKEY_PASSWD;
}

bool pmc_is_cpck_enabled(void)
{
        if(PMC->PMC_SCSR & PMC_SCSR_CPCK) {
                return 1;
        } else {
                return 0;
        }
}

void pmc_enable_cpbmck(void)
{
        PMC->PMC_SCER = PMC_SCER_CPBMCK | PMC_SCER_CPKEY_PASSWD;
}

void pmc_disable_cpbmck(void)
{
        PMC->PMC_SCDR = PMC_SCDR_CPBMCK | PMC_SCDR_CPKEY_PASSWD;
}

bool pmc_is_cpbmck_enabled(void)
{
        if(PMC->PMC_SCSR & PMC_SCSR_CPBMCK) {
                return 1;
        } else {
                return 0;
        }
}

void pmc_cpck_set_prescaler(uint32_t ul_pres)
{
        PMC->PMC_MCKR =
                        (PMC->PMC_MCKR & (~PMC_MCKR_CPPRES_Msk)) | PMC_MCKR_CPPRES(ul_pres);
}

void pmc_cpck_set_source(uint32_t ul_source)
{
        PMC->PMC_MCKR =
                        (PMC->PMC_MCKR & (~PMC_MCKR_CPCSS_Msk)) | ul_source;
}
#endif

#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)

void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv)
{
        PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv);
}
#endif

#if (SAM3S || SAM4S || SAMG55)

void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv)
{
        PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS;
}
#endif

#if (SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70)

void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv)
{
        PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(ul_usbdiv);
}
#endif

#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)

void pmc_enable_udpck(void)
{
#if (SAM3S || SAM4S || SAM4E || SAMG55)
        PMC->PMC_SCER = PMC_SCER_UDP;
#elif (SAMV71 || SAMV70 || SAME70 || SAMS70)
        PMC->PMC_SCER = PMC_SCER_USBCLK;
#else
        PMC->PMC_SCER = PMC_SCER_UOTGCLK;
# endif
}

void pmc_disable_udpck(void)
{
#if (SAM3S || SAM4S || SAM4E || SAMG55)
        PMC->PMC_SCDR = PMC_SCDR_UDP;
#elif (SAMV71 || SAMV70 || SAME70 || SAMS70)
        PMC->PMC_SCDR = PMC_SCDR_USBCLK;
#else
        PMC->PMC_SCDR = PMC_SCDR_UOTGCLK;
# endif
}
#endif

#if SAMG55

void pmc_switch_uhpck_to_pllack(uint32_t ul_usbdiv)
{
        PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv);
}

void pmc_switch_uhpck_to_pllbck(uint32_t ul_usbdiv)
{
        PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS;
}

void pmc_enable_uhpck(void)
{
        PMC->PMC_SCER = PMC_SCER_UHP;
}
#endif

void pmc_enable_interrupt(uint32_t ul_sources)
{
        PMC->PMC_IER = ul_sources;
}

void pmc_disable_interrupt(uint32_t ul_sources)
{
        PMC->PMC_IDR = ul_sources;
}

uint32_t pmc_get_interrupt_mask(void)
{
        return PMC->PMC_IMR;
}

uint32_t pmc_get_status(void)
{
        return PMC->PMC_SR;
}

void pmc_set_fast_startup_input(uint32_t ul_inputs)
{
        ul_inputs &= PMC_FAST_STARTUP_Msk;
        PMC->PMC_FSMR |= ul_inputs;
}

void pmc_clr_fast_startup_input(uint32_t ul_inputs)
{
        ul_inputs &= PMC_FAST_STARTUP_Msk;
        PMC->PMC_FSMR &= ~ul_inputs;
}

#if (SAM4C || SAM4CM || SAM4CP)

void pmc_cp_set_fast_startup_input(uint32_t ul_inputs)
{
        ul_inputs &= PMC_FAST_STARTUP_Msk;
        PMC->PMC_CPFSMR |= ul_inputs;
}

void pmc_cp_clr_fast_startup_input(uint32_t ul_inputs)
{
        ul_inputs &= PMC_FAST_STARTUP_Msk;
        PMC->PMC_CPFSMR &= ~ul_inputs;
}
#endif

void pmc_enable_sleepmode(uint8_t uc_type)
{
#if !(SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
        PMC->PMC_FSMR &= (uint32_t) ~ PMC_FSMR_LPM; // Enter Sleep mode
#endif
        SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep

#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
        UNUSED(uc_type);
        __DSB();
        __WFI();
#else
        if (uc_type == 0) {
                __DSB();
                __WFI();
        } else {
                __DSB();
                __WFE();
        }
#endif
}

#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
static uint32_t ul_flash_in_wait_mode = PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN;
void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state)
{
        ul_flash_in_wait_mode = ul_flash_state;
}

void pmc_enable_waitmode(void)
{
        uint32_t i;

        /* Flash in wait mode */
        i = PMC->PMC_FSMR;
        i &= ~PMC_FSMR_FLPM_Msk;
#if !(SAMV71 || SAMV70 || SAME70 || SAMS70)
        i |= ul_flash_in_wait_mode;
#else
        (void)ul_flash_in_wait_mode;
        i |= PMC_WAIT_MODE_FLASH_IDLE;
#endif
        PMC->PMC_FSMR = i;

        /* Set the WAITMODE bit = 1 */
        PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_WAITMODE;

        /* Waiting for Master Clock Ready MCKRDY = 1 */
        while (!(PMC->PMC_SR & PMC_SR_MCKRDY));

        /* Waiting for MOSCRCEN bit cleared is strongly recommended
         * to ensure that the core will not execute undesired instructions
         */
        for (i = 0; i < 500; i++) {
                __NOP();
        }
        while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));

#if (!SAMG)
        /* Restore Flash in idle mode */
        i = PMC->PMC_FSMR;
        i &= ~PMC_FSMR_FLPM_Msk;
        i |= PMC_WAIT_MODE_FLASH_IDLE;
        PMC->PMC_FSMR = i;
#endif
}
#else

void pmc_enable_waitmode(void)
{
        uint32_t i;

        PMC->PMC_FSMR |= PMC_FSMR_LPM; /* Enter Wait mode */
        SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; /* Deep sleep */

        __DSB();
        __WFE();

        /* Waiting for MOSCRCEN bit cleared is strongly recommended
         * to ensure that the core will not execute undesired instructions
         */
        for (i = 0; i < 500; i++) {
                __NOP();
        }
        while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));

}
#endif

#if (!(SAMG51 || SAMG53 || SAMG54))

void pmc_enable_backupmode(void)
{
#if (SAM4C || SAM4CM || SAM4CP)
        uint32_t tmp = SUPC->SUPC_MR & ~(SUPC_MR_BUPPOREN | SUPC_MR_KEY_Msk);
        SUPC->SUPC_MR = tmp | SUPC_MR_KEY_PASSWD;
        while (SUPC->SUPC_SR & SUPC_SR_BUPPORS);
#endif
        SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
        SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG;
        uint32_t ul_dummy = SUPC->SUPC_MR;
        UNUSED(ul_dummy);
        __DSB();
        __WFE();
        __WFI();
#else
        __DSB();
        __WFE();
#endif
}
#endif

void pmc_enable_clock_failure_detector(void)
{
        uint32_t ul_reg = PMC->CKGR_MOR;

        PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_CFDEN | ul_reg;
}

void pmc_disable_clock_failure_detector(void)
{
        uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN);

        PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg;
}

#if (SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)

void pmc_enable_sclk_osc_freq_monitor(void)
{
        uint32_t ul_reg = PMC->CKGR_MOR;

        PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_XT32KFME | ul_reg;
}

void pmc_disable_sclk_osc_freq_monitor(void)
{
        uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_XT32KFME);

        PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg;
}
#endif

void pmc_set_writeprotect(uint32_t ul_enable)
{
        if (ul_enable) {
                PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD | PMC_WPMR_WPEN;
        } else {
                PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD;
        }
}

uint32_t pmc_get_writeprotect_status(void)
{
        return PMC->PMC_WPSR;
}

#if (SAMG53 || SAMG54 || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)

uint32_t pmc_enable_sleepwalking(uint32_t ul_id)
{
        uint32_t temp;
#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
        if ((7 <= ul_id) && (ul_id<= 29)) {
#else
        if ((8 <= ul_id) && (ul_id<= 29)) {
#endif
                temp = pmc_get_active_status0();
                if (temp & (1 << ul_id)) {
                        return 1;
                }
                PMC->PMC_SLPWK_ER0 = 1 << ul_id;
                temp = pmc_get_active_status0();
                if (temp & (1 << ul_id)) {
                        pmc_disable_sleepwalking(ul_id);
                        return 1;
                }
                return 0;
        }
#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
        else if ((32 <= ul_id) && (ul_id<= 60)) {
                ul_id -= 32;
                temp = pmc_get_active_status1();
                if (temp & (1 << ul_id)) {
                        return 1;
                }
                PMC->PMC_SLPWK_ER1 = 1 << ul_id;
                temp = pmc_get_active_status1();
                if (temp & (1 << ul_id)) {
                        pmc_disable_sleepwalking(ul_id);
                        return 1;
                }
                return 0;
        }
#endif
        else {
                return 1;
        }
}

uint32_t pmc_disable_sleepwalking(uint32_t ul_id)
{
#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
        if ((7 <= ul_id) && (ul_id<= 29)) {
#else
        if ((8 <= ul_id) && (ul_id<= 29)) {
#endif
                PMC->PMC_SLPWK_DR0 = 1 << ul_id;
                return 0;
        }
#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
        else if ((32 <= ul_id) && (ul_id<= 60)) {
                ul_id -= 32;
                PMC->PMC_SLPWK_DR1 = 1 << ul_id;
                return 0;
        }
#endif
        else {
                return 1;
        }
}

uint32_t pmc_get_sleepwalking_status0(void)
{
        return PMC->PMC_SLPWK_SR0;
}

uint32_t pmc_get_active_status0(void)
{
        return PMC->PMC_SLPWK_ASR0;
}

#endif

#if (SAMV71 || SAMV70 || SAME70 || SAMS70)

uint32_t pmc_get_sleepwalking_status1(void)
{
        return PMC->PMC_SLPWK_SR1;
}

uint32_t pmc_get_active_status1(void)
{
        return PMC->PMC_SLPWK_ASR1;
}
#endif


#ifdef __cplusplus
}
#endif

---

inertial_sense_ros
Author(s):
autogenerated on Sun Feb 28 2021 03:17:58