drivers/afec/afec.h

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/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */

#ifndef AFEC_H_INCLUDED
#define AFEC_H_INCLUDED

#include "compiler.h"
#include "status_codes.h"

#if (SAMV71 || SAMV70 || SAME70 || SAMS70)

enum afec_resolution {
        AFEC_12_BITS = AFEC_EMR_RES_NO_AVERAGE,    /* AFEC 12-bit resolution */
        AFEC_13_BITS = AFEC_EMR_RES_OSR4,          /* AFEC 13-bit resolution */
        AFEC_14_BITS = AFEC_EMR_RES_OSR16,         /* AFEC 14-bit resolution */
        AFEC_15_BITS = AFEC_EMR_RES_OSR64,         /* AFEC 15-bit resolution */
        AFEC_16_BITS = AFEC_EMR_RES_OSR256         /* AFEC 16-bit resolution */
};
#else

enum afec_resolution {
        AFEC_10_BITS = AFEC_EMR_RES_LOW_RES,       /* AFEC 10-bit resolution */
        AFEC_12_BITS = AFEC_EMR_RES_NO_AVERAGE,    /* AFEC 12-bit resolution */
        AFEC_13_BITS = AFEC_EMR_RES_OSR4,          /* AFEC 13-bit resolution */
        AFEC_14_BITS = AFEC_EMR_RES_OSR16,         /* AFEC 14-bit resolution */
        AFEC_15_BITS = AFEC_EMR_RES_OSR64,         /* AFEC 15-bit resolution */
        AFEC_16_BITS = AFEC_EMR_RES_OSR256         /* AFEC 16-bit resolution */
};
#endif

enum afec_power_mode {
        /* AFEC core on and reference voltage circuitry on */
        AFEC_POWER_MODE_0 = 0,
        /* AFEC core off and reference voltage circuitry on */
        AFEC_POWER_MODE_1,
        /* AFEC core off and reference voltage circuitry off */
        AFEC_POWER_MODE_2
};

enum afec_trigger {
        /* Starting a conversion is only possible by software. */
        AFEC_TRIG_SW = AFEC_MR_TRGEN_DIS,
        /* External trigger */
        AFEC_TRIG_EXT = AFEC_MR_TRGSEL_AFEC_TRIG0 | AFEC_MR_TRGEN,
        /* TIO Output of the Timer Counter Channel 0 */
        AFEC_TRIG_TIO_CH_0 = AFEC_MR_TRGSEL_AFEC_TRIG1 | AFEC_MR_TRGEN,
        /* TIO Output of the Timer Counter Channel 1 */
        AFEC_TRIG_TIO_CH_1 = AFEC_MR_TRGSEL_AFEC_TRIG2 | AFEC_MR_TRGEN,
        /* TIO Output of the Timer Counter Channel 2 */
        AFEC_TRIG_TIO_CH_2 = AFEC_MR_TRGSEL_AFEC_TRIG3 | AFEC_MR_TRGEN,
        /* PWM Event Line 0 */
        AFEC_TRIG_PWM_EVENT_LINE_0 = AFEC_MR_TRGSEL_AFEC_TRIG4 | AFEC_MR_TRGEN,
        /* PWM Event Line 1 */
        AFEC_TRIG_PWM_EVENT_LINE_1 = AFEC_MR_TRGSEL_AFEC_TRIG5 | AFEC_MR_TRGEN,
#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
        /*Analog Comparator*/
        AFEC_TRIG_ANALOG_COMPARATOR = AFEC_MR_TRGSEL_AFEC_TRIG6 | AFEC_MR_TRGEN,
#endif  
        /* Freerun mode conversion. */
        AFEC_TRIG_FREERUN = 0xFF,
};

#if defined __SAM4E8C__  || defined __SAM4E16C__ || defined __SAM4E8CB__  || defined __SAM4E16CB__

enum afec_channel_num {
        AFEC_CHANNEL_0 = 0,
        AFEC_CHANNEL_1,
        AFEC_CHANNEL_2,
        AFEC_CHANNEL_3,
        AFEC_CHANNEL_4,
        AFEC_CHANNEL_5,
        AFEC_TEMPERATURE_SENSOR = 15,
        AFEC_CHANNEL_ALL = 0x803F,
} ;
#elif defined __SAM4E8E__  || defined __SAM4E16E__

enum afec_channel_num {
        AFEC_CHANNEL_0 = 0,
        AFEC_CHANNEL_1,
        AFEC_CHANNEL_2,
        AFEC_CHANNEL_3,
        AFEC_CHANNEL_4,
        AFEC_CHANNEL_5,
        AFEC_CHANNEL_6,
        AFEC_CHANNEL_7,
        AFEC_CHANNEL_8,
        AFEC_CHANNEL_9,
        AFEC_CHANNEL_10,
        AFEC_CHANNEL_11,
        AFEC_CHANNEL_12,
        AFEC_CHANNEL_13,
        AFEC_CHANNEL_14,
        AFEC_TEMPERATURE_SENSOR,
        AFEC_CHANNEL_ALL = 0xFFFF,
} ;
#elif (SAMV71 || SAMV70 || SAME70 || SAMS70)

enum afec_channel_num {
        AFEC_CHANNEL_0 = 0,
        AFEC_CHANNEL_1,
        AFEC_CHANNEL_2,
        AFEC_CHANNEL_3,
        AFEC_CHANNEL_4,
        AFEC_CHANNEL_5,
        AFEC_CHANNEL_6,
        AFEC_CHANNEL_7,
        AFEC_CHANNEL_8,
        AFEC_CHANNEL_9,
        AFEC_CHANNEL_10,
        AFEC_TEMPERATURE_SENSOR,
        AFEC_CHANNEL_ALL = 0x0FFF,
} ;

#define NB_CH_AFE0  (12UL)
#define NB_CH_AFE1  (12UL)
#endif

#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
enum afec_sample_hold_mode {
        /*Single Sample-and-Hold mode*/
        AFEC_SAMPLE_HOLD_MODE_0,
        /*Dual Sample-and-Hold mode*/
        AFEC_SAMPLE_HOLD_MODE_1,
};
#endif

enum afec_gainvalue {
        AFEC_GAINVALUE_0 = 0,
        AFEC_GAINVALUE_1 = 1,
        AFEC_GAINVALUE_2 = 2,
        AFEC_GAINVALUE_3 = 3
};

enum afec_startup_time {
        AFEC_STARTUP_TIME_0 = AFEC_MR_STARTUP_SUT0,
        AFEC_STARTUP_TIME_1 = AFEC_MR_STARTUP_SUT8,
        AFEC_STARTUP_TIME_2 = AFEC_MR_STARTUP_SUT16,
        AFEC_STARTUP_TIME_3 = AFEC_MR_STARTUP_SUT24,
        AFEC_STARTUP_TIME_4 = AFEC_MR_STARTUP_SUT64,
        AFEC_STARTUP_TIME_5 = AFEC_MR_STARTUP_SUT80,
        AFEC_STARTUP_TIME_6 = AFEC_MR_STARTUP_SUT96,
        AFEC_STARTUP_TIME_7 = AFEC_MR_STARTUP_SUT112,
        AFEC_STARTUP_TIME_8 = AFEC_MR_STARTUP_SUT512,
        AFEC_STARTUP_TIME_9 = AFEC_MR_STARTUP_SUT576,
        AFEC_STARTUP_TIME_10 = AFEC_MR_STARTUP_SUT640,
        AFEC_STARTUP_TIME_11 = AFEC_MR_STARTUP_SUT704,
        AFEC_STARTUP_TIME_12 = AFEC_MR_STARTUP_SUT768,
        AFEC_STARTUP_TIME_13 = AFEC_MR_STARTUP_SUT832,
        AFEC_STARTUP_TIME_14 = AFEC_MR_STARTUP_SUT896,
        AFEC_STARTUP_TIME_15 = AFEC_MR_STARTUP_SUT960
};

#if SAM4E

enum afec_settling_time {
        AFEC_SETTLING_TIME_0 = AFEC_MR_SETTLING_AST3,
        AFEC_SETTLING_TIME_1 = AFEC_MR_SETTLING_AST5,
        AFEC_SETTLING_TIME_2 = AFEC_MR_SETTLING_AST9,
        AFEC_SETTLING_TIME_3 = AFEC_MR_SETTLING_AST17
};
#endif

enum afec_cmp_mode {
        AFEC_CMP_MODE_0 = AFEC_EMR_CMPMODE_LOW,
        AFEC_CMP_MODE_1 = AFEC_EMR_CMPMODE_HIGH,
        AFEC_CMP_MODE_2 = AFEC_EMR_CMPMODE_IN,
        AFEC_CMP_MODE_3 = AFEC_EMR_CMPMODE_OUT
};

enum afec_temp_cmp_mode {
        AFEC_TEMP_CMP_MODE_0 = AFEC_TEMPMR_TEMPCMPMOD_LOW,
        AFEC_TEMP_CMP_MODE_1 = AFEC_TEMPMR_TEMPCMPMOD_HIGH,
        AFEC_TEMP_CMP_MODE_2 = AFEC_TEMPMR_TEMPCMPMOD_IN,
        AFEC_TEMP_CMP_MODE_3 = AFEC_TEMPMR_TEMPCMPMOD_OUT
};

struct afec_config {
        enum afec_resolution resolution;
        uint32_t mck;
        uint32_t afec_clock;
        enum afec_startup_time startup_time;
        #if  SAM4E

                enum afec_settling_time settling_time;
        #endif

        uint8_t tracktim;
        uint8_t transfer;
        bool anach;
        bool useq;
        bool tag;
        bool stm;
        uint8_t ibctl;
};

struct afec_ch_config {
        bool diff;
        enum afec_gainvalue gain;
};

struct afec_temp_sensor_config {
        bool rctc;
        enum afec_temp_cmp_mode mode;
        uint16_t low_threshold;
        uint16_t high_threshold;
};

#if defined __SAM4E8C__  || defined __SAM4E16C__ || defined __SAM4E8CB__  || defined __SAM4E16CB__

enum afec_interrupt_source {
        AFEC_INTERRUPT_EOC_0 = 0,
        AFEC_INTERRUPT_EOC_1,
        AFEC_INTERRUPT_EOC_2,
        AFEC_INTERRUPT_EOC_3,
        AFEC_INTERRUPT_EOC_4,
        AFEC_INTERRUPT_EOC_5,
        AFEC_INTERRUPT_EOC_15,
        AFEC_INTERRUPT_DATA_READY,
        AFEC_INTERRUPT_OVERRUN_ERROR,
        AFEC_INTERRUPT_COMP_ERROR,
        AFEC_INTERRUPT_END_RXBUF,
        AFEC_INTERRUPT_RXBUF_FULL,
        AFEC_INTERRUPT_TEMP_CHANGE,
        AFEC_INTERRUPT_END_CAL,
        _AFEC_NUM_OF_INTERRUPT_SOURCE,
        AFEC_INTERRUPT_ALL = 0xDF00803F,
};
#elif defined __SAM4E8E__  || defined __SAM4E16E__

enum afec_interrupt_source {
        AFEC_INTERRUPT_EOC_0 = 0,
        AFEC_INTERRUPT_EOC_1,
        AFEC_INTERRUPT_EOC_2,
        AFEC_INTERRUPT_EOC_3,
        AFEC_INTERRUPT_EOC_4,
        AFEC_INTERRUPT_EOC_5,
        AFEC_INTERRUPT_EOC_6,
        AFEC_INTERRUPT_EOC_7,
        AFEC_INTERRUPT_EOC_8,
        AFEC_INTERRUPT_EOC_9,
        AFEC_INTERRUPT_EOC_10,
        AFEC_INTERRUPT_EOC_11,
        AFEC_INTERRUPT_EOC_12,
        AFEC_INTERRUPT_EOC_13,
        AFEC_INTERRUPT_EOC_14,
        AFEC_INTERRUPT_EOC_15,
        AFEC_INTERRUPT_DATA_READY,
        AFEC_INTERRUPT_OVERRUN_ERROR,
        AFEC_INTERRUPT_COMP_ERROR,
        AFEC_INTERRUPT_END_RXBUF,
        AFEC_INTERRUPT_RXBUF_FULL,
        AFEC_INTERRUPT_TEMP_CHANGE,
        AFEC_INTERRUPT_END_CAL,
        _AFEC_NUM_OF_INTERRUPT_SOURCE,
        AFEC_INTERRUPT_ALL = 0xDF00FFFF,
};
#elif (SAMV71 || SAMV70 || SAME70 || SAMS70)

enum afec_interrupt_source {
        AFEC_INTERRUPT_EOC_0 = 0,
        AFEC_INTERRUPT_EOC_1,
        AFEC_INTERRUPT_EOC_2,
        AFEC_INTERRUPT_EOC_3,
        AFEC_INTERRUPT_EOC_4,
        AFEC_INTERRUPT_EOC_5,
        AFEC_INTERRUPT_EOC_6,
        AFEC_INTERRUPT_EOC_7,
        AFEC_INTERRUPT_EOC_8,
        AFEC_INTERRUPT_EOC_9,
        AFEC_INTERRUPT_EOC_10,
        AFEC_INTERRUPT_EOC_11,
        AFEC_INTERRUPT_DATA_READY,
        AFEC_INTERRUPT_OVERRUN_ERROR,
        AFEC_INTERRUPT_COMP_ERROR,
        AFEC_INTERRUPT_TEMP_CHANGE,
        _AFEC_NUM_OF_INTERRUPT_SOURCE,
        AFEC_INTERRUPT_ALL = 0x47000FFF,
};
#endif

typedef void (*afec_callback_t)(void);

void afec_get_config_defaults(struct afec_config *const cfg);
void afec_ch_get_config_defaults(struct afec_ch_config *const cfg);
void afec_temp_sensor_get_config_defaults(
                struct afec_temp_sensor_config *const cfg);
enum status_code afec_init(Afec *const afec, struct afec_config *const config);
void afec_temp_sensor_set_config(Afec *const afec,
                struct afec_temp_sensor_config *config);
void afec_ch_set_config(Afec *const afec, const enum afec_channel_num channel,
                struct afec_ch_config *config);
void afec_configure_sequence(Afec *const afec,
                const enum afec_channel_num ch_list[], const uint8_t uc_num);
void afec_enable(Afec *const afec);
void afec_disable(Afec *const afec);
void afec_set_callback(Afec *const afec, enum afec_interrupt_source source,
                afec_callback_t callback, uint8_t irq_level);

#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
void afec_configure_auto_error_correction(Afec *const afec,
                const enum afec_channel_num channel,int16_t offsetcorr, uint16_t gaincorr);

uint32_t afec_get_correction_value(Afec *const afec,
           const enum afec_channel_num afec_ch);
void afec_set_sample_hold_mode(Afec *const afec,
                const enum afec_channel_num channel,const enum afec_sample_hold_mode mode);

#endif

static inline void afec_ch_sanity_check(Afec *const afec,
                const enum afec_channel_num channel)
{
        if (afec == AFEC0) {
        #if defined __SAM4E8C__  || defined __SAM4E16C__ || defined __SAM4E8CB__  || defined __SAM4E16CB__
                Assert((channel < NB_CH_AFE0) || (channel == AFEC_TEMPERATURE_SENSOR));
        #elif defined __SAM4E8E__  || defined __SAM4E16E__
                Assert(channel < NB_CH_AFE0);
        #elif (SAMV71 || SAMV70 || SAME70 || SAMS70)
                Assert(channel < NB_CH_AFE0);
        #endif
        } else if (afec == AFEC1) {
                Assert(channel < NB_CH_AFE1);
        }
        UNUSED(channel);
}

static inline void afec_set_trigger(Afec *const afec,
                const enum afec_trigger trigger)
{
        uint32_t reg;

        reg = afec->AFEC_MR;

        if (trigger == AFEC_TRIG_FREERUN) {
                reg |= AFEC_MR_FREERUN_ON;
        } else {
                reg &= ~(AFEC_MR_TRGSEL_Msk | AFEC_MR_TRGEN | AFEC_MR_FREERUN_ON);
                reg |= trigger;
        }

        afec->AFEC_MR = reg;
}

static inline void afec_set_resolution(Afec *const afec,
                const enum afec_resolution res)
{
        uint32_t reg;

        reg = afec->AFEC_EMR;

        reg &= ~AFEC_EMR_RES_Msk;
        reg |= res;

        afec->AFEC_EMR = reg;
}

void afec_set_comparison_mode(Afec *const afec,
                const enum afec_cmp_mode mode, const enum afec_channel_num channel,
                uint8_t cmp_filter);

static inline enum afec_cmp_mode afec_get_comparison_mode(Afec *const afec)
{
        return (enum afec_cmp_mode)(afec->AFEC_EMR & AFEC_EMR_CMPMODE_Msk);
}

static inline void afec_set_comparison_window(Afec *const afec,
                const uint16_t us_low_threshold, const uint16_t us_high_threshold)
{
        afec->AFEC_CWR = AFEC_CWR_LOWTHRES(us_low_threshold) |
                        AFEC_CWR_HIGHTHRES(us_high_threshold);
}

static inline void afec_set_writeprotect(Afec *const afec,
                const bool is_enable)
{
        if (is_enable) {
                afec->AFEC_WPMR = AFEC_WPMR_WPEN | AFEC_WPMR_WPKEY_PASSWD;
        } else {
                afec->AFEC_WPMR = AFEC_WPMR_WPKEY_PASSWD;
        }
}

static inline uint32_t afec_get_writeprotect_status(Afec *const afec)
{
        uint32_t reg_value;

        reg_value = afec->AFEC_WPSR;
        if (reg_value & AFEC_WPSR_WPVS) {
                return (reg_value & AFEC_WPSR_WPVSRC_Msk) >> AFEC_WPSR_WPVSRC_Pos;
        } else {
                return 0;
        }
}

static inline uint32_t afec_get_overrun_status(Afec *const afec)
{
        return afec->AFEC_OVER;
}

static inline void afec_start_software_conversion(Afec *const afec)
{
        afec->AFEC_CR = AFEC_CR_START;
}

void afec_set_power_mode(Afec *const afec,
                const enum afec_power_mode mode);

static inline void afec_channel_enable(Afec *const afec,
                const enum afec_channel_num afec_ch)
{
        if (afec_ch != AFEC_CHANNEL_ALL) {
                afec_ch_sanity_check(afec, afec_ch);
        }

        afec->AFEC_CHER = (afec_ch == AFEC_CHANNEL_ALL) ?
                        AFEC_CHANNEL_ALL : 1 << afec_ch;
}

static inline void afec_channel_disable(Afec *const afec,
                const enum afec_channel_num afec_ch)
{
        if (afec_ch != AFEC_CHANNEL_ALL) {
                afec_ch_sanity_check(afec, afec_ch);
        }

        afec->AFEC_CHDR = (afec_ch == AFEC_CHANNEL_ALL) ?
                        AFEC_CHANNEL_ALL : 1 << afec_ch;
}

static inline uint32_t afec_channel_get_status(Afec *const afec,
                const enum afec_channel_num afec_ch)
{
        afec_ch_sanity_check(afec, afec_ch);

        return afec->AFEC_CHSR & (1 << afec_ch);
}

static inline uint32_t afec_channel_get_value(Afec *const afec,
                enum afec_channel_num afec_ch)
{
        afec_ch_sanity_check(afec, afec_ch);

        afec->AFEC_CSELR = afec_ch;
        return afec->AFEC_CDR;
}

static inline void afec_channel_set_analog_offset(Afec *const afec,
                enum afec_channel_num afec_ch, uint16_t aoffset)
{
        afec_ch_sanity_check(afec, afec_ch);

        afec->AFEC_CSELR = afec_ch;
        afec->AFEC_COCR = (aoffset & AFEC_COCR_AOFF_Msk);
}

static inline uint32_t afec_get_latest_value(Afec *const afec)
{
        return afec->AFEC_LCDR & AFEC_LCDR_LDATA_Msk;
}

static inline uint32_t afec_get_latest_chan_num(Afec *const afec)
{
        return (afec->AFEC_LCDR & AFEC_LCDR_CHNB_Msk) >> AFEC_LCDR_CHNB_Pos;
}

void afec_enable_interrupt(Afec *const afec,
                enum afec_interrupt_source interrupt_source);

void afec_disable_interrupt(Afec *const afec,
                enum afec_interrupt_source interrupt_source);

static inline uint32_t afec_get_interrupt_status(Afec *const afec)
{
        return afec->AFEC_ISR;
}

static inline uint32_t afec_get_interrupt_mask(Afec *const afec)
{
        return afec->AFEC_IMR;
}

#if SAM4E

static inline Pdc *afec_get_pdc_base(Afec *const afec)
{
        Pdc *p_pdc_base = NULL;

#ifdef PDC_AFEC0
        if (afec == AFEC0) {
                p_pdc_base = PDC_AFEC0;
        }
#endif

#ifdef PDC_AFEC1
        else if (afec == AFEC1) {
                p_pdc_base = PDC_AFEC1;
        }
#endif

        return p_pdc_base;
}

static inline enum status_code afec_start_calibration(Afec *const afec)
{
        uint32_t reg;

        reg = afec->AFEC_CHSR;
        afec->AFEC_CDOR = reg;

        if ((afec->AFEC_MR & AFEC_MR_FREERUN) == AFEC_MR_FREERUN_ON) {
                return STATUS_ERR_BUSY;
        }
        afec->AFEC_CR = AFEC_CR_AUTOCAL;
        return STATUS_OK;
}
#endif

#endif /* AFEC_H_INCLUDED */