core_cm4.h
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1 /**************************************************************************/
10 /* Copyright (c) 2009 - 2014 ARM LIMITED
11 
12  All rights reserved.
13  Redistribution and use in source and binary forms, with or without
14  modification, are permitted provided that the following conditions are met:
15  - Redistributions of source code must retain the above copyright
16  notice, this list of conditions and the following disclaimer.
17  - Redistributions in binary form must reproduce the above copyright
18  notice, this list of conditions and the following disclaimer in the
19  documentation and/or other materials provided with the distribution.
20  - Neither the name of ARM nor the names of its contributors may be used
21  to endorse or promote products derived from this software without
22  specific prior written permission.
23  *
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  POSSIBILITY OF SUCH DAMAGE.
35  ---------------------------------------------------------------------------*/
36 
37 
38 #if defined ( __ICCARM__ )
39  #pragma system_include /* treat file as system include file for MISRA check */
40 #endif
41 
42 #ifndef __CORE_CM4_H_GENERIC
43 #define __CORE_CM4_H_GENERIC
44 
45 #ifdef __cplusplus
46  extern "C" {
47 #endif
48 
63 /*******************************************************************************
64  * CMSIS definitions
65  ******************************************************************************/
70 /* CMSIS CM4 definitions */
71 #define __CM4_CMSIS_VERSION_MAIN (0x04)
72 #define __CM4_CMSIS_VERSION_SUB (0x00)
73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
74  __CM4_CMSIS_VERSION_SUB )
76 #define __CORTEX_M (0x04)
79 #if defined ( __CC_ARM )
80  #define __ASM __asm
81  #define __INLINE __inline
82  #define __STATIC_INLINE static __inline
83 
84 #elif defined ( __GNUC__ )
85  #define __ASM __asm
86  #define __INLINE inline
87  #define __STATIC_INLINE static inline
88 
89 #elif defined ( __ICCARM__ )
90  #define __ASM __asm
91  #define __INLINE inline
92  #define __STATIC_INLINE static inline
93 
94 #elif defined ( __TMS470__ )
95  #define __ASM __asm
96  #define __STATIC_INLINE static inline
97 
98 #elif defined ( __TASKING__ )
99  #define __ASM __asm
100  #define __INLINE inline
101  #define __STATIC_INLINE static inline
102 
103 #elif defined ( __CSMC__ )
104  #define __packed
105  #define __ASM _asm
106  #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107  #define __STATIC_INLINE static inline
108 
109 #endif
110 
114 #if defined ( __CC_ARM )
115  #if defined __TARGET_FPU_VFP
116  #if (__FPU_PRESENT == 1)
117  #define __FPU_USED 1
118  #else
119  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
120  #define __FPU_USED 0
121  #endif
122  #else
123  #define __FPU_USED 0
124  #endif
125 
126 #elif defined ( __GNUC__ )
127  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
128  #if (__FPU_PRESENT == 1)
129  #define __FPU_USED 1
130  #else
131  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
132  #define __FPU_USED 0
133  #endif
134  #else
135  #define __FPU_USED 0
136  #endif
137 
138 #elif defined ( __ICCARM__ )
139  #if defined __ARMVFP__
140  #if (__FPU_PRESENT == 1)
141  #define __FPU_USED 1
142  #else
143  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144  #define __FPU_USED 0
145  #endif
146  #else
147  #define __FPU_USED 0
148  #endif
149 
150 #elif defined ( __TMS470__ )
151  #if defined __TI_VFP_SUPPORT__
152  #if (__FPU_PRESENT == 1)
153  #define __FPU_USED 1
154  #else
155  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
156  #define __FPU_USED 0
157  #endif
158  #else
159  #define __FPU_USED 0
160  #endif
161 
162 #elif defined ( __TASKING__ )
163  #if defined __FPU_VFP__
164  #if (__FPU_PRESENT == 1)
165  #define __FPU_USED 1
166  #else
167  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
168  #define __FPU_USED 0
169  #endif
170  #else
171  #define __FPU_USED 0
172  #endif
173 
174 #elif defined ( __CSMC__ ) /* Cosmic */
175  #if ( __CSMC__ & 0x400) // FPU present for parser
176  #if (__FPU_PRESENT == 1)
177  #define __FPU_USED 1
178  #else
179  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
180  #define __FPU_USED 0
181  #endif
182  #else
183  #define __FPU_USED 0
184  #endif
185 #endif
186 
187 #include <stdint.h> /* standard types definitions */
188 #include <core_cmInstr.h> /* Core Instruction Access */
189 #include <core_cmFunc.h> /* Core Function Access */
190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
191 
192 #ifdef __cplusplus
193 }
194 #endif
195 
196 #endif /* __CORE_CM4_H_GENERIC */
197 
198 #ifndef __CMSIS_GENERIC
199 
200 #ifndef __CORE_CM4_H_DEPENDANT
201 #define __CORE_CM4_H_DEPENDANT
202 
203 #ifdef __cplusplus
204  extern "C" {
205 #endif
206 
207 /* check device defines and use defaults */
208 #if defined __CHECK_DEVICE_DEFINES
209  #ifndef __CM4_REV
210  #define __CM4_REV 0x0000
211  #warning "__CM4_REV not defined in device header file; using default!"
212  #endif
213 
214  #ifndef __FPU_PRESENT
215  #define __FPU_PRESENT 0
216  #warning "__FPU_PRESENT not defined in device header file; using default!"
217  #endif
218 
219  #ifndef __MPU_PRESENT
220  #define __MPU_PRESENT 0
221  #warning "__MPU_PRESENT not defined in device header file; using default!"
222  #endif
223 
224  #ifndef __NVIC_PRIO_BITS
225  #define __NVIC_PRIO_BITS 4
226  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
227  #endif
228 
229  #ifndef __Vendor_SysTickConfig
230  #define __Vendor_SysTickConfig 0
231  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
232  #endif
233 #endif
234 
235 /* IO definitions (access restrictions to peripheral registers) */
243 #ifdef __cplusplus
244  #define __I volatile
245 #else
246  #define __I volatile const
247 #endif
248 #define __O volatile
249 #define __IO volatile
251 
255 /*******************************************************************************
256  * Register Abstraction
257  Core Register contain:
258  - Core Register
259  - Core NVIC Register
260  - Core SCB Register
261  - Core SysTick Register
262  - Core Debug Register
263  - Core MPU Register
264  - Core FPU Register
265  ******************************************************************************/
266 
278 typedef union
279 {
280  struct
281  {
282 #if (__CORTEX_M != 0x04)
283  uint32_t _reserved0:27;
284 #else
285  uint32_t _reserved0:16;
286  uint32_t GE:4;
287  uint32_t _reserved1:7;
288 #endif
289  uint32_t Q:1;
290  uint32_t V:1;
291  uint32_t C:1;
292  uint32_t Z:1;
293  uint32_t N:1;
294  } b;
295  uint32_t w;
296 } APSR_Type;
297 
298 
301 typedef union
302 {
303  struct
304  {
305  uint32_t ISR:9;
306  uint32_t _reserved0:23;
307  } b;
308  uint32_t w;
309 } IPSR_Type;
310 
311 
314 typedef union
315 {
316  struct
317  {
318  uint32_t ISR:9;
319 #if (__CORTEX_M != 0x04)
320  uint32_t _reserved0:15;
321 #else
322  uint32_t _reserved0:7;
323  uint32_t GE:4;
324  uint32_t _reserved1:4;
325 #endif
326  uint32_t T:1;
327  uint32_t IT:2;
328  uint32_t Q:1;
329  uint32_t V:1;
330  uint32_t C:1;
331  uint32_t Z:1;
332  uint32_t N:1;
333  } b;
334  uint32_t w;
335 } xPSR_Type;
336 
337 
340 typedef union
341 {
342  struct
343  {
344  uint32_t nPRIV:1;
345  uint32_t SPSEL:1;
346  uint32_t FPCA:1;
347  uint32_t _reserved0:29;
348  } b;
349  uint32_t w;
350 } CONTROL_Type;
351 
363 typedef struct
364 {
365  __IO uint32_t ISER[8];
366  uint32_t RESERVED0[24];
367  __IO uint32_t ICER[8];
368  uint32_t RSERVED1[24];
369  __IO uint32_t ISPR[8];
370  uint32_t RESERVED2[24];
371  __IO uint32_t ICPR[8];
372  uint32_t RESERVED3[24];
373  __IO uint32_t IABR[8];
374  uint32_t RESERVED4[56];
375  __IO uint8_t IP[240];
376  uint32_t RESERVED5[644];
377  __O uint32_t STIR;
378 } NVIC_Type;
379 
380 /* Software Triggered Interrupt Register Definitions */
381 #define NVIC_STIR_INTID_Pos 0
382 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos)
384 
395 typedef struct
396 {
397  __I uint32_t CPUID;
398  __IO uint32_t ICSR;
399  __IO uint32_t VTOR;
400  __IO uint32_t AIRCR;
401  __IO uint32_t SCR;
402  __IO uint32_t CCR;
403  __IO uint8_t SHP[12];
404  __IO uint32_t SHCSR;
405  __IO uint32_t CFSR;
406  __IO uint32_t HFSR;
407  __IO uint32_t DFSR;
408  __IO uint32_t MMFAR;
409  __IO uint32_t BFAR;
410  __IO uint32_t AFSR;
411  __I uint32_t PFR[2];
412  __I uint32_t DFR;
413  __I uint32_t ADR;
414  __I uint32_t MMFR[4];
415  __I uint32_t ISAR[5];
416  uint32_t RESERVED0[5];
417  __IO uint32_t CPACR;
418 } SCB_Type;
419 
420 /* SCB CPUID Register Definitions */
421 #define SCB_CPUID_IMPLEMENTER_Pos 24
422 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
424 #define SCB_CPUID_VARIANT_Pos 20
425 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
427 #define SCB_CPUID_ARCHITECTURE_Pos 16
428 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
430 #define SCB_CPUID_PARTNO_Pos 4
431 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
433 #define SCB_CPUID_REVISION_Pos 0
434 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)
436 /* SCB Interrupt Control State Register Definitions */
437 #define SCB_ICSR_NMIPENDSET_Pos 31
438 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
440 #define SCB_ICSR_PENDSVSET_Pos 28
441 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
443 #define SCB_ICSR_PENDSVCLR_Pos 27
444 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
446 #define SCB_ICSR_PENDSTSET_Pos 26
447 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
449 #define SCB_ICSR_PENDSTCLR_Pos 25
450 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
452 #define SCB_ICSR_ISRPREEMPT_Pos 23
453 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
455 #define SCB_ICSR_ISRPENDING_Pos 22
456 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
458 #define SCB_ICSR_VECTPENDING_Pos 12
459 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
461 #define SCB_ICSR_RETTOBASE_Pos 11
462 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
464 #define SCB_ICSR_VECTACTIVE_Pos 0
465 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
467 /* SCB Vector Table Offset Register Definitions */
468 #define SCB_VTOR_TBLOFF_Pos 7
469 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
471 /* SCB Application Interrupt and Reset Control Register Definitions */
472 #define SCB_AIRCR_VECTKEY_Pos 16
473 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
475 #define SCB_AIRCR_VECTKEYSTAT_Pos 16
476 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
478 #define SCB_AIRCR_ENDIANESS_Pos 15
479 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
481 #define SCB_AIRCR_PRIGROUP_Pos 8
482 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
484 #define SCB_AIRCR_SYSRESETREQ_Pos 2
485 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
487 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1
488 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
490 #define SCB_AIRCR_VECTRESET_Pos 0
491 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos)
493 /* SCB System Control Register Definitions */
494 #define SCB_SCR_SEVONPEND_Pos 4
495 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
497 #define SCB_SCR_SLEEPDEEP_Pos 2
498 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
500 #define SCB_SCR_SLEEPONEXIT_Pos 1
501 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
503 /* SCB Configuration Control Register Definitions */
504 #define SCB_CCR_STKALIGN_Pos 9
505 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
507 #define SCB_CCR_BFHFNMIGN_Pos 8
508 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
510 #define SCB_CCR_DIV_0_TRP_Pos 4
511 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
513 #define SCB_CCR_UNALIGN_TRP_Pos 3
514 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
516 #define SCB_CCR_USERSETMPEND_Pos 1
517 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
519 #define SCB_CCR_NONBASETHRDENA_Pos 0
520 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos)
522 /* SCB System Handler Control and State Register Definitions */
523 #define SCB_SHCSR_USGFAULTENA_Pos 18
524 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
526 #define SCB_SHCSR_BUSFAULTENA_Pos 17
527 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
529 #define SCB_SHCSR_MEMFAULTENA_Pos 16
530 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
532 #define SCB_SHCSR_SVCALLPENDED_Pos 15
533 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
535 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14
536 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
538 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13
539 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
541 #define SCB_SHCSR_USGFAULTPENDED_Pos 12
542 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
544 #define SCB_SHCSR_SYSTICKACT_Pos 11
545 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
547 #define SCB_SHCSR_PENDSVACT_Pos 10
548 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
550 #define SCB_SHCSR_MONITORACT_Pos 8
551 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
553 #define SCB_SHCSR_SVCALLACT_Pos 7
554 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
556 #define SCB_SHCSR_USGFAULTACT_Pos 3
557 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
559 #define SCB_SHCSR_BUSFAULTACT_Pos 1
560 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
562 #define SCB_SHCSR_MEMFAULTACT_Pos 0
563 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos)
565 /* SCB Configurable Fault Status Registers Definitions */
566 #define SCB_CFSR_USGFAULTSR_Pos 16
567 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
569 #define SCB_CFSR_BUSFAULTSR_Pos 8
570 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
572 #define SCB_CFSR_MEMFAULTSR_Pos 0
573 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)
575 /* SCB Hard Fault Status Registers Definitions */
576 #define SCB_HFSR_DEBUGEVT_Pos 31
577 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
579 #define SCB_HFSR_FORCED_Pos 30
580 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
582 #define SCB_HFSR_VECTTBL_Pos 1
583 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
585 /* SCB Debug Fault Status Register Definitions */
586 #define SCB_DFSR_EXTERNAL_Pos 4
587 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
589 #define SCB_DFSR_VCATCH_Pos 3
590 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
592 #define SCB_DFSR_DWTTRAP_Pos 2
593 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
595 #define SCB_DFSR_BKPT_Pos 1
596 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
598 #define SCB_DFSR_HALTED_Pos 0
599 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos)
601 
612 typedef struct
613 {
614  uint32_t RESERVED0[1];
615  __I uint32_t ICTR;
616  __IO uint32_t ACTLR;
617 } SCnSCB_Type;
618 
619 /* Interrupt Controller Type Register Definitions */
620 #define SCnSCB_ICTR_INTLINESNUM_Pos 0
621 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)
623 /* Auxiliary Control Register Definitions */
624 #define SCnSCB_ACTLR_DISOOFP_Pos 9
625 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos)
627 #define SCnSCB_ACTLR_DISFPCA_Pos 8
628 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos)
630 #define SCnSCB_ACTLR_DISFOLD_Pos 2
631 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
633 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1
634 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
636 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0
637 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)
639 
650 typedef struct
651 {
652  __IO uint32_t CTRL;
653  __IO uint32_t LOAD;
654  __IO uint32_t VAL;
655  __I uint32_t CALIB;
656 } SysTick_Type;
657 
658 /* SysTick Control / Status Register Definitions */
659 #define SysTick_CTRL_COUNTFLAG_Pos 16
660 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
662 #define SysTick_CTRL_CLKSOURCE_Pos 2
663 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
665 #define SysTick_CTRL_TICKINT_Pos 1
666 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
668 #define SysTick_CTRL_ENABLE_Pos 0
669 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos)
671 /* SysTick Reload Register Definitions */
672 #define SysTick_LOAD_RELOAD_Pos 0
673 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)
675 /* SysTick Current Register Definitions */
676 #define SysTick_VAL_CURRENT_Pos 0
677 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
679 /* SysTick Calibration Register Definitions */
680 #define SysTick_CALIB_NOREF_Pos 31
681 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
683 #define SysTick_CALIB_SKEW_Pos 30
684 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
686 #define SysTick_CALIB_TENMS_Pos 0
687 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)
689 
700 typedef struct
701 {
702  __O union
703  {
704  __O uint8_t u8;
705  __O uint16_t u16;
706  __O uint32_t u32;
707  } PORT [32];
708  uint32_t RESERVED0[864];
709  __IO uint32_t TER;
710  uint32_t RESERVED1[15];
711  __IO uint32_t TPR;
712  uint32_t RESERVED2[15];
713  __IO uint32_t TCR;
714  uint32_t RESERVED3[29];
715  __O uint32_t IWR;
716  __I uint32_t IRR;
717  __IO uint32_t IMCR;
718  uint32_t RESERVED4[43];
719  __O uint32_t LAR;
720  __I uint32_t LSR;
721  uint32_t RESERVED5[6];
722  __I uint32_t PID4;
723  __I uint32_t PID5;
724  __I uint32_t PID6;
725  __I uint32_t PID7;
726  __I uint32_t PID0;
727  __I uint32_t PID1;
728  __I uint32_t PID2;
729  __I uint32_t PID3;
730  __I uint32_t CID0;
731  __I uint32_t CID1;
732  __I uint32_t CID2;
733  __I uint32_t CID3;
734 } ITM_Type;
735 
736 /* ITM Trace Privilege Register Definitions */
737 #define ITM_TPR_PRIVMASK_Pos 0
738 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos)
740 /* ITM Trace Control Register Definitions */
741 #define ITM_TCR_BUSY_Pos 23
742 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
744 #define ITM_TCR_TraceBusID_Pos 16
745 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
747 #define ITM_TCR_GTSFREQ_Pos 10
748 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
750 #define ITM_TCR_TSPrescale_Pos 8
751 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
753 #define ITM_TCR_SWOENA_Pos 4
754 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
756 #define ITM_TCR_DWTENA_Pos 3
757 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
759 #define ITM_TCR_SYNCENA_Pos 2
760 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
762 #define ITM_TCR_TSENA_Pos 1
763 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
765 #define ITM_TCR_ITMENA_Pos 0
766 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos)
768 /* ITM Integration Write Register Definitions */
769 #define ITM_IWR_ATVALIDM_Pos 0
770 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos)
772 /* ITM Integration Read Register Definitions */
773 #define ITM_IRR_ATREADYM_Pos 0
774 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos)
776 /* ITM Integration Mode Control Register Definitions */
777 #define ITM_IMCR_INTEGRATION_Pos 0
778 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos)
780 /* ITM Lock Status Register Definitions */
781 #define ITM_LSR_ByteAcc_Pos 2
782 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
784 #define ITM_LSR_Access_Pos 1
785 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
787 #define ITM_LSR_Present_Pos 0
788 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos)
790  /* end of group CMSIS_ITM */
791 
792 
801 typedef struct
802 {
803  __IO uint32_t CTRL;
804  __IO uint32_t CYCCNT;
805  __IO uint32_t CPICNT;
806  __IO uint32_t EXCCNT;
807  __IO uint32_t SLEEPCNT;
808  __IO uint32_t LSUCNT;
809  __IO uint32_t FOLDCNT;
810  __I uint32_t PCSR;
811  __IO uint32_t COMP0;
812  __IO uint32_t MASK0;
813  __IO uint32_t FUNCTION0;
814  uint32_t RESERVED0[1];
815  __IO uint32_t COMP1;
816  __IO uint32_t MASK1;
817  __IO uint32_t FUNCTION1;
818  uint32_t RESERVED1[1];
819  __IO uint32_t COMP2;
820  __IO uint32_t MASK2;
821  __IO uint32_t FUNCTION2;
822  uint32_t RESERVED2[1];
823  __IO uint32_t COMP3;
824  __IO uint32_t MASK3;
825  __IO uint32_t FUNCTION3;
826 } DWT_Type;
827 
828 /* DWT Control Register Definitions */
829 #define DWT_CTRL_NUMCOMP_Pos 28
830 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
832 #define DWT_CTRL_NOTRCPKT_Pos 27
833 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
835 #define DWT_CTRL_NOEXTTRIG_Pos 26
836 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
838 #define DWT_CTRL_NOCYCCNT_Pos 25
839 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
841 #define DWT_CTRL_NOPRFCNT_Pos 24
842 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
844 #define DWT_CTRL_CYCEVTENA_Pos 22
845 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
847 #define DWT_CTRL_FOLDEVTENA_Pos 21
848 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
850 #define DWT_CTRL_LSUEVTENA_Pos 20
851 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
853 #define DWT_CTRL_SLEEPEVTENA_Pos 19
854 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
856 #define DWT_CTRL_EXCEVTENA_Pos 18
857 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
859 #define DWT_CTRL_CPIEVTENA_Pos 17
860 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
862 #define DWT_CTRL_EXCTRCENA_Pos 16
863 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
865 #define DWT_CTRL_PCSAMPLENA_Pos 12
866 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
868 #define DWT_CTRL_SYNCTAP_Pos 10
869 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
871 #define DWT_CTRL_CYCTAP_Pos 9
872 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
874 #define DWT_CTRL_POSTINIT_Pos 5
875 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
877 #define DWT_CTRL_POSTPRESET_Pos 1
878 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
880 #define DWT_CTRL_CYCCNTENA_Pos 0
881 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos)
883 /* DWT CPI Count Register Definitions */
884 #define DWT_CPICNT_CPICNT_Pos 0
885 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos)
887 /* DWT Exception Overhead Count Register Definitions */
888 #define DWT_EXCCNT_EXCCNT_Pos 0
889 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)
891 /* DWT Sleep Count Register Definitions */
892 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0
893 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)
895 /* DWT LSU Count Register Definitions */
896 #define DWT_LSUCNT_LSUCNT_Pos 0
897 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)
899 /* DWT Folded-instruction Count Register Definitions */
900 #define DWT_FOLDCNT_FOLDCNT_Pos 0
901 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)
903 /* DWT Comparator Mask Register Definitions */
904 #define DWT_MASK_MASK_Pos 0
905 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos)
907 /* DWT Comparator Function Register Definitions */
908 #define DWT_FUNCTION_MATCHED_Pos 24
909 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
911 #define DWT_FUNCTION_DATAVADDR1_Pos 16
912 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
914 #define DWT_FUNCTION_DATAVADDR0_Pos 12
915 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
917 #define DWT_FUNCTION_DATAVSIZE_Pos 10
918 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
920 #define DWT_FUNCTION_LNK1ENA_Pos 9
921 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
923 #define DWT_FUNCTION_DATAVMATCH_Pos 8
924 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
926 #define DWT_FUNCTION_CYCMATCH_Pos 7
927 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
929 #define DWT_FUNCTION_EMITRANGE_Pos 5
930 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
932 #define DWT_FUNCTION_FUNCTION_Pos 0
933 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos)
935  /* end of group CMSIS_DWT */
936 
937 
946 typedef struct
947 {
948  __IO uint32_t SSPSR;
949  __IO uint32_t CSPSR;
950  uint32_t RESERVED0[2];
951  __IO uint32_t ACPR;
952  uint32_t RESERVED1[55];
953  __IO uint32_t SPPR;
954  uint32_t RESERVED2[131];
955  __I uint32_t FFSR;
956  __IO uint32_t FFCR;
957  __I uint32_t FSCR;
958  uint32_t RESERVED3[759];
959  __I uint32_t TRIGGER;
960  __I uint32_t FIFO0;
961  __I uint32_t ITATBCTR2;
962  uint32_t RESERVED4[1];
963  __I uint32_t ITATBCTR0;
964  __I uint32_t FIFO1;
965  __IO uint32_t ITCTRL;
966  uint32_t RESERVED5[39];
967  __IO uint32_t CLAIMSET;
968  __IO uint32_t CLAIMCLR;
969  uint32_t RESERVED7[8];
970  __I uint32_t DEVID;
971  __I uint32_t DEVTYPE;
972 } TPI_Type;
973 
974 /* TPI Asynchronous Clock Prescaler Register Definitions */
975 #define TPI_ACPR_PRESCALER_Pos 0
976 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)
978 /* TPI Selected Pin Protocol Register Definitions */
979 #define TPI_SPPR_TXMODE_Pos 0
980 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos)
982 /* TPI Formatter and Flush Status Register Definitions */
983 #define TPI_FFSR_FtNonStop_Pos 3
984 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
986 #define TPI_FFSR_TCPresent_Pos 2
987 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
989 #define TPI_FFSR_FtStopped_Pos 1
990 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
992 #define TPI_FFSR_FlInProg_Pos 0
993 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos)
995 /* TPI Formatter and Flush Control Register Definitions */
996 #define TPI_FFCR_TrigIn_Pos 8
997 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
999 #define TPI_FFCR_EnFCont_Pos 1
1000 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1002 /* TPI TRIGGER Register Definitions */
1003 #define TPI_TRIGGER_TRIGGER_Pos 0
1004 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos)
1006 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1007 #define TPI_FIFO0_ITM_ATVALID_Pos 29
1008 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
1010 #define TPI_FIFO0_ITM_bytecount_Pos 27
1011 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
1013 #define TPI_FIFO0_ETM_ATVALID_Pos 26
1014 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
1016 #define TPI_FIFO0_ETM_bytecount_Pos 24
1017 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
1019 #define TPI_FIFO0_ETM2_Pos 16
1020 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
1022 #define TPI_FIFO0_ETM1_Pos 8
1023 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
1025 #define TPI_FIFO0_ETM0_Pos 0
1026 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos)
1028 /* TPI ITATBCTR2 Register Definitions */
1029 #define TPI_ITATBCTR2_ATREADY_Pos 0
1030 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)
1032 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1033 #define TPI_FIFO1_ITM_ATVALID_Pos 29
1034 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
1036 #define TPI_FIFO1_ITM_bytecount_Pos 27
1037 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
1039 #define TPI_FIFO1_ETM_ATVALID_Pos 26
1040 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
1042 #define TPI_FIFO1_ETM_bytecount_Pos 24
1043 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
1045 #define TPI_FIFO1_ITM2_Pos 16
1046 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
1048 #define TPI_FIFO1_ITM1_Pos 8
1049 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
1051 #define TPI_FIFO1_ITM0_Pos 0
1052 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos)
1054 /* TPI ITATBCTR0 Register Definitions */
1055 #define TPI_ITATBCTR0_ATREADY_Pos 0
1056 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)
1058 /* TPI Integration Mode Control Register Definitions */
1059 #define TPI_ITCTRL_Mode_Pos 0
1060 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos)
1062 /* TPI DEVID Register Definitions */
1063 #define TPI_DEVID_NRZVALID_Pos 11
1064 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1066 #define TPI_DEVID_MANCVALID_Pos 10
1067 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1069 #define TPI_DEVID_PTINVALID_Pos 9
1070 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1072 #define TPI_DEVID_MinBufSz_Pos 6
1073 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1075 #define TPI_DEVID_AsynClkIn_Pos 5
1076 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1078 #define TPI_DEVID_NrTraceInput_Pos 0
1079 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos)
1081 /* TPI DEVTYPE Register Definitions */
1082 #define TPI_DEVTYPE_SubType_Pos 0
1083 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos)
1085 #define TPI_DEVTYPE_MajorType_Pos 4
1086 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1088  /* end of group CMSIS_TPI */
1089 
1090 
1091 #if (__MPU_PRESENT == 1)
1092 
1100 typedef struct
1101 {
1102  __I uint32_t TYPE;
1103  __IO uint32_t CTRL;
1104  __IO uint32_t RNR;
1105  __IO uint32_t RBAR;
1106  __IO uint32_t RASR;
1107  __IO uint32_t RBAR_A1;
1108  __IO uint32_t RASR_A1;
1109  __IO uint32_t RBAR_A2;
1110  __IO uint32_t RASR_A2;
1111  __IO uint32_t RBAR_A3;
1112  __IO uint32_t RASR_A3;
1113 } MPU_Type;
1114 
1115 /* MPU Type Register */
1116 #define MPU_TYPE_IREGION_Pos 16
1117 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1119 #define MPU_TYPE_DREGION_Pos 8
1120 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1122 #define MPU_TYPE_SEPARATE_Pos 0
1123 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos)
1125 /* MPU Control Register */
1126 #define MPU_CTRL_PRIVDEFENA_Pos 2
1127 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1129 #define MPU_CTRL_HFNMIENA_Pos 1
1130 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1132 #define MPU_CTRL_ENABLE_Pos 0
1133 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos)
1135 /* MPU Region Number Register */
1136 #define MPU_RNR_REGION_Pos 0
1137 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos)
1139 /* MPU Region Base Address Register */
1140 #define MPU_RBAR_ADDR_Pos 5
1141 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1143 #define MPU_RBAR_VALID_Pos 4
1144 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
1146 #define MPU_RBAR_REGION_Pos 0
1147 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos)
1149 /* MPU Region Attribute and Size Register */
1150 #define MPU_RASR_ATTRS_Pos 16
1151 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
1153 #define MPU_RASR_XN_Pos 28
1154 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
1156 #define MPU_RASR_AP_Pos 24
1157 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
1159 #define MPU_RASR_TEX_Pos 19
1160 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
1162 #define MPU_RASR_S_Pos 18
1163 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
1165 #define MPU_RASR_C_Pos 17
1166 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
1168 #define MPU_RASR_B_Pos 16
1169 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
1171 #define MPU_RASR_SRD_Pos 8
1172 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
1174 #define MPU_RASR_SIZE_Pos 1
1175 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
1177 #define MPU_RASR_ENABLE_Pos 0
1178 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos)
1180 
1181 #endif
1182 
1183 
1184 #if (__FPU_PRESENT == 1)
1185 
1193 typedef struct
1194 {
1195  uint32_t RESERVED0[1];
1196  __IO uint32_t FPCCR;
1197  __IO uint32_t FPCAR;
1198  __IO uint32_t FPDSCR;
1199  __I uint32_t MVFR0;
1200  __I uint32_t MVFR1;
1201 } FPU_Type;
1202 
1203 /* Floating-Point Context Control Register */
1204 #define FPU_FPCCR_ASPEN_Pos 31
1205 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1207 #define FPU_FPCCR_LSPEN_Pos 30
1208 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1210 #define FPU_FPCCR_MONRDY_Pos 8
1211 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1213 #define FPU_FPCCR_BFRDY_Pos 6
1214 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1216 #define FPU_FPCCR_MMRDY_Pos 5
1217 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1219 #define FPU_FPCCR_HFRDY_Pos 4
1220 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1222 #define FPU_FPCCR_THREAD_Pos 3
1223 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1225 #define FPU_FPCCR_USER_Pos 1
1226 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1228 #define FPU_FPCCR_LSPACT_Pos 0
1229 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos)
1231 /* Floating-Point Context Address Register */
1232 #define FPU_FPCAR_ADDRESS_Pos 3
1233 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1235 /* Floating-Point Default Status Control Register */
1236 #define FPU_FPDSCR_AHP_Pos 26
1237 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1239 #define FPU_FPDSCR_DN_Pos 25
1240 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1242 #define FPU_FPDSCR_FZ_Pos 24
1243 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1245 #define FPU_FPDSCR_RMode_Pos 22
1246 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1248 /* Media and FP Feature Register 0 */
1249 #define FPU_MVFR0_FP_rounding_modes_Pos 28
1250 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1252 #define FPU_MVFR0_Short_vectors_Pos 24
1253 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1255 #define FPU_MVFR0_Square_root_Pos 20
1256 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1258 #define FPU_MVFR0_Divide_Pos 16
1259 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1261 #define FPU_MVFR0_FP_excep_trapping_Pos 12
1262 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1264 #define FPU_MVFR0_Double_precision_Pos 8
1265 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1267 #define FPU_MVFR0_Single_precision_Pos 4
1268 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1270 #define FPU_MVFR0_A_SIMD_registers_Pos 0
1271 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)
1273 /* Media and FP Feature Register 1 */
1274 #define FPU_MVFR1_FP_fused_MAC_Pos 28
1275 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1277 #define FPU_MVFR1_FP_HPFP_Pos 24
1278 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1280 #define FPU_MVFR1_D_NaN_mode_Pos 4
1281 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1283 #define FPU_MVFR1_FtZ_mode_Pos 0
1284 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos)
1286 
1287 #endif
1288 
1289 
1298 typedef struct
1299 {
1300  __IO uint32_t DHCSR;
1301  __O uint32_t DCRSR;
1302  __IO uint32_t DCRDR;
1303  __IO uint32_t DEMCR;
1304 } CoreDebug_Type;
1305 
1306 /* Debug Halting Control and Status Register */
1307 #define CoreDebug_DHCSR_DBGKEY_Pos 16
1308 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1310 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25
1311 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1313 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24
1314 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1316 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19
1317 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1319 #define CoreDebug_DHCSR_S_SLEEP_Pos 18
1320 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1322 #define CoreDebug_DHCSR_S_HALT_Pos 17
1323 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1325 #define CoreDebug_DHCSR_S_REGRDY_Pos 16
1326 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1328 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5
1329 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1331 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3
1332 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1334 #define CoreDebug_DHCSR_C_STEP_Pos 2
1335 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1337 #define CoreDebug_DHCSR_C_HALT_Pos 1
1338 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1340 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0
1341 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)
1343 /* Debug Core Register Selector Register */
1344 #define CoreDebug_DCRSR_REGWnR_Pos 16
1345 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1347 #define CoreDebug_DCRSR_REGSEL_Pos 0
1348 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)
1350 /* Debug Exception and Monitor Control Register */
1351 #define CoreDebug_DEMCR_TRCENA_Pos 24
1352 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1354 #define CoreDebug_DEMCR_MON_REQ_Pos 19
1355 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1357 #define CoreDebug_DEMCR_MON_STEP_Pos 18
1358 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1360 #define CoreDebug_DEMCR_MON_PEND_Pos 17
1361 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1363 #define CoreDebug_DEMCR_MON_EN_Pos 16
1364 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1366 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10
1367 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1369 #define CoreDebug_DEMCR_VC_INTERR_Pos 9
1370 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1372 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8
1373 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1375 #define CoreDebug_DEMCR_VC_STATERR_Pos 7
1376 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1378 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6
1379 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1381 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5
1382 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1384 #define CoreDebug_DEMCR_VC_MMERR_Pos 4
1385 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1387 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0
1388 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)
1390 
1399 /* Memory mapping of Cortex-M4 Hardware */
1400 #define SCS_BASE (0xE000E000UL)
1401 #define ITM_BASE (0xE0000000UL)
1402 #define DWT_BASE (0xE0001000UL)
1403 #define TPI_BASE (0xE0040000UL)
1404 #define CoreDebug_BASE (0xE000EDF0UL)
1405 #define SysTick_BASE (SCS_BASE + 0x0010UL)
1406 #define NVIC_BASE (SCS_BASE + 0x0100UL)
1407 #define SCB_BASE (SCS_BASE + 0x0D00UL)
1409 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1410 #define SCB ((SCB_Type *) SCB_BASE )
1411 #define SysTick ((SysTick_Type *) SysTick_BASE )
1412 #define NVIC ((NVIC_Type *) NVIC_BASE )
1413 #define ITM ((ITM_Type *) ITM_BASE )
1414 #define DWT ((DWT_Type *) DWT_BASE )
1415 #define TPI ((TPI_Type *) TPI_BASE )
1416 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
1418 #if (__MPU_PRESENT == 1)
1419  #define MPU_BASE (SCS_BASE + 0x0D90UL)
1420  #define MPU ((MPU_Type *) MPU_BASE )
1421 #endif
1422 
1423 #if (__FPU_PRESENT == 1)
1424  #define FPU_BASE (SCS_BASE + 0x0F30UL)
1425  #define FPU ((FPU_Type *) FPU_BASE )
1426 #endif
1427 
1432 /*******************************************************************************
1433  * Hardware Abstraction Layer
1434  Core Function Interface contains:
1435  - Core NVIC Functions
1436  - Core SysTick Functions
1437  - Core Debug Functions
1438  - Core Register Access Functions
1439  ******************************************************************************/
1445 /* ########################## NVIC functions #################################### */
1462 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1463 {
1464  uint32_t reg_value;
1465  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
1466 
1467  reg_value = SCB->AIRCR; /* read old register configuration */
1468  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1469  reg_value = (reg_value |
1470  ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1471  (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1472  SCB->AIRCR = reg_value;
1473 }
1474 
1475 
1482 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1483 {
1484  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1485 }
1486 
1487 
1494 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1495 {
1496 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
1497  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
1498 }
1499 
1500 
1507 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1508 {
1509  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1510 }
1511 
1512 
1523 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1524 {
1525  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1526 }
1527 
1528 
1535 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1536 {
1537  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1538 }
1539 
1540 
1547 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1548 {
1549  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1550 }
1551 
1552 
1562 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1563 {
1564  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1565 }
1566 
1567 
1577 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1578 {
1579  if(IRQn < 0) {
1580  SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1581  else {
1582  NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1583 }
1584 
1585 
1597 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1598 {
1599 
1600  if(IRQn < 0) {
1601  return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
1602  else {
1603  return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1604 }
1605 
1606 
1619 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1620 {
1621  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1622  uint32_t PreemptPriorityBits;
1623  uint32_t SubPriorityBits;
1624 
1625  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1626  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1627 
1628  return (
1629  ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1630  ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1631  );
1632 }
1633 
1634 
1647 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1648 {
1649  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1650  uint32_t PreemptPriorityBits;
1651  uint32_t SubPriorityBits;
1652 
1653  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1654  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1655 
1656  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1657  *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1658 }
1659 
1660 
1665 __STATIC_INLINE void NVIC_CoreReset(void)
1666 {
1667  __DSB(); /* Ensure all outstanding memory accesses included
1668  buffered write are completed before reset */
1669  SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1670  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1671  CoreDebug_DEMCR_VC_CORERESET_Msk); /* Keep priority group unchanged */
1672  __DSB(); /* Ensure completion of memory access */
1673  while(1); /* wait until reset */
1674 }
1675 
1680 __STATIC_INLINE void NVIC_SystemReset(void)
1681 {
1682  __DSB(); /* Ensure all outstanding memory accesses included
1683  buffered write are completed before reset */
1684  SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1685  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1686  SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1687  __DSB(); /* Ensure completion of memory access */
1688  while(1); /* wait until reset */
1689 }
1690 
1695 /* ################################## SysTick function ############################################ */
1702 #if (__Vendor_SysTickConfig == 0)
1703 
1719 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1720 {
1721  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1722 
1723  SysTick->LOAD = ticks - 1; /* set reload register */
1724  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
1725  SysTick->VAL = 0; /* Load the SysTick Counter Value */
1726  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1727  SysTick_CTRL_TICKINT_Msk |
1728  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1729  return (0); /* Function successful */
1730 }
1731 
1732 #endif
1733 
1738 /* ##################################### Debug In/Output function ########################################### */
1745 extern volatile int32_t ITM_RxBuffer;
1746 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5
1759 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1760 {
1761  if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1762  (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
1763  {
1764  while (ITM->PORT[0].u32 == 0);
1765  ITM->PORT[0].u8 = (uint8_t) ch;
1766  }
1767  return (ch);
1768 }
1769 
1770 
1778 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
1779  int32_t ch = -1; /* no character available */
1780 
1781  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1782  ch = ITM_RxBuffer;
1783  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1784  }
1785 
1786  return (ch);
1787 }
1788 
1789 
1797 __STATIC_INLINE int32_t ITM_CheckChar (void) {
1798 
1799  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1800  return (0); /* no character available */
1801  } else {
1802  return (1); /* character available */
1803  }
1804 }
1805 
1811 #ifdef __cplusplus
1812 }
1813 #endif
1814 
1815 #endif /* __CORE_CM4_H_DEPENDANT */
1816 
1817 #endif /* __CMSIS_GENERIC */
SysTick_IRQn
Definition: stm32f4xx.h:196
core_cmFunc.h
CMSIS Cortex-M Core Function Access Header File.
__I
#define __I
Definition: core_cm4.h:246
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h:1630
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm4.h:472
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:309
IRQn_Type
enum IRQn IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm4.h:663
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:334
ITM
#define ITM
Definition: core_cm4.h:1413
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h:761
core_cmInstr.h
CMSIS Cortex-M Core Instruction Access Header File.
IRQn
IRQn
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f4xx.h:186
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h:1467
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_cm4.h:1746
CoreDebug_DEMCR_VC_CORERESET_Msk
#define CoreDebug_DEMCR_VC_CORERESET_Msk
Definition: core_cm4.h:1388
NVIC_SetPriority
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm0.h:611
__IO
#define __IO
Definition: core_cm4.h:249
__O
#define __O
Definition: core_cm4.h:248
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm4.h:666
SCB
#define SCB
Definition: core_cm4.h:1410
NVIC_DisableIRQ
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm0.h:556
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:439
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h:1152
core_cmSimd.h
CMSIS Cortex-M SIMD Header File.
NVIC_SystemReset
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm0.h:647
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0.h:224
NVIC_EnableIRQ
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm0.h:544
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_cm4.h:473
NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm0.h:572
SysTick
#define SysTick
Definition: core_cm4.h:1411
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_cm4.h:482
SysTick_Config
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm0.h:685
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_cm0.h:286
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h:906
NVIC
#define NVIC
Definition: core_cm4.h:1412
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm4.h:673
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Decode Priority.
Definition: airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h:1495
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h:573
NVIC_SetPendingIRQ
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm0.h:584
NVIC_ClearPendingIRQ
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm0.h:596
SCnSCB_Type::ACTLR
__IO uint32_t ACTLR
Definition: core_cm4.h:616
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0.h:247
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h:1611
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0.h:260
NVIC_GetPriority
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm0.h:633
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm4.h:669
u16
uint16_t u16
Definition: stm32f4xx.h:691
NVIC_GetActive
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h:1410
NVIC_SetPriorityGrouping
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h:1311
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: stm32f4xx.h:178
NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h:1331
u32
uint32_t u32
Definition: stm32f4xx.h:690
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_cm4.h:766
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm4.h:485
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h:660
u8
uint8_t u8
Definition: stm32f4xx.h:692
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_cm4.h:481
NVIC_CoreReset
__STATIC_INLINE void NVIC_CoreReset(void)
System Reset.
Definition: core_cm4.h:1665

rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Apr 15 2021 05:07:46