stm32f4xx.h
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1 
53 #ifndef __STM32F4xx_H
54 #define __STM32F4xx_H
55 
56 #ifdef __cplusplus
57  extern "C" {
58 #endif /* __cplusplus */
59 
64 /* Uncomment the line below according to the target STM32 device used in your
65  application
66  */
67 
68 #if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \
69  !defined(STM32F411xE) && !defined(STM32F446xx) && !defined(STM32F469_479xx)
70  /* #define STM32F40_41xxx */
74  /* #define STM32F427_437xx */
77  /* #define STM32F429_439xx */
82  /* #define STM32F401xx */
85  /* #define STM32F410xx */
87  /* #define STM32F411xE */
89  /* #define STM32F446xx */
92  /* #define STM32F469_479xx */
94 #endif /* STM32F40_41xxx && STM32F427_437xx && STM32F429_439xx && STM32F401xx && STM32F410xx && STM32F411xE && STM32F446xx && STM32F469_479xx */
95 
96 /* Old STM32F40XX definition, maintained for legacy purpose */
97 #ifdef STM32F40XX
98  #define STM32F40_41xxx
99 #endif /* STM32F40XX */
100 
101 /* Old STM32F427X definition, maintained for legacy purpose */
102 #ifdef STM32F427X
103  #define STM32F427_437xx
104 #endif /* STM32F427X */
105 
106 /* Tip: To avoid modifying this file each time you need to switch between these
107  devices, you can define the device in your toolchain compiler preprocessor.
108  */
109 
110 #if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \
111  !defined(STM32F411xE) && !defined(STM32F446xx) && !defined(STM32F469_479xx)
112  #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
113 #endif
114 
115 #if !defined (USE_STDPERIPH_DRIVER)
116 
121  /*#define USE_STDPERIPH_DRIVER */
122 #endif /* USE_STDPERIPH_DRIVER */
123 
131 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || \
132  defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
133  #if !defined (HSE_VALUE)
134  #define HSE_VALUE ((uint32_t)25000000)
135  #endif /* HSE_VALUE */
136 #elif defined(STM32F446xx)
137  #if !defined (HSE_VALUE)
138  #define HSE_VALUE ((uint32_t)8000000)
139  #endif /* HSE_VALUE */
140 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
141 
145 #if !defined (HSE_STARTUP_TIMEOUT)
146  #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000)
147 #endif /* HSE_STARTUP_TIMEOUT */
148 
149 #if !defined (HSI_VALUE)
150  #define HSI_VALUE ((uint32_t)16000000)
151 #endif /* HSI_VALUE */
152 
156 #define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01)
157 #define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x06)
158 #define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x01)
159 #define __STM32F4XX_STDPERIPH_VERSION_RC (0x00)
160 #define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
161  |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
162  |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
163  |(__STM32F4XX_STDPERIPH_VERSION_RC))
164 
176 #define __CM4_REV 0x0001
177 #define __MPU_PRESENT 1
178 #define __NVIC_PRIO_BITS 4
179 #define __Vendor_SysTickConfig 0
180 #define __FPU_PRESENT 1
186 typedef enum IRQn
187 {
188 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
189  NonMaskableInt_IRQn = -14,
190  MemoryManagement_IRQn = -12,
191  BusFault_IRQn = -11,
192  UsageFault_IRQn = -10,
193  SVCall_IRQn = -5,
194  DebugMonitor_IRQn = -4,
195  PendSV_IRQn = -2,
196  SysTick_IRQn = -1,
197 /****** STM32 specific Interrupt Numbers **********************************************************************/
198  WWDG_IRQn = 0,
199  PVD_IRQn = 1,
200  TAMP_STAMP_IRQn = 2,
201  RTC_WKUP_IRQn = 3,
202  FLASH_IRQn = 4,
203  RCC_IRQn = 5,
204  EXTI0_IRQn = 6,
205  EXTI1_IRQn = 7,
206  EXTI2_IRQn = 8,
207  EXTI3_IRQn = 9,
208  EXTI4_IRQn = 10,
209  DMA1_Stream0_IRQn = 11,
210  DMA1_Stream1_IRQn = 12,
211  DMA1_Stream2_IRQn = 13,
212  DMA1_Stream3_IRQn = 14,
213  DMA1_Stream4_IRQn = 15,
214  DMA1_Stream5_IRQn = 16,
215  DMA1_Stream6_IRQn = 17,
216  ADC_IRQn = 18,
218 #if defined(STM32F40_41xxx)
219  CAN1_TX_IRQn = 19,
220  CAN1_RX0_IRQn = 20,
221  CAN1_RX1_IRQn = 21,
222  CAN1_SCE_IRQn = 22,
223  EXTI9_5_IRQn = 23,
224  TIM1_BRK_TIM9_IRQn = 24,
225  TIM1_UP_TIM10_IRQn = 25,
226  TIM1_TRG_COM_TIM11_IRQn = 26,
227  TIM1_CC_IRQn = 27,
228  TIM2_IRQn = 28,
229  TIM3_IRQn = 29,
230  TIM4_IRQn = 30,
231  I2C1_EV_IRQn = 31,
232  I2C1_ER_IRQn = 32,
233  I2C2_EV_IRQn = 33,
234  I2C2_ER_IRQn = 34,
235  SPI1_IRQn = 35,
236  SPI2_IRQn = 36,
237  USART1_IRQn = 37,
238  USART2_IRQn = 38,
239  USART3_IRQn = 39,
240  EXTI15_10_IRQn = 40,
241  RTC_Alarm_IRQn = 41,
242  OTG_FS_WKUP_IRQn = 42,
243  TIM8_BRK_TIM12_IRQn = 43,
244  TIM8_UP_TIM13_IRQn = 44,
245  TIM8_TRG_COM_TIM14_IRQn = 45,
246  TIM8_CC_IRQn = 46,
247  DMA1_Stream7_IRQn = 47,
248  FSMC_IRQn = 48,
249  SDIO_IRQn = 49,
250  TIM5_IRQn = 50,
251  SPI3_IRQn = 51,
252  UART4_IRQn = 52,
253  UART5_IRQn = 53,
254  TIM6_DAC_IRQn = 54,
255  TIM7_IRQn = 55,
256  DMA2_Stream0_IRQn = 56,
257  DMA2_Stream1_IRQn = 57,
258  DMA2_Stream2_IRQn = 58,
259  DMA2_Stream3_IRQn = 59,
260  DMA2_Stream4_IRQn = 60,
261  ETH_IRQn = 61,
262  ETH_WKUP_IRQn = 62,
263  CAN2_TX_IRQn = 63,
264  CAN2_RX0_IRQn = 64,
265  CAN2_RX1_IRQn = 65,
266  CAN2_SCE_IRQn = 66,
267  OTG_FS_IRQn = 67,
268  DMA2_Stream5_IRQn = 68,
269  DMA2_Stream6_IRQn = 69,
270  DMA2_Stream7_IRQn = 70,
271  USART6_IRQn = 71,
272  I2C3_EV_IRQn = 72,
273  I2C3_ER_IRQn = 73,
274  OTG_HS_EP1_OUT_IRQn = 74,
275  OTG_HS_EP1_IN_IRQn = 75,
276  OTG_HS_WKUP_IRQn = 76,
277  OTG_HS_IRQn = 77,
278  DCMI_IRQn = 78,
279  CRYP_IRQn = 79,
280  HASH_RNG_IRQn = 80,
281  FPU_IRQn = 81
282 #endif /* STM32F40_41xxx */
283 
284 #if defined(STM32F427_437xx)
285  CAN1_TX_IRQn = 19,
286  CAN1_RX0_IRQn = 20,
287  CAN1_RX1_IRQn = 21,
288  CAN1_SCE_IRQn = 22,
289  EXTI9_5_IRQn = 23,
290  TIM1_BRK_TIM9_IRQn = 24,
291  TIM1_UP_TIM10_IRQn = 25,
292  TIM1_TRG_COM_TIM11_IRQn = 26,
293  TIM1_CC_IRQn = 27,
294  TIM2_IRQn = 28,
295  TIM3_IRQn = 29,
296  TIM4_IRQn = 30,
297  I2C1_EV_IRQn = 31,
298  I2C1_ER_IRQn = 32,
299  I2C2_EV_IRQn = 33,
300  I2C2_ER_IRQn = 34,
301  SPI1_IRQn = 35,
302  SPI2_IRQn = 36,
303  USART1_IRQn = 37,
304  USART2_IRQn = 38,
305  USART3_IRQn = 39,
306  EXTI15_10_IRQn = 40,
307  RTC_Alarm_IRQn = 41,
308  OTG_FS_WKUP_IRQn = 42,
309  TIM8_BRK_TIM12_IRQn = 43,
310  TIM8_UP_TIM13_IRQn = 44,
311  TIM8_TRG_COM_TIM14_IRQn = 45,
312  TIM8_CC_IRQn = 46,
313  DMA1_Stream7_IRQn = 47,
314  FMC_IRQn = 48,
315  SDIO_IRQn = 49,
316  TIM5_IRQn = 50,
317  SPI3_IRQn = 51,
318  UART4_IRQn = 52,
319  UART5_IRQn = 53,
320  TIM6_DAC_IRQn = 54,
321  TIM7_IRQn = 55,
322  DMA2_Stream0_IRQn = 56,
323  DMA2_Stream1_IRQn = 57,
324  DMA2_Stream2_IRQn = 58,
325  DMA2_Stream3_IRQn = 59,
326  DMA2_Stream4_IRQn = 60,
327  ETH_IRQn = 61,
328  ETH_WKUP_IRQn = 62,
329  CAN2_TX_IRQn = 63,
330  CAN2_RX0_IRQn = 64,
331  CAN2_RX1_IRQn = 65,
332  CAN2_SCE_IRQn = 66,
333  OTG_FS_IRQn = 67,
334  DMA2_Stream5_IRQn = 68,
335  DMA2_Stream6_IRQn = 69,
336  DMA2_Stream7_IRQn = 70,
337  USART6_IRQn = 71,
338  I2C3_EV_IRQn = 72,
339  I2C3_ER_IRQn = 73,
340  OTG_HS_EP1_OUT_IRQn = 74,
341  OTG_HS_EP1_IN_IRQn = 75,
342  OTG_HS_WKUP_IRQn = 76,
343  OTG_HS_IRQn = 77,
344  DCMI_IRQn = 78,
345  CRYP_IRQn = 79,
346  HASH_RNG_IRQn = 80,
347  FPU_IRQn = 81,
348  UART7_IRQn = 82,
349  UART8_IRQn = 83,
350  SPI4_IRQn = 84,
351  SPI5_IRQn = 85,
352  SPI6_IRQn = 86,
353  SAI1_IRQn = 87,
354  DMA2D_IRQn = 90
355 #endif /* STM32F427_437xx */
356 
357 #if defined(STM32F429_439xx)
358  CAN1_TX_IRQn = 19,
359  CAN1_RX0_IRQn = 20,
360  CAN1_RX1_IRQn = 21,
361  CAN1_SCE_IRQn = 22,
362  EXTI9_5_IRQn = 23,
363  TIM1_BRK_TIM9_IRQn = 24,
364  TIM1_UP_TIM10_IRQn = 25,
365  TIM1_TRG_COM_TIM11_IRQn = 26,
366  TIM1_CC_IRQn = 27,
367  TIM2_IRQn = 28,
368  TIM3_IRQn = 29,
369  TIM4_IRQn = 30,
370  I2C1_EV_IRQn = 31,
371  I2C1_ER_IRQn = 32,
372  I2C2_EV_IRQn = 33,
373  I2C2_ER_IRQn = 34,
374  SPI1_IRQn = 35,
375  SPI2_IRQn = 36,
376  USART1_IRQn = 37,
377  USART2_IRQn = 38,
378  USART3_IRQn = 39,
379  EXTI15_10_IRQn = 40,
380  RTC_Alarm_IRQn = 41,
381  OTG_FS_WKUP_IRQn = 42,
382  TIM8_BRK_TIM12_IRQn = 43,
383  TIM8_UP_TIM13_IRQn = 44,
384  TIM8_TRG_COM_TIM14_IRQn = 45,
385  TIM8_CC_IRQn = 46,
386  DMA1_Stream7_IRQn = 47,
387  FMC_IRQn = 48,
388  SDIO_IRQn = 49,
389  TIM5_IRQn = 50,
390  SPI3_IRQn = 51,
391  UART4_IRQn = 52,
392  UART5_IRQn = 53,
393  TIM6_DAC_IRQn = 54,
394  TIM7_IRQn = 55,
395  DMA2_Stream0_IRQn = 56,
396  DMA2_Stream1_IRQn = 57,
397  DMA2_Stream2_IRQn = 58,
398  DMA2_Stream3_IRQn = 59,
399  DMA2_Stream4_IRQn = 60,
400  ETH_IRQn = 61,
401  ETH_WKUP_IRQn = 62,
402  CAN2_TX_IRQn = 63,
403  CAN2_RX0_IRQn = 64,
404  CAN2_RX1_IRQn = 65,
405  CAN2_SCE_IRQn = 66,
406  OTG_FS_IRQn = 67,
407  DMA2_Stream5_IRQn = 68,
408  DMA2_Stream6_IRQn = 69,
409  DMA2_Stream7_IRQn = 70,
410  USART6_IRQn = 71,
411  I2C3_EV_IRQn = 72,
412  I2C3_ER_IRQn = 73,
413  OTG_HS_EP1_OUT_IRQn = 74,
414  OTG_HS_EP1_IN_IRQn = 75,
415  OTG_HS_WKUP_IRQn = 76,
416  OTG_HS_IRQn = 77,
417  DCMI_IRQn = 78,
418  CRYP_IRQn = 79,
419  HASH_RNG_IRQn = 80,
420  FPU_IRQn = 81,
421  UART7_IRQn = 82,
422  UART8_IRQn = 83,
423  SPI4_IRQn = 84,
424  SPI5_IRQn = 85,
425  SPI6_IRQn = 86,
426  SAI1_IRQn = 87,
427  LTDC_IRQn = 88,
428  LTDC_ER_IRQn = 89,
429  DMA2D_IRQn = 90
430 #endif /* STM32F429_439xx */
431 
432 #if defined(STM32F410xx)
433  EXTI9_5_IRQn = 23,
434  TIM1_BRK_TIM9_IRQn = 24,
435  TIM1_UP_IRQn = 25,
436  TIM1_TRG_COM_TIM11_IRQn = 26,
437  TIM1_CC_IRQn = 27,
438  I2C1_EV_IRQn = 31,
439  I2C1_ER_IRQn = 32,
440  I2C2_EV_IRQn = 33,
441  I2C2_ER_IRQn = 34,
442  SPI1_IRQn = 35,
443  SPI2_IRQn = 36,
444  USART1_IRQn = 37,
445  USART2_IRQn = 38,
446  EXTI15_10_IRQn = 40,
447  RTC_Alarm_IRQn = 41,
448  DMA1_Stream7_IRQn = 47,
449  TIM5_IRQn = 50,
450  TIM6_DAC_IRQn = 54,
451  DMA2_Stream0_IRQn = 56,
452  DMA2_Stream1_IRQn = 57,
453  DMA2_Stream2_IRQn = 58,
454  DMA2_Stream3_IRQn = 59,
455  DMA2_Stream4_IRQn = 60,
456  DMA2_Stream5_IRQn = 68,
457  DMA2_Stream6_IRQn = 69,
458  DMA2_Stream7_IRQn = 70,
459  USART6_IRQn = 71,
460  RNG_IRQn = 80,
461  FPU_IRQn = 81,
462  SPI5_IRQn = 85,
463  FMPI2C1_EV_IRQn = 95,
464  FMPI2C1_ER_IRQn = 96,
465  LPTIM1_IRQn = 97
466 #endif /* STM32F410xx */
467 
468 #if defined(STM32F401xx) || defined(STM32F411xE)
469  EXTI9_5_IRQn = 23,
470  TIM1_BRK_TIM9_IRQn = 24,
471  TIM1_UP_TIM10_IRQn = 25,
472  TIM1_TRG_COM_TIM11_IRQn = 26,
473  TIM1_CC_IRQn = 27,
474  TIM2_IRQn = 28,
475  TIM3_IRQn = 29,
476  TIM4_IRQn = 30,
477  I2C1_EV_IRQn = 31,
478  I2C1_ER_IRQn = 32,
479  I2C2_EV_IRQn = 33,
480  I2C2_ER_IRQn = 34,
481  SPI1_IRQn = 35,
482  SPI2_IRQn = 36,
483  USART1_IRQn = 37,
484  USART2_IRQn = 38,
485  EXTI15_10_IRQn = 40,
486  RTC_Alarm_IRQn = 41,
487  OTG_FS_WKUP_IRQn = 42,
488  DMA1_Stream7_IRQn = 47,
489  SDIO_IRQn = 49,
490  TIM5_IRQn = 50,
491  SPI3_IRQn = 51,
492  DMA2_Stream0_IRQn = 56,
493  DMA2_Stream1_IRQn = 57,
494  DMA2_Stream2_IRQn = 58,
495  DMA2_Stream3_IRQn = 59,
496  DMA2_Stream4_IRQn = 60,
497  OTG_FS_IRQn = 67,
498  DMA2_Stream5_IRQn = 68,
499  DMA2_Stream6_IRQn = 69,
500  DMA2_Stream7_IRQn = 70,
501  USART6_IRQn = 71,
502  I2C3_EV_IRQn = 72,
503  I2C3_ER_IRQn = 73,
504  FPU_IRQn = 81,
505 #if defined(STM32F401xx)
506  SPI4_IRQn = 84
507 #endif /* STM32F411xE */
508 #if defined(STM32F411xE)
509  SPI4_IRQn = 84,
510  SPI5_IRQn = 85
511 #endif /* STM32F411xE */
512 #endif /* STM32F401xx || STM32F411xE */
513 
514 #if defined(STM32F469_479xx)
515  CAN1_TX_IRQn = 19,
516  CAN1_RX0_IRQn = 20,
517  CAN1_RX1_IRQn = 21,
518  CAN1_SCE_IRQn = 22,
519  EXTI9_5_IRQn = 23,
520  TIM1_BRK_TIM9_IRQn = 24,
521  TIM1_UP_TIM10_IRQn = 25,
522  TIM1_TRG_COM_TIM11_IRQn = 26,
523  TIM1_CC_IRQn = 27,
524  TIM2_IRQn = 28,
525  TIM3_IRQn = 29,
526  TIM4_IRQn = 30,
527  I2C1_EV_IRQn = 31,
528  I2C1_ER_IRQn = 32,
529  I2C2_EV_IRQn = 33,
530  I2C2_ER_IRQn = 34,
531  SPI1_IRQn = 35,
532  SPI2_IRQn = 36,
533  USART1_IRQn = 37,
534  USART2_IRQn = 38,
535  USART3_IRQn = 39,
536  EXTI15_10_IRQn = 40,
537  RTC_Alarm_IRQn = 41,
538  OTG_FS_WKUP_IRQn = 42,
539  TIM8_BRK_TIM12_IRQn = 43,
540  TIM8_UP_TIM13_IRQn = 44,
541  TIM8_TRG_COM_TIM14_IRQn = 45,
542  TIM8_CC_IRQn = 46,
543  DMA1_Stream7_IRQn = 47,
544  FMC_IRQn = 48,
545  SDIO_IRQn = 49,
546  TIM5_IRQn = 50,
547  SPI3_IRQn = 51,
548  UART4_IRQn = 52,
549  UART5_IRQn = 53,
550  TIM6_DAC_IRQn = 54,
551  TIM7_IRQn = 55,
552  DMA2_Stream0_IRQn = 56,
553  DMA2_Stream1_IRQn = 57,
554  DMA2_Stream2_IRQn = 58,
555  DMA2_Stream3_IRQn = 59,
556  DMA2_Stream4_IRQn = 60,
557  ETH_IRQn = 61,
558  ETH_WKUP_IRQn = 62,
559  CAN2_TX_IRQn = 63,
560  CAN2_RX0_IRQn = 64,
561  CAN2_RX1_IRQn = 65,
562  CAN2_SCE_IRQn = 66,
563  OTG_FS_IRQn = 67,
564  DMA2_Stream5_IRQn = 68,
565  DMA2_Stream6_IRQn = 69,
566  DMA2_Stream7_IRQn = 70,
567  USART6_IRQn = 71,
568  I2C3_EV_IRQn = 72,
569  I2C3_ER_IRQn = 73,
570  OTG_HS_EP1_OUT_IRQn = 74,
571  OTG_HS_EP1_IN_IRQn = 75,
572  OTG_HS_WKUP_IRQn = 76,
573  OTG_HS_IRQn = 77,
574  DCMI_IRQn = 78,
575  CRYP_IRQn = 79,
576  HASH_RNG_IRQn = 80,
577  FPU_IRQn = 81,
578  UART7_IRQn = 82,
579  UART8_IRQn = 83,
580  SPI4_IRQn = 84,
581  SPI5_IRQn = 85,
582  SPI6_IRQn = 86,
583  SAI1_IRQn = 87,
584  LTDC_IRQn = 88,
585  LTDC_ER_IRQn = 89,
586  DMA2D_IRQn = 90,
587  QUADSPI_IRQn = 91,
588  DSI_IRQn = 92
589 #endif /* STM32F469_479xx */
590 
591 #if defined(STM32F446xx)
592  CAN1_TX_IRQn = 19,
593  CAN1_RX0_IRQn = 20,
594  CAN1_RX1_IRQn = 21,
595  CAN1_SCE_IRQn = 22,
596  EXTI9_5_IRQn = 23,
597  TIM1_BRK_TIM9_IRQn = 24,
598  TIM1_UP_TIM10_IRQn = 25,
599  TIM1_TRG_COM_TIM11_IRQn = 26,
600  TIM1_CC_IRQn = 27,
601  TIM2_IRQn = 28,
602  TIM3_IRQn = 29,
603  TIM4_IRQn = 30,
604  I2C1_EV_IRQn = 31,
605  I2C1_ER_IRQn = 32,
606  I2C2_EV_IRQn = 33,
607  I2C2_ER_IRQn = 34,
608  SPI1_IRQn = 35,
609  SPI2_IRQn = 36,
610  USART1_IRQn = 37,
611  USART2_IRQn = 38,
612  USART3_IRQn = 39,
613  EXTI15_10_IRQn = 40,
614  RTC_Alarm_IRQn = 41,
615  OTG_FS_WKUP_IRQn = 42,
616  TIM8_BRK_IRQn = 43,
617  TIM8_BRK_TIM12_IRQn = 43,
618  TIM8_UP_TIM13_IRQn = 44,
619  TIM8_TRG_COM_TIM14_IRQn = 45,
620  DMA1_Stream7_IRQn = 47,
621  FMC_IRQn = 48,
622  SDIO_IRQn = 49,
623  TIM5_IRQn = 50,
624  SPI3_IRQn = 51,
625  UART4_IRQn = 52,
626  UART5_IRQn = 53,
627  TIM6_DAC_IRQn = 54,
628  TIM7_IRQn = 55,
629  DMA2_Stream0_IRQn = 56,
630  DMA2_Stream1_IRQn = 57,
631  DMA2_Stream2_IRQn = 58,
632  DMA2_Stream3_IRQn = 59,
633  DMA2_Stream4_IRQn = 60,
634  CAN2_TX_IRQn = 63,
635  CAN2_RX0_IRQn = 64,
636  CAN2_RX1_IRQn = 65,
637  CAN2_SCE_IRQn = 66,
638  OTG_FS_IRQn = 67,
639  DMA2_Stream5_IRQn = 68,
640  DMA2_Stream6_IRQn = 69,
641  DMA2_Stream7_IRQn = 70,
642  USART6_IRQn = 71,
643  I2C3_EV_IRQn = 72,
644  I2C3_ER_IRQn = 73,
645  OTG_HS_EP1_OUT_IRQn = 74,
646  OTG_HS_EP1_IN_IRQn = 75,
647  OTG_HS_WKUP_IRQn = 76,
648  OTG_HS_IRQn = 77,
649  DCMI_IRQn = 78,
650  FPU_IRQn = 81,
651  SPI4_IRQn = 84,
652  SAI1_IRQn = 87,
653  SAI2_IRQn = 91,
654  QUADSPI_IRQn = 92,
655  CEC_IRQn = 93,
656  SPDIF_RX_IRQn = 94,
657  FMPI2C1_EV_IRQn = 95,
658  FMPI2C1_ER_IRQn = 96
659 #endif /* STM32F446xx */
660 } IRQn_Type;
661 
666 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
667 #include "system_stm32f4xx.h"
668 #include <stdint.h>
669 
674 typedef int32_t s32;
675 typedef int16_t s16;
676 typedef int8_t s8;
677 
678 typedef const int32_t sc32;
679 typedef const int16_t sc16;
680 typedef const int8_t sc8;
682 typedef __IO int32_t vs32;
683 typedef __IO int16_t vs16;
684 typedef __IO int8_t vs8;
685 
686 typedef __I int32_t vsc32;
687 typedef __I int16_t vsc16;
688 typedef __I int8_t vsc8;
690 typedef uint32_t u32;
691 typedef uint16_t u16;
692 typedef uint8_t u8;
693 
694 typedef const uint32_t uc32;
695 typedef const uint16_t uc16;
696 typedef const uint8_t uc8;
698 typedef __IO uint32_t vu32;
699 typedef __IO uint16_t vu16;
700 typedef __IO uint8_t vu8;
701 
702 typedef __I uint32_t vuc32;
703 typedef __I uint16_t vuc16;
704 typedef __I uint8_t vuc8;
706 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
707 
708 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
709 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
710 
711 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
712 
725 typedef struct
726 {
727  __IO uint32_t SR;
728  __IO uint32_t CR1;
729  __IO uint32_t CR2;
730  __IO uint32_t SMPR1;
731  __IO uint32_t SMPR2;
732  __IO uint32_t JOFR1;
733  __IO uint32_t JOFR2;
734  __IO uint32_t JOFR3;
735  __IO uint32_t JOFR4;
736  __IO uint32_t HTR;
737  __IO uint32_t LTR;
738  __IO uint32_t SQR1;
739  __IO uint32_t SQR2;
740  __IO uint32_t SQR3;
741  __IO uint32_t JSQR;
742  __IO uint32_t JDR1;
743  __IO uint32_t JDR2;
744  __IO uint32_t JDR3;
745  __IO uint32_t JDR4;
746  __IO uint32_t DR;
747 } ADC_TypeDef;
748 
749 typedef struct
750 {
751  __IO uint32_t CSR;
752  __IO uint32_t CCR;
753  __IO uint32_t CDR;
755 } ADC_Common_TypeDef;
756 
757 
762 typedef struct
763 {
764  __IO uint32_t TIR;
765  __IO uint32_t TDTR;
766  __IO uint32_t TDLR;
767  __IO uint32_t TDHR;
768 } CAN_TxMailBox_TypeDef;
769 
774 typedef struct
775 {
776  __IO uint32_t RIR;
777  __IO uint32_t RDTR;
778  __IO uint32_t RDLR;
779  __IO uint32_t RDHR;
780 } CAN_FIFOMailBox_TypeDef;
781 
786 typedef struct
787 {
788  __IO uint32_t FR1;
789  __IO uint32_t FR2;
790 } CAN_FilterRegister_TypeDef;
791 
796 typedef struct
797 {
798  __IO uint32_t MCR;
799  __IO uint32_t MSR;
800  __IO uint32_t TSR;
801  __IO uint32_t RF0R;
802  __IO uint32_t RF1R;
803  __IO uint32_t IER;
804  __IO uint32_t ESR;
805  __IO uint32_t BTR;
806  uint32_t RESERVED0[88];
807  CAN_TxMailBox_TypeDef sTxMailBox[3];
808  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
809  uint32_t RESERVED1[12];
810  __IO uint32_t FMR;
811  __IO uint32_t FM1R;
812  uint32_t RESERVED2;
813  __IO uint32_t FS1R;
814  uint32_t RESERVED3;
815  __IO uint32_t FFA1R;
816  uint32_t RESERVED4;
817  __IO uint32_t FA1R;
818  uint32_t RESERVED5[8];
819  CAN_FilterRegister_TypeDef sFilterRegister[28];
820 } CAN_TypeDef;
821 
822 #if defined(STM32F446xx)
823 
826 typedef struct
827 {
828  __IO uint32_t CR;
829  __IO uint32_t CFGR;
830  __IO uint32_t TXDR;
831  __IO uint32_t RXDR;
832  __IO uint32_t ISR;
833  __IO uint32_t IER;
834 }CEC_TypeDef;
835 #endif /* STM32F446xx */
836 
841 typedef struct
842 {
843  __IO uint32_t DR;
844  __IO uint8_t IDR;
845  uint8_t RESERVED0;
846  uint16_t RESERVED1;
847  __IO uint32_t CR;
848 } CRC_TypeDef;
849 
854 typedef struct
855 {
856  __IO uint32_t CR;
857  __IO uint32_t SWTRIGR;
858  __IO uint32_t DHR12R1;
859  __IO uint32_t DHR12L1;
860  __IO uint32_t DHR8R1;
861  __IO uint32_t DHR12R2;
862  __IO uint32_t DHR12L2;
863  __IO uint32_t DHR8R2;
864  __IO uint32_t DHR12RD;
865  __IO uint32_t DHR12LD;
866  __IO uint32_t DHR8RD;
867  __IO uint32_t DOR1;
868  __IO uint32_t DOR2;
869  __IO uint32_t SR;
870 } DAC_TypeDef;
871 
876 typedef struct
877 {
878  __IO uint32_t IDCODE;
879  __IO uint32_t CR;
880  __IO uint32_t APB1FZ;
881  __IO uint32_t APB2FZ;
882 }DBGMCU_TypeDef;
883 
888 typedef struct
889 {
890  __IO uint32_t CR;
891  __IO uint32_t SR;
892  __IO uint32_t RISR;
893  __IO uint32_t IER;
894  __IO uint32_t MISR;
895  __IO uint32_t ICR;
896  __IO uint32_t ESCR;
897  __IO uint32_t ESUR;
898  __IO uint32_t CWSTRTR;
899  __IO uint32_t CWSIZER;
900  __IO uint32_t DR;
901 } DCMI_TypeDef;
902 
907 typedef struct
908 {
909  __IO uint32_t CR;
910  __IO uint32_t NDTR;
911  __IO uint32_t PAR;
912  __IO uint32_t M0AR;
913  __IO uint32_t M1AR;
914  __IO uint32_t FCR;
915 } DMA_Stream_TypeDef;
916 
917 typedef struct
918 {
919  __IO uint32_t LISR;
920  __IO uint32_t HISR;
921  __IO uint32_t LIFCR;
922  __IO uint32_t HIFCR;
923 } DMA_TypeDef;
924 
929 typedef struct
930 {
931  __IO uint32_t CR;
932  __IO uint32_t ISR;
933  __IO uint32_t IFCR;
934  __IO uint32_t FGMAR;
935  __IO uint32_t FGOR;
936  __IO uint32_t BGMAR;
937  __IO uint32_t BGOR;
938  __IO uint32_t FGPFCCR;
939  __IO uint32_t FGCOLR;
940  __IO uint32_t BGPFCCR;
941  __IO uint32_t BGCOLR;
942  __IO uint32_t FGCMAR;
943  __IO uint32_t BGCMAR;
944  __IO uint32_t OPFCCR;
945  __IO uint32_t OCOLR;
946  __IO uint32_t OMAR;
947  __IO uint32_t OOR;
948  __IO uint32_t NLR;
949  __IO uint32_t LWR;
950  __IO uint32_t AMTCR;
951  uint32_t RESERVED[236];
952  __IO uint32_t FGCLUT[256];
953  __IO uint32_t BGCLUT[256];
954 } DMA2D_TypeDef;
955 
956 #if defined(STM32F469_479xx)
957 
961 typedef struct
962 {
963  __IO uint32_t VR;
964  __IO uint32_t CR;
965  __IO uint32_t CCR;
966  __IO uint32_t LVCIDR;
967  __IO uint32_t LCOLCR;
968  __IO uint32_t LPCR;
969  __IO uint32_t LPMCR;
970  uint32_t RESERVED0[4];
971  __IO uint32_t PCR;
972  __IO uint32_t GVCIDR;
973  __IO uint32_t MCR;
974  __IO uint32_t VMCR;
975  __IO uint32_t VPCR;
976  __IO uint32_t VCCR;
977  __IO uint32_t VNPCR;
978  __IO uint32_t VHSACR;
979  __IO uint32_t VHBPCR;
980  __IO uint32_t VLCR;
981  __IO uint32_t VVSACR;
982  __IO uint32_t VVBPCR;
983  __IO uint32_t VVFPCR;
984  __IO uint32_t VVACR;
985  __IO uint32_t LCCR;
986  __IO uint32_t CMCR;
987  __IO uint32_t GHCR;
988  __IO uint32_t GPDR;
989  __IO uint32_t GPSR;
990  __IO uint32_t TCCR[6];
991  __IO uint32_t TDCR;
992  __IO uint32_t CLCR;
993  __IO uint32_t CLTCR;
994  __IO uint32_t DLTCR;
995  __IO uint32_t PCTLR;
996  __IO uint32_t PCONFR;
997  __IO uint32_t PUCR;
998  __IO uint32_t PTTCR;
999  __IO uint32_t PSR;
1000  uint32_t RESERVED1[2];
1001  __IO uint32_t ISR[2];
1002  __IO uint32_t IER[2];
1003  uint32_t RESERVED2[3];
1004  __IO uint32_t FIR[2];
1005  uint32_t RESERVED3[8];
1006  __IO uint32_t VSCR;
1007  uint32_t RESERVED4[2];
1008  __IO uint32_t LCVCIDR;
1009  __IO uint32_t LCCCR;
1010  uint32_t RESERVED5;
1011  __IO uint32_t LPMCCR;
1012  uint32_t RESERVED6[7];
1013  __IO uint32_t VMCCR;
1014  __IO uint32_t VPCCR;
1015  __IO uint32_t VCCCR;
1016  __IO uint32_t VNPCCR;
1017  __IO uint32_t VHSACCR;
1018  __IO uint32_t VHBPCCR;
1019  __IO uint32_t VLCCR;
1020  __IO uint32_t VVSACCR;
1021  __IO uint32_t VVBPCCR;
1022  __IO uint32_t VVFPCCR;
1023  __IO uint32_t VVACCR;
1024  uint32_t RESERVED7[11];
1025  __IO uint32_t TDCCR;
1026  uint32_t RESERVED8[155];
1027  __IO uint32_t WCFGR;
1028  __IO uint32_t WCR;
1029  __IO uint32_t WIER;
1030  __IO uint32_t WISR;
1031  __IO uint32_t WIFCR;
1032  uint32_t RESERVED9;
1033  __IO uint32_t WPCR[5];
1034  uint32_t RESERVED10;
1035  __IO uint32_t WRPCR;
1036 } DSI_TypeDef;
1037 #endif /* STM32F469_479xx */
1038 
1043 typedef struct
1044 {
1045  __IO uint32_t MACCR;
1046  __IO uint32_t MACFFR;
1047  __IO uint32_t MACHTHR;
1048  __IO uint32_t MACHTLR;
1049  __IO uint32_t MACMIIAR;
1050  __IO uint32_t MACMIIDR;
1051  __IO uint32_t MACFCR;
1052  __IO uint32_t MACVLANTR; /* 8 */
1053  uint32_t RESERVED0[2];
1054  __IO uint32_t MACRWUFFR; /* 11 */
1055  __IO uint32_t MACPMTCSR;
1056  uint32_t RESERVED1[2];
1057  __IO uint32_t MACSR; /* 15 */
1058  __IO uint32_t MACIMR;
1059  __IO uint32_t MACA0HR;
1060  __IO uint32_t MACA0LR;
1061  __IO uint32_t MACA1HR;
1062  __IO uint32_t MACA1LR;
1063  __IO uint32_t MACA2HR;
1064  __IO uint32_t MACA2LR;
1065  __IO uint32_t MACA3HR;
1066  __IO uint32_t MACA3LR; /* 24 */
1067  uint32_t RESERVED2[40];
1068  __IO uint32_t MMCCR; /* 65 */
1069  __IO uint32_t MMCRIR;
1070  __IO uint32_t MMCTIR;
1071  __IO uint32_t MMCRIMR;
1072  __IO uint32_t MMCTIMR; /* 69 */
1073  uint32_t RESERVED3[14];
1074  __IO uint32_t MMCTGFSCCR; /* 84 */
1075  __IO uint32_t MMCTGFMSCCR;
1076  uint32_t RESERVED4[5];
1077  __IO uint32_t MMCTGFCR;
1078  uint32_t RESERVED5[10];
1079  __IO uint32_t MMCRFCECR;
1080  __IO uint32_t MMCRFAECR;
1081  uint32_t RESERVED6[10];
1082  __IO uint32_t MMCRGUFCR;
1083  uint32_t RESERVED7[334];
1084  __IO uint32_t PTPTSCR;
1085  __IO uint32_t PTPSSIR;
1086  __IO uint32_t PTPTSHR;
1087  __IO uint32_t PTPTSLR;
1088  __IO uint32_t PTPTSHUR;
1089  __IO uint32_t PTPTSLUR;
1090  __IO uint32_t PTPTSAR;
1091  __IO uint32_t PTPTTHR;
1092  __IO uint32_t PTPTTLR;
1093  __IO uint32_t RESERVED8;
1094  __IO uint32_t PTPTSSR;
1095  uint32_t RESERVED9[565];
1096  __IO uint32_t DMABMR;
1097  __IO uint32_t DMATPDR;
1098  __IO uint32_t DMARPDR;
1099  __IO uint32_t DMARDLAR;
1100  __IO uint32_t DMATDLAR;
1101  __IO uint32_t DMASR;
1102  __IO uint32_t DMAOMR;
1103  __IO uint32_t DMAIER;
1104  __IO uint32_t DMAMFBOCR;
1105  __IO uint32_t DMARSWTR;
1106  uint32_t RESERVED10[8];
1107  __IO uint32_t DMACHTDR;
1108  __IO uint32_t DMACHRDR;
1109  __IO uint32_t DMACHTBAR;
1110  __IO uint32_t DMACHRBAR;
1111 } ETH_TypeDef;
1112 
1117 typedef struct
1118 {
1119  __IO uint32_t IMR;
1120  __IO uint32_t EMR;
1121  __IO uint32_t RTSR;
1122  __IO uint32_t FTSR;
1123  __IO uint32_t SWIER;
1124  __IO uint32_t PR;
1125 } EXTI_TypeDef;
1126 
1131 typedef struct
1132 {
1133  __IO uint32_t ACR;
1134  __IO uint32_t KEYR;
1135  __IO uint32_t OPTKEYR;
1136  __IO uint32_t SR;
1137  __IO uint32_t CR;
1138  __IO uint32_t OPTCR;
1139  __IO uint32_t OPTCR1;
1140 } FLASH_TypeDef;
1141 
1142 #if defined(STM32F40_41xxx)
1143 
1147 typedef struct
1148 {
1149  __IO uint32_t BTCR[8];
1150 } FSMC_Bank1_TypeDef;
1151 
1156 typedef struct
1157 {
1158  __IO uint32_t BWTR[7];
1159 } FSMC_Bank1E_TypeDef;
1160 
1165 typedef struct
1166 {
1167  __IO uint32_t PCR2;
1168  __IO uint32_t SR2;
1169  __IO uint32_t PMEM2;
1170  __IO uint32_t PATT2;
1171  uint32_t RESERVED0;
1172  __IO uint32_t ECCR2;
1173 } FSMC_Bank2_TypeDef;
1174 
1179 typedef struct
1180 {
1181  __IO uint32_t PCR3;
1182  __IO uint32_t SR3;
1183  __IO uint32_t PMEM3;
1184  __IO uint32_t PATT3;
1185  uint32_t RESERVED0;
1186  __IO uint32_t ECCR3;
1187 } FSMC_Bank3_TypeDef;
1188 
1193 typedef struct
1194 {
1195  __IO uint32_t PCR4;
1196  __IO uint32_t SR4;
1197  __IO uint32_t PMEM4;
1198  __IO uint32_t PATT4;
1199  __IO uint32_t PIO4;
1200 } FSMC_Bank4_TypeDef;
1201 #endif /* STM32F40_41xxx */
1202 
1203 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
1204 
1208 typedef struct
1209 {
1210  __IO uint32_t BTCR[8];
1211 } FMC_Bank1_TypeDef;
1212 
1217 typedef struct
1218 {
1219  __IO uint32_t BWTR[7];
1220 } FMC_Bank1E_TypeDef;
1221 
1226 typedef struct
1227 {
1228  __IO uint32_t PCR2;
1229  __IO uint32_t SR2;
1230  __IO uint32_t PMEM2;
1231  __IO uint32_t PATT2;
1232  uint32_t RESERVED0;
1233  __IO uint32_t ECCR2;
1234 } FMC_Bank2_TypeDef;
1235 
1240 typedef struct
1241 {
1242  __IO uint32_t PCR3;
1243  __IO uint32_t SR3;
1244  __IO uint32_t PMEM3;
1245  __IO uint32_t PATT3;
1246  uint32_t RESERVED0;
1247  __IO uint32_t ECCR3;
1248 } FMC_Bank3_TypeDef;
1249 
1254 typedef struct
1255 {
1256  __IO uint32_t PCR4;
1257  __IO uint32_t SR4;
1258  __IO uint32_t PMEM4;
1259  __IO uint32_t PATT4;
1260  __IO uint32_t PIO4;
1261 } FMC_Bank4_TypeDef;
1262 
1267 typedef struct
1268 {
1269  __IO uint32_t SDCR[2];
1270  __IO uint32_t SDTR[2];
1271  __IO uint32_t SDCMR;
1272  __IO uint32_t SDRTR;
1273  __IO uint32_t SDSR;
1274 } FMC_Bank5_6_TypeDef;
1275 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
1276 
1281 typedef struct
1282 {
1283  __IO uint32_t MODER;
1284  __IO uint32_t OTYPER;
1285  __IO uint32_t OSPEEDR;
1286  __IO uint32_t PUPDR;
1287  __IO uint32_t IDR;
1288  __IO uint32_t ODR;
1289  __IO uint16_t BSRRL;
1290  __IO uint16_t BSRRH;
1291  __IO uint32_t LCKR;
1292  __IO uint32_t AFR[2];
1293 } GPIO_TypeDef;
1294 
1299 typedef struct
1300 {
1301  __IO uint32_t MEMRMP;
1302  __IO uint32_t PMC;
1303  __IO uint32_t EXTICR[4];
1304 #if defined (STM32F410xx)
1305  uint32_t RESERVED;
1306  uint32_t CFGR2;
1307  __IO uint32_t CMPCR;
1308  uint32_t RESERVED1[2];
1309  __IO uint32_t CFGR;
1310 #else /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F469_479xx */
1311  uint32_t RESERVED[2];
1312  __IO uint32_t CMPCR;
1313 #endif /* STM32F410xx */
1314 } SYSCFG_TypeDef;
1315 
1320 typedef struct
1321 {
1322  __IO uint16_t CR1;
1323  uint16_t RESERVED0;
1324  __IO uint16_t CR2;
1325  uint16_t RESERVED1;
1326  __IO uint16_t OAR1;
1327  uint16_t RESERVED2;
1328  __IO uint16_t OAR2;
1329  uint16_t RESERVED3;
1330  __IO uint16_t DR;
1331  uint16_t RESERVED4;
1332  __IO uint16_t SR1;
1333  uint16_t RESERVED5;
1334  __IO uint16_t SR2;
1335  uint16_t RESERVED6;
1336  __IO uint16_t CCR;
1337  uint16_t RESERVED7;
1338  __IO uint16_t TRISE;
1339  uint16_t RESERVED8;
1340  __IO uint16_t FLTR;
1341  uint16_t RESERVED9;
1342 } I2C_TypeDef;
1343 
1344 #if defined(STM32F410xx) || defined(STM32F446xx)
1345 
1349 typedef struct
1350 {
1351  __IO uint32_t CR1;
1352  __IO uint32_t CR2;
1353  __IO uint32_t OAR1;
1354  __IO uint32_t OAR2;
1355  __IO uint32_t TIMINGR;
1356  __IO uint32_t TIMEOUTR;
1357  __IO uint32_t ISR;
1358  __IO uint32_t ICR;
1359  __IO uint32_t PECR;
1360  __IO uint32_t RXDR;
1361  __IO uint32_t TXDR;
1362 }FMPI2C_TypeDef;
1363 #endif /* STM32F410xx || STM32F446xx */
1364 
1369 typedef struct
1370 {
1371  __IO uint32_t KR;
1372  __IO uint32_t PR;
1373  __IO uint32_t RLR;
1374  __IO uint32_t SR;
1375 } IWDG_TypeDef;
1376 
1381 typedef struct
1382 {
1383  uint32_t RESERVED0[2];
1384  __IO uint32_t SSCR;
1385  __IO uint32_t BPCR;
1386  __IO uint32_t AWCR;
1387  __IO uint32_t TWCR;
1388  __IO uint32_t GCR;
1389  uint32_t RESERVED1[2];
1390  __IO uint32_t SRCR;
1391  uint32_t RESERVED2[1];
1392  __IO uint32_t BCCR;
1393  uint32_t RESERVED3[1];
1394  __IO uint32_t IER;
1395  __IO uint32_t ISR;
1396  __IO uint32_t ICR;
1397  __IO uint32_t LIPCR;
1398  __IO uint32_t CPSR;
1399  __IO uint32_t CDSR;
1400 } LTDC_TypeDef;
1401 
1406 typedef struct
1407 {
1408  __IO uint32_t CR;
1409  __IO uint32_t WHPCR;
1410  __IO uint32_t WVPCR;
1411  __IO uint32_t CKCR;
1412  __IO uint32_t PFCR;
1413  __IO uint32_t CACR;
1414  __IO uint32_t DCCR;
1415  __IO uint32_t BFCR;
1416  uint32_t RESERVED0[2];
1417  __IO uint32_t CFBAR;
1418  __IO uint32_t CFBLR;
1419  __IO uint32_t CFBLNR;
1420  uint32_t RESERVED1[3];
1421  __IO uint32_t CLUTWR;
1423 } LTDC_Layer_TypeDef;
1424 
1429 typedef struct
1430 {
1431  __IO uint32_t CR;
1432  __IO uint32_t CSR;
1433 } PWR_TypeDef;
1434 
1439 typedef struct
1440 {
1441  __IO uint32_t CR;
1442  __IO uint32_t PLLCFGR;
1443  __IO uint32_t CFGR;
1444  __IO uint32_t CIR;
1445  __IO uint32_t AHB1RSTR;
1446  __IO uint32_t AHB2RSTR;
1447  __IO uint32_t AHB3RSTR;
1448  uint32_t RESERVED0;
1449  __IO uint32_t APB1RSTR;
1450  __IO uint32_t APB2RSTR;
1451  uint32_t RESERVED1[2];
1452  __IO uint32_t AHB1ENR;
1453  __IO uint32_t AHB2ENR;
1454  __IO uint32_t AHB3ENR;
1455  uint32_t RESERVED2;
1456  __IO uint32_t APB1ENR;
1457  __IO uint32_t APB2ENR;
1458  uint32_t RESERVED3[2];
1459  __IO uint32_t AHB1LPENR;
1460  __IO uint32_t AHB2LPENR;
1461  __IO uint32_t AHB3LPENR;
1462  uint32_t RESERVED4;
1463  __IO uint32_t APB1LPENR;
1464  __IO uint32_t APB2LPENR;
1465  uint32_t RESERVED5[2];
1466  __IO uint32_t BDCR;
1467  __IO uint32_t CSR;
1468  uint32_t RESERVED6[2];
1469  __IO uint32_t SSCGR;
1470  __IO uint32_t PLLI2SCFGR;
1471  __IO uint32_t PLLSAICFGR;
1472  __IO uint32_t DCKCFGR;
1473  __IO uint32_t CKGATENR; /* Only for STM32F446xx devices */
1474  __IO uint32_t DCKCFGR2; /* Only for STM32F446xx devices and STM32F410xx devices */
1475 
1476 } RCC_TypeDef;
1477 
1482 typedef struct
1483 {
1484  __IO uint32_t TR;
1485  __IO uint32_t DR;
1486  __IO uint32_t CR;
1487  __IO uint32_t ISR;
1488  __IO uint32_t PRER;
1489  __IO uint32_t WUTR;
1490  __IO uint32_t CALIBR;
1491  __IO uint32_t ALRMAR;
1492  __IO uint32_t ALRMBR;
1493  __IO uint32_t WPR;
1494  __IO uint32_t SSR;
1495  __IO uint32_t SHIFTR;
1496  __IO uint32_t TSTR;
1497  __IO uint32_t TSDR;
1498  __IO uint32_t TSSSR;
1499  __IO uint32_t CALR;
1500  __IO uint32_t TAFCR;
1501  __IO uint32_t ALRMASSR;
1502  __IO uint32_t ALRMBSSR;
1503  uint32_t RESERVED7;
1504  __IO uint32_t BKP0R;
1505  __IO uint32_t BKP1R;
1506  __IO uint32_t BKP2R;
1507  __IO uint32_t BKP3R;
1508  __IO uint32_t BKP4R;
1509  __IO uint32_t BKP5R;
1510  __IO uint32_t BKP6R;
1511  __IO uint32_t BKP7R;
1512  __IO uint32_t BKP8R;
1513  __IO uint32_t BKP9R;
1514  __IO uint32_t BKP10R;
1515  __IO uint32_t BKP11R;
1516  __IO uint32_t BKP12R;
1517  __IO uint32_t BKP13R;
1518  __IO uint32_t BKP14R;
1519  __IO uint32_t BKP15R;
1520  __IO uint32_t BKP16R;
1521  __IO uint32_t BKP17R;
1522  __IO uint32_t BKP18R;
1523  __IO uint32_t BKP19R;
1524 } RTC_TypeDef;
1525 
1526 
1531 typedef struct
1532 {
1533  __IO uint32_t GCR;
1534 } SAI_TypeDef;
1535 
1536 typedef struct
1537 {
1538  __IO uint32_t CR1;
1539  __IO uint32_t CR2;
1540  __IO uint32_t FRCR;
1541  __IO uint32_t SLOTR;
1542  __IO uint32_t IMR;
1543  __IO uint32_t SR;
1544  __IO uint32_t CLRFR;
1545  __IO uint32_t DR;
1546 } SAI_Block_TypeDef;
1547 
1552 typedef struct
1553 {
1554  __IO uint32_t POWER;
1555  __IO uint32_t CLKCR;
1556  __IO uint32_t ARG;
1557  __IO uint32_t CMD;
1558  __I uint32_t RESPCMD;
1559  __I uint32_t RESP1;
1560  __I uint32_t RESP2;
1561  __I uint32_t RESP3;
1562  __I uint32_t RESP4;
1563  __IO uint32_t DTIMER;
1564  __IO uint32_t DLEN;
1565  __IO uint32_t DCTRL;
1566  __I uint32_t DCOUNT;
1567  __I uint32_t STA;
1568  __IO uint32_t ICR;
1569  __IO uint32_t MASK;
1570  uint32_t RESERVED0[2];
1571  __I uint32_t FIFOCNT;
1572  uint32_t RESERVED1[13];
1573  __IO uint32_t FIFO;
1574 } SDIO_TypeDef;
1575 
1580 typedef struct
1581 {
1582  __IO uint16_t CR1;
1583  uint16_t RESERVED0;
1584  __IO uint16_t CR2;
1585  uint16_t RESERVED1;
1586  __IO uint16_t SR;
1587  uint16_t RESERVED2;
1588  __IO uint16_t DR;
1589  uint16_t RESERVED3;
1590  __IO uint16_t CRCPR;
1591  uint16_t RESERVED4;
1592  __IO uint16_t RXCRCR;
1593  uint16_t RESERVED5;
1594  __IO uint16_t TXCRCR;
1595  uint16_t RESERVED6;
1596  __IO uint16_t I2SCFGR;
1597  uint16_t RESERVED7;
1598  __IO uint16_t I2SPR;
1599  uint16_t RESERVED8;
1600 } SPI_TypeDef;
1601 
1602 #if defined(STM32F446xx)
1603 
1606 typedef struct
1607 {
1608  __IO uint32_t CR;
1609  __IO uint16_t IMR;
1610  uint16_t RESERVED0;
1611  __IO uint32_t SR;
1612  __IO uint16_t IFCR;
1613  uint16_t RESERVED1;
1614  __IO uint32_t DR;
1615  __IO uint32_t CSR;
1616  __IO uint32_t DIR;
1617  uint16_t RESERVED2;
1618 } SPDIFRX_TypeDef;
1619 #endif /* STM32F446xx */
1620 
1621 #if defined(STM32F446xx) || defined(STM32F469_479xx)
1622 
1625 typedef struct
1626 {
1627  __IO uint32_t CR;
1628  __IO uint32_t DCR;
1629  __IO uint32_t SR;
1630  __IO uint32_t FCR;
1631  __IO uint32_t DLR;
1632  __IO uint32_t CCR;
1633  __IO uint32_t AR;
1634  __IO uint32_t ABR;
1635  __IO uint32_t DR;
1636  __IO uint32_t PSMKR;
1637  __IO uint32_t PSMAR;
1638  __IO uint32_t PIR;
1639  __IO uint32_t LPTR;
1640 } QUADSPI_TypeDef;
1641 #endif /* STM32F446xx || STM32F469_479xx */
1642 
1643 #if defined(STM32F446xx)
1644 
1647 typedef struct
1648 {
1649  __IO uint32_t CR;
1650  __IO uint16_t IMR;
1651  uint16_t RESERVED0;
1652  __IO uint32_t SR;
1653  __IO uint16_t IFCR;
1654  uint16_t RESERVED1;
1655  __IO uint32_t DR;
1656  __IO uint32_t CSR;
1657  __IO uint32_t DIR;
1658  uint16_t RESERVED2;
1659 } SPDIF_TypeDef;
1660 #endif /* STM32F446xx */
1661 
1666 typedef struct
1667 {
1668  __IO uint16_t CR1;
1669  uint16_t RESERVED0;
1670  __IO uint16_t CR2;
1671  uint16_t RESERVED1;
1672  __IO uint16_t SMCR;
1673  uint16_t RESERVED2;
1674  __IO uint16_t DIER;
1675  uint16_t RESERVED3;
1676  __IO uint16_t SR;
1677  uint16_t RESERVED4;
1678  __IO uint16_t EGR;
1679  uint16_t RESERVED5;
1680  __IO uint16_t CCMR1;
1681  uint16_t RESERVED6;
1682  __IO uint16_t CCMR2;
1683  uint16_t RESERVED7;
1684  __IO uint16_t CCER;
1685  uint16_t RESERVED8;
1686  __IO uint32_t CNT;
1687  __IO uint16_t PSC;
1688  uint16_t RESERVED9;
1689  __IO uint32_t ARR;
1690  __IO uint16_t RCR;
1691  uint16_t RESERVED10;
1692  __IO uint32_t CCR1;
1693  __IO uint32_t CCR2;
1694  __IO uint32_t CCR3;
1695  __IO uint32_t CCR4;
1696  __IO uint16_t BDTR;
1697  uint16_t RESERVED11;
1698  __IO uint16_t DCR;
1699  uint16_t RESERVED12;
1700  __IO uint16_t DMAR;
1701  uint16_t RESERVED13;
1702  __IO uint16_t OR;
1703  uint16_t RESERVED14;
1704 } TIM_TypeDef;
1705 
1710 typedef struct
1711 {
1712  __IO uint16_t SR;
1713  uint16_t RESERVED0;
1714  __IO uint16_t DR;
1715  uint16_t RESERVED1;
1716  __IO uint16_t BRR;
1717  uint16_t RESERVED2;
1718  __IO uint16_t CR1;
1719  uint16_t RESERVED3;
1720  __IO uint16_t CR2;
1721  uint16_t RESERVED4;
1722  __IO uint16_t CR3;
1723  uint16_t RESERVED5;
1724  __IO uint16_t GTPR;
1725  uint16_t RESERVED6;
1726 } USART_TypeDef;
1727 
1732 typedef struct
1733 {
1734  __IO uint32_t CR;
1735  __IO uint32_t CFR;
1736  __IO uint32_t SR;
1737 } WWDG_TypeDef;
1738 
1743 typedef struct
1744 {
1745  __IO uint32_t CR;
1746  __IO uint32_t SR;
1747  __IO uint32_t DR;
1748  __IO uint32_t DOUT;
1749  __IO uint32_t DMACR;
1750  __IO uint32_t IMSCR;
1751  __IO uint32_t RISR;
1752  __IO uint32_t MISR;
1753  __IO uint32_t K0LR;
1754  __IO uint32_t K0RR;
1755  __IO uint32_t K1LR;
1756  __IO uint32_t K1RR;
1757  __IO uint32_t K2LR;
1758  __IO uint32_t K2RR;
1759  __IO uint32_t K3LR;
1760  __IO uint32_t K3RR;
1761  __IO uint32_t IV0LR;
1762  __IO uint32_t IV0RR;
1763  __IO uint32_t IV1LR;
1764  __IO uint32_t IV1RR;
1765  __IO uint32_t CSGCMCCM0R;
1766  __IO uint32_t CSGCMCCM1R;
1767  __IO uint32_t CSGCMCCM2R;
1768  __IO uint32_t CSGCMCCM3R;
1769  __IO uint32_t CSGCMCCM4R;
1770  __IO uint32_t CSGCMCCM5R;
1771  __IO uint32_t CSGCMCCM6R;
1772  __IO uint32_t CSGCMCCM7R;
1773  __IO uint32_t CSGCM0R;
1774  __IO uint32_t CSGCM1R;
1775  __IO uint32_t CSGCM2R;
1776  __IO uint32_t CSGCM3R;
1777  __IO uint32_t CSGCM4R;
1778  __IO uint32_t CSGCM5R;
1779  __IO uint32_t CSGCM6R;
1780  __IO uint32_t CSGCM7R;
1781 } CRYP_TypeDef;
1782 
1787 typedef struct
1788 {
1789  __IO uint32_t CR;
1790  __IO uint32_t DIN;
1791  __IO uint32_t STR;
1792  __IO uint32_t HR[5];
1793  __IO uint32_t IMR;
1794  __IO uint32_t SR;
1795  uint32_t RESERVED[52];
1796  __IO uint32_t CSR[54];
1797 } HASH_TypeDef;
1798 
1803 typedef struct
1804 {
1805  __IO uint32_t HR[8];
1806 } HASH_DIGEST_TypeDef;
1807 
1812 typedef struct
1813 {
1814  __IO uint32_t CR;
1815  __IO uint32_t SR;
1816  __IO uint32_t DR;
1817 } RNG_TypeDef;
1818 
1819 #if defined(STM32F410xx)
1820 
1823 typedef struct
1824 {
1825  __IO uint32_t ISR;
1826  __IO uint32_t ICR;
1827  __IO uint32_t IER;
1828  __IO uint32_t CFGR;
1829  __IO uint32_t CR;
1830  __IO uint32_t CMP;
1831  __IO uint32_t ARR;
1832  __IO uint32_t CNT;
1833  __IO uint32_t OR;
1834 } LPTIM_TypeDef;
1835 #endif /* STM32F410xx */
1836 
1843 #define FLASH_BASE ((uint32_t)0x08000000)
1844 #define CCMDATARAM_BASE ((uint32_t)0x10000000)
1845 #define SRAM1_BASE ((uint32_t)0x20000000)
1846 #define SRAM2_BASE ((uint32_t)0x2001C000)
1847 #define SRAM3_BASE ((uint32_t)0x20020000)
1848 #define PERIPH_BASE ((uint32_t)0x40000000)
1849 #define BKPSRAM_BASE ((uint32_t)0x40024000)
1851 #if defined(STM32F40_41xxx)
1852 #define FSMC_R_BASE ((uint32_t)0xA0000000)
1853 #endif /* STM32F40_41xxx */
1854 
1855 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
1856 #define FMC_R_BASE ((uint32_t)0xA0000000)
1857 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
1858 
1859 #if defined(STM32F446xx) || defined(STM32F469_479xx)
1860 #define QSPI_R_BASE ((uint32_t)0xA0001000)
1861 #endif /* STM32F446xx || STM32F469_479xx */
1862 
1863 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000)
1864 #define SRAM1_BB_BASE ((uint32_t)0x22000000)
1865 #define SRAM2_BB_BASE ((uint32_t)0x2201C000)
1866 #define SRAM3_BB_BASE ((uint32_t)0x22400000)
1867 #define PERIPH_BB_BASE ((uint32_t)0x42000000)
1868 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000)
1870 /* Legacy defines */
1871 #define SRAM_BASE SRAM1_BASE
1872 #define SRAM_BB_BASE SRAM1_BB_BASE
1873 
1874 
1876 #define APB1PERIPH_BASE PERIPH_BASE
1877 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
1878 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
1879 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
1880 
1882 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
1883 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
1884 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
1885 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
1886 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
1887 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
1888 #if defined(STM32F410xx)
1889 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400)
1890 #endif /* STM32F410xx */
1891 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
1892 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
1893 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
1894 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
1895 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
1896 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
1897 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
1898 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
1899 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
1900 #if defined(STM32F446xx)
1901 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000)
1902 #endif /* STM32F446xx */
1903 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
1904 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
1905 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
1906 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
1907 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
1908 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
1909 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
1910 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
1911 #if defined(STM32F410xx) || defined(STM32F446xx)
1912 #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000)
1913 #endif /* STM32F410xx || STM32F446xx */
1914 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
1915 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
1916 #if defined(STM32F446xx)
1917 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00)
1918 #endif /* STM32F446xx */
1919 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
1920 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
1921 #define UART7_BASE (APB1PERIPH_BASE + 0x7800)
1922 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
1923 
1925 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
1926 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
1927 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
1928 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
1929 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
1930 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
1931 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
1932 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
1933 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
1934 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
1935 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
1936 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
1937 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
1938 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
1939 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
1940 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
1941 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
1942 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
1943 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
1944 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
1945 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
1946 #if defined(STM32F446xx)
1947 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00)
1948 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
1949 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
1950 #endif /* STM32F446xx */
1951 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
1952 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
1953 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
1954 #if defined(STM32F469_479xx)
1955 #define DSI_BASE (APB2PERIPH_BASE + 0x6C00)
1956 #endif /* STM32F469_479xx */
1957 
1959 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
1960 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
1961 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
1962 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
1963 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
1964 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
1965 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
1966 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
1967 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
1968 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
1969 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
1970 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
1971 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
1972 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
1973 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
1974 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
1975 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
1976 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
1977 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
1978 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
1979 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
1980 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
1981 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
1982 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
1983 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
1984 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
1985 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
1986 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
1987 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
1988 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
1989 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
1990 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
1991 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
1992 #define ETH_MAC_BASE (ETH_BASE)
1993 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
1994 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
1995 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
1996 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
1997 
1999 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
2000 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
2001 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
2002 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)
2003 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
2004 
2005 #if defined(STM32F40_41xxx)
2006 
2007 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
2008 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
2009 #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
2010 #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
2011 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
2012 #endif /* STM32F40_41xxx */
2013 
2014 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
2015 
2016 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
2017 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
2018 #define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
2019 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
2020 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
2021 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
2022 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
2023 
2024 /* Debug MCU registers base address */
2025 #define DBGMCU_BASE ((uint32_t )0xE0042000)
2026 
2034 #if defined(STM32F446xx) || defined(STM32F469_479xx)
2035 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
2036 #endif /* STM32F446xx || STM32F469_479xx */
2037 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
2038 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
2039 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
2040 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
2041 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
2042 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
2043 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
2044 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
2045 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
2046 #define RTC ((RTC_TypeDef *) RTC_BASE)
2047 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
2048 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
2049 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
2050 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
2051 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
2052 #if defined(STM32F446xx)
2053 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
2054 #endif /* STM32F446xx */
2055 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
2056 #define USART2 ((USART_TypeDef *) USART2_BASE)
2057 #define USART3 ((USART_TypeDef *) USART3_BASE)
2058 #define UART4 ((USART_TypeDef *) UART4_BASE)
2059 #define UART5 ((USART_TypeDef *) UART5_BASE)
2060 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
2061 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
2062 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
2063 #if defined(STM32F410xx) || defined(STM32F446xx)
2064 #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
2065 #endif /* STM32F410xx || STM32F446xx */
2066 #if defined(STM32F410xx)
2067 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
2068 #endif /* STM32F410xx */
2069 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
2070 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
2071 #if defined(STM32F446xx)
2072 #define CEC ((CEC_TypeDef *) CEC_BASE)
2073 #endif /* STM32F446xx */
2074 #define PWR ((PWR_TypeDef *) PWR_BASE)
2075 #define DAC ((DAC_TypeDef *) DAC_BASE)
2076 #define UART7 ((USART_TypeDef *) UART7_BASE)
2077 #define UART8 ((USART_TypeDef *) UART8_BASE)
2078 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
2079 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
2080 #define USART1 ((USART_TypeDef *) USART1_BASE)
2081 #define USART6 ((USART_TypeDef *) USART6_BASE)
2082 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
2083 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
2084 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
2085 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
2086 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
2087 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
2088 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
2089 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
2090 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
2091 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
2092 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
2093 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
2094 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
2095 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
2096 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
2097 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
2098 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
2099 #if defined(STM32F446xx)
2100 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
2101 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
2102 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
2103 #endif /* STM32F446xx */
2104 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
2105 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
2106 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
2107 #if defined(STM32F469_479xx)
2108 #define DSI ((DSI_TypeDef *)DSI_BASE)
2109 #endif /* STM32F469_479xx */
2110 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
2111 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
2112 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
2113 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
2114 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
2115 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
2116 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
2117 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
2118 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
2119 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
2120 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
2121 #define CRC ((CRC_TypeDef *) CRC_BASE)
2122 #define RCC ((RCC_TypeDef *) RCC_BASE)
2123 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
2124 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
2125 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
2126 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
2127 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
2128 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
2129 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
2130 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
2131 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
2132 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
2133 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
2134 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
2135 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
2136 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
2137 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
2138 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
2139 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
2140 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
2141 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
2142 #define ETH ((ETH_TypeDef *) ETH_BASE)
2143 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
2144 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
2145 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
2146 #define HASH ((HASH_TypeDef *) HASH_BASE)
2147 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
2148 #define RNG ((RNG_TypeDef *) RNG_BASE)
2149 
2150 #if defined(STM32F40_41xxx)
2151 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
2152 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
2153 #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
2154 #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
2155 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
2156 #endif /* STM32F40_41xxx */
2157 
2158 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
2159 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
2160 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
2161 #define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
2162 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
2163 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
2164 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
2165 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
2166 
2167 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
2168 
2181 /******************************************************************************/
2182 /* Peripheral Registers_Bits_Definition */
2183 /******************************************************************************/
2184 
2185 /******************************************************************************/
2186 /* */
2187 /* Analog to Digital Converter */
2188 /* */
2189 /******************************************************************************/
2190 /******************** Bit definition for ADC_SR register ********************/
2191 #define ADC_SR_AWD ((uint8_t)0x01)
2192 #define ADC_SR_EOC ((uint8_t)0x02)
2193 #define ADC_SR_JEOC ((uint8_t)0x04)
2194 #define ADC_SR_JSTRT ((uint8_t)0x08)
2195 #define ADC_SR_STRT ((uint8_t)0x10)
2196 #define ADC_SR_OVR ((uint8_t)0x20)
2198 /******************* Bit definition for ADC_CR1 register ********************/
2199 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F)
2200 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001)
2201 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002)
2202 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004)
2203 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008)
2204 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010)
2205 #define ADC_CR1_EOCIE ((uint32_t)0x00000020)
2206 #define ADC_CR1_AWDIE ((uint32_t)0x00000040)
2207 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080)
2208 #define ADC_CR1_SCAN ((uint32_t)0x00000100)
2209 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200)
2210 #define ADC_CR1_JAUTO ((uint32_t)0x00000400)
2211 #define ADC_CR1_DISCEN ((uint32_t)0x00000800)
2212 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000)
2213 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000)
2214 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000)
2215 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000)
2216 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000)
2217 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000)
2218 #define ADC_CR1_AWDEN ((uint32_t)0x00800000)
2219 #define ADC_CR1_RES ((uint32_t)0x03000000)
2220 #define ADC_CR1_RES_0 ((uint32_t)0x01000000)
2221 #define ADC_CR1_RES_1 ((uint32_t)0x02000000)
2222 #define ADC_CR1_OVRIE ((uint32_t)0x04000000)
2224 /******************* Bit definition for ADC_CR2 register ********************/
2225 #define ADC_CR2_ADON ((uint32_t)0x00000001)
2226 #define ADC_CR2_CONT ((uint32_t)0x00000002)
2227 #define ADC_CR2_DMA ((uint32_t)0x00000100)
2228 #define ADC_CR2_DDS ((uint32_t)0x00000200)
2229 #define ADC_CR2_EOCS ((uint32_t)0x00000400)
2230 #define ADC_CR2_ALIGN ((uint32_t)0x00000800)
2231 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000)
2232 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000)
2233 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000)
2234 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000)
2235 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000)
2236 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000)
2237 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000)
2238 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000)
2239 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000)
2240 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000)
2241 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000)
2242 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000)
2243 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000)
2244 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000)
2245 #define ADC_CR2_EXTEN ((uint32_t)0x30000000)
2246 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000)
2247 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000)
2248 #define ADC_CR2_SWSTART ((uint32_t)0x40000000)
2250 /****************** Bit definition for ADC_SMPR1 register *******************/
2251 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007)
2252 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001)
2253 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002)
2254 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004)
2255 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038)
2256 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008)
2257 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010)
2258 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020)
2259 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0)
2260 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040)
2261 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080)
2262 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100)
2263 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00)
2264 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200)
2265 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400)
2266 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800)
2267 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000)
2268 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000)
2269 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000)
2270 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000)
2271 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000)
2272 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000)
2273 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000)
2274 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000)
2275 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000)
2276 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000)
2277 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000)
2278 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000)
2279 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000)
2280 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000)
2281 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000)
2282 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000)
2283 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000)
2284 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000)
2285 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000)
2286 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000)
2288 /****************** Bit definition for ADC_SMPR2 register *******************/
2289 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007)
2290 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001)
2291 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002)
2292 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004)
2293 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038)
2294 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008)
2295 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010)
2296 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020)
2297 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0)
2298 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040)
2299 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080)
2300 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100)
2301 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00)
2302 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200)
2303 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400)
2304 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800)
2305 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000)
2306 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000)
2307 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000)
2308 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000)
2309 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000)
2310 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000)
2311 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000)
2312 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000)
2313 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000)
2314 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000)
2315 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000)
2316 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000)
2317 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000)
2318 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000)
2319 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000)
2320 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000)
2321 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000)
2322 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000)
2323 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000)
2324 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000)
2325 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000)
2326 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000)
2327 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000)
2328 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000)
2330 /****************** Bit definition for ADC_JOFR1 register *******************/
2331 #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF)
2333 /****************** Bit definition for ADC_JOFR2 register *******************/
2334 #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF)
2336 /****************** Bit definition for ADC_JOFR3 register *******************/
2337 #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF)
2339 /****************** Bit definition for ADC_JOFR4 register *******************/
2340 #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF)
2342 /******************* Bit definition for ADC_HTR register ********************/
2343 #define ADC_HTR_HT ((uint16_t)0x0FFF)
2345 /******************* Bit definition for ADC_LTR register ********************/
2346 #define ADC_LTR_LT ((uint16_t)0x0FFF)
2348 /******************* Bit definition for ADC_SQR1 register *******************/
2349 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F)
2350 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001)
2351 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002)
2352 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004)
2353 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008)
2354 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010)
2355 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0)
2356 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020)
2357 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040)
2358 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080)
2359 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100)
2360 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200)
2361 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00)
2362 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400)
2363 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800)
2364 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000)
2365 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000)
2366 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000)
2367 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000)
2368 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000)
2369 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000)
2370 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000)
2371 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000)
2372 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000)
2373 #define ADC_SQR1_L ((uint32_t)0x00F00000)
2374 #define ADC_SQR1_L_0 ((uint32_t)0x00100000)
2375 #define ADC_SQR1_L_1 ((uint32_t)0x00200000)
2376 #define ADC_SQR1_L_2 ((uint32_t)0x00400000)
2377 #define ADC_SQR1_L_3 ((uint32_t)0x00800000)
2379 /******************* Bit definition for ADC_SQR2 register *******************/
2380 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F)
2381 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001)
2382 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002)
2383 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004)
2384 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008)
2385 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010)
2386 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0)
2387 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020)
2388 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040)
2389 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080)
2390 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100)
2391 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200)
2392 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00)
2393 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400)
2394 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800)
2395 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000)
2396 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000)
2397 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000)
2398 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000)
2399 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000)
2400 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000)
2401 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000)
2402 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000)
2403 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000)
2404 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000)
2405 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000)
2406 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000)
2407 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000)
2408 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000)
2409 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000)
2410 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000)
2411 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000)
2412 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000)
2413 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000)
2414 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000)
2415 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000)
2417 /******************* Bit definition for ADC_SQR3 register *******************/
2418 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F)
2419 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001)
2420 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002)
2421 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004)
2422 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008)
2423 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010)
2424 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0)
2425 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020)
2426 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040)
2427 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080)
2428 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100)
2429 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200)
2430 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00)
2431 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400)
2432 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800)
2433 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000)
2434 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000)
2435 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000)
2436 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000)
2437 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000)
2438 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000)
2439 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000)
2440 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000)
2441 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000)
2442 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000)
2443 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000)
2444 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000)
2445 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000)
2446 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000)
2447 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000)
2448 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000)
2449 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000)
2450 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000)
2451 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000)
2452 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000)
2453 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000)
2455 /******************* Bit definition for ADC_JSQR register *******************/
2456 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F)
2457 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001)
2458 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002)
2459 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004)
2460 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008)
2461 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010)
2462 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0)
2463 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020)
2464 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040)
2465 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080)
2466 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100)
2467 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200)
2468 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00)
2469 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400)
2470 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800)
2471 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000)
2472 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000)
2473 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000)
2474 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000)
2475 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000)
2476 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000)
2477 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000)
2478 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000)
2479 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000)
2480 #define ADC_JSQR_JL ((uint32_t)0x00300000)
2481 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000)
2482 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000)
2484 /******************* Bit definition for ADC_JDR1 register *******************/
2485 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF)
2487 /******************* Bit definition for ADC_JDR2 register *******************/
2488 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF)
2490 /******************* Bit definition for ADC_JDR3 register *******************/
2491 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF)
2493 /******************* Bit definition for ADC_JDR4 register *******************/
2494 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF)
2496 /******************** Bit definition for ADC_DR register ********************/
2497 #define ADC_DR_DATA ((uint32_t)0x0000FFFF)
2498 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000)
2500 /******************* Bit definition for ADC_CSR register ********************/
2501 #define ADC_CSR_AWD1 ((uint32_t)0x00000001)
2502 #define ADC_CSR_EOC1 ((uint32_t)0x00000002)
2503 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004)
2504 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008)
2505 #define ADC_CSR_STRT1 ((uint32_t)0x00000010)
2506 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020)
2507 #define ADC_CSR_AWD2 ((uint32_t)0x00000100)
2508 #define ADC_CSR_EOC2 ((uint32_t)0x00000200)
2509 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400)
2510 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800)
2511 #define ADC_CSR_STRT2 ((uint32_t)0x00001000)
2512 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000)
2513 #define ADC_CSR_AWD3 ((uint32_t)0x00010000)
2514 #define ADC_CSR_EOC3 ((uint32_t)0x00020000)
2515 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000)
2516 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000)
2517 #define ADC_CSR_STRT3 ((uint32_t)0x00100000)
2518 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000)
2520 /******************* Bit definition for ADC_CCR register ********************/
2521 #define ADC_CCR_MULTI ((uint32_t)0x0000001F)
2522 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001)
2523 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002)
2524 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004)
2525 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008)
2526 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010)
2527 #define ADC_CCR_DELAY ((uint32_t)0x00000F00)
2528 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100)
2529 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200)
2530 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400)
2531 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800)
2532 #define ADC_CCR_DDS ((uint32_t)0x00002000)
2533 #define ADC_CCR_DMA ((uint32_t)0x0000C000)
2534 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000)
2535 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000)
2536 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000)
2537 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000)
2538 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000)
2539 #define ADC_CCR_VBATE ((uint32_t)0x00400000)
2540 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000)
2542 /******************* Bit definition for ADC_CDR register ********************/
2543 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF)
2544 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000)
2546 /******************************************************************************/
2547 /* */
2548 /* Controller Area Network */
2549 /* */
2550 /******************************************************************************/
2552 /******************* Bit definition for CAN_MCR register ********************/
2553 #define CAN_MCR_INRQ ((uint16_t)0x0001)
2554 #define CAN_MCR_SLEEP ((uint16_t)0x0002)
2555 #define CAN_MCR_TXFP ((uint16_t)0x0004)
2556 #define CAN_MCR_RFLM ((uint16_t)0x0008)
2557 #define CAN_MCR_NART ((uint16_t)0x0010)
2558 #define CAN_MCR_AWUM ((uint16_t)0x0020)
2559 #define CAN_MCR_ABOM ((uint16_t)0x0040)
2560 #define CAN_MCR_TTCM ((uint16_t)0x0080)
2561 #define CAN_MCR_RESET ((uint16_t)0x8000)
2563 /******************* Bit definition for CAN_MSR register ********************/
2564 #define CAN_MSR_INAK ((uint16_t)0x0001)
2565 #define CAN_MSR_SLAK ((uint16_t)0x0002)
2566 #define CAN_MSR_ERRI ((uint16_t)0x0004)
2567 #define CAN_MSR_WKUI ((uint16_t)0x0008)
2568 #define CAN_MSR_SLAKI ((uint16_t)0x0010)
2569 #define CAN_MSR_TXM ((uint16_t)0x0100)
2570 #define CAN_MSR_RXM ((uint16_t)0x0200)
2571 #define CAN_MSR_SAMP ((uint16_t)0x0400)
2572 #define CAN_MSR_RX ((uint16_t)0x0800)
2574 /******************* Bit definition for CAN_TSR register ********************/
2575 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001)
2576 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002)
2577 #define CAN_TSR_ALST0 ((uint32_t)0x00000004)
2578 #define CAN_TSR_TERR0 ((uint32_t)0x00000008)
2579 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080)
2580 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100)
2581 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200)
2582 #define CAN_TSR_ALST1 ((uint32_t)0x00000400)
2583 #define CAN_TSR_TERR1 ((uint32_t)0x00000800)
2584 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000)
2585 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000)
2586 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000)
2587 #define CAN_TSR_ALST2 ((uint32_t)0x00040000)
2588 #define CAN_TSR_TERR2 ((uint32_t)0x00080000)
2589 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000)
2590 #define CAN_TSR_CODE ((uint32_t)0x03000000)
2592 #define CAN_TSR_TME ((uint32_t)0x1C000000)
2593 #define CAN_TSR_TME0 ((uint32_t)0x04000000)
2594 #define CAN_TSR_TME1 ((uint32_t)0x08000000)
2595 #define CAN_TSR_TME2 ((uint32_t)0x10000000)
2597 #define CAN_TSR_LOW ((uint32_t)0xE0000000)
2598 #define CAN_TSR_LOW0 ((uint32_t)0x20000000)
2599 #define CAN_TSR_LOW1 ((uint32_t)0x40000000)
2600 #define CAN_TSR_LOW2 ((uint32_t)0x80000000)
2602 /******************* Bit definition for CAN_RF0R register *******************/
2603 #define CAN_RF0R_FMP0 ((uint8_t)0x03)
2604 #define CAN_RF0R_FULL0 ((uint8_t)0x08)
2605 #define CAN_RF0R_FOVR0 ((uint8_t)0x10)
2606 #define CAN_RF0R_RFOM0 ((uint8_t)0x20)
2608 /******************* Bit definition for CAN_RF1R register *******************/
2609 #define CAN_RF1R_FMP1 ((uint8_t)0x03)
2610 #define CAN_RF1R_FULL1 ((uint8_t)0x08)
2611 #define CAN_RF1R_FOVR1 ((uint8_t)0x10)
2612 #define CAN_RF1R_RFOM1 ((uint8_t)0x20)
2614 /******************** Bit definition for CAN_IER register *******************/
2615 #define CAN_IER_TMEIE ((uint32_t)0x00000001)
2616 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002)
2617 #define CAN_IER_FFIE0 ((uint32_t)0x00000004)
2618 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008)
2619 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010)
2620 #define CAN_IER_FFIE1 ((uint32_t)0x00000020)
2621 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040)
2622 #define CAN_IER_EWGIE ((uint32_t)0x00000100)
2623 #define CAN_IER_EPVIE ((uint32_t)0x00000200)
2624 #define CAN_IER_BOFIE ((uint32_t)0x00000400)
2625 #define CAN_IER_LECIE ((uint32_t)0x00000800)
2626 #define CAN_IER_ERRIE ((uint32_t)0x00008000)
2627 #define CAN_IER_WKUIE ((uint32_t)0x00010000)
2628 #define CAN_IER_SLKIE ((uint32_t)0x00020000)
2630 /******************** Bit definition for CAN_ESR register *******************/
2631 #define CAN_ESR_EWGF ((uint32_t)0x00000001)
2632 #define CAN_ESR_EPVF ((uint32_t)0x00000002)
2633 #define CAN_ESR_BOFF ((uint32_t)0x00000004)
2635 #define CAN_ESR_LEC ((uint32_t)0x00000070)
2636 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010)
2637 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020)
2638 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040)
2640 #define CAN_ESR_TEC ((uint32_t)0x00FF0000)
2641 #define CAN_ESR_REC ((uint32_t)0xFF000000)
2643 /******************* Bit definition for CAN_BTR register ********************/
2644 #define CAN_BTR_BRP ((uint32_t)0x000003FF)
2645 #define CAN_BTR_TS1 ((uint32_t)0x000F0000)
2646 #define CAN_BTR_TS2 ((uint32_t)0x00700000)
2647 #define CAN_BTR_SJW ((uint32_t)0x03000000)
2648 #define CAN_BTR_LBKM ((uint32_t)0x40000000)
2649 #define CAN_BTR_SILM ((uint32_t)0x80000000)
2652 /****************** Bit definition for CAN_TI0R register ********************/
2653 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001)
2654 #define CAN_TI0R_RTR ((uint32_t)0x00000002)
2655 #define CAN_TI0R_IDE ((uint32_t)0x00000004)
2656 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8)
2657 #define CAN_TI0R_STID ((uint32_t)0xFFE00000)
2659 /****************** Bit definition for CAN_TDT0R register *******************/
2660 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F)
2661 #define CAN_TDT0R_TGT ((uint32_t)0x00000100)
2662 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000)
2664 /****************** Bit definition for CAN_TDL0R register *******************/
2665 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF)
2666 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00)
2667 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000)
2668 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000)
2670 /****************** Bit definition for CAN_TDH0R register *******************/
2671 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF)
2672 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00)
2673 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000)
2674 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000)
2676 /******************* Bit definition for CAN_TI1R register *******************/
2677 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001)
2678 #define CAN_TI1R_RTR ((uint32_t)0x00000002)
2679 #define CAN_TI1R_IDE ((uint32_t)0x00000004)
2680 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8)
2681 #define CAN_TI1R_STID ((uint32_t)0xFFE00000)
2683 /******************* Bit definition for CAN_TDT1R register ******************/
2684 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F)
2685 #define CAN_TDT1R_TGT ((uint32_t)0x00000100)
2686 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000)
2688 /******************* Bit definition for CAN_TDL1R register ******************/
2689 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF)
2690 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00)
2691 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000)
2692 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000)
2694 /******************* Bit definition for CAN_TDH1R register ******************/
2695 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF)
2696 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00)
2697 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000)
2698 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000)
2700 /******************* Bit definition for CAN_TI2R register *******************/
2701 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001)
2702 #define CAN_TI2R_RTR ((uint32_t)0x00000002)
2703 #define CAN_TI2R_IDE ((uint32_t)0x00000004)
2704 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8)
2705 #define CAN_TI2R_STID ((uint32_t)0xFFE00000)
2707 /******************* Bit definition for CAN_TDT2R register ******************/
2708 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F)
2709 #define CAN_TDT2R_TGT ((uint32_t)0x00000100)
2710 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000)
2712 /******************* Bit definition for CAN_TDL2R register ******************/
2713 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF)
2714 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00)
2715 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000)
2716 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000)
2718 /******************* Bit definition for CAN_TDH2R register ******************/
2719 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF)
2720 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00)
2721 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000)
2722 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000)
2724 /******************* Bit definition for CAN_RI0R register *******************/
2725 #define CAN_RI0R_RTR ((uint32_t)0x00000002)
2726 #define CAN_RI0R_IDE ((uint32_t)0x00000004)
2727 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8)
2728 #define CAN_RI0R_STID ((uint32_t)0xFFE00000)
2730 /******************* Bit definition for CAN_RDT0R register ******************/
2731 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F)
2732 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00)
2733 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000)
2735 /******************* Bit definition for CAN_RDL0R register ******************/
2736 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF)
2737 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00)
2738 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000)
2739 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000)
2741 /******************* Bit definition for CAN_RDH0R register ******************/
2742 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF)
2743 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00)
2744 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000)
2745 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000)
2747 /******************* Bit definition for CAN_RI1R register *******************/
2748 #define CAN_RI1R_RTR ((uint32_t)0x00000002)
2749 #define CAN_RI1R_IDE ((uint32_t)0x00000004)
2750 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8)
2751 #define CAN_RI1R_STID ((uint32_t)0xFFE00000)
2753 /******************* Bit definition for CAN_RDT1R register ******************/
2754 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F)
2755 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00)
2756 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000)
2758 /******************* Bit definition for CAN_RDL1R register ******************/
2759 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF)
2760 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00)
2761 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000)
2762 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000)
2764 /******************* Bit definition for CAN_RDH1R register ******************/
2765 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF)
2766 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00)
2767 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000)
2768 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000)
2771 /******************* Bit definition for CAN_FMR register ********************/
2772 #define CAN_FMR_FINIT ((uint8_t)0x01)
2774 /******************* Bit definition for CAN_FM1R register *******************/
2775 #define CAN_FM1R_FBM ((uint16_t)0x3FFF)
2776 #define CAN_FM1R_FBM0 ((uint16_t)0x0001)
2777 #define CAN_FM1R_FBM1 ((uint16_t)0x0002)
2778 #define CAN_FM1R_FBM2 ((uint16_t)0x0004)
2779 #define CAN_FM1R_FBM3 ((uint16_t)0x0008)
2780 #define CAN_FM1R_FBM4 ((uint16_t)0x0010)
2781 #define CAN_FM1R_FBM5 ((uint16_t)0x0020)
2782 #define CAN_FM1R_FBM6 ((uint16_t)0x0040)
2783 #define CAN_FM1R_FBM7 ((uint16_t)0x0080)
2784 #define CAN_FM1R_FBM8 ((uint16_t)0x0100)
2785 #define CAN_FM1R_FBM9 ((uint16_t)0x0200)
2786 #define CAN_FM1R_FBM10 ((uint16_t)0x0400)
2787 #define CAN_FM1R_FBM11 ((uint16_t)0x0800)
2788 #define CAN_FM1R_FBM12 ((uint16_t)0x1000)
2789 #define CAN_FM1R_FBM13 ((uint16_t)0x2000)
2791 /******************* Bit definition for CAN_FS1R register *******************/
2792 #define CAN_FS1R_FSC ((uint16_t)0x3FFF)
2793 #define CAN_FS1R_FSC0 ((uint16_t)0x0001)
2794 #define CAN_FS1R_FSC1 ((uint16_t)0x0002)
2795 #define CAN_FS1R_FSC2 ((uint16_t)0x0004)
2796 #define CAN_FS1R_FSC3 ((uint16_t)0x0008)
2797 #define CAN_FS1R_FSC4 ((uint16_t)0x0010)
2798 #define CAN_FS1R_FSC5 ((uint16_t)0x0020)
2799 #define CAN_FS1R_FSC6 ((uint16_t)0x0040)
2800 #define CAN_FS1R_FSC7 ((uint16_t)0x0080)
2801 #define CAN_FS1R_FSC8 ((uint16_t)0x0100)
2802 #define CAN_FS1R_FSC9 ((uint16_t)0x0200)
2803 #define CAN_FS1R_FSC10 ((uint16_t)0x0400)
2804 #define CAN_FS1R_FSC11 ((uint16_t)0x0800)
2805 #define CAN_FS1R_FSC12 ((uint16_t)0x1000)
2806 #define CAN_FS1R_FSC13 ((uint16_t)0x2000)
2808 /****************** Bit definition for CAN_FFA1R register *******************/
2809 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF)
2810 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001)
2811 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002)
2812 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004)
2813 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008)
2814 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010)
2815 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020)
2816 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040)
2817 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080)
2818 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100)
2819 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200)
2820 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400)
2821 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800)
2822 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000)
2823 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000)
2825 /******************* Bit definition for CAN_FA1R register *******************/
2826 #define CAN_FA1R_FACT ((uint16_t)0x3FFF)
2827 #define CAN_FA1R_FACT0 ((uint16_t)0x0001)
2828 #define CAN_FA1R_FACT1 ((uint16_t)0x0002)
2829 #define CAN_FA1R_FACT2 ((uint16_t)0x0004)
2830 #define CAN_FA1R_FACT3 ((uint16_t)0x0008)
2831 #define CAN_FA1R_FACT4 ((uint16_t)0x0010)
2832 #define CAN_FA1R_FACT5 ((uint16_t)0x0020)
2833 #define CAN_FA1R_FACT6 ((uint16_t)0x0040)
2834 #define CAN_FA1R_FACT7 ((uint16_t)0x0080)
2835 #define CAN_FA1R_FACT8 ((uint16_t)0x0100)
2836 #define CAN_FA1R_FACT9 ((uint16_t)0x0200)
2837 #define CAN_FA1R_FACT10 ((uint16_t)0x0400)
2838 #define CAN_FA1R_FACT11 ((uint16_t)0x0800)
2839 #define CAN_FA1R_FACT12 ((uint16_t)0x1000)
2840 #define CAN_FA1R_FACT13 ((uint16_t)0x2000)
2842 /******************* Bit definition for CAN_F0R1 register *******************/
2843 #define CAN_F0R1_FB0 ((uint32_t)0x00000001)
2844 #define CAN_F0R1_FB1 ((uint32_t)0x00000002)
2845 #define CAN_F0R1_FB2 ((uint32_t)0x00000004)
2846 #define CAN_F0R1_FB3 ((uint32_t)0x00000008)
2847 #define CAN_F0R1_FB4 ((uint32_t)0x00000010)
2848 #define CAN_F0R1_FB5 ((uint32_t)0x00000020)
2849 #define CAN_F0R1_FB6 ((uint32_t)0x00000040)
2850 #define CAN_F0R1_FB7 ((uint32_t)0x00000080)
2851 #define CAN_F0R1_FB8 ((uint32_t)0x00000100)
2852 #define CAN_F0R1_FB9 ((uint32_t)0x00000200)
2853 #define CAN_F0R1_FB10 ((uint32_t)0x00000400)
2854 #define CAN_F0R1_FB11 ((uint32_t)0x00000800)
2855 #define CAN_F0R1_FB12 ((uint32_t)0x00001000)
2856 #define CAN_F0R1_FB13 ((uint32_t)0x00002000)
2857 #define CAN_F0R1_FB14 ((uint32_t)0x00004000)
2858 #define CAN_F0R1_FB15 ((uint32_t)0x00008000)
2859 #define CAN_F0R1_FB16 ((uint32_t)0x00010000)
2860 #define CAN_F0R1_FB17 ((uint32_t)0x00020000)
2861 #define CAN_F0R1_FB18 ((uint32_t)0x00040000)
2862 #define CAN_F0R1_FB19 ((uint32_t)0x00080000)
2863 #define CAN_F0R1_FB20 ((uint32_t)0x00100000)
2864 #define CAN_F0R1_FB21 ((uint32_t)0x00200000)
2865 #define CAN_F0R1_FB22 ((uint32_t)0x00400000)
2866 #define CAN_F0R1_FB23 ((uint32_t)0x00800000)
2867 #define CAN_F0R1_FB24 ((uint32_t)0x01000000)
2868 #define CAN_F0R1_FB25 ((uint32_t)0x02000000)
2869 #define CAN_F0R1_FB26 ((uint32_t)0x04000000)
2870 #define CAN_F0R1_FB27 ((uint32_t)0x08000000)
2871 #define CAN_F0R1_FB28 ((uint32_t)0x10000000)
2872 #define CAN_F0R1_FB29 ((uint32_t)0x20000000)
2873 #define CAN_F0R1_FB30 ((uint32_t)0x40000000)
2874 #define CAN_F0R1_FB31 ((uint32_t)0x80000000)
2876 /******************* Bit definition for CAN_F1R1 register *******************/
2877 #define CAN_F1R1_FB0 ((uint32_t)0x00000001)
2878 #define CAN_F1R1_FB1 ((uint32_t)0x00000002)
2879 #define CAN_F1R1_FB2 ((uint32_t)0x00000004)
2880 #define CAN_F1R1_FB3 ((uint32_t)0x00000008)
2881 #define CAN_F1R1_FB4 ((uint32_t)0x00000010)
2882 #define CAN_F1R1_FB5 ((uint32_t)0x00000020)
2883 #define CAN_F1R1_FB6 ((uint32_t)0x00000040)
2884 #define CAN_F1R1_FB7 ((uint32_t)0x00000080)
2885 #define CAN_F1R1_FB8 ((uint32_t)0x00000100)
2886 #define CAN_F1R1_FB9 ((uint32_t)0x00000200)
2887 #define CAN_F1R1_FB10 ((uint32_t)0x00000400)
2888 #define CAN_F1R1_FB11 ((uint32_t)0x00000800)
2889 #define CAN_F1R1_FB12 ((uint32_t)0x00001000)
2890 #define CAN_F1R1_FB13 ((uint32_t)0x00002000)
2891 #define CAN_F1R1_FB14 ((uint32_t)0x00004000)
2892 #define CAN_F1R1_FB15 ((uint32_t)0x00008000)
2893 #define CAN_F1R1_FB16 ((uint32_t)0x00010000)
2894 #define CAN_F1R1_FB17 ((uint32_t)0x00020000)
2895 #define CAN_F1R1_FB18 ((uint32_t)0x00040000)
2896 #define CAN_F1R1_FB19 ((uint32_t)0x00080000)
2897 #define CAN_F1R1_FB20 ((uint32_t)0x00100000)
2898 #define CAN_F1R1_FB21 ((uint32_t)0x00200000)
2899 #define CAN_F1R1_FB22 ((uint32_t)0x00400000)
2900 #define CAN_F1R1_FB23 ((uint32_t)0x00800000)
2901 #define CAN_F1R1_FB24 ((uint32_t)0x01000000)
2902 #define CAN_F1R1_FB25 ((uint32_t)0x02000000)
2903 #define CAN_F1R1_FB26 ((uint32_t)0x04000000)
2904 #define CAN_F1R1_FB27 ((uint32_t)0x08000000)
2905 #define CAN_F1R1_FB28 ((uint32_t)0x10000000)
2906 #define CAN_F1R1_FB29 ((uint32_t)0x20000000)
2907 #define CAN_F1R1_FB30 ((uint32_t)0x40000000)
2908 #define CAN_F1R1_FB31 ((uint32_t)0x80000000)
2910 /******************* Bit definition for CAN_F2R1 register *******************/
2911 #define CAN_F2R1_FB0 ((uint32_t)0x00000001)
2912 #define CAN_F2R1_FB1 ((uint32_t)0x00000002)
2913 #define CAN_F2R1_FB2 ((uint32_t)0x00000004)
2914 #define CAN_F2R1_FB3 ((uint32_t)0x00000008)
2915 #define CAN_F2R1_FB4 ((uint32_t)0x00000010)
2916 #define CAN_F2R1_FB5 ((uint32_t)0x00000020)
2917 #define CAN_F2R1_FB6 ((uint32_t)0x00000040)
2918 #define CAN_F2R1_FB7 ((uint32_t)0x00000080)
2919 #define CAN_F2R1_FB8 ((uint32_t)0x00000100)
2920 #define CAN_F2R1_FB9 ((uint32_t)0x00000200)
2921 #define CAN_F2R1_FB10 ((uint32_t)0x00000400)
2922 #define CAN_F2R1_FB11 ((uint32_t)0x00000800)
2923 #define CAN_F2R1_FB12 ((uint32_t)0x00001000)
2924 #define CAN_F2R1_FB13 ((uint32_t)0x00002000)
2925 #define CAN_F2R1_FB14 ((uint32_t)0x00004000)
2926 #define CAN_F2R1_FB15 ((uint32_t)0x00008000)
2927 #define CAN_F2R1_FB16 ((uint32_t)0x00010000)
2928 #define CAN_F2R1_FB17 ((uint32_t)0x00020000)
2929 #define CAN_F2R1_FB18 ((uint32_t)0x00040000)
2930 #define CAN_F2R1_FB19 ((uint32_t)0x00080000)
2931 #define CAN_F2R1_FB20 ((uint32_t)0x00100000)
2932 #define CAN_F2R1_FB21 ((uint32_t)0x00200000)
2933 #define CAN_F2R1_FB22 ((uint32_t)0x00400000)
2934 #define CAN_F2R1_FB23 ((uint32_t)0x00800000)
2935 #define CAN_F2R1_FB24 ((uint32_t)0x01000000)
2936 #define CAN_F2R1_FB25 ((uint32_t)0x02000000)
2937 #define CAN_F2R1_FB26 ((uint32_t)0x04000000)
2938 #define CAN_F2R1_FB27 ((uint32_t)0x08000000)
2939 #define CAN_F2R1_FB28 ((uint32_t)0x10000000)
2940 #define CAN_F2R1_FB29 ((uint32_t)0x20000000)
2941 #define CAN_F2R1_FB30 ((uint32_t)0x40000000)
2942 #define CAN_F2R1_FB31 ((uint32_t)0x80000000)
2944 /******************* Bit definition for CAN_F3R1 register *******************/
2945 #define CAN_F3R1_FB0 ((uint32_t)0x00000001)
2946 #define CAN_F3R1_FB1 ((uint32_t)0x00000002)
2947 #define CAN_F3R1_FB2 ((uint32_t)0x00000004)
2948 #define CAN_F3R1_FB3 ((uint32_t)0x00000008)
2949 #define CAN_F3R1_FB4 ((uint32_t)0x00000010)
2950 #define CAN_F3R1_FB5 ((uint32_t)0x00000020)
2951 #define CAN_F3R1_FB6 ((uint32_t)0x00000040)
2952 #define CAN_F3R1_FB7 ((uint32_t)0x00000080)
2953 #define CAN_F3R1_FB8 ((uint32_t)0x00000100)
2954 #define CAN_F3R1_FB9 ((uint32_t)0x00000200)
2955 #define CAN_F3R1_FB10 ((uint32_t)0x00000400)
2956 #define CAN_F3R1_FB11 ((uint32_t)0x00000800)
2957 #define CAN_F3R1_FB12 ((uint32_t)0x00001000)
2958 #define CAN_F3R1_FB13 ((uint32_t)0x00002000)
2959 #define CAN_F3R1_FB14 ((uint32_t)0x00004000)
2960 #define CAN_F3R1_FB15 ((uint32_t)0x00008000)
2961 #define CAN_F3R1_FB16 ((uint32_t)0x00010000)
2962 #define CAN_F3R1_FB17 ((uint32_t)0x00020000)
2963 #define CAN_F3R1_FB18 ((uint32_t)0x00040000)
2964 #define CAN_F3R1_FB19 ((uint32_t)0x00080000)
2965 #define CAN_F3R1_FB20 ((uint32_t)0x00100000)
2966 #define CAN_F3R1_FB21 ((uint32_t)0x00200000)
2967 #define CAN_F3R1_FB22 ((uint32_t)0x00400000)
2968 #define CAN_F3R1_FB23 ((uint32_t)0x00800000)
2969 #define CAN_F3R1_FB24 ((uint32_t)0x01000000)
2970 #define CAN_F3R1_FB25 ((uint32_t)0x02000000)
2971 #define CAN_F3R1_FB26 ((uint32_t)0x04000000)
2972 #define CAN_F3R1_FB27 ((uint32_t)0x08000000)
2973 #define CAN_F3R1_FB28 ((uint32_t)0x10000000)
2974 #define CAN_F3R1_FB29 ((uint32_t)0x20000000)
2975 #define CAN_F3R1_FB30 ((uint32_t)0x40000000)
2976 #define CAN_F3R1_FB31 ((uint32_t)0x80000000)
2978 /******************* Bit definition for CAN_F4R1 register *******************/
2979 #define CAN_F4R1_FB0 ((uint32_t)0x00000001)
2980 #define CAN_F4R1_FB1 ((uint32_t)0x00000002)
2981 #define CAN_F4R1_FB2 ((uint32_t)0x00000004)
2982 #define CAN_F4R1_FB3 ((uint32_t)0x00000008)
2983 #define CAN_F4R1_FB4 ((uint32_t)0x00000010)
2984 #define CAN_F4R1_FB5 ((uint32_t)0x00000020)
2985 #define CAN_F4R1_FB6 ((uint32_t)0x00000040)
2986 #define CAN_F4R1_FB7 ((uint32_t)0x00000080)
2987 #define CAN_F4R1_FB8 ((uint32_t)0x00000100)
2988 #define CAN_F4R1_FB9 ((uint32_t)0x00000200)
2989 #define CAN_F4R1_FB10 ((uint32_t)0x00000400)
2990 #define CAN_F4R1_FB11 ((uint32_t)0x00000800)
2991 #define CAN_F4R1_FB12 ((uint32_t)0x00001000)
2992 #define CAN_F4R1_FB13 ((uint32_t)0x00002000)
2993 #define CAN_F4R1_FB14 ((uint32_t)0x00004000)
2994 #define CAN_F4R1_FB15 ((uint32_t)0x00008000)
2995 #define CAN_F4R1_FB16 ((uint32_t)0x00010000)
2996 #define CAN_F4R1_FB17 ((uint32_t)0x00020000)
2997 #define CAN_F4R1_FB18 ((uint32_t)0x00040000)
2998 #define CAN_F4R1_FB19 ((uint32_t)0x00080000)
2999 #define CAN_F4R1_FB20 ((uint32_t)0x00100000)
3000 #define CAN_F4R1_FB21 ((uint32_t)0x00200000)
3001 #define CAN_F4R1_FB22 ((uint32_t)0x00400000)
3002 #define CAN_F4R1_FB23 ((uint32_t)0x00800000)
3003 #define CAN_F4R1_FB24 ((uint32_t)0x01000000)
3004 #define CAN_F4R1_FB25 ((uint32_t)0x02000000)
3005 #define CAN_F4R1_FB26 ((uint32_t)0x04000000)
3006 #define CAN_F4R1_FB27 ((uint32_t)0x08000000)
3007 #define CAN_F4R1_FB28 ((uint32_t)0x10000000)
3008 #define CAN_F4R1_FB29 ((uint32_t)0x20000000)
3009 #define CAN_F4R1_FB30 ((uint32_t)0x40000000)
3010 #define CAN_F4R1_FB31 ((uint32_t)0x80000000)
3012 /******************* Bit definition for CAN_F5R1 register *******************/
3013 #define CAN_F5R1_FB0 ((uint32_t)0x00000001)
3014 #define CAN_F5R1_FB1 ((uint32_t)0x00000002)
3015 #define CAN_F5R1_FB2 ((uint32_t)0x00000004)
3016 #define CAN_F5R1_FB3 ((uint32_t)0x00000008)
3017 #define CAN_F5R1_FB4 ((uint32_t)0x00000010)
3018 #define CAN_F5R1_FB5 ((uint32_t)0x00000020)
3019 #define CAN_F5R1_FB6 ((uint32_t)0x00000040)
3020 #define CAN_F5R1_FB7 ((uint32_t)0x00000080)
3021 #define CAN_F5R1_FB8 ((uint32_t)0x00000100)
3022 #define CAN_F5R1_FB9 ((uint32_t)0x00000200)
3023 #define CAN_F5R1_FB10 ((uint32_t)0x00000400)
3024 #define CAN_F5R1_FB11 ((uint32_t)0x00000800)
3025 #define CAN_F5R1_FB12 ((uint32_t)0x00001000)
3026 #define CAN_F5R1_FB13 ((uint32_t)0x00002000)
3027 #define CAN_F5R1_FB14 ((uint32_t)0x00004000)
3028 #define CAN_F5R1_FB15 ((uint32_t)0x00008000)
3029 #define CAN_F5R1_FB16 ((uint32_t)0x00010000)
3030 #define CAN_F5R1_FB17 ((uint32_t)0x00020000)
3031 #define CAN_F5R1_FB18 ((uint32_t)0x00040000)
3032 #define CAN_F5R1_FB19 ((uint32_t)0x00080000)
3033 #define CAN_F5R1_FB20 ((uint32_t)0x00100000)
3034 #define CAN_F5R1_FB21 ((uint32_t)0x00200000)
3035 #define CAN_F5R1_FB22 ((uint32_t)0x00400000)
3036 #define CAN_F5R1_FB23 ((uint32_t)0x00800000)
3037 #define CAN_F5R1_FB24 ((uint32_t)0x01000000)
3038 #define CAN_F5R1_FB25 ((uint32_t)0x02000000)
3039 #define CAN_F5R1_FB26 ((uint32_t)0x04000000)
3040 #define CAN_F5R1_FB27 ((uint32_t)0x08000000)
3041 #define CAN_F5R1_FB28 ((uint32_t)0x10000000)
3042 #define CAN_F5R1_FB29 ((uint32_t)0x20000000)
3043 #define CAN_F5R1_FB30 ((uint32_t)0x40000000)
3044 #define CAN_F5R1_FB31 ((uint32_t)0x80000000)
3046 /******************* Bit definition for CAN_F6R1 register *******************/
3047 #define CAN_F6R1_FB0 ((uint32_t)0x00000001)
3048 #define CAN_F6R1_FB1 ((uint32_t)0x00000002)
3049 #define CAN_F6R1_FB2 ((uint32_t)0x00000004)
3050 #define CAN_F6R1_FB3 ((uint32_t)0x00000008)
3051 #define CAN_F6R1_FB4 ((uint32_t)0x00000010)
3052 #define CAN_F6R1_FB5 ((uint32_t)0x00000020)
3053 #define CAN_F6R1_FB6 ((uint32_t)0x00000040)
3054 #define CAN_F6R1_FB7 ((uint32_t)0x00000080)
3055 #define CAN_F6R1_FB8 ((uint32_t)0x00000100)
3056 #define CAN_F6R1_FB9 ((uint32_t)0x00000200)
3057 #define CAN_F6R1_FB10 ((uint32_t)0x00000400)
3058 #define CAN_F6R1_FB11 ((uint32_t)0x00000800)
3059 #define CAN_F6R1_FB12 ((uint32_t)0x00001000)
3060 #define CAN_F6R1_FB13 ((uint32_t)0x00002000)
3061 #define CAN_F6R1_FB14 ((uint32_t)0x00004000)
3062 #define CAN_F6R1_FB15 ((uint32_t)0x00008000)
3063 #define CAN_F6R1_FB16 ((uint32_t)0x00010000)
3064 #define CAN_F6R1_FB17 ((uint32_t)0x00020000)
3065 #define CAN_F6R1_FB18 ((uint32_t)0x00040000)
3066 #define CAN_F6R1_FB19 ((uint32_t)0x00080000)
3067 #define CAN_F6R1_FB20 ((uint32_t)0x00100000)
3068 #define CAN_F6R1_FB21 ((uint32_t)0x00200000)
3069 #define CAN_F6R1_FB22 ((uint32_t)0x00400000)
3070 #define CAN_F6R1_FB23 ((uint32_t)0x00800000)
3071 #define CAN_F6R1_FB24 ((uint32_t)0x01000000)
3072 #define CAN_F6R1_FB25 ((uint32_t)0x02000000)
3073 #define CAN_F6R1_FB26 ((uint32_t)0x04000000)
3074 #define CAN_F6R1_FB27 ((uint32_t)0x08000000)
3075 #define CAN_F6R1_FB28 ((uint32_t)0x10000000)
3076 #define CAN_F6R1_FB29 ((uint32_t)0x20000000)
3077 #define CAN_F6R1_FB30 ((uint32_t)0x40000000)
3078 #define CAN_F6R1_FB31 ((uint32_t)0x80000000)
3080 /******************* Bit definition for CAN_F7R1 register *******************/
3081 #define CAN_F7R1_FB0 ((uint32_t)0x00000001)
3082 #define CAN_F7R1_FB1 ((uint32_t)0x00000002)
3083 #define CAN_F7R1_FB2 ((uint32_t)0x00000004)
3084 #define CAN_F7R1_FB3 ((uint32_t)0x00000008)
3085 #define CAN_F7R1_FB4 ((uint32_t)0x00000010)
3086 #define CAN_F7R1_FB5 ((uint32_t)0x00000020)
3087 #define CAN_F7R1_FB6 ((uint32_t)0x00000040)
3088 #define CAN_F7R1_FB7 ((uint32_t)0x00000080)
3089 #define CAN_F7R1_FB8 ((uint32_t)0x00000100)
3090 #define CAN_F7R1_FB9 ((uint32_t)0x00000200)
3091 #define CAN_F7R1_FB10 ((uint32_t)0x00000400)
3092 #define CAN_F7R1_FB11 ((uint32_t)0x00000800)
3093 #define CAN_F7R1_FB12 ((uint32_t)0x00001000)
3094 #define CAN_F7R1_FB13 ((uint32_t)0x00002000)
3095 #define CAN_F7R1_FB14 ((uint32_t)0x00004000)
3096 #define CAN_F7R1_FB15 ((uint32_t)0x00008000)
3097 #define CAN_F7R1_FB16 ((uint32_t)0x00010000)
3098 #define CAN_F7R1_FB17 ((uint32_t)0x00020000)
3099 #define CAN_F7R1_FB18 ((uint32_t)0x00040000)
3100 #define CAN_F7R1_FB19 ((uint32_t)0x00080000)
3101 #define CAN_F7R1_FB20 ((uint32_t)0x00100000)
3102 #define CAN_F7R1_FB21 ((uint32_t)0x00200000)
3103 #define CAN_F7R1_FB22 ((uint32_t)0x00400000)
3104 #define CAN_F7R1_FB23 ((uint32_t)0x00800000)
3105 #define CAN_F7R1_FB24 ((uint32_t)0x01000000)
3106 #define CAN_F7R1_FB25 ((uint32_t)0x02000000)
3107 #define CAN_F7R1_FB26 ((uint32_t)0x04000000)
3108 #define CAN_F7R1_FB27 ((uint32_t)0x08000000)
3109 #define CAN_F7R1_FB28 ((uint32_t)0x10000000)
3110 #define CAN_F7R1_FB29 ((uint32_t)0x20000000)
3111 #define CAN_F7R1_FB30 ((uint32_t)0x40000000)
3112 #define CAN_F7R1_FB31 ((uint32_t)0x80000000)
3114 /******************* Bit definition for CAN_F8R1 register *******************/
3115 #define CAN_F8R1_FB0 ((uint32_t)0x00000001)
3116 #define CAN_F8R1_FB1 ((uint32_t)0x00000002)
3117 #define CAN_F8R1_FB2 ((uint32_t)0x00000004)
3118 #define CAN_F8R1_FB3 ((uint32_t)0x00000008)
3119 #define CAN_F8R1_FB4 ((uint32_t)0x00000010)
3120 #define CAN_F8R1_FB5 ((uint32_t)0x00000020)
3121 #define CAN_F8R1_FB6 ((uint32_t)0x00000040)
3122 #define CAN_F8R1_FB7 ((uint32_t)0x00000080)
3123 #define CAN_F8R1_FB8 ((uint32_t)0x00000100)
3124 #define CAN_F8R1_FB9 ((uint32_t)0x00000200)
3125 #define CAN_F8R1_FB10 ((uint32_t)0x00000400)
3126 #define CAN_F8R1_FB11 ((uint32_t)0x00000800)
3127 #define CAN_F8R1_FB12 ((uint32_t)0x00001000)
3128 #define CAN_F8R1_FB13 ((uint32_t)0x00002000)
3129 #define CAN_F8R1_FB14 ((uint32_t)0x00004000)
3130 #define CAN_F8R1_FB15 ((uint32_t)0x00008000)
3131 #define CAN_F8R1_FB16 ((uint32_t)0x00010000)
3132 #define CAN_F8R1_FB17 ((uint32_t)0x00020000)
3133 #define CAN_F8R1_FB18 ((uint32_t)0x00040000)
3134 #define CAN_F8R1_FB19 ((uint32_t)0x00080000)
3135 #define CAN_F8R1_FB20 ((uint32_t)0x00100000)
3136 #define CAN_F8R1_FB21 ((uint32_t)0x00200000)
3137 #define CAN_F8R1_FB22 ((uint32_t)0x00400000)
3138 #define CAN_F8R1_FB23 ((uint32_t)0x00800000)
3139 #define CAN_F8R1_FB24 ((uint32_t)0x01000000)
3140 #define CAN_F8R1_FB25 ((uint32_t)0x02000000)
3141 #define CAN_F8R1_FB26 ((uint32_t)0x04000000)
3142 #define CAN_F8R1_FB27 ((uint32_t)0x08000000)
3143 #define CAN_F8R1_FB28 ((uint32_t)0x10000000)
3144 #define CAN_F8R1_FB29 ((uint32_t)0x20000000)
3145 #define CAN_F8R1_FB30 ((uint32_t)0x40000000)
3146 #define CAN_F8R1_FB31 ((uint32_t)0x80000000)
3148 /******************* Bit definition for CAN_F9R1 register *******************/
3149 #define CAN_F9R1_FB0 ((uint32_t)0x00000001)
3150 #define CAN_F9R1_FB1 ((uint32_t)0x00000002)
3151 #define CAN_F9R1_FB2 ((uint32_t)0x00000004)
3152 #define CAN_F9R1_FB3 ((uint32_t)0x00000008)
3153 #define CAN_F9R1_FB4 ((uint32_t)0x00000010)
3154 #define CAN_F9R1_FB5 ((uint32_t)0x00000020)
3155 #define CAN_F9R1_FB6 ((uint32_t)0x00000040)
3156 #define CAN_F9R1_FB7 ((uint32_t)0x00000080)
3157 #define CAN_F9R1_FB8 ((uint32_t)0x00000100)
3158 #define CAN_F9R1_FB9 ((uint32_t)0x00000200)
3159 #define CAN_F9R1_FB10 ((uint32_t)0x00000400)
3160 #define CAN_F9R1_FB11 ((uint32_t)0x00000800)
3161 #define CAN_F9R1_FB12 ((uint32_t)0x00001000)
3162 #define CAN_F9R1_FB13 ((uint32_t)0x00002000)
3163 #define CAN_F9R1_FB14 ((uint32_t)0x00004000)
3164 #define CAN_F9R1_FB15 ((uint32_t)0x00008000)
3165 #define CAN_F9R1_FB16 ((uint32_t)0x00010000)
3166 #define CAN_F9R1_FB17 ((uint32_t)0x00020000)
3167 #define CAN_F9R1_FB18 ((uint32_t)0x00040000)
3168 #define CAN_F9R1_FB19 ((uint32_t)0x00080000)
3169 #define CAN_F9R1_FB20 ((uint32_t)0x00100000)
3170 #define CAN_F9R1_FB21 ((uint32_t)0x00200000)
3171 #define CAN_F9R1_FB22 ((uint32_t)0x00400000)
3172 #define CAN_F9R1_FB23 ((uint32_t)0x00800000)
3173 #define CAN_F9R1_FB24 ((uint32_t)0x01000000)
3174 #define CAN_F9R1_FB25 ((uint32_t)0x02000000)
3175 #define CAN_F9R1_FB26 ((uint32_t)0x04000000)
3176 #define CAN_F9R1_FB27 ((uint32_t)0x08000000)
3177 #define CAN_F9R1_FB28 ((uint32_t)0x10000000)
3178 #define CAN_F9R1_FB29 ((uint32_t)0x20000000)
3179 #define CAN_F9R1_FB30 ((uint32_t)0x40000000)
3180 #define CAN_F9R1_FB31 ((uint32_t)0x80000000)
3182 /******************* Bit definition for CAN_F10R1 register ******************/
3183 #define CAN_F10R1_FB0 ((uint32_t)0x00000001)
3184 #define CAN_F10R1_FB1 ((uint32_t)0x00000002)
3185 #define CAN_F10R1_FB2 ((uint32_t)0x00000004)
3186 #define CAN_F10R1_FB3 ((uint32_t)0x00000008)
3187 #define CAN_F10R1_FB4 ((uint32_t)0x00000010)
3188 #define CAN_F10R1_FB5 ((uint32_t)0x00000020)
3189 #define CAN_F10R1_FB6 ((uint32_t)0x00000040)
3190 #define CAN_F10R1_FB7 ((uint32_t)0x00000080)
3191 #define CAN_F10R1_FB8 ((uint32_t)0x00000100)
3192 #define CAN_F10R1_FB9 ((uint32_t)0x00000200)
3193 #define CAN_F10R1_FB10 ((uint32_t)0x00000400)
3194 #define CAN_F10R1_FB11 ((uint32_t)0x00000800)
3195 #define CAN_F10R1_FB12 ((uint32_t)0x00001000)
3196 #define CAN_F10R1_FB13 ((uint32_t)0x00002000)
3197 #define CAN_F10R1_FB14 ((uint32_t)0x00004000)
3198 #define CAN_F10R1_FB15 ((uint32_t)0x00008000)
3199 #define CAN_F10R1_FB16 ((uint32_t)0x00010000)
3200 #define CAN_F10R1_FB17 ((uint32_t)0x00020000)
3201 #define CAN_F10R1_FB18 ((uint32_t)0x00040000)
3202 #define CAN_F10R1_FB19 ((uint32_t)0x00080000)
3203 #define CAN_F10R1_FB20 ((uint32_t)0x00100000)
3204 #define CAN_F10R1_FB21 ((uint32_t)0x00200000)
3205 #define CAN_F10R1_FB22 ((uint32_t)0x00400000)
3206 #define CAN_F10R1_FB23 ((uint32_t)0x00800000)
3207 #define CAN_F10R1_FB24 ((uint32_t)0x01000000)
3208 #define CAN_F10R1_FB25 ((uint32_t)0x02000000)
3209 #define CAN_F10R1_FB26 ((uint32_t)0x04000000)
3210 #define CAN_F10R1_FB27 ((uint32_t)0x08000000)
3211 #define CAN_F10R1_FB28 ((uint32_t)0x10000000)
3212 #define CAN_F10R1_FB29 ((uint32_t)0x20000000)
3213 #define CAN_F10R1_FB30 ((uint32_t)0x40000000)
3214 #define CAN_F10R1_FB31 ((uint32_t)0x80000000)
3216 /******************* Bit definition for CAN_F11R1 register ******************/
3217 #define CAN_F11R1_FB0 ((uint32_t)0x00000001)
3218 #define CAN_F11R1_FB1 ((uint32_t)0x00000002)
3219 #define CAN_F11R1_FB2 ((uint32_t)0x00000004)
3220 #define CAN_F11R1_FB3 ((uint32_t)0x00000008)
3221 #define CAN_F11R1_FB4 ((uint32_t)0x00000010)
3222 #define CAN_F11R1_FB5 ((uint32_t)0x00000020)
3223 #define CAN_F11R1_FB6 ((uint32_t)0x00000040)
3224 #define CAN_F11R1_FB7 ((uint32_t)0x00000080)
3225 #define CAN_F11R1_FB8 ((uint32_t)0x00000100)
3226 #define CAN_F11R1_FB9 ((uint32_t)0x00000200)
3227 #define CAN_F11R1_FB10 ((uint32_t)0x00000400)
3228 #define CAN_F11R1_FB11 ((uint32_t)0x00000800)
3229 #define CAN_F11R1_FB12 ((uint32_t)0x00001000)
3230 #define CAN_F11R1_FB13 ((uint32_t)0x00002000)
3231 #define CAN_F11R1_FB14 ((uint32_t)0x00004000)
3232 #define CAN_F11R1_FB15 ((uint32_t)0x00008000)
3233 #define CAN_F11R1_FB16 ((uint32_t)0x00010000)
3234 #define CAN_F11R1_FB17 ((uint32_t)0x00020000)
3235 #define CAN_F11R1_FB18 ((uint32_t)0x00040000)
3236 #define CAN_F11R1_FB19 ((uint32_t)0x00080000)
3237 #define CAN_F11R1_FB20 ((uint32_t)0x00100000)
3238 #define CAN_F11R1_FB21 ((uint32_t)0x00200000)
3239 #define CAN_F11R1_FB22 ((uint32_t)0x00400000)
3240 #define CAN_F11R1_FB23 ((uint32_t)0x00800000)
3241 #define CAN_F11R1_FB24 ((uint32_t)0x01000000)
3242 #define CAN_F11R1_FB25 ((uint32_t)0x02000000)
3243 #define CAN_F11R1_FB26 ((uint32_t)0x04000000)
3244 #define CAN_F11R1_FB27 ((uint32_t)0x08000000)
3245 #define CAN_F11R1_FB28 ((uint32_t)0x10000000)
3246 #define CAN_F11R1_FB29 ((uint32_t)0x20000000)
3247 #define CAN_F11R1_FB30 ((uint32_t)0x40000000)
3248 #define CAN_F11R1_FB31 ((uint32_t)0x80000000)
3250 /******************* Bit definition for CAN_F12R1 register ******************/
3251 #define CAN_F12R1_FB0 ((uint32_t)0x00000001)
3252 #define CAN_F12R1_FB1 ((uint32_t)0x00000002)
3253 #define CAN_F12R1_FB2 ((uint32_t)0x00000004)
3254 #define CAN_F12R1_FB3 ((uint32_t)0x00000008)
3255 #define CAN_F12R1_FB4 ((uint32_t)0x00000010)
3256 #define CAN_F12R1_FB5 ((uint32_t)0x00000020)
3257 #define CAN_F12R1_FB6 ((uint32_t)0x00000040)
3258 #define CAN_F12R1_FB7 ((uint32_t)0x00000080)
3259 #define CAN_F12R1_FB8 ((uint32_t)0x00000100)
3260 #define CAN_F12R1_FB9 ((uint32_t)0x00000200)
3261 #define CAN_F12R1_FB10 ((uint32_t)0x00000400)
3262 #define CAN_F12R1_FB11 ((uint32_t)0x00000800)
3263 #define CAN_F12R1_FB12 ((uint32_t)0x00001000)
3264 #define CAN_F12R1_FB13 ((uint32_t)0x00002000)
3265 #define CAN_F12R1_FB14 ((uint32_t)0x00004000)
3266 #define CAN_F12R1_FB15 ((uint32_t)0x00008000)
3267 #define CAN_F12R1_FB16 ((uint32_t)0x00010000)
3268 #define CAN_F12R1_FB17 ((uint32_t)0x00020000)
3269 #define CAN_F12R1_FB18 ((uint32_t)0x00040000)
3270 #define CAN_F12R1_FB19 ((uint32_t)0x00080000)
3271 #define CAN_F12R1_FB20 ((uint32_t)0x00100000)
3272 #define CAN_F12R1_FB21 ((uint32_t)0x00200000)
3273 #define CAN_F12R1_FB22 ((uint32_t)0x00400000)
3274 #define CAN_F12R1_FB23 ((uint32_t)0x00800000)
3275 #define CAN_F12R1_FB24 ((uint32_t)0x01000000)
3276 #define CAN_F12R1_FB25 ((uint32_t)0x02000000)
3277 #define CAN_F12R1_FB26 ((uint32_t)0x04000000)
3278 #define CAN_F12R1_FB27 ((uint32_t)0x08000000)
3279 #define CAN_F12R1_FB28 ((uint32_t)0x10000000)
3280 #define CAN_F12R1_FB29 ((uint32_t)0x20000000)
3281 #define CAN_F12R1_FB30 ((uint32_t)0x40000000)
3282 #define CAN_F12R1_FB31 ((uint32_t)0x80000000)
3284 /******************* Bit definition for CAN_F13R1 register ******************/
3285 #define CAN_F13R1_FB0 ((uint32_t)0x00000001)
3286 #define CAN_F13R1_FB1 ((uint32_t)0x00000002)
3287 #define CAN_F13R1_FB2 ((uint32_t)0x00000004)
3288 #define CAN_F13R1_FB3 ((uint32_t)0x00000008)
3289 #define CAN_F13R1_FB4 ((uint32_t)0x00000010)
3290 #define CAN_F13R1_FB5 ((uint32_t)0x00000020)
3291 #define CAN_F13R1_FB6 ((uint32_t)0x00000040)
3292 #define CAN_F13R1_FB7 ((uint32_t)0x00000080)
3293 #define CAN_F13R1_FB8 ((uint32_t)0x00000100)
3294 #define CAN_F13R1_FB9 ((uint32_t)0x00000200)
3295 #define CAN_F13R1_FB10 ((uint32_t)0x00000400)
3296 #define CAN_F13R1_FB11 ((uint32_t)0x00000800)
3297 #define CAN_F13R1_FB12 ((uint32_t)0x00001000)
3298 #define CAN_F13R1_FB13 ((uint32_t)0x00002000)
3299 #define CAN_F13R1_FB14 ((uint32_t)0x00004000)
3300 #define CAN_F13R1_FB15 ((uint32_t)0x00008000)
3301 #define CAN_F13R1_FB16 ((uint32_t)0x00010000)
3302 #define CAN_F13R1_FB17 ((uint32_t)0x00020000)
3303 #define CAN_F13R1_FB18 ((uint32_t)0x00040000)
3304 #define CAN_F13R1_FB19 ((uint32_t)0x00080000)
3305 #define CAN_F13R1_FB20 ((uint32_t)0x00100000)
3306 #define CAN_F13R1_FB21 ((uint32_t)0x00200000)
3307 #define CAN_F13R1_FB22 ((uint32_t)0x00400000)
3308 #define CAN_F13R1_FB23 ((uint32_t)0x00800000)
3309 #define CAN_F13R1_FB24 ((uint32_t)0x01000000)
3310 #define CAN_F13R1_FB25 ((uint32_t)0x02000000)
3311 #define CAN_F13R1_FB26 ((uint32_t)0x04000000)
3312 #define CAN_F13R1_FB27 ((uint32_t)0x08000000)
3313 #define CAN_F13R1_FB28 ((uint32_t)0x10000000)
3314 #define CAN_F13R1_FB29 ((uint32_t)0x20000000)
3315 #define CAN_F13R1_FB30 ((uint32_t)0x40000000)
3316 #define CAN_F13R1_FB31 ((uint32_t)0x80000000)
3318 /******************* Bit definition for CAN_F0R2 register *******************/
3319 #define CAN_F0R2_FB0 ((uint32_t)0x00000001)
3320 #define CAN_F0R2_FB1 ((uint32_t)0x00000002)
3321 #define CAN_F0R2_FB2 ((uint32_t)0x00000004)
3322 #define CAN_F0R2_FB3 ((uint32_t)0x00000008)
3323 #define CAN_F0R2_FB4 ((uint32_t)0x00000010)
3324 #define CAN_F0R2_FB5 ((uint32_t)0x00000020)
3325 #define CAN_F0R2_FB6 ((uint32_t)0x00000040)
3326 #define CAN_F0R2_FB7 ((uint32_t)0x00000080)
3327 #define CAN_F0R2_FB8 ((uint32_t)0x00000100)
3328 #define CAN_F0R2_FB9 ((uint32_t)0x00000200)
3329 #define CAN_F0R2_FB10 ((uint32_t)0x00000400)
3330 #define CAN_F0R2_FB11 ((uint32_t)0x00000800)
3331 #define CAN_F0R2_FB12 ((uint32_t)0x00001000)
3332 #define CAN_F0R2_FB13 ((uint32_t)0x00002000)
3333 #define CAN_F0R2_FB14 ((uint32_t)0x00004000)
3334 #define CAN_F0R2_FB15 ((uint32_t)0x00008000)
3335 #define CAN_F0R2_FB16 ((uint32_t)0x00010000)
3336 #define CAN_F0R2_FB17 ((uint32_t)0x00020000)
3337 #define CAN_F0R2_FB18 ((uint32_t)0x00040000)
3338 #define CAN_F0R2_FB19 ((uint32_t)0x00080000)
3339 #define CAN_F0R2_FB20 ((uint32_t)0x00100000)
3340 #define CAN_F0R2_FB21 ((uint32_t)0x00200000)
3341 #define CAN_F0R2_FB22 ((uint32_t)0x00400000)
3342 #define CAN_F0R2_FB23 ((uint32_t)0x00800000)
3343 #define CAN_F0R2_FB24 ((uint32_t)0x01000000)
3344 #define CAN_F0R2_FB25 ((uint32_t)0x02000000)
3345 #define CAN_F0R2_FB26 ((uint32_t)0x04000000)
3346 #define CAN_F0R2_FB27 ((uint32_t)0x08000000)
3347 #define CAN_F0R2_FB28 ((uint32_t)0x10000000)
3348 #define CAN_F0R2_FB29 ((uint32_t)0x20000000)
3349 #define CAN_F0R2_FB30 ((uint32_t)0x40000000)
3350 #define CAN_F0R2_FB31 ((uint32_t)0x80000000)
3352 /******************* Bit definition for CAN_F1R2 register *******************/
3353 #define CAN_F1R2_FB0 ((uint32_t)0x00000001)
3354 #define CAN_F1R2_FB1 ((uint32_t)0x00000002)
3355 #define CAN_F1R2_FB2 ((uint32_t)0x00000004)
3356 #define CAN_F1R2_FB3 ((uint32_t)0x00000008)
3357 #define CAN_F1R2_FB4 ((uint32_t)0x00000010)
3358 #define CAN_F1R2_FB5 ((uint32_t)0x00000020)
3359 #define CAN_F1R2_FB6 ((uint32_t)0x00000040)
3360 #define CAN_F1R2_FB7 ((uint32_t)0x00000080)
3361 #define CAN_F1R2_FB8 ((uint32_t)0x00000100)
3362 #define CAN_F1R2_FB9 ((uint32_t)0x00000200)
3363 #define CAN_F1R2_FB10 ((uint32_t)0x00000400)
3364 #define CAN_F1R2_FB11 ((uint32_t)0x00000800)
3365 #define CAN_F1R2_FB12 ((uint32_t)0x00001000)
3366 #define CAN_F1R2_FB13 ((uint32_t)0x00002000)
3367 #define CAN_F1R2_FB14 ((uint32_t)0x00004000)
3368 #define CAN_F1R2_FB15 ((uint32_t)0x00008000)
3369 #define CAN_F1R2_FB16 ((uint32_t)0x00010000)
3370 #define CAN_F1R2_FB17 ((uint32_t)0x00020000)
3371 #define CAN_F1R2_FB18 ((uint32_t)0x00040000)
3372 #define CAN_F1R2_FB19 ((uint32_t)0x00080000)
3373 #define CAN_F1R2_FB20 ((uint32_t)0x00100000)
3374 #define CAN_F1R2_FB21 ((uint32_t)0x00200000)
3375 #define CAN_F1R2_FB22 ((uint32_t)0x00400000)
3376 #define CAN_F1R2_FB23 ((uint32_t)0x00800000)
3377 #define CAN_F1R2_FB24 ((uint32_t)0x01000000)
3378 #define CAN_F1R2_FB25 ((uint32_t)0x02000000)
3379 #define CAN_F1R2_FB26 ((uint32_t)0x04000000)
3380 #define CAN_F1R2_FB27 ((uint32_t)0x08000000)
3381 #define CAN_F1R2_FB28 ((uint32_t)0x10000000)
3382 #define CAN_F1R2_FB29 ((uint32_t)0x20000000)
3383 #define CAN_F1R2_FB30 ((uint32_t)0x40000000)
3384 #define CAN_F1R2_FB31 ((uint32_t)0x80000000)
3386 /******************* Bit definition for CAN_F2R2 register *******************/
3387 #define CAN_F2R2_FB0 ((uint32_t)0x00000001)
3388 #define CAN_F2R2_FB1 ((uint32_t)0x00000002)
3389 #define CAN_F2R2_FB2 ((uint32_t)0x00000004)
3390 #define CAN_F2R2_FB3 ((uint32_t)0x00000008)
3391 #define CAN_F2R2_FB4 ((uint32_t)0x00000010)
3392 #define CAN_F2R2_FB5 ((uint32_t)0x00000020)
3393 #define CAN_F2R2_FB6 ((uint32_t)0x00000040)
3394 #define CAN_F2R2_FB7 ((uint32_t)0x00000080)
3395 #define CAN_F2R2_FB8 ((uint32_t)0x00000100)
3396 #define CAN_F2R2_FB9 ((uint32_t)0x00000200)
3397 #define CAN_F2R2_FB10 ((uint32_t)0x00000400)
3398 #define CAN_F2R2_FB11 ((uint32_t)0x00000800)
3399 #define CAN_F2R2_FB12 ((uint32_t)0x00001000)
3400 #define CAN_F2R2_FB13 ((uint32_t)0x00002000)
3401 #define CAN_F2R2_FB14 ((uint32_t)0x00004000)
3402 #define CAN_F2R2_FB15 ((uint32_t)0x00008000)
3403 #define CAN_F2R2_FB16 ((uint32_t)0x00010000)
3404 #define CAN_F2R2_FB17 ((uint32_t)0x00020000)
3405 #define CAN_F2R2_FB18 ((uint32_t)0x00040000)
3406 #define CAN_F2R2_FB19 ((uint32_t)0x00080000)
3407 #define CAN_F2R2_FB20 ((uint32_t)0x00100000)
3408 #define CAN_F2R2_FB21 ((uint32_t)0x00200000)
3409 #define CAN_F2R2_FB22 ((uint32_t)0x00400000)
3410 #define CAN_F2R2_FB23 ((uint32_t)0x00800000)
3411 #define CAN_F2R2_FB24 ((uint32_t)0x01000000)
3412 #define CAN_F2R2_FB25 ((uint32_t)0x02000000)
3413 #define CAN_F2R2_FB26 ((uint32_t)0x04000000)
3414 #define CAN_F2R2_FB27 ((uint32_t)0x08000000)
3415 #define CAN_F2R2_FB28 ((uint32_t)0x10000000)
3416 #define CAN_F2R2_FB29 ((uint32_t)0x20000000)
3417 #define CAN_F2R2_FB30 ((uint32_t)0x40000000)
3418 #define CAN_F2R2_FB31 ((uint32_t)0x80000000)
3420 /******************* Bit definition for CAN_F3R2 register *******************/
3421 #define CAN_F3R2_FB0 ((uint32_t)0x00000001)
3422 #define CAN_F3R2_FB1 ((uint32_t)0x00000002)
3423 #define CAN_F3R2_FB2 ((uint32_t)0x00000004)
3424 #define CAN_F3R2_FB3 ((uint32_t)0x00000008)
3425 #define CAN_F3R2_FB4 ((uint32_t)0x00000010)
3426 #define CAN_F3R2_FB5 ((uint32_t)0x00000020)
3427 #define CAN_F3R2_FB6 ((uint32_t)0x00000040)
3428 #define CAN_F3R2_FB7 ((uint32_t)0x00000080)
3429 #define CAN_F3R2_FB8 ((uint32_t)0x00000100)
3430 #define CAN_F3R2_FB9 ((uint32_t)0x00000200)
3431 #define CAN_F3R2_FB10 ((uint32_t)0x00000400)
3432 #define CAN_F3R2_FB11 ((uint32_t)0x00000800)
3433 #define CAN_F3R2_FB12 ((uint32_t)0x00001000)
3434 #define CAN_F3R2_FB13 ((uint32_t)0x00002000)
3435 #define CAN_F3R2_FB14 ((uint32_t)0x00004000)
3436 #define CAN_F3R2_FB15 ((uint32_t)0x00008000)
3437 #define CAN_F3R2_FB16 ((uint32_t)0x00010000)
3438 #define CAN_F3R2_FB17 ((uint32_t)0x00020000)
3439 #define CAN_F3R2_FB18 ((uint32_t)0x00040000)
3440 #define CAN_F3R2_FB19 ((uint32_t)0x00080000)
3441 #define CAN_F3R2_FB20 ((uint32_t)0x00100000)
3442 #define CAN_F3R2_FB21 ((uint32_t)0x00200000)
3443 #define CAN_F3R2_FB22 ((uint32_t)0x00400000)
3444 #define CAN_F3R2_FB23 ((uint32_t)0x00800000)
3445 #define CAN_F3R2_FB24 ((uint32_t)0x01000000)
3446 #define CAN_F3R2_FB25 ((uint32_t)0x02000000)
3447 #define CAN_F3R2_FB26 ((uint32_t)0x04000000)
3448 #define CAN_F3R2_FB27 ((uint32_t)0x08000000)
3449 #define CAN_F3R2_FB28 ((uint32_t)0x10000000)
3450 #define CAN_F3R2_FB29 ((uint32_t)0x20000000)
3451 #define CAN_F3R2_FB30 ((uint32_t)0x40000000)
3452 #define CAN_F3R2_FB31 ((uint32_t)0x80000000)
3454 /******************* Bit definition for CAN_F4R2 register *******************/
3455 #define CAN_F4R2_FB0 ((uint32_t)0x00000001)
3456 #define CAN_F4R2_FB1 ((uint32_t)0x00000002)
3457 #define CAN_F4R2_FB2 ((uint32_t)0x00000004)
3458 #define CAN_F4R2_FB3 ((uint32_t)0x00000008)
3459 #define CAN_F4R2_FB4 ((uint32_t)0x00000010)
3460 #define CAN_F4R2_FB5 ((uint32_t)0x00000020)
3461 #define CAN_F4R2_FB6 ((uint32_t)0x00000040)
3462 #define CAN_F4R2_FB7 ((uint32_t)0x00000080)
3463 #define CAN_F4R2_FB8 ((uint32_t)0x00000100)
3464 #define CAN_F4R2_FB9 ((uint32_t)0x00000200)
3465 #define CAN_F4R2_FB10 ((uint32_t)0x00000400)
3466 #define CAN_F4R2_FB11 ((uint32_t)0x00000800)
3467 #define CAN_F4R2_FB12 ((uint32_t)0x00001000)
3468 #define CAN_F4R2_FB13 ((uint32_t)0x00002000)
3469 #define CAN_F4R2_FB14 ((uint32_t)0x00004000)
3470 #define CAN_F4R2_FB15 ((uint32_t)0x00008000)
3471 #define CAN_F4R2_FB16 ((uint32_t)0x00010000)
3472 #define CAN_F4R2_FB17 ((uint32_t)0x00020000)
3473 #define CAN_F4R2_FB18 ((uint32_t)0x00040000)
3474 #define CAN_F4R2_FB19 ((uint32_t)0x00080000)
3475 #define CAN_F4R2_FB20 ((uint32_t)0x00100000)
3476 #define CAN_F4R2_FB21 ((uint32_t)0x00200000)
3477 #define CAN_F4R2_FB22 ((uint32_t)0x00400000)
3478 #define CAN_F4R2_FB23 ((uint32_t)0x00800000)
3479 #define CAN_F4R2_FB24 ((uint32_t)0x01000000)
3480 #define CAN_F4R2_FB25 ((uint32_t)0x02000000)
3481 #define CAN_F4R2_FB26 ((uint32_t)0x04000000)
3482 #define CAN_F4R2_FB27 ((uint32_t)0x08000000)
3483 #define CAN_F4R2_FB28 ((uint32_t)0x10000000)
3484 #define CAN_F4R2_FB29 ((uint32_t)0x20000000)
3485 #define CAN_F4R2_FB30 ((uint32_t)0x40000000)
3486 #define CAN_F4R2_FB31 ((uint32_t)0x80000000)
3488 /******************* Bit definition for CAN_F5R2 register *******************/
3489 #define CAN_F5R2_FB0 ((uint32_t)0x00000001)
3490 #define CAN_F5R2_FB1 ((uint32_t)0x00000002)
3491 #define CAN_F5R2_FB2 ((uint32_t)0x00000004)
3492 #define CAN_F5R2_FB3 ((uint32_t)0x00000008)
3493 #define CAN_F5R2_FB4 ((uint32_t)0x00000010)
3494 #define CAN_F5R2_FB5 ((uint32_t)0x00000020)
3495 #define CAN_F5R2_FB6 ((uint32_t)0x00000040)
3496 #define CAN_F5R2_FB7 ((uint32_t)0x00000080)
3497 #define CAN_F5R2_FB8 ((uint32_t)0x00000100)
3498 #define CAN_F5R2_FB9 ((uint32_t)0x00000200)
3499 #define CAN_F5R2_FB10 ((uint32_t)0x00000400)
3500 #define CAN_F5R2_FB11 ((uint32_t)0x00000800)
3501 #define CAN_F5R2_FB12 ((uint32_t)0x00001000)
3502 #define CAN_F5R2_FB13 ((uint32_t)0x00002000)
3503 #define CAN_F5R2_FB14 ((uint32_t)0x00004000)
3504 #define CAN_F5R2_FB15 ((uint32_t)0x00008000)
3505 #define CAN_F5R2_FB16 ((uint32_t)0x00010000)
3506 #define CAN_F5R2_FB17 ((uint32_t)0x00020000)
3507 #define CAN_F5R2_FB18 ((uint32_t)0x00040000)
3508 #define CAN_F5R2_FB19 ((uint32_t)0x00080000)
3509 #define CAN_F5R2_FB20 ((uint32_t)0x00100000)
3510 #define CAN_F5R2_FB21 ((uint32_t)0x00200000)
3511 #define CAN_F5R2_FB22 ((uint32_t)0x00400000)
3512 #define CAN_F5R2_FB23 ((uint32_t)0x00800000)
3513 #define CAN_F5R2_FB24 ((uint32_t)0x01000000)
3514 #define CAN_F5R2_FB25 ((uint32_t)0x02000000)
3515 #define CAN_F5R2_FB26 ((uint32_t)0x04000000)
3516 #define CAN_F5R2_FB27 ((uint32_t)0x08000000)
3517 #define CAN_F5R2_FB28 ((uint32_t)0x10000000)
3518 #define CAN_F5R2_FB29 ((uint32_t)0x20000000)
3519 #define CAN_F5R2_FB30 ((uint32_t)0x40000000)
3520 #define CAN_F5R2_FB31 ((uint32_t)0x80000000)
3522 /******************* Bit definition for CAN_F6R2 register *******************/
3523 #define CAN_F6R2_FB0 ((uint32_t)0x00000001)
3524 #define CAN_F6R2_FB1 ((uint32_t)0x00000002)
3525 #define CAN_F6R2_FB2 ((uint32_t)0x00000004)
3526 #define CAN_F6R2_FB3 ((uint32_t)0x00000008)
3527 #define CAN_F6R2_FB4 ((uint32_t)0x00000010)
3528 #define CAN_F6R2_FB5 ((uint32_t)0x00000020)
3529 #define CAN_F6R2_FB6 ((uint32_t)0x00000040)
3530 #define CAN_F6R2_FB7 ((uint32_t)0x00000080)
3531 #define CAN_F6R2_FB8 ((uint32_t)0x00000100)
3532 #define CAN_F6R2_FB9 ((uint32_t)0x00000200)
3533 #define CAN_F6R2_FB10 ((uint32_t)0x00000400)
3534 #define CAN_F6R2_FB11 ((uint32_t)0x00000800)
3535 #define CAN_F6R2_FB12 ((uint32_t)0x00001000)
3536 #define CAN_F6R2_FB13 ((uint32_t)0x00002000)
3537 #define CAN_F6R2_FB14 ((uint32_t)0x00004000)
3538 #define CAN_F6R2_FB15 ((uint32_t)0x00008000)
3539 #define CAN_F6R2_FB16 ((uint32_t)0x00010000)
3540 #define CAN_F6R2_FB17 ((uint32_t)0x00020000)
3541 #define CAN_F6R2_FB18 ((uint32_t)0x00040000)
3542 #define CAN_F6R2_FB19 ((uint32_t)0x00080000)
3543 #define CAN_F6R2_FB20 ((uint32_t)0x00100000)
3544 #define CAN_F6R2_FB21 ((uint32_t)0x00200000)
3545 #define CAN_F6R2_FB22 ((uint32_t)0x00400000)
3546 #define CAN_F6R2_FB23 ((uint32_t)0x00800000)
3547 #define CAN_F6R2_FB24 ((uint32_t)0x01000000)
3548 #define CAN_F6R2_FB25 ((uint32_t)0x02000000)
3549 #define CAN_F6R2_FB26 ((uint32_t)0x04000000)
3550 #define CAN_F6R2_FB27 ((uint32_t)0x08000000)
3551 #define CAN_F6R2_FB28 ((uint32_t)0x10000000)
3552 #define CAN_F6R2_FB29 ((uint32_t)0x20000000)
3553 #define CAN_F6R2_FB30 ((uint32_t)0x40000000)
3554 #define CAN_F6R2_FB31 ((uint32_t)0x80000000)
3556 /******************* Bit definition for CAN_F7R2 register *******************/
3557 #define CAN_F7R2_FB0 ((uint32_t)0x00000001)
3558 #define CAN_F7R2_FB1 ((uint32_t)0x00000002)
3559 #define CAN_F7R2_FB2 ((uint32_t)0x00000004)
3560 #define CAN_F7R2_FB3 ((uint32_t)0x00000008)
3561 #define CAN_F7R2_FB4 ((uint32_t)0x00000010)
3562 #define CAN_F7R2_FB5 ((uint32_t)0x00000020)
3563 #define CAN_F7R2_FB6 ((uint32_t)0x00000040)
3564 #define CAN_F7R2_FB7 ((uint32_t)0x00000080)
3565 #define CAN_F7R2_FB8 ((uint32_t)0x00000100)
3566 #define CAN_F7R2_FB9 ((uint32_t)0x00000200)
3567 #define CAN_F7R2_FB10 ((uint32_t)0x00000400)
3568 #define CAN_F7R2_FB11 ((uint32_t)0x00000800)
3569 #define CAN_F7R2_FB12 ((uint32_t)0x00001000)
3570 #define CAN_F7R2_FB13 ((uint32_t)0x00002000)
3571 #define CAN_F7R2_FB14 ((uint32_t)0x00004000)
3572 #define CAN_F7R2_FB15 ((uint32_t)0x00008000)
3573 #define CAN_F7R2_FB16 ((uint32_t)0x00010000)
3574 #define CAN_F7R2_FB17 ((uint32_t)0x00020000)
3575 #define CAN_F7R2_FB18 ((uint32_t)0x00040000)
3576 #define CAN_F7R2_FB19 ((uint32_t)0x00080000)
3577 #define CAN_F7R2_FB20 ((uint32_t)0x00100000)
3578 #define CAN_F7R2_FB21 ((uint32_t)0x00200000)
3579 #define CAN_F7R2_FB22 ((uint32_t)0x00400000)
3580 #define CAN_F7R2_FB23 ((uint32_t)0x00800000)
3581 #define CAN_F7R2_FB24 ((uint32_t)0x01000000)
3582 #define CAN_F7R2_FB25 ((uint32_t)0x02000000)
3583 #define CAN_F7R2_FB26 ((uint32_t)0x04000000)
3584 #define CAN_F7R2_FB27 ((uint32_t)0x08000000)
3585 #define CAN_F7R2_FB28 ((uint32_t)0x10000000)
3586 #define CAN_F7R2_FB29 ((uint32_t)0x20000000)
3587 #define CAN_F7R2_FB30 ((uint32_t)0x40000000)
3588 #define CAN_F7R2_FB31 ((uint32_t)0x80000000)
3590 /******************* Bit definition for CAN_F8R2 register *******************/
3591 #define CAN_F8R2_FB0 ((uint32_t)0x00000001)
3592 #define CAN_F8R2_FB1 ((uint32_t)0x00000002)
3593 #define CAN_F8R2_FB2 ((uint32_t)0x00000004)
3594 #define CAN_F8R2_FB3 ((uint32_t)0x00000008)
3595 #define CAN_F8R2_FB4 ((uint32_t)0x00000010)
3596 #define CAN_F8R2_FB5 ((uint32_t)0x00000020)
3597 #define CAN_F8R2_FB6 ((uint32_t)0x00000040)
3598 #define CAN_F8R2_FB7 ((uint32_t)0x00000080)
3599 #define CAN_F8R2_FB8 ((uint32_t)0x00000100)
3600 #define CAN_F8R2_FB9 ((uint32_t)0x00000200)
3601 #define CAN_F8R2_FB10 ((uint32_t)0x00000400)
3602 #define CAN_F8R2_FB11 ((uint32_t)0x00000800)
3603 #define CAN_F8R2_FB12 ((uint32_t)0x00001000)
3604 #define CAN_F8R2_FB13 ((uint32_t)0x00002000)
3605 #define CAN_F8R2_FB14 ((uint32_t)0x00004000)
3606 #define CAN_F8R2_FB15 ((uint32_t)0x00008000)
3607 #define CAN_F8R2_FB16 ((uint32_t)0x00010000)
3608 #define CAN_F8R2_FB17 ((uint32_t)0x00020000)
3609 #define CAN_F8R2_FB18 ((uint32_t)0x00040000)
3610 #define CAN_F8R2_FB19 ((uint32_t)0x00080000)
3611 #define CAN_F8R2_FB20 ((uint32_t)0x00100000)
3612 #define CAN_F8R2_FB21 ((uint32_t)0x00200000)
3613 #define CAN_F8R2_FB22 ((uint32_t)0x00400000)
3614 #define CAN_F8R2_FB23 ((uint32_t)0x00800000)
3615 #define CAN_F8R2_FB24 ((uint32_t)0x01000000)
3616 #define CAN_F8R2_FB25 ((uint32_t)0x02000000)
3617 #define CAN_F8R2_FB26 ((uint32_t)0x04000000)
3618 #define CAN_F8R2_FB27 ((uint32_t)0x08000000)
3619 #define CAN_F8R2_FB28 ((uint32_t)0x10000000)
3620 #define CAN_F8R2_FB29 ((uint32_t)0x20000000)
3621 #define CAN_F8R2_FB30 ((uint32_t)0x40000000)
3622 #define CAN_F8R2_FB31 ((uint32_t)0x80000000)
3624 /******************* Bit definition for CAN_F9R2 register *******************/
3625 #define CAN_F9R2_FB0 ((uint32_t)0x00000001)
3626 #define CAN_F9R2_FB1 ((uint32_t)0x00000002)
3627 #define CAN_F9R2_FB2 ((uint32_t)0x00000004)
3628 #define CAN_F9R2_FB3 ((uint32_t)0x00000008)
3629 #define CAN_F9R2_FB4 ((uint32_t)0x00000010)
3630 #define CAN_F9R2_FB5 ((uint32_t)0x00000020)
3631 #define CAN_F9R2_FB6 ((uint32_t)0x00000040)
3632 #define CAN_F9R2_FB7 ((uint32_t)0x00000080)
3633 #define CAN_F9R2_FB8 ((uint32_t)0x00000100)
3634 #define CAN_F9R2_FB9 ((uint32_t)0x00000200)
3635 #define CAN_F9R2_FB10 ((uint32_t)0x00000400)
3636 #define CAN_F9R2_FB11 ((uint32_t)0x00000800)
3637 #define CAN_F9R2_FB12 ((uint32_t)0x00001000)
3638 #define CAN_F9R2_FB13 ((uint32_t)0x00002000)
3639 #define CAN_F9R2_FB14 ((uint32_t)0x00004000)
3640 #define CAN_F9R2_FB15 ((uint32_t)0x00008000)
3641 #define CAN_F9R2_FB16 ((uint32_t)0x00010000)
3642 #define CAN_F9R2_FB17 ((uint32_t)0x00020000)
3643 #define CAN_F9R2_FB18 ((uint32_t)0x00040000)
3644 #define CAN_F9R2_FB19 ((uint32_t)0x00080000)
3645 #define CAN_F9R2_FB20 ((uint32_t)0x00100000)
3646 #define CAN_F9R2_FB21 ((uint32_t)0x00200000)
3647 #define CAN_F9R2_FB22 ((uint32_t)0x00400000)
3648 #define CAN_F9R2_FB23 ((uint32_t)0x00800000)
3649 #define CAN_F9R2_FB24 ((uint32_t)0x01000000)
3650 #define CAN_F9R2_FB25 ((uint32_t)0x02000000)
3651 #define CAN_F9R2_FB26 ((uint32_t)0x04000000)
3652 #define CAN_F9R2_FB27 ((uint32_t)0x08000000)
3653 #define CAN_F9R2_FB28 ((uint32_t)0x10000000)
3654 #define CAN_F9R2_FB29 ((uint32_t)0x20000000)
3655 #define CAN_F9R2_FB30 ((uint32_t)0x40000000)
3656 #define CAN_F9R2_FB31 ((uint32_t)0x80000000)
3658 /******************* Bit definition for CAN_F10R2 register ******************/
3659 #define CAN_F10R2_FB0 ((uint32_t)0x00000001)
3660 #define CAN_F10R2_FB1 ((uint32_t)0x00000002)
3661 #define CAN_F10R2_FB2 ((uint32_t)0x00000004)
3662 #define CAN_F10R2_FB3 ((uint32_t)0x00000008)
3663 #define CAN_F10R2_FB4 ((uint32_t)0x00000010)
3664 #define CAN_F10R2_FB5 ((uint32_t)0x00000020)
3665 #define CAN_F10R2_FB6 ((uint32_t)0x00000040)
3666 #define CAN_F10R2_FB7 ((uint32_t)0x00000080)
3667 #define CAN_F10R2_FB8 ((uint32_t)0x00000100)
3668 #define CAN_F10R2_FB9 ((uint32_t)0x00000200)
3669 #define CAN_F10R2_FB10 ((uint32_t)0x00000400)
3670 #define CAN_F10R2_FB11 ((uint32_t)0x00000800)
3671 #define CAN_F10R2_FB12 ((uint32_t)0x00001000)
3672 #define CAN_F10R2_FB13 ((uint32_t)0x00002000)
3673 #define CAN_F10R2_FB14 ((uint32_t)0x00004000)
3674 #define CAN_F10R2_FB15 ((uint32_t)0x00008000)
3675 #define CAN_F10R2_FB16 ((uint32_t)0x00010000)
3676 #define CAN_F10R2_FB17 ((uint32_t)0x00020000)
3677 #define CAN_F10R2_FB18 ((uint32_t)0x00040000)
3678 #define CAN_F10R2_FB19 ((uint32_t)0x00080000)
3679 #define CAN_F10R2_FB20 ((uint32_t)0x00100000)
3680 #define CAN_F10R2_FB21 ((uint32_t)0x00200000)
3681 #define CAN_F10R2_FB22 ((uint32_t)0x00400000)
3682 #define CAN_F10R2_FB23 ((uint32_t)0x00800000)
3683 #define CAN_F10R2_FB24 ((uint32_t)0x01000000)
3684 #define CAN_F10R2_FB25 ((uint32_t)0x02000000)
3685 #define CAN_F10R2_FB26 ((uint32_t)0x04000000)
3686 #define CAN_F10R2_FB27 ((uint32_t)0x08000000)
3687 #define CAN_F10R2_FB28 ((uint32_t)0x10000000)
3688 #define CAN_F10R2_FB29 ((uint32_t)0x20000000)
3689 #define CAN_F10R2_FB30 ((uint32_t)0x40000000)
3690 #define CAN_F10R2_FB31 ((uint32_t)0x80000000)
3692 /******************* Bit definition for CAN_F11R2 register ******************/
3693 #define CAN_F11R2_FB0 ((uint32_t)0x00000001)
3694 #define CAN_F11R2_FB1 ((uint32_t)0x00000002)
3695 #define CAN_F11R2_FB2 ((uint32_t)0x00000004)
3696 #define CAN_F11R2_FB3 ((uint32_t)0x00000008)
3697 #define CAN_F11R2_FB4 ((uint32_t)0x00000010)
3698 #define CAN_F11R2_FB5 ((uint32_t)0x00000020)
3699 #define CAN_F11R2_FB6 ((uint32_t)0x00000040)
3700 #define CAN_F11R2_FB7 ((uint32_t)0x00000080)
3701 #define CAN_F11R2_FB8 ((uint32_t)0x00000100)
3702 #define CAN_F11R2_FB9 ((uint32_t)0x00000200)
3703 #define CAN_F11R2_FB10 ((uint32_t)0x00000400)
3704 #define CAN_F11R2_FB11 ((uint32_t)0x00000800)
3705 #define CAN_F11R2_FB12 ((uint32_t)0x00001000)
3706 #define CAN_F11R2_FB13 ((uint32_t)0x00002000)
3707 #define CAN_F11R2_FB14 ((uint32_t)0x00004000)
3708 #define CAN_F11R2_FB15 ((uint32_t)0x00008000)
3709 #define CAN_F11R2_FB16 ((uint32_t)0x00010000)
3710 #define CAN_F11R2_FB17 ((uint32_t)0x00020000)
3711 #define CAN_F11R2_FB18 ((uint32_t)0x00040000)
3712 #define CAN_F11R2_FB19 ((uint32_t)0x00080000)
3713 #define CAN_F11R2_FB20 ((uint32_t)0x00100000)
3714 #define CAN_F11R2_FB21 ((uint32_t)0x00200000)
3715 #define CAN_F11R2_FB22 ((uint32_t)0x00400000)
3716 #define CAN_F11R2_FB23 ((uint32_t)0x00800000)
3717 #define CAN_F11R2_FB24 ((uint32_t)0x01000000)
3718 #define CAN_F11R2_FB25 ((uint32_t)0x02000000)
3719 #define CAN_F11R2_FB26 ((uint32_t)0x04000000)
3720 #define CAN_F11R2_FB27 ((uint32_t)0x08000000)
3721 #define CAN_F11R2_FB28 ((uint32_t)0x10000000)
3722 #define CAN_F11R2_FB29 ((uint32_t)0x20000000)
3723 #define CAN_F11R2_FB30 ((uint32_t)0x40000000)
3724 #define CAN_F11R2_FB31 ((uint32_t)0x80000000)
3726 /******************* Bit definition for CAN_F12R2 register ******************/
3727 #define CAN_F12R2_FB0 ((uint32_t)0x00000001)
3728 #define CAN_F12R2_FB1 ((uint32_t)0x00000002)
3729 #define CAN_F12R2_FB2 ((uint32_t)0x00000004)
3730 #define CAN_F12R2_FB3 ((uint32_t)0x00000008)
3731 #define CAN_F12R2_FB4 ((uint32_t)0x00000010)
3732 #define CAN_F12R2_FB5 ((uint32_t)0x00000020)
3733 #define CAN_F12R2_FB6 ((uint32_t)0x00000040)
3734 #define CAN_F12R2_FB7 ((uint32_t)0x00000080)
3735 #define CAN_F12R2_FB8 ((uint32_t)0x00000100)
3736 #define CAN_F12R2_FB9 ((uint32_t)0x00000200)
3737 #define CAN_F12R2_FB10 ((uint32_t)0x00000400)
3738 #define CAN_F12R2_FB11 ((uint32_t)0x00000800)
3739 #define CAN_F12R2_FB12 ((uint32_t)0x00001000)
3740 #define CAN_F12R2_FB13 ((uint32_t)0x00002000)
3741 #define CAN_F12R2_FB14 ((uint32_t)0x00004000)
3742 #define CAN_F12R2_FB15 ((uint32_t)0x00008000)
3743 #define CAN_F12R2_FB16 ((uint32_t)0x00010000)
3744 #define CAN_F12R2_FB17 ((uint32_t)0x00020000)
3745 #define CAN_F12R2_FB18 ((uint32_t)0x00040000)
3746 #define CAN_F12R2_FB19 ((uint32_t)0x00080000)
3747 #define CAN_F12R2_FB20 ((uint32_t)0x00100000)
3748 #define CAN_F12R2_FB21 ((uint32_t)0x00200000)
3749 #define CAN_F12R2_FB22 ((uint32_t)0x00400000)
3750 #define CAN_F12R2_FB23 ((uint32_t)0x00800000)
3751 #define CAN_F12R2_FB24 ((uint32_t)0x01000000)
3752 #define CAN_F12R2_FB25 ((uint32_t)0x02000000)
3753 #define CAN_F12R2_FB26 ((uint32_t)0x04000000)
3754 #define CAN_F12R2_FB27 ((uint32_t)0x08000000)
3755 #define CAN_F12R2_FB28 ((uint32_t)0x10000000)
3756 #define CAN_F12R2_FB29 ((uint32_t)0x20000000)
3757 #define CAN_F12R2_FB30 ((uint32_t)0x40000000)
3758 #define CAN_F12R2_FB31 ((uint32_t)0x80000000)
3760 /******************* Bit definition for CAN_F13R2 register ******************/
3761 #define CAN_F13R2_FB0 ((uint32_t)0x00000001)
3762 #define CAN_F13R2_FB1 ((uint32_t)0x00000002)
3763 #define CAN_F13R2_FB2 ((uint32_t)0x00000004)
3764 #define CAN_F13R2_FB3 ((uint32_t)0x00000008)
3765 #define CAN_F13R2_FB4 ((uint32_t)0x00000010)
3766 #define CAN_F13R2_FB5 ((uint32_t)0x00000020)
3767 #define CAN_F13R2_FB6 ((uint32_t)0x00000040)
3768 #define CAN_F13R2_FB7 ((uint32_t)0x00000080)
3769 #define CAN_F13R2_FB8 ((uint32_t)0x00000100)
3770 #define CAN_F13R2_FB9 ((uint32_t)0x00000200)
3771 #define CAN_F13R2_FB10 ((uint32_t)0x00000400)
3772 #define CAN_F13R2_FB11 ((uint32_t)0x00000800)
3773 #define CAN_F13R2_FB12 ((uint32_t)0x00001000)
3774 #define CAN_F13R2_FB13 ((uint32_t)0x00002000)
3775 #define CAN_F13R2_FB14 ((uint32_t)0x00004000)
3776 #define CAN_F13R2_FB15 ((uint32_t)0x00008000)
3777 #define CAN_F13R2_FB16 ((uint32_t)0x00010000)
3778 #define CAN_F13R2_FB17 ((uint32_t)0x00020000)
3779 #define CAN_F13R2_FB18 ((uint32_t)0x00040000)
3780 #define CAN_F13R2_FB19 ((uint32_t)0x00080000)
3781 #define CAN_F13R2_FB20 ((uint32_t)0x00100000)
3782 #define CAN_F13R2_FB21 ((uint32_t)0x00200000)
3783 #define CAN_F13R2_FB22 ((uint32_t)0x00400000)
3784 #define CAN_F13R2_FB23 ((uint32_t)0x00800000)
3785 #define CAN_F13R2_FB24 ((uint32_t)0x01000000)
3786 #define CAN_F13R2_FB25 ((uint32_t)0x02000000)
3787 #define CAN_F13R2_FB26 ((uint32_t)0x04000000)
3788 #define CAN_F13R2_FB27 ((uint32_t)0x08000000)
3789 #define CAN_F13R2_FB28 ((uint32_t)0x10000000)
3790 #define CAN_F13R2_FB29 ((uint32_t)0x20000000)
3791 #define CAN_F13R2_FB30 ((uint32_t)0x40000000)
3792 #define CAN_F13R2_FB31 ((uint32_t)0x80000000)
3794 #if defined(STM32F446xx)
3795 /******************************************************************************/
3796 /* */
3797 /* HDMI-CEC (CEC) */
3798 /* */
3799 /******************************************************************************/
3800 
3801 /******************* Bit definition for CEC_CR register *********************/
3802 #define CEC_CR_CECEN ((uint32_t)0x00000001)
3803 #define CEC_CR_TXSOM ((uint32_t)0x00000002)
3804 #define CEC_CR_TXEOM ((uint32_t)0x00000004)
3806 /******************* Bit definition for CEC_CFGR register *******************/
3807 #define CEC_CFGR_SFT ((uint32_t)0x00000007)
3808 #define CEC_CFGR_RXTOL ((uint32_t)0x00000008)
3809 #define CEC_CFGR_BRESTP ((uint32_t)0x00000010)
3810 #define CEC_CFGR_BREGEN ((uint32_t)0x00000020)
3811 #define CEC_CFGR_LREGEN ((uint32_t)0x00000040)
3812 #define CEC_CFGR_SFTOPT ((uint32_t)0x00000100)
3813 #define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080)
3814 #define CEC_CFGR_OAR ((uint32_t)0x7FFF0000)
3815 #define CEC_CFGR_LSTN ((uint32_t)0x80000000)
3817 /******************* Bit definition for CEC_TXDR register *******************/
3818 #define CEC_TXDR_TXD ((uint32_t)0x000000FF)
3820 /******************* Bit definition for CEC_RXDR register *******************/
3821 #define CEC_TXDR_RXD ((uint32_t)0x000000FF)
3823 /******************* Bit definition for CEC_ISR register ********************/
3824 #define CEC_ISR_RXBR ((uint32_t)0x00000001)
3825 #define CEC_ISR_RXEND ((uint32_t)0x00000002)
3826 #define CEC_ISR_RXOVR ((uint32_t)0x00000004)
3827 #define CEC_ISR_BRE ((uint32_t)0x00000008)
3828 #define CEC_ISR_SBPE ((uint32_t)0x00000010)
3829 #define CEC_ISR_LBPE ((uint32_t)0x00000020)
3830 #define CEC_ISR_RXACKE ((uint32_t)0x00000040)
3831 #define CEC_ISR_ARBLST ((uint32_t)0x00000080)
3832 #define CEC_ISR_TXBR ((uint32_t)0x00000100)
3833 #define CEC_ISR_TXEND ((uint32_t)0x00000200)
3834 #define CEC_ISR_TXUDR ((uint32_t)0x00000400)
3835 #define CEC_ISR_TXERR ((uint32_t)0x00000800)
3836 #define CEC_ISR_TXACKE ((uint32_t)0x00001000)
3838 /******************* Bit definition for CEC_IER register ********************/
3839 #define CEC_IER_RXBRIE ((uint32_t)0x00000001)
3840 #define CEC_IER_RXENDIE ((uint32_t)0x00000002)
3841 #define CEC_IER_RXOVRIE ((uint32_t)0x00000004)
3842 #define CEC_IER_BREIEIE ((uint32_t)0x00000008)
3843 #define CEC_IER_SBPEIE ((uint32_t)0x00000010)
3844 #define CEC_IER_LBPEIE ((uint32_t)0x00000020)
3845 #define CEC_IER_RXACKEIE ((uint32_t)0x00000040)
3846 #define CEC_IER_ARBLSTIE ((uint32_t)0x00000080)
3847 #define CEC_IER_TXBRIE ((uint32_t)0x00000100)
3848 #define CEC_IER_TXENDIE ((uint32_t)0x00000200)
3849 #define CEC_IER_TXUDRIE ((uint32_t)0x00000400)
3850 #define CEC_IER_TXERRIE ((uint32_t)0x00000800)
3851 #define CEC_IER_TXACKEIE ((uint32_t)0x00001000)
3852 #endif /* STM32F446xx */
3853 
3854 /******************************************************************************/
3855 /* */
3856 /* CRC calculation unit */
3857 /* */
3858 /******************************************************************************/
3859 /******************* Bit definition for CRC_DR register *********************/
3860 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF)
3863 /******************* Bit definition for CRC_IDR register ********************/
3864 #define CRC_IDR_IDR ((uint8_t)0xFF)
3867 /******************** Bit definition for CRC_CR register ********************/
3868 #define CRC_CR_RESET ((uint8_t)0x01)
3870 /******************************************************************************/
3871 /* */
3872 /* Crypto Processor */
3873 /* */
3874 /******************************************************************************/
3875 /******************* Bits definition for CRYP_CR register ********************/
3876 #define CRYP_CR_ALGODIR ((uint32_t)0x00000004)
3877 
3878 #define CRYP_CR_ALGOMODE ((uint32_t)0x00080038)
3879 #define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)
3880 #define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)
3881 #define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)
3882 #define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
3883 #define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)
3884 #define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)
3885 #define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)
3886 #define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)
3887 #define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)
3888 #define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)
3889 #define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)
3890 
3891 #define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)
3892 #define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)
3893 #define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)
3894 #define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)
3895 #define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)
3896 #define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)
3897 #define CRYP_CR_FFLUSH ((uint32_t)0x00004000)
3898 #define CRYP_CR_CRYPEN ((uint32_t)0x00008000)
3899 
3900 #define CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000)
3901 #define CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000)
3902 #define CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000)
3903 #define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
3904 
3905 /****************** Bits definition for CRYP_SR register *********************/
3906 #define CRYP_SR_IFEM ((uint32_t)0x00000001)
3907 #define CRYP_SR_IFNF ((uint32_t)0x00000002)
3908 #define CRYP_SR_OFNE ((uint32_t)0x00000004)
3909 #define CRYP_SR_OFFU ((uint32_t)0x00000008)
3910 #define CRYP_SR_BUSY ((uint32_t)0x00000010)
3911 /****************** Bits definition for CRYP_DMACR register ******************/
3912 #define CRYP_DMACR_DIEN ((uint32_t)0x00000001)
3913 #define CRYP_DMACR_DOEN ((uint32_t)0x00000002)
3914 /***************** Bits definition for CRYP_IMSCR register ******************/
3915 #define CRYP_IMSCR_INIM ((uint32_t)0x00000001)
3916 #define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)
3917 /****************** Bits definition for CRYP_RISR register *******************/
3918 #define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)
3919 #define CRYP_RISR_INRIS ((uint32_t)0x00000002)
3920 /****************** Bits definition for CRYP_MISR register *******************/
3921 #define CRYP_MISR_INMIS ((uint32_t)0x00000001)
3922 #define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)
3923 
3924 /******************************************************************************/
3925 /* */
3926 /* Digital to Analog Converter */
3927 /* */
3928 /******************************************************************************/
3929 /******************** Bit definition for DAC_CR register ********************/
3930 #define DAC_CR_EN1 ((uint32_t)0x00000001)
3931 #define DAC_CR_BOFF1 ((uint32_t)0x00000002)
3932 #define DAC_CR_TEN1 ((uint32_t)0x00000004)
3934 #define DAC_CR_TSEL1 ((uint32_t)0x00000038)
3935 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008)
3936 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010)
3937 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020)
3939 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0)
3940 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040)
3941 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080)
3943 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00)
3944 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100)
3945 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200)
3946 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400)
3947 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800)
3949 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000)
3950 #define DAC_CR_EN2 ((uint32_t)0x00010000)
3951 #define DAC_CR_BOFF2 ((uint32_t)0x00020000)
3952 #define DAC_CR_TEN2 ((uint32_t)0x00040000)
3954 #define DAC_CR_TSEL2 ((uint32_t)0x00380000)
3955 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000)
3956 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000)
3957 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000)
3959 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000)
3960 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000)
3961 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000)
3963 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000)
3964 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000)
3965 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000)
3966 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000)
3967 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000)
3969 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000)
3971 /***************** Bit definition for DAC_SWTRIGR register ******************/
3972 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01)
3973 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02)
3975 /***************** Bit definition for DAC_DHR12R1 register ******************/
3976 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF)
3978 /***************** Bit definition for DAC_DHR12L1 register ******************/
3979 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0)
3981 /****************** Bit definition for DAC_DHR8R1 register ******************/
3982 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF)
3984 /***************** Bit definition for DAC_DHR12R2 register ******************/
3985 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF)
3987 /***************** Bit definition for DAC_DHR12L2 register ******************/
3988 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0)
3990 /****************** Bit definition for DAC_DHR8R2 register ******************/
3991 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF)
3993 /***************** Bit definition for DAC_DHR12RD register ******************/
3994 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF)
3995 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000)
3997 /***************** Bit definition for DAC_DHR12LD register ******************/
3998 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0)
3999 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000)
4001 /****************** Bit definition for DAC_DHR8RD register ******************/
4002 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF)
4003 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00)
4005 /******************* Bit definition for DAC_DOR1 register *******************/
4006 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF)
4008 /******************* Bit definition for DAC_DOR2 register *******************/
4009 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF)
4011 /******************** Bit definition for DAC_SR register ********************/
4012 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000)
4013 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000)
4015 /******************************************************************************/
4016 /* */
4017 /* Debug MCU */
4018 /* */
4019 /******************************************************************************/
4020 
4021 /******************************************************************************/
4022 /* */
4023 /* DCMI */
4024 /* */
4025 /******************************************************************************/
4026 /******************** Bits definition for DCMI_CR register ******************/
4027 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
4028 #define DCMI_CR_CM ((uint32_t)0x00000002)
4029 #define DCMI_CR_CROP ((uint32_t)0x00000004)
4030 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
4031 #define DCMI_CR_ESS ((uint32_t)0x00000010)
4032 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
4033 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
4034 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
4035 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
4036 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
4037 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
4038 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
4039 #define DCMI_CR_CRE ((uint32_t)0x00001000)
4040 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
4041 
4042 /******************** Bits definition for DCMI_SR register ******************/
4043 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
4044 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
4045 #define DCMI_SR_FNE ((uint32_t)0x00000004)
4046 
4047 /******************** Bits definition for DCMI_RISR register ****************/
4048 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
4049 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
4050 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
4051 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
4052 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
4053 
4054 /******************** Bits definition for DCMI_IER register *****************/
4055 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
4056 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
4057 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
4058 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
4059 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
4060 
4061 /******************** Bits definition for DCMI_MISR register ****************/
4062 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
4063 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
4064 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
4065 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
4066 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
4067 
4068 /******************** Bits definition for DCMI_ICR register *****************/
4069 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
4070 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
4071 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
4072 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
4073 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
4074 
4075 /******************************************************************************/
4076 /* */
4077 /* DMA Controller */
4078 /* */
4079 /******************************************************************************/
4080 /******************** Bits definition for DMA_SxCR register *****************/
4081 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
4082 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
4083 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
4084 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
4085 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
4086 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
4087 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
4088 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
4089 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
4090 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
4091 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
4092 #define DMA_SxCR_CT ((uint32_t)0x00080000)
4093 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
4094 #define DMA_SxCR_PL ((uint32_t)0x00030000)
4095 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
4096 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
4097 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
4098 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
4099 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
4100 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
4101 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
4102 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
4103 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
4104 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
4105 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
4106 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
4107 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
4108 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
4109 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
4110 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
4111 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
4112 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
4113 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
4114 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
4115 #define DMA_SxCR_EN ((uint32_t)0x00000001)
4116 
4117 /******************** Bits definition for DMA_SxCNDTR register **************/
4118 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
4119 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
4120 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
4121 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
4122 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
4123 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
4124 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
4125 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
4126 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
4127 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
4128 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
4129 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
4130 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
4131 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
4132 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
4133 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
4134 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
4135 
4136 /******************** Bits definition for DMA_SxFCR register ****************/
4137 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
4138 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
4139 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
4140 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
4141 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
4142 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
4143 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
4144 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
4145 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
4146 
4147 /******************** Bits definition for DMA_LISR register *****************/
4148 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
4149 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
4150 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
4151 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
4152 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
4153 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
4154 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
4155 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
4156 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
4157 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
4158 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
4159 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
4160 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
4161 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
4162 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
4163 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
4164 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
4165 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
4166 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
4167 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
4168 
4169 /******************** Bits definition for DMA_HISR register *****************/
4170 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
4171 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
4172 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
4173 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
4174 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
4175 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
4176 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
4177 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
4178 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
4179 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
4180 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
4181 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
4182 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
4183 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
4184 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
4185 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
4186 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
4187 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
4188 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
4189 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
4190 
4191 /******************** Bits definition for DMA_LIFCR register ****************/
4192 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
4193 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
4194 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
4195 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
4196 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
4197 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
4198 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
4199 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
4200 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
4201 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
4202 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
4203 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
4204 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
4205 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
4206 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
4207 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
4208 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
4209 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
4210 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
4211 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
4212 
4213 /******************** Bits definition for DMA_HIFCR register ****************/
4214 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
4215 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
4216 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
4217 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
4218 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
4219 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
4220 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
4221 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
4222 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
4223 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
4224 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
4225 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
4226 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
4227 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
4228 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
4229 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
4230 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
4231 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
4232 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
4233 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
4234 
4235 /******************************************************************************/
4236 /* */
4237 /* AHB Master DMA2D Controller (DMA2D) */
4238 /* */
4239 /******************************************************************************/
4240 
4241 /******************** Bit definition for DMA2D_CR register ******************/
4242 
4243 #define DMA2D_CR_START ((uint32_t)0x00000001)
4244 #define DMA2D_CR_SUSP ((uint32_t)0x00000002)
4245 #define DMA2D_CR_ABORT ((uint32_t)0x00000004)
4246 #define DMA2D_CR_TEIE ((uint32_t)0x00000100)
4247 #define DMA2D_CR_TCIE ((uint32_t)0x00000200)
4248 #define DMA2D_CR_TWIE ((uint32_t)0x00000400)
4249 #define DMA2D_CR_CAEIE ((uint32_t)0x00000800)
4250 #define DMA2D_CR_CTCIE ((uint32_t)0x00001000)
4251 #define DMA2D_CR_CEIE ((uint32_t)0x00002000)
4252 #define DMA2D_CR_MODE ((uint32_t)0x00030000)
4254 /******************** Bit definition for DMA2D_ISR register *****************/
4255 
4256 #define DMA2D_ISR_TEIF ((uint32_t)0x00000001)
4257 #define DMA2D_ISR_TCIF ((uint32_t)0x00000002)
4258 #define DMA2D_ISR_TWIF ((uint32_t)0x00000004)
4259 #define DMA2D_ISR_CAEIF ((uint32_t)0x00000008)
4260 #define DMA2D_ISR_CTCIF ((uint32_t)0x00000010)
4261 #define DMA2D_ISR_CEIF ((uint32_t)0x00000020)
4263 /******************** Bit definition for DMA2D_IFSR register ****************/
4264 
4265 #define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001)
4266 #define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002)
4267 #define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004)
4268 #define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008)
4269 #define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010)
4270 #define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020)
4272 /******************** Bit definition for DMA2D_FGMAR register ***************/
4273 
4274 #define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF)
4276 /******************** Bit definition for DMA2D_FGOR register ****************/
4277 
4278 #define DMA2D_FGOR_LO ((uint32_t)0x00003FFF)
4280 /******************** Bit definition for DMA2D_BGMAR register ***************/
4281 
4282 #define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF)
4284 /******************** Bit definition for DMA2D_BGOR register ****************/
4285 
4286 #define DMA2D_BGOR_LO ((uint32_t)0x00003FFF)
4288 /******************** Bit definition for DMA2D_FGPFCCR register *************/
4289 
4290 #define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F)
4291 #define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010)
4292 #define DMA2D_FGPFCCR_START ((uint32_t)0x00000020)
4293 #define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00)
4294 #define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000)
4295 #define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000)
4297 /******************** Bit definition for DMA2D_FGCOLR register **************/
4298 
4299 #define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF)
4300 #define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00)
4301 #define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000)
4303 /******************** Bit definition for DMA2D_BGPFCCR register *************/
4304 
4305 #define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F)
4306 #define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010)
4307 #define DMA2D_BGPFCCR_START ((uint32_t)0x00000020)
4308 #define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00)
4309 #define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000)
4310 #define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000)
4312 /******************** Bit definition for DMA2D_BGCOLR register **************/
4313 
4314 #define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF)
4315 #define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00)
4316 #define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000)
4318 /******************** Bit definition for DMA2D_FGCMAR register **************/
4319 
4320 #define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF)
4322 /******************** Bit definition for DMA2D_BGCMAR register **************/
4323 
4324 #define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF)
4326 /******************** Bit definition for DMA2D_OPFCCR register **************/
4327 
4328 #define DMA2D_OPFCCR_CM ((uint32_t)0x00000007)
4330 /******************** Bit definition for DMA2D_OCOLR register ***************/
4331 
4334 #define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF)
4335 #define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00)
4336 #define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000)
4337 #define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000)
4340 #define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F)
4341 #define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0)
4342 #define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800)
4345 #define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F)
4346 #define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0)
4347 #define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00)
4348 #define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000)
4351 #define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F)
4352 #define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0)
4353 #define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00)
4354 #define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000)
4356 /******************** Bit definition for DMA2D_OMAR register ****************/
4357 
4358 #define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF)
4360 /******************** Bit definition for DMA2D_OOR register *****************/
4361 
4362 #define DMA2D_OOR_LO ((uint32_t)0x00003FFF)
4364 /******************** Bit definition for DMA2D_NLR register *****************/
4365 
4366 #define DMA2D_NLR_NL ((uint32_t)0x0000FFFF)
4367 #define DMA2D_NLR_PL ((uint32_t)0x3FFF0000)
4369 /******************** Bit definition for DMA2D_LWR register *****************/
4370 
4371 #define DMA2D_LWR_LW ((uint32_t)0x0000FFFF)
4373 /******************** Bit definition for DMA2D_AMTCR register ***************/
4374 
4375 #define DMA2D_AMTCR_EN ((uint32_t)0x00000001)
4376 #define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00)
4380 /******************** Bit definition for DMA2D_FGCLUT register **************/
4381 
4382 /******************** Bit definition for DMA2D_BGCLUT register **************/
4383 
4384 
4385 /******************************************************************************/
4386 /* */
4387 /* External Interrupt/Event Controller */
4388 /* */
4389 /******************************************************************************/
4390 /******************* Bit definition for EXTI_IMR register *******************/
4391 #define EXTI_IMR_MR0 ((uint32_t)0x00000001)
4392 #define EXTI_IMR_MR1 ((uint32_t)0x00000002)
4393 #define EXTI_IMR_MR2 ((uint32_t)0x00000004)
4394 #define EXTI_IMR_MR3 ((uint32_t)0x00000008)
4395 #define EXTI_IMR_MR4 ((uint32_t)0x00000010)
4396 #define EXTI_IMR_MR5 ((uint32_t)0x00000020)
4397 #define EXTI_IMR_MR6 ((uint32_t)0x00000040)
4398 #define EXTI_IMR_MR7 ((uint32_t)0x00000080)
4399 #define EXTI_IMR_MR8 ((uint32_t)0x00000100)
4400 #define EXTI_IMR_MR9 ((uint32_t)0x00000200)
4401 #define EXTI_IMR_MR10 ((uint32_t)0x00000400)
4402 #define EXTI_IMR_MR11 ((uint32_t)0x00000800)
4403 #define EXTI_IMR_MR12 ((uint32_t)0x00001000)
4404 #define EXTI_IMR_MR13 ((uint32_t)0x00002000)
4405 #define EXTI_IMR_MR14 ((uint32_t)0x00004000)
4406 #define EXTI_IMR_MR15 ((uint32_t)0x00008000)
4407 #define EXTI_IMR_MR16 ((uint32_t)0x00010000)
4408 #define EXTI_IMR_MR17 ((uint32_t)0x00020000)
4409 #define EXTI_IMR_MR18 ((uint32_t)0x00040000)
4410 #define EXTI_IMR_MR19 ((uint32_t)0x00080000)
4411 #define EXTI_IMR_MR23 ((uint32_t)0x00800000)
4413 /******************* Bit definition for EXTI_EMR register *******************/
4414 #define EXTI_EMR_MR0 ((uint32_t)0x00000001)
4415 #define EXTI_EMR_MR1 ((uint32_t)0x00000002)
4416 #define EXTI_EMR_MR2 ((uint32_t)0x00000004)
4417 #define EXTI_EMR_MR3 ((uint32_t)0x00000008)
4418 #define EXTI_EMR_MR4 ((uint32_t)0x00000010)
4419 #define EXTI_EMR_MR5 ((uint32_t)0x00000020)
4420 #define EXTI_EMR_MR6 ((uint32_t)0x00000040)
4421 #define EXTI_EMR_MR7 ((uint32_t)0x00000080)
4422 #define EXTI_EMR_MR8 ((uint32_t)0x00000100)
4423 #define EXTI_EMR_MR9 ((uint32_t)0x00000200)
4424 #define EXTI_EMR_MR10 ((uint32_t)0x00000400)
4425 #define EXTI_EMR_MR11 ((uint32_t)0x00000800)
4426 #define EXTI_EMR_MR12 ((uint32_t)0x00001000)
4427 #define EXTI_EMR_MR13 ((uint32_t)0x00002000)
4428 #define EXTI_EMR_MR14 ((uint32_t)0x00004000)
4429 #define EXTI_EMR_MR15 ((uint32_t)0x00008000)
4430 #define EXTI_EMR_MR16 ((uint32_t)0x00010000)
4431 #define EXTI_EMR_MR17 ((uint32_t)0x00020000)
4432 #define EXTI_EMR_MR18 ((uint32_t)0x00040000)
4433 #define EXTI_EMR_MR19 ((uint32_t)0x00080000)
4434 #define EXTI_EMR_MR23 ((uint32_t)0x00800000)
4436 /****************** Bit definition for EXTI_RTSR register *******************/
4437 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001)
4438 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002)
4439 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004)
4440 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008)
4441 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010)
4442 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020)
4443 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040)
4444 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080)
4445 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100)
4446 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200)
4447 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400)
4448 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800)
4449 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000)
4450 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000)
4451 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000)
4452 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000)
4453 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000)
4454 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000)
4455 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000)
4456 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000)
4457 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000)
4459 /****************** Bit definition for EXTI_FTSR register *******************/
4460 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001)
4461 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002)
4462 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004)
4463 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008)
4464 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010)
4465 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020)
4466 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040)
4467 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080)
4468 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100)
4469 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200)
4470 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400)
4471 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800)
4472 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000)
4473 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000)
4474 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000)
4475 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000)
4476 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000)
4477 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000)
4478 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000)
4479 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000)
4480 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000)
4482 /****************** Bit definition for EXTI_SWIER register ******************/
4483 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001)
4484 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002)
4485 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004)
4486 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008)
4487 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010)
4488 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020)
4489 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040)
4490 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080)
4491 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100)
4492 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200)
4493 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400)
4494 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800)
4495 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000)
4496 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000)
4497 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000)
4498 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000)
4499 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000)
4500 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000)
4501 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000)
4502 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000)
4503 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000)
4505 /******************* Bit definition for EXTI_PR register ********************/
4506 #define EXTI_PR_PR0 ((uint32_t)0x00000001)
4507 #define EXTI_PR_PR1 ((uint32_t)0x00000002)
4508 #define EXTI_PR_PR2 ((uint32_t)0x00000004)
4509 #define EXTI_PR_PR3 ((uint32_t)0x00000008)
4510 #define EXTI_PR_PR4 ((uint32_t)0x00000010)
4511 #define EXTI_PR_PR5 ((uint32_t)0x00000020)
4512 #define EXTI_PR_PR6 ((uint32_t)0x00000040)
4513 #define EXTI_PR_PR7 ((uint32_t)0x00000080)
4514 #define EXTI_PR_PR8 ((uint32_t)0x00000100)
4515 #define EXTI_PR_PR9 ((uint32_t)0x00000200)
4516 #define EXTI_PR_PR10 ((uint32_t)0x00000400)
4517 #define EXTI_PR_PR11 ((uint32_t)0x00000800)
4518 #define EXTI_PR_PR12 ((uint32_t)0x00001000)
4519 #define EXTI_PR_PR13 ((uint32_t)0x00002000)
4520 #define EXTI_PR_PR14 ((uint32_t)0x00004000)
4521 #define EXTI_PR_PR15 ((uint32_t)0x00008000)
4522 #define EXTI_PR_PR16 ((uint32_t)0x00010000)
4523 #define EXTI_PR_PR17 ((uint32_t)0x00020000)
4524 #define EXTI_PR_PR18 ((uint32_t)0x00040000)
4525 #define EXTI_PR_PR19 ((uint32_t)0x00080000)
4526 #define EXTI_PR_PR23 ((uint32_t)0x00800000)
4528 /******************************************************************************/
4529 /* */
4530 /* FLASH */
4531 /* */
4532 /******************************************************************************/
4533 /******************* Bits definition for FLASH_ACR register *****************/
4534 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
4535 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
4536 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
4537 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
4538 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
4539 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
4540 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
4541 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
4542 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
4543 #define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
4544 #define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
4545 #define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
4546 #define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
4547 #define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
4548 #define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
4549 #define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
4550 #define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
4551 
4552 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
4553 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
4554 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)