core_cm0.h
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1 /**************************************************************************/
10 /* Copyright (c) 2009 - 2014 ARM LIMITED
11 
12  All rights reserved.
13  Redistribution and use in source and binary forms, with or without
14  modification, are permitted provided that the following conditions are met:
15  - Redistributions of source code must retain the above copyright
16  notice, this list of conditions and the following disclaimer.
17  - Redistributions in binary form must reproduce the above copyright
18  notice, this list of conditions and the following disclaimer in the
19  documentation and/or other materials provided with the distribution.
20  - Neither the name of ARM nor the names of its contributors may be used
21  to endorse or promote products derived from this software without
22  specific prior written permission.
23  *
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  POSSIBILITY OF SUCH DAMAGE.
35  ---------------------------------------------------------------------------*/
36 
37 
38 #if defined ( __ICCARM__ )
39  #pragma system_include /* treat file as system include file for MISRA check */
40 #endif
41 
42 #ifndef __CORE_CM0_H_GENERIC
43 #define __CORE_CM0_H_GENERIC
44 
45 #ifdef __cplusplus
46  extern "C" {
47 #endif
48 
63 /*******************************************************************************
64  * CMSIS definitions
65  ******************************************************************************/
70 /* CMSIS CM0 definitions */
71 #define __CM0_CMSIS_VERSION_MAIN (0x04)
72 #define __CM0_CMSIS_VERSION_SUB (0x00)
73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
74  __CM0_CMSIS_VERSION_SUB )
76 #define __CORTEX_M (0x00)
79 #if defined ( __CC_ARM )
80  #define __ASM __asm
81  #define __INLINE __inline
82  #define __STATIC_INLINE static __inline
83 
84 #elif defined ( __GNUC__ )
85  #define __ASM __asm
86  #define __INLINE inline
87  #define __STATIC_INLINE static inline
88 
89 #elif defined ( __ICCARM__ )
90  #define __ASM __asm
91  #define __INLINE inline
92  #define __STATIC_INLINE static inline
93 
94 #elif defined ( __TMS470__ )
95  #define __ASM __asm
96  #define __STATIC_INLINE static inline
97 
98 #elif defined ( __TASKING__ )
99  #define __ASM __asm
100  #define __INLINE inline
101  #define __STATIC_INLINE static inline
102 
103 #elif defined ( __CSMC__ )
104  #define __packed
105  #define __ASM _asm
106  #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107  #define __STATIC_INLINE static inline
108 
109 #endif
110 
114 #define __FPU_USED 0
115 
116 #if defined ( __CC_ARM )
117  #if defined __TARGET_FPU_VFP
118  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
119  #endif
120 
121 #elif defined ( __GNUC__ )
122  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
123  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
124  #endif
125 
126 #elif defined ( __ICCARM__ )
127  #if defined __ARMVFP__
128  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129  #endif
130 
131 #elif defined ( __TMS470__ )
132  #if defined __TI__VFP_SUPPORT____
133  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134  #endif
135 
136 #elif defined ( __TASKING__ )
137  #if defined __FPU_VFP__
138  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139  #endif
140 
141 #elif defined ( __CSMC__ ) /* Cosmic */
142  #if ( __CSMC__ & 0x400) // FPU present for parser
143  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144  #endif
145 #endif
146 
147 #include <stdint.h> /* standard types definitions */
148 #include <core_cmInstr.h> /* Core Instruction Access */
149 #include <core_cmFunc.h> /* Core Function Access */
150 
151 #ifdef __cplusplus
152 }
153 #endif
154 
155 #endif /* __CORE_CM0_H_GENERIC */
156 
157 #ifndef __CMSIS_GENERIC
158 
159 #ifndef __CORE_CM0_H_DEPENDANT
160 #define __CORE_CM0_H_DEPENDANT
161 
162 #ifdef __cplusplus
163  extern "C" {
164 #endif
165 
166 /* check device defines and use defaults */
167 #if defined __CHECK_DEVICE_DEFINES
168  #ifndef __CM0_REV
169  #define __CM0_REV 0x0000
170  #warning "__CM0_REV not defined in device header file; using default!"
171  #endif
172 
173  #ifndef __NVIC_PRIO_BITS
174  #define __NVIC_PRIO_BITS 2
175  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
176  #endif
177 
178  #ifndef __Vendor_SysTickConfig
179  #define __Vendor_SysTickConfig 0
180  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
181  #endif
182 #endif
183 
184 /* IO definitions (access restrictions to peripheral registers) */
192 #ifdef __cplusplus
193  #define __I volatile
194 #else
195  #define __I volatile const
196 #endif
197 #define __O volatile
198 #define __IO volatile
200 
204 /*******************************************************************************
205  * Register Abstraction
206  Core Register contain:
207  - Core Register
208  - Core NVIC Register
209  - Core SCB Register
210  - Core SysTick Register
211  ******************************************************************************/
212 
224 typedef union
225 {
226  struct
227  {
228 #if (__CORTEX_M != 0x04)
229  uint32_t _reserved0:27;
230 #else
231  uint32_t _reserved0:16;
232  uint32_t GE:4;
233  uint32_t _reserved1:7;
234 #endif
235  uint32_t Q:1;
236  uint32_t V:1;
237  uint32_t C:1;
238  uint32_t Z:1;
239  uint32_t N:1;
240  } b;
241  uint32_t w;
242 } APSR_Type;
243 
244 
247 typedef union
248 {
249  struct
250  {
251  uint32_t ISR:9;
252  uint32_t _reserved0:23;
253  } b;
254  uint32_t w;
255 } IPSR_Type;
256 
257 
260 typedef union
261 {
262  struct
263  {
264  uint32_t ISR:9;
265 #if (__CORTEX_M != 0x04)
266  uint32_t _reserved0:15;
267 #else
268  uint32_t _reserved0:7;
269  uint32_t GE:4;
270  uint32_t _reserved1:4;
271 #endif
272  uint32_t T:1;
273  uint32_t IT:2;
274  uint32_t Q:1;
275  uint32_t V:1;
276  uint32_t C:1;
277  uint32_t Z:1;
278  uint32_t N:1;
279  } b;
280  uint32_t w;
281 } xPSR_Type;
282 
283 
286 typedef union
287 {
288  struct
289  {
290  uint32_t nPRIV:1;
291  uint32_t SPSEL:1;
292  uint32_t FPCA:1;
293  uint32_t _reserved0:29;
294  } b;
295  uint32_t w;
296 } CONTROL_Type;
297 
309 typedef struct
310 {
311  __IO uint32_t ISER[1];
312  uint32_t RESERVED0[31];
313  __IO uint32_t ICER[1];
314  uint32_t RSERVED1[31];
315  __IO uint32_t ISPR[1];
316  uint32_t RESERVED2[31];
317  __IO uint32_t ICPR[1];
318  uint32_t RESERVED3[31];
319  uint32_t RESERVED4[64];
320  __IO uint32_t IP[8];
321 } NVIC_Type;
322 
334 typedef struct
335 {
336  __I uint32_t CPUID;
337  __IO uint32_t ICSR;
338  uint32_t RESERVED0;
339  __IO uint32_t AIRCR;
340  __IO uint32_t SCR;
341  __IO uint32_t CCR;
342  uint32_t RESERVED1;
343  __IO uint32_t SHP[2];
344  __IO uint32_t SHCSR;
345 } SCB_Type;
346 
347 /* SCB CPUID Register Definitions */
348 #define SCB_CPUID_IMPLEMENTER_Pos 24
349 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
351 #define SCB_CPUID_VARIANT_Pos 20
352 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
354 #define SCB_CPUID_ARCHITECTURE_Pos 16
355 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
357 #define SCB_CPUID_PARTNO_Pos 4
358 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
360 #define SCB_CPUID_REVISION_Pos 0
361 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)
363 /* SCB Interrupt Control State Register Definitions */
364 #define SCB_ICSR_NMIPENDSET_Pos 31
365 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
367 #define SCB_ICSR_PENDSVSET_Pos 28
368 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
370 #define SCB_ICSR_PENDSVCLR_Pos 27
371 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
373 #define SCB_ICSR_PENDSTSET_Pos 26
374 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
376 #define SCB_ICSR_PENDSTCLR_Pos 25
377 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
379 #define SCB_ICSR_ISRPREEMPT_Pos 23
380 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
382 #define SCB_ICSR_ISRPENDING_Pos 22
383 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
385 #define SCB_ICSR_VECTPENDING_Pos 12
386 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
388 #define SCB_ICSR_VECTACTIVE_Pos 0
389 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
391 /* SCB Application Interrupt and Reset Control Register Definitions */
392 #define SCB_AIRCR_VECTKEY_Pos 16
393 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
395 #define SCB_AIRCR_VECTKEYSTAT_Pos 16
396 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
398 #define SCB_AIRCR_ENDIANESS_Pos 15
399 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
401 #define SCB_AIRCR_SYSRESETREQ_Pos 2
402 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
404 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1
405 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
407 /* SCB System Control Register Definitions */
408 #define SCB_SCR_SEVONPEND_Pos 4
409 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
411 #define SCB_SCR_SLEEPDEEP_Pos 2
412 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
414 #define SCB_SCR_SLEEPONEXIT_Pos 1
415 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
417 /* SCB Configuration Control Register Definitions */
418 #define SCB_CCR_STKALIGN_Pos 9
419 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
421 #define SCB_CCR_UNALIGN_TRP_Pos 3
422 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
424 /* SCB System Handler Control and State Register Definitions */
425 #define SCB_SHCSR_SVCALLPENDED_Pos 15
426 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
428 
439 typedef struct
440 {
441  __IO uint32_t CTRL;
442  __IO uint32_t LOAD;
443  __IO uint32_t VAL;
444  __I uint32_t CALIB;
445 } SysTick_Type;
446 
447 /* SysTick Control / Status Register Definitions */
448 #define SysTick_CTRL_COUNTFLAG_Pos 16
449 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
451 #define SysTick_CTRL_CLKSOURCE_Pos 2
452 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
454 #define SysTick_CTRL_TICKINT_Pos 1
455 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
457 #define SysTick_CTRL_ENABLE_Pos 0
458 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos)
460 /* SysTick Reload Register Definitions */
461 #define SysTick_LOAD_RELOAD_Pos 0
462 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)
464 /* SysTick Current Register Definitions */
465 #define SysTick_VAL_CURRENT_Pos 0
466 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
468 /* SysTick Calibration Register Definitions */
469 #define SysTick_CALIB_NOREF_Pos 31
470 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
472 #define SysTick_CALIB_SKEW_Pos 30
473 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
475 #define SysTick_CALIB_TENMS_Pos 0
476 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)
478 
488 
497 /* Memory mapping of Cortex-M0 Hardware */
498 #define SCS_BASE (0xE000E000UL)
499 #define SysTick_BASE (SCS_BASE + 0x0010UL)
500 #define NVIC_BASE (SCS_BASE + 0x0100UL)
501 #define SCB_BASE (SCS_BASE + 0x0D00UL)
503 #define SCB ((SCB_Type *) SCB_BASE )
504 #define SysTick ((SysTick_Type *) SysTick_BASE )
505 #define NVIC ((NVIC_Type *) NVIC_BASE )
508 
512 /*******************************************************************************
513  * Hardware Abstraction Layer
514  Core Function Interface contains:
515  - Core NVIC Functions
516  - Core SysTick Functions
517  - Core Register Access Functions
518  ******************************************************************************/
519 
524 /* ########################## NVIC functions #################################### */
531 /* Interrupt Priorities are WORD accessible only under ARMv6M */
532 /* The following MACROS handle generation of the register offset and byte masks */
533 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
534 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
535 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
536 
537 
544 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
545 {
546  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
547 }
548 
549 
556 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
557 {
558  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
559 }
560 
561 
572 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
573 {
574  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
575 }
576 
577 
584 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
585 {
586  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
587 }
588 
589 
596 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
597 {
598  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
599 }
600 
601 
611 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
612 {
613  if(IRQn < 0) {
614  SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
615  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
616  else {
617  NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
618  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
619 }
620 
621 
633 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
634 {
635 
636  if(IRQn < 0) {
637  return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
638  else {
639  return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
640 }
641 
642 
647 __STATIC_INLINE void NVIC_SystemReset(void)
648 {
649  __DSB(); /* Ensure all outstanding memory accesses included
650  buffered write are completed before reset */
651  SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
652  SCB_AIRCR_SYSRESETREQ_Msk);
653  __DSB(); /* Ensure completion of memory access */
654  while(1); /* wait until reset */
655 }
656 
661 /* ################################## SysTick function ############################################ */
668 #if (__Vendor_SysTickConfig == 0)
669 
685 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
686 {
687  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
688 
689  SysTick->LOAD = ticks - 1; /* set reload register */
690  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
691  SysTick->VAL = 0; /* Load the SysTick Counter Value */
692  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
693  SysTick_CTRL_TICKINT_Msk |
694  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
695  return (0); /* Function successful */
696 }
697 
698 #endif
699 
705 #ifdef __cplusplus
706 }
707 #endif
708 
709 #endif /* __CORE_CM0_H_DEPENDANT */
710 
711 #endif /* __CMSIS_GENERIC */
SysTick_IRQn
Definition: stm32f4xx.h:196
IPSR_Type::w
uint32_t w
Definition: core_cm0.h:254
core_cmFunc.h
CMSIS Cortex-M Core Function Access Header File.
SCB_Type::SHCSR
__IO uint32_t SHCSR
Definition: core_cm0.h:344
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm0.h:392
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:309
IRQn_Type
enum IRQn IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
_SHP_IDX
#define _SHP_IDX(IRQn)
Definition: core_cm0.h:534
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm0.h:452
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:334
CONTROL_Type::w
uint32_t w
Definition: core_cm0.h:295
core_cmInstr.h
CMSIS Cortex-M Core Instruction Access Header File.
IRQn
IRQn
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f4xx.h:186
SysTick_Type::VAL
__IO uint32_t VAL
Definition: core_cm0.h:443
NVIC_SetPriority
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm0.h:611
SysTick_Type::CALIB
__I uint32_t CALIB
Definition: core_cm0.h:444
_BIT_SHIFT
#define _BIT_SHIFT(IRQn)
Definition: core_cm0.h:533
__I
#define __I
Definition: core_cm0.h:195
SCB_Type::ICSR
__IO uint32_t ICSR
Definition: core_cm0.h:337
SCB_Type::AIRCR
__IO uint32_t AIRCR
Definition: core_cm0.h:339
SCB_Type::RESERVED1
uint32_t RESERVED1
Definition: core_cm0.h:342
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm0.h:455
SCB
#define SCB
Definition: core_cm0.h:503
NVIC_DisableIRQ
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm0.h:556
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:439
NVIC_SystemReset
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm0.h:647
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0.h:224
NVIC_EnableIRQ
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm0.h:544
__IO
#define __IO
Definition: core_cm0.h:198
NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm0.h:572
SysTick
#define SysTick
Definition: core_cm0.h:504
SysTick_Config
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm0.h:685
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_cm0.h:286
SCB_Type::CPUID
__I uint32_t CPUID
Definition: core_cm0.h:336
SysTick_Type::CTRL
__IO uint32_t CTRL
Definition: core_cm0.h:441
NVIC
#define NVIC
Definition: core_cm0.h:505
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm0.h:462
SCB_Type::SCR
__IO uint32_t SCR
Definition: core_cm0.h:340
NVIC_SetPendingIRQ
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm0.h:584
NVIC_ClearPendingIRQ
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm0.h:596
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0.h:247
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0.h:260
_IP_IDX
#define _IP_IDX(IRQn)
Definition: core_cm0.h:535
NVIC_GetPriority
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm0.h:633
SysTick_Type::LOAD
__IO uint32_t LOAD
Definition: core_cm0.h:442
SysTick_CTRL_ENABLE_Msk
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Definition: core_cm0.h:458
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Definition: core_cm0.h:341
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Definition: core_cm0.h:280
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Definition: stm32f4xx.h:178
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rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Apr 15 2021 05:07:46