Type definitions for the Trace Port Interface (TPI) More...
|
Classes | |
| struct | TPI_Type |
| Structure type to access the Trace Port Interface Register (TPI). More... | |
Macros | |
| #define | TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) |
| #define | TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) |
| #define | TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) |
| #define | TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) |
| #define | TPI_ACPR_PRESCALER_Pos 0 |
| #define | TPI_ACPR_PRESCALER_Pos 0 |
| #define | TPI_ACPR_PRESCALER_Pos 0 |
| #define | TPI_ACPR_PRESCALER_Pos 0 |
| #define | TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
| #define | TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
| #define | TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
| #define | TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
| #define | TPI_DEVID_AsynClkIn_Pos 5 |
| #define | TPI_DEVID_AsynClkIn_Pos 5 |
| #define | TPI_DEVID_AsynClkIn_Pos 5 |
| #define | TPI_DEVID_AsynClkIn_Pos 5 |
| #define | TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
| #define | TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
| #define | TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
| #define | TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
| #define | TPI_DEVID_MANCVALID_Pos 10 |
| #define | TPI_DEVID_MANCVALID_Pos 10 |
| #define | TPI_DEVID_MANCVALID_Pos 10 |
| #define | TPI_DEVID_MANCVALID_Pos 10 |
| #define | TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
| #define | TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
| #define | TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
| #define | TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
| #define | TPI_DEVID_MinBufSz_Pos 6 |
| #define | TPI_DEVID_MinBufSz_Pos 6 |
| #define | TPI_DEVID_MinBufSz_Pos 6 |
| #define | TPI_DEVID_MinBufSz_Pos 6 |
| #define | TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) |
| #define | TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) |
| #define | TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) |
| #define | TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) |
| #define | TPI_DEVID_NrTraceInput_Pos 0 |
| #define | TPI_DEVID_NrTraceInput_Pos 0 |
| #define | TPI_DEVID_NrTraceInput_Pos 0 |
| #define | TPI_DEVID_NrTraceInput_Pos 0 |
| #define | TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
| #define | TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
| #define | TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
| #define | TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
| #define | TPI_DEVID_NRZVALID_Pos 11 |
| #define | TPI_DEVID_NRZVALID_Pos 11 |
| #define | TPI_DEVID_NRZVALID_Pos 11 |
| #define | TPI_DEVID_NRZVALID_Pos 11 |
| #define | TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
| #define | TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
| #define | TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
| #define | TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
| #define | TPI_DEVID_PTINVALID_Pos 9 |
| #define | TPI_DEVID_PTINVALID_Pos 9 |
| #define | TPI_DEVID_PTINVALID_Pos 9 |
| #define | TPI_DEVID_PTINVALID_Pos 9 |
| #define | TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
| #define | TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
| #define | TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
| #define | TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
| #define | TPI_DEVTYPE_MajorType_Pos 4 |
| #define | TPI_DEVTYPE_MajorType_Pos 4 |
| #define | TPI_DEVTYPE_MajorType_Pos 4 |
| #define | TPI_DEVTYPE_MajorType_Pos 4 |
| #define | TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) |
| #define | TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) |
| #define | TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) |
| #define | TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) |
| #define | TPI_DEVTYPE_SubType_Pos 0 |
| #define | TPI_DEVTYPE_SubType_Pos 0 |
| #define | TPI_DEVTYPE_SubType_Pos 0 |
| #define | TPI_DEVTYPE_SubType_Pos 0 |
| #define | TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
| #define | TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
| #define | TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
| #define | TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
| #define | TPI_FFCR_EnFCont_Pos 1 |
| #define | TPI_FFCR_EnFCont_Pos 1 |
| #define | TPI_FFCR_EnFCont_Pos 1 |
| #define | TPI_FFCR_EnFCont_Pos 1 |
| #define | TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
| #define | TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
| #define | TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
| #define | TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
| #define | TPI_FFCR_TrigIn_Pos 8 |
| #define | TPI_FFCR_TrigIn_Pos 8 |
| #define | TPI_FFCR_TrigIn_Pos 8 |
| #define | TPI_FFCR_TrigIn_Pos 8 |
| #define | TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) |
| #define | TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) |
| #define | TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) |
| #define | TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) |
| #define | TPI_FFSR_FlInProg_Pos 0 |
| #define | TPI_FFSR_FlInProg_Pos 0 |
| #define | TPI_FFSR_FlInProg_Pos 0 |
| #define | TPI_FFSR_FlInProg_Pos 0 |
| #define | TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
| #define | TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
| #define | TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
| #define | TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
| #define | TPI_FFSR_FtNonStop_Pos 3 |
| #define | TPI_FFSR_FtNonStop_Pos 3 |
| #define | TPI_FFSR_FtNonStop_Pos 3 |
| #define | TPI_FFSR_FtNonStop_Pos 3 |
| #define | TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
| #define | TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
| #define | TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
| #define | TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
| #define | TPI_FFSR_FtStopped_Pos 1 |
| #define | TPI_FFSR_FtStopped_Pos 1 |
| #define | TPI_FFSR_FtStopped_Pos 1 |
| #define | TPI_FFSR_FtStopped_Pos 1 |
| #define | TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
| #define | TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
| #define | TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
| #define | TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
| #define | TPI_FFSR_TCPresent_Pos 2 |
| #define | TPI_FFSR_TCPresent_Pos 2 |
| #define | TPI_FFSR_TCPresent_Pos 2 |
| #define | TPI_FFSR_TCPresent_Pos 2 |
| #define | TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) |
| #define | TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) |
| #define | TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) |
| #define | TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) |
| #define | TPI_FIFO0_ETM0_Pos 0 |
| #define | TPI_FIFO0_ETM0_Pos 0 |
| #define | TPI_FIFO0_ETM0_Pos 0 |
| #define | TPI_FIFO0_ETM0_Pos 0 |
| #define | TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
| #define | TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
| #define | TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
| #define | TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
| #define | TPI_FIFO0_ETM1_Pos 8 |
| #define | TPI_FIFO0_ETM1_Pos 8 |
| #define | TPI_FIFO0_ETM1_Pos 8 |
| #define | TPI_FIFO0_ETM1_Pos 8 |
| #define | TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
| #define | TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
| #define | TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
| #define | TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
| #define | TPI_FIFO0_ETM2_Pos 16 |
| #define | TPI_FIFO0_ETM2_Pos 16 |
| #define | TPI_FIFO0_ETM2_Pos 16 |
| #define | TPI_FIFO0_ETM2_Pos 16 |
| #define | TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
| #define | TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
| #define | TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
| #define | TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
| #define | TPI_FIFO0_ETM_ATVALID_Pos 26 |
| #define | TPI_FIFO0_ETM_ATVALID_Pos 26 |
| #define | TPI_FIFO0_ETM_ATVALID_Pos 26 |
| #define | TPI_FIFO0_ETM_ATVALID_Pos 26 |
| #define | TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
| #define | TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
| #define | TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
| #define | TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
| #define | TPI_FIFO0_ETM_bytecount_Pos 24 |
| #define | TPI_FIFO0_ETM_bytecount_Pos 24 |
| #define | TPI_FIFO0_ETM_bytecount_Pos 24 |
| #define | TPI_FIFO0_ETM_bytecount_Pos 24 |
| #define | TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
| #define | TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
| #define | TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
| #define | TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
| #define | TPI_FIFO0_ITM_ATVALID_Pos 29 |
| #define | TPI_FIFO0_ITM_ATVALID_Pos 29 |
| #define | TPI_FIFO0_ITM_ATVALID_Pos 29 |
| #define | TPI_FIFO0_ITM_ATVALID_Pos 29 |
| #define | TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
| #define | TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
| #define | TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
| #define | TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
| #define | TPI_FIFO0_ITM_bytecount_Pos 27 |
| #define | TPI_FIFO0_ITM_bytecount_Pos 27 |
| #define | TPI_FIFO0_ITM_bytecount_Pos 27 |
| #define | TPI_FIFO0_ITM_bytecount_Pos 27 |
| #define | TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
| #define | TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
| #define | TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
| #define | TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
| #define | TPI_FIFO1_ETM_ATVALID_Pos 26 |
| #define | TPI_FIFO1_ETM_ATVALID_Pos 26 |
| #define | TPI_FIFO1_ETM_ATVALID_Pos 26 |
| #define | TPI_FIFO1_ETM_ATVALID_Pos 26 |
| #define | TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
| #define | TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
| #define | TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
| #define | TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
| #define | TPI_FIFO1_ETM_bytecount_Pos 24 |
| #define | TPI_FIFO1_ETM_bytecount_Pos 24 |
| #define | TPI_FIFO1_ETM_bytecount_Pos 24 |
| #define | TPI_FIFO1_ETM_bytecount_Pos 24 |
| #define | TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) |
| #define | TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) |
| #define | TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) |
| #define | TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) |
| #define | TPI_FIFO1_ITM0_Pos 0 |
| #define | TPI_FIFO1_ITM0_Pos 0 |
| #define | TPI_FIFO1_ITM0_Pos 0 |
| #define | TPI_FIFO1_ITM0_Pos 0 |
| #define | TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
| #define | TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
| #define | TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
| #define | TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
| #define | TPI_FIFO1_ITM1_Pos 8 |
| #define | TPI_FIFO1_ITM1_Pos 8 |
| #define | TPI_FIFO1_ITM1_Pos 8 |
| #define | TPI_FIFO1_ITM1_Pos 8 |
| #define | TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
| #define | TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
| #define | TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
| #define | TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
| #define | TPI_FIFO1_ITM2_Pos 16 |
| #define | TPI_FIFO1_ITM2_Pos 16 |
| #define | TPI_FIFO1_ITM2_Pos 16 |
| #define | TPI_FIFO1_ITM2_Pos 16 |
| #define | TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
| #define | TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
| #define | TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
| #define | TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
| #define | TPI_FIFO1_ITM_ATVALID_Pos 29 |
| #define | TPI_FIFO1_ITM_ATVALID_Pos 29 |
| #define | TPI_FIFO1_ITM_ATVALID_Pos 29 |
| #define | TPI_FIFO1_ITM_ATVALID_Pos 29 |
| #define | TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
| #define | TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
| #define | TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
| #define | TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
| #define | TPI_FIFO1_ITM_bytecount_Pos 27 |
| #define | TPI_FIFO1_ITM_bytecount_Pos 27 |
| #define | TPI_FIFO1_ITM_bytecount_Pos 27 |
| #define | TPI_FIFO1_ITM_bytecount_Pos 27 |
| #define | TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) |
| #define | TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) |
| #define | TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) |
| #define | TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) |
| #define | TPI_ITATBCTR0_ATREADY_Pos 0 |
| #define | TPI_ITATBCTR0_ATREADY_Pos 0 |
| #define | TPI_ITATBCTR0_ATREADY_Pos 0 |
| #define | TPI_ITATBCTR0_ATREADY_Pos 0 |
| #define | TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) |
| #define | TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) |
| #define | TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) |
| #define | TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) |
| #define | TPI_ITATBCTR2_ATREADY_Pos 0 |
| #define | TPI_ITATBCTR2_ATREADY_Pos 0 |
| #define | TPI_ITATBCTR2_ATREADY_Pos 0 |
| #define | TPI_ITATBCTR2_ATREADY_Pos 0 |
| #define | TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) |
| #define | TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) |
| #define | TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) |
| #define | TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) |
| #define | TPI_ITCTRL_Mode_Pos 0 |
| #define | TPI_ITCTRL_Mode_Pos 0 |
| #define | TPI_ITCTRL_Mode_Pos 0 |
| #define | TPI_ITCTRL_Mode_Pos 0 |
| #define | TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) |
| #define | TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) |
| #define | TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) |
| #define | TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) |
| #define | TPI_SPPR_TXMODE_Pos 0 |
| #define | TPI_SPPR_TXMODE_Pos 0 |
| #define | TPI_SPPR_TXMODE_Pos 0 |
| #define | TPI_SPPR_TXMODE_Pos 0 |
| #define | TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) |
| #define | TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) |
| #define | TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) |
| #define | TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) |
| #define | TPI_TRIGGER_TRIGGER_Pos 0 |
| #define | TPI_TRIGGER_TRIGGER_Pos 0 |
| #define | TPI_TRIGGER_TRIGGER_Pos 0 |
| #define | TPI_TRIGGER_TRIGGER_Pos 0 |
Detailed Description
Type definitions for the Trace Port Interface (TPI)
Macro Definition Documentation
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) |
TPI ACPR: PRESCALER Mask
Definition at line 916 of file core_sc300.h.
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) |
TPI ACPR: PRESCALER Mask
Definition at line 936 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) |
TPI ACPR: PRESCALER Mask
Definition at line 976 of file core_cm4.h.
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) |
TPI ACPR: PRESCALER Mask
Definition at line 1160 of file core_cm7.h.
| #define TPI_ACPR_PRESCALER_Pos 0 |
TPI ACPR: PRESCALER Position
Definition at line 915 of file core_sc300.h.
| #define TPI_ACPR_PRESCALER_Pos 0 |
TPI ACPR: PRESCALER Position
Definition at line 935 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_ACPR_PRESCALER_Pos 0 |
TPI ACPR: PRESCALER Position
Definition at line 975 of file core_cm4.h.
| #define TPI_ACPR_PRESCALER_Pos 0 |
TPI ACPR: PRESCALER Position
Definition at line 1159 of file core_cm7.h.
| #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
Definition at line 1016 of file core_sc300.h.
| #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
Definition at line 1036 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
Definition at line 1076 of file core_cm4.h.
| #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
Definition at line 1260 of file core_cm7.h.
| #define TPI_DEVID_AsynClkIn_Pos 5 |
TPI DEVID: AsynClkIn Position
Definition at line 1015 of file core_sc300.h.
| #define TPI_DEVID_AsynClkIn_Pos 5 |
TPI DEVID: AsynClkIn Position
Definition at line 1035 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_DEVID_AsynClkIn_Pos 5 |
TPI DEVID: AsynClkIn Position
Definition at line 1075 of file core_cm4.h.
| #define TPI_DEVID_AsynClkIn_Pos 5 |
TPI DEVID: AsynClkIn Position
Definition at line 1259 of file core_cm7.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 1007 of file core_sc300.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 1027 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 1067 of file core_cm4.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 1251 of file core_cm7.h.
| #define TPI_DEVID_MANCVALID_Pos 10 |
TPI DEVID: MANCVALID Position
Definition at line 1006 of file core_sc300.h.
| #define TPI_DEVID_MANCVALID_Pos 10 |
TPI DEVID: MANCVALID Position
Definition at line 1026 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_DEVID_MANCVALID_Pos 10 |
TPI DEVID: MANCVALID Position
Definition at line 1066 of file core_cm4.h.
| #define TPI_DEVID_MANCVALID_Pos 10 |
TPI DEVID: MANCVALID Position
Definition at line 1250 of file core_cm7.h.
| #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
Definition at line 1013 of file core_sc300.h.
| #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
Definition at line 1033 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
Definition at line 1073 of file core_cm4.h.
| #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
Definition at line 1257 of file core_cm7.h.
| #define TPI_DEVID_MinBufSz_Pos 6 |
TPI DEVID: MinBufSz Position
Definition at line 1012 of file core_sc300.h.
| #define TPI_DEVID_MinBufSz_Pos 6 |
TPI DEVID: MinBufSz Position
Definition at line 1032 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_DEVID_MinBufSz_Pos 6 |
TPI DEVID: MinBufSz Position
Definition at line 1072 of file core_cm4.h.
| #define TPI_DEVID_MinBufSz_Pos 6 |
TPI DEVID: MinBufSz Position
Definition at line 1256 of file core_cm7.h.
| #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) |
TPI DEVID: NrTraceInput Mask
Definition at line 1019 of file core_sc300.h.
| #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) |
TPI DEVID: NrTraceInput Mask
Definition at line 1039 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) |
TPI DEVID: NrTraceInput Mask
Definition at line 1079 of file core_cm4.h.
| #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) |
TPI DEVID: NrTraceInput Mask
Definition at line 1263 of file core_cm7.h.
| #define TPI_DEVID_NrTraceInput_Pos 0 |
TPI DEVID: NrTraceInput Position
Definition at line 1018 of file core_sc300.h.
| #define TPI_DEVID_NrTraceInput_Pos 0 |
TPI DEVID: NrTraceInput Position
Definition at line 1038 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_DEVID_NrTraceInput_Pos 0 |
TPI DEVID: NrTraceInput Position
Definition at line 1078 of file core_cm4.h.
| #define TPI_DEVID_NrTraceInput_Pos 0 |
TPI DEVID: NrTraceInput Position
Definition at line 1262 of file core_cm7.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 1004 of file core_sc300.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 1024 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 1064 of file core_cm4.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 1248 of file core_cm7.h.
| #define TPI_DEVID_NRZVALID_Pos 11 |
TPI DEVID: NRZVALID Position
Definition at line 1003 of file core_sc300.h.
| #define TPI_DEVID_NRZVALID_Pos 11 |
TPI DEVID: NRZVALID Position
Definition at line 1023 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_DEVID_NRZVALID_Pos 11 |
TPI DEVID: NRZVALID Position
Definition at line 1063 of file core_cm4.h.
| #define TPI_DEVID_NRZVALID_Pos 11 |
TPI DEVID: NRZVALID Position
Definition at line 1247 of file core_cm7.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 1010 of file core_sc300.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 1030 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 1070 of file core_cm4.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 1254 of file core_cm7.h.
| #define TPI_DEVID_PTINVALID_Pos 9 |
TPI DEVID: PTINVALID Position
Definition at line 1009 of file core_sc300.h.
| #define TPI_DEVID_PTINVALID_Pos 9 |
TPI DEVID: PTINVALID Position
Definition at line 1029 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_DEVID_PTINVALID_Pos 9 |
TPI DEVID: PTINVALID Position
Definition at line 1069 of file core_cm4.h.
| #define TPI_DEVID_PTINVALID_Pos 9 |
TPI DEVID: PTINVALID Position
Definition at line 1253 of file core_cm7.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 1026 of file core_sc300.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 1046 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 1086 of file core_cm4.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 1270 of file core_cm7.h.
| #define TPI_DEVTYPE_MajorType_Pos 4 |
TPI DEVTYPE: MajorType Position
Definition at line 1025 of file core_sc300.h.
| #define TPI_DEVTYPE_MajorType_Pos 4 |
TPI DEVTYPE: MajorType Position
Definition at line 1045 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_DEVTYPE_MajorType_Pos 4 |
TPI DEVTYPE: MajorType Position
Definition at line 1085 of file core_cm4.h.
| #define TPI_DEVTYPE_MajorType_Pos 4 |
TPI DEVTYPE: MajorType Position
Definition at line 1269 of file core_cm7.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) |
TPI DEVTYPE: SubType Mask
Definition at line 1023 of file core_sc300.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) |
TPI DEVTYPE: SubType Mask
Definition at line 1043 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) |
TPI DEVTYPE: SubType Mask
Definition at line 1083 of file core_cm4.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) |
TPI DEVTYPE: SubType Mask
Definition at line 1267 of file core_cm7.h.
| #define TPI_DEVTYPE_SubType_Pos 0 |
TPI DEVTYPE: SubType Position
Definition at line 1022 of file core_sc300.h.
| #define TPI_DEVTYPE_SubType_Pos 0 |
TPI DEVTYPE: SubType Position
Definition at line 1042 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_DEVTYPE_SubType_Pos 0 |
TPI DEVTYPE: SubType Position
Definition at line 1082 of file core_cm4.h.
| #define TPI_DEVTYPE_SubType_Pos 0 |
TPI DEVTYPE: SubType Position
Definition at line 1266 of file core_cm7.h.
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
Definition at line 940 of file core_sc300.h.
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
Definition at line 960 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
Definition at line 1000 of file core_cm4.h.
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
Definition at line 1184 of file core_cm7.h.
| #define TPI_FFCR_EnFCont_Pos 1 |
TPI FFCR: EnFCont Position
Definition at line 939 of file core_sc300.h.
| #define TPI_FFCR_EnFCont_Pos 1 |
TPI FFCR: EnFCont Position
Definition at line 959 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FFCR_EnFCont_Pos 1 |
TPI FFCR: EnFCont Position
Definition at line 999 of file core_cm4.h.
| #define TPI_FFCR_EnFCont_Pos 1 |
TPI FFCR: EnFCont Position
Definition at line 1183 of file core_cm7.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 937 of file core_sc300.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 957 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 997 of file core_cm4.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 1181 of file core_cm7.h.
| #define TPI_FFCR_TrigIn_Pos 8 |
TPI FFCR: TrigIn Position
Definition at line 936 of file core_sc300.h.
| #define TPI_FFCR_TrigIn_Pos 8 |
TPI FFCR: TrigIn Position
Definition at line 956 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FFCR_TrigIn_Pos 8 |
TPI FFCR: TrigIn Position
Definition at line 996 of file core_cm4.h.
| #define TPI_FFCR_TrigIn_Pos 8 |
TPI FFCR: TrigIn Position
Definition at line 1180 of file core_cm7.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) |
TPI FFSR: FlInProg Mask
Definition at line 933 of file core_sc300.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) |
TPI FFSR: FlInProg Mask
Definition at line 953 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) |
TPI FFSR: FlInProg Mask
Definition at line 993 of file core_cm4.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) |
TPI FFSR: FlInProg Mask
Definition at line 1177 of file core_cm7.h.
| #define TPI_FFSR_FlInProg_Pos 0 |
TPI FFSR: FlInProg Position
Definition at line 932 of file core_sc300.h.
| #define TPI_FFSR_FlInProg_Pos 0 |
TPI FFSR: FlInProg Position
Definition at line 952 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FFSR_FlInProg_Pos 0 |
TPI FFSR: FlInProg Position
Definition at line 992 of file core_cm4.h.
| #define TPI_FFSR_FlInProg_Pos 0 |
TPI FFSR: FlInProg Position
Definition at line 1176 of file core_cm7.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 924 of file core_sc300.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 944 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 984 of file core_cm4.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 1168 of file core_cm7.h.
| #define TPI_FFSR_FtNonStop_Pos 3 |
TPI FFSR: FtNonStop Position
Definition at line 923 of file core_sc300.h.
| #define TPI_FFSR_FtNonStop_Pos 3 |
TPI FFSR: FtNonStop Position
Definition at line 943 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FFSR_FtNonStop_Pos 3 |
TPI FFSR: FtNonStop Position
Definition at line 983 of file core_cm4.h.
| #define TPI_FFSR_FtNonStop_Pos 3 |
TPI FFSR: FtNonStop Position
Definition at line 1167 of file core_cm7.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 930 of file core_sc300.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 950 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 990 of file core_cm4.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 1174 of file core_cm7.h.
| #define TPI_FFSR_FtStopped_Pos 1 |
TPI FFSR: FtStopped Position
Definition at line 929 of file core_sc300.h.
| #define TPI_FFSR_FtStopped_Pos 1 |
TPI FFSR: FtStopped Position
Definition at line 949 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FFSR_FtStopped_Pos 1 |
TPI FFSR: FtStopped Position
Definition at line 989 of file core_cm4.h.
| #define TPI_FFSR_FtStopped_Pos 1 |
TPI FFSR: FtStopped Position
Definition at line 1173 of file core_cm7.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 927 of file core_sc300.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 947 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 987 of file core_cm4.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 1171 of file core_cm7.h.
| #define TPI_FFSR_TCPresent_Pos 2 |
TPI FFSR: TCPresent Position
Definition at line 926 of file core_sc300.h.
| #define TPI_FFSR_TCPresent_Pos 2 |
TPI FFSR: TCPresent Position
Definition at line 946 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FFSR_TCPresent_Pos 2 |
TPI FFSR: TCPresent Position
Definition at line 986 of file core_cm4.h.
| #define TPI_FFSR_TCPresent_Pos 2 |
TPI FFSR: TCPresent Position
Definition at line 1170 of file core_cm7.h.
| #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) |
TPI FIFO0: ETM0 Mask
Definition at line 966 of file core_sc300.h.
| #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) |
TPI FIFO0: ETM0 Mask
Definition at line 986 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) |
TPI FIFO0: ETM0 Mask
Definition at line 1026 of file core_cm4.h.
| #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) |
TPI FIFO0: ETM0 Mask
Definition at line 1210 of file core_cm7.h.
| #define TPI_FIFO0_ETM0_Pos 0 |
TPI FIFO0: ETM0 Position
Definition at line 965 of file core_sc300.h.
| #define TPI_FIFO0_ETM0_Pos 0 |
TPI FIFO0: ETM0 Position
Definition at line 985 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO0_ETM0_Pos 0 |
TPI FIFO0: ETM0 Position
Definition at line 1025 of file core_cm4.h.
| #define TPI_FIFO0_ETM0_Pos 0 |
TPI FIFO0: ETM0 Position
Definition at line 1209 of file core_cm7.h.
| #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
Definition at line 963 of file core_sc300.h.
| #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
Definition at line 983 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
Definition at line 1023 of file core_cm4.h.
| #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
Definition at line 1207 of file core_cm7.h.
| #define TPI_FIFO0_ETM1_Pos 8 |
TPI FIFO0: ETM1 Position
Definition at line 962 of file core_sc300.h.
| #define TPI_FIFO0_ETM1_Pos 8 |
TPI FIFO0: ETM1 Position
Definition at line 982 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO0_ETM1_Pos 8 |
TPI FIFO0: ETM1 Position
Definition at line 1022 of file core_cm4.h.
| #define TPI_FIFO0_ETM1_Pos 8 |
TPI FIFO0: ETM1 Position
Definition at line 1206 of file core_cm7.h.
| #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
Definition at line 960 of file core_sc300.h.
| #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
Definition at line 980 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
Definition at line 1020 of file core_cm4.h.
| #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
Definition at line 1204 of file core_cm7.h.
| #define TPI_FIFO0_ETM2_Pos 16 |
TPI FIFO0: ETM2 Position
Definition at line 959 of file core_sc300.h.
| #define TPI_FIFO0_ETM2_Pos 16 |
TPI FIFO0: ETM2 Position
Definition at line 979 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO0_ETM2_Pos 16 |
TPI FIFO0: ETM2 Position
Definition at line 1019 of file core_cm4.h.
| #define TPI_FIFO0_ETM2_Pos 16 |
TPI FIFO0: ETM2 Position
Definition at line 1203 of file core_cm7.h.
| #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
Definition at line 954 of file core_sc300.h.
| #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
Definition at line 974 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
Definition at line 1014 of file core_cm4.h.
| #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
Definition at line 1198 of file core_cm7.h.
| #define TPI_FIFO0_ETM_ATVALID_Pos 26 |
TPI FIFO0: ETM_ATVALID Position
Definition at line 953 of file core_sc300.h.
| #define TPI_FIFO0_ETM_ATVALID_Pos 26 |
TPI FIFO0: ETM_ATVALID Position
Definition at line 973 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO0_ETM_ATVALID_Pos 26 |
TPI FIFO0: ETM_ATVALID Position
Definition at line 1013 of file core_cm4.h.
| #define TPI_FIFO0_ETM_ATVALID_Pos 26 |
TPI FIFO0: ETM_ATVALID Position
Definition at line 1197 of file core_cm7.h.
| #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
Definition at line 957 of file core_sc300.h.
| #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
Definition at line 977 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
Definition at line 1017 of file core_cm4.h.
| #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
Definition at line 1201 of file core_cm7.h.
| #define TPI_FIFO0_ETM_bytecount_Pos 24 |
TPI FIFO0: ETM_bytecount Position
Definition at line 956 of file core_sc300.h.
| #define TPI_FIFO0_ETM_bytecount_Pos 24 |
TPI FIFO0: ETM_bytecount Position
Definition at line 976 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO0_ETM_bytecount_Pos 24 |
TPI FIFO0: ETM_bytecount Position
Definition at line 1016 of file core_cm4.h.
| #define TPI_FIFO0_ETM_bytecount_Pos 24 |
TPI FIFO0: ETM_bytecount Position
Definition at line 1200 of file core_cm7.h.
| #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
Definition at line 948 of file core_sc300.h.
| #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
Definition at line 968 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
Definition at line 1008 of file core_cm4.h.
| #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
Definition at line 1192 of file core_cm7.h.
| #define TPI_FIFO0_ITM_ATVALID_Pos 29 |
TPI FIFO0: ITM_ATVALID Position
Definition at line 947 of file core_sc300.h.
| #define TPI_FIFO0_ITM_ATVALID_Pos 29 |
TPI FIFO0: ITM_ATVALID Position
Definition at line 967 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO0_ITM_ATVALID_Pos 29 |
TPI FIFO0: ITM_ATVALID Position
Definition at line 1007 of file core_cm4.h.
| #define TPI_FIFO0_ITM_ATVALID_Pos 29 |
TPI FIFO0: ITM_ATVALID Position
Definition at line 1191 of file core_cm7.h.
| #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
Definition at line 951 of file core_sc300.h.
| #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
Definition at line 971 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
Definition at line 1011 of file core_cm4.h.
| #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
Definition at line 1195 of file core_cm7.h.
| #define TPI_FIFO0_ITM_bytecount_Pos 27 |
TPI FIFO0: ITM_bytecount Position
Definition at line 950 of file core_sc300.h.
| #define TPI_FIFO0_ITM_bytecount_Pos 27 |
TPI FIFO0: ITM_bytecount Position
Definition at line 970 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO0_ITM_bytecount_Pos 27 |
TPI FIFO0: ITM_bytecount Position
Definition at line 1010 of file core_cm4.h.
| #define TPI_FIFO0_ITM_bytecount_Pos 27 |
TPI FIFO0: ITM_bytecount Position
Definition at line 1194 of file core_cm7.h.
| #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
Definition at line 980 of file core_sc300.h.
| #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
Definition at line 1000 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
Definition at line 1040 of file core_cm4.h.
| #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
Definition at line 1224 of file core_cm7.h.
| #define TPI_FIFO1_ETM_ATVALID_Pos 26 |
TPI FIFO1: ETM_ATVALID Position
Definition at line 979 of file core_sc300.h.
| #define TPI_FIFO1_ETM_ATVALID_Pos 26 |
TPI FIFO1: ETM_ATVALID Position
Definition at line 999 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO1_ETM_ATVALID_Pos 26 |
TPI FIFO1: ETM_ATVALID Position
Definition at line 1039 of file core_cm4.h.
| #define TPI_FIFO1_ETM_ATVALID_Pos 26 |
TPI FIFO1: ETM_ATVALID Position
Definition at line 1223 of file core_cm7.h.
| #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
Definition at line 983 of file core_sc300.h.
| #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
Definition at line 1003 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
Definition at line 1043 of file core_cm4.h.
| #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
Definition at line 1227 of file core_cm7.h.
| #define TPI_FIFO1_ETM_bytecount_Pos 24 |
TPI FIFO1: ETM_bytecount Position
Definition at line 982 of file core_sc300.h.
| #define TPI_FIFO1_ETM_bytecount_Pos 24 |
TPI FIFO1: ETM_bytecount Position
Definition at line 1002 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO1_ETM_bytecount_Pos 24 |
TPI FIFO1: ETM_bytecount Position
Definition at line 1042 of file core_cm4.h.
| #define TPI_FIFO1_ETM_bytecount_Pos 24 |
TPI FIFO1: ETM_bytecount Position
Definition at line 1226 of file core_cm7.h.
| #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) |
TPI FIFO1: ITM0 Mask
Definition at line 992 of file core_sc300.h.
| #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) |
TPI FIFO1: ITM0 Mask
Definition at line 1012 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) |
TPI FIFO1: ITM0 Mask
Definition at line 1052 of file core_cm4.h.
| #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) |
TPI FIFO1: ITM0 Mask
Definition at line 1236 of file core_cm7.h.
| #define TPI_FIFO1_ITM0_Pos 0 |
TPI FIFO1: ITM0 Position
Definition at line 991 of file core_sc300.h.
| #define TPI_FIFO1_ITM0_Pos 0 |
TPI FIFO1: ITM0 Position
Definition at line 1011 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO1_ITM0_Pos 0 |
TPI FIFO1: ITM0 Position
Definition at line 1051 of file core_cm4.h.
| #define TPI_FIFO1_ITM0_Pos 0 |
TPI FIFO1: ITM0 Position
Definition at line 1235 of file core_cm7.h.
| #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
Definition at line 989 of file core_sc300.h.
| #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
Definition at line 1009 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
Definition at line 1049 of file core_cm4.h.
| #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
Definition at line 1233 of file core_cm7.h.
| #define TPI_FIFO1_ITM1_Pos 8 |
TPI FIFO1: ITM1 Position
Definition at line 988 of file core_sc300.h.
| #define TPI_FIFO1_ITM1_Pos 8 |
TPI FIFO1: ITM1 Position
Definition at line 1008 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO1_ITM1_Pos 8 |
TPI FIFO1: ITM1 Position
Definition at line 1048 of file core_cm4.h.
| #define TPI_FIFO1_ITM1_Pos 8 |
TPI FIFO1: ITM1 Position
Definition at line 1232 of file core_cm7.h.
| #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
Definition at line 986 of file core_sc300.h.
| #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
Definition at line 1006 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
Definition at line 1046 of file core_cm4.h.
| #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
Definition at line 1230 of file core_cm7.h.
| #define TPI_FIFO1_ITM2_Pos 16 |
TPI FIFO1: ITM2 Position
Definition at line 985 of file core_sc300.h.
| #define TPI_FIFO1_ITM2_Pos 16 |
TPI FIFO1: ITM2 Position
Definition at line 1005 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO1_ITM2_Pos 16 |
TPI FIFO1: ITM2 Position
Definition at line 1045 of file core_cm4.h.
| #define TPI_FIFO1_ITM2_Pos 16 |
TPI FIFO1: ITM2 Position
Definition at line 1229 of file core_cm7.h.
| #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
Definition at line 974 of file core_sc300.h.
| #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
Definition at line 994 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
Definition at line 1034 of file core_cm4.h.
| #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
Definition at line 1218 of file core_cm7.h.
| #define TPI_FIFO1_ITM_ATVALID_Pos 29 |
TPI FIFO1: ITM_ATVALID Position
Definition at line 973 of file core_sc300.h.
| #define TPI_FIFO1_ITM_ATVALID_Pos 29 |
TPI FIFO1: ITM_ATVALID Position
Definition at line 993 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO1_ITM_ATVALID_Pos 29 |
TPI FIFO1: ITM_ATVALID Position
Definition at line 1033 of file core_cm4.h.
| #define TPI_FIFO1_ITM_ATVALID_Pos 29 |
TPI FIFO1: ITM_ATVALID Position
Definition at line 1217 of file core_cm7.h.
| #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
Definition at line 977 of file core_sc300.h.
| #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
Definition at line 997 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
Definition at line 1037 of file core_cm4.h.
| #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
Definition at line 1221 of file core_cm7.h.
| #define TPI_FIFO1_ITM_bytecount_Pos 27 |
TPI FIFO1: ITM_bytecount Position
Definition at line 976 of file core_sc300.h.
| #define TPI_FIFO1_ITM_bytecount_Pos 27 |
TPI FIFO1: ITM_bytecount Position
Definition at line 996 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_FIFO1_ITM_bytecount_Pos 27 |
TPI FIFO1: ITM_bytecount Position
Definition at line 1036 of file core_cm4.h.
| #define TPI_FIFO1_ITM_bytecount_Pos 27 |
TPI FIFO1: ITM_bytecount Position
Definition at line 1220 of file core_cm7.h.
| #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) |
TPI ITATBCTR0: ATREADY Mask
Definition at line 996 of file core_sc300.h.
| #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) |
TPI ITATBCTR0: ATREADY Mask
Definition at line 1016 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) |
TPI ITATBCTR0: ATREADY Mask
Definition at line 1056 of file core_cm4.h.
| #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) |
TPI ITATBCTR0: ATREADY Mask
Definition at line 1240 of file core_cm7.h.
| #define TPI_ITATBCTR0_ATREADY_Pos 0 |
TPI ITATBCTR0: ATREADY Position
Definition at line 995 of file core_sc300.h.
| #define TPI_ITATBCTR0_ATREADY_Pos 0 |
TPI ITATBCTR0: ATREADY Position
Definition at line 1015 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_ITATBCTR0_ATREADY_Pos 0 |
TPI ITATBCTR0: ATREADY Position
Definition at line 1055 of file core_cm4.h.
| #define TPI_ITATBCTR0_ATREADY_Pos 0 |
TPI ITATBCTR0: ATREADY Position
Definition at line 1239 of file core_cm7.h.
| #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) |
TPI ITATBCTR2: ATREADY Mask
Definition at line 970 of file core_sc300.h.
| #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) |
TPI ITATBCTR2: ATREADY Mask
Definition at line 990 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) |
TPI ITATBCTR2: ATREADY Mask
Definition at line 1030 of file core_cm4.h.
| #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) |
TPI ITATBCTR2: ATREADY Mask
Definition at line 1214 of file core_cm7.h.
| #define TPI_ITATBCTR2_ATREADY_Pos 0 |
TPI ITATBCTR2: ATREADY Position
Definition at line 969 of file core_sc300.h.
| #define TPI_ITATBCTR2_ATREADY_Pos 0 |
TPI ITATBCTR2: ATREADY Position
Definition at line 989 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_ITATBCTR2_ATREADY_Pos 0 |
TPI ITATBCTR2: ATREADY Position
Definition at line 1029 of file core_cm4.h.
| #define TPI_ITATBCTR2_ATREADY_Pos 0 |
TPI ITATBCTR2: ATREADY Position
Definition at line 1213 of file core_cm7.h.
| #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) |
TPI ITCTRL: Mode Mask
Definition at line 1000 of file core_sc300.h.
| #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) |
TPI ITCTRL: Mode Mask
Definition at line 1020 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) |
TPI ITCTRL: Mode Mask
Definition at line 1060 of file core_cm4.h.
| #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) |
TPI ITCTRL: Mode Mask
Definition at line 1244 of file core_cm7.h.
| #define TPI_ITCTRL_Mode_Pos 0 |
TPI ITCTRL: Mode Position
Definition at line 999 of file core_sc300.h.
| #define TPI_ITCTRL_Mode_Pos 0 |
TPI ITCTRL: Mode Position
Definition at line 1019 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_ITCTRL_Mode_Pos 0 |
TPI ITCTRL: Mode Position
Definition at line 1059 of file core_cm4.h.
| #define TPI_ITCTRL_Mode_Pos 0 |
TPI ITCTRL: Mode Position
Definition at line 1243 of file core_cm7.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) |
TPI SPPR: TXMODE Mask
Definition at line 920 of file core_sc300.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) |
TPI SPPR: TXMODE Mask
Definition at line 940 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) |
TPI SPPR: TXMODE Mask
Definition at line 980 of file core_cm4.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) |
TPI SPPR: TXMODE Mask
Definition at line 1164 of file core_cm7.h.
| #define TPI_SPPR_TXMODE_Pos 0 |
TPI SPPR: TXMODE Position
Definition at line 919 of file core_sc300.h.
| #define TPI_SPPR_TXMODE_Pos 0 |
TPI SPPR: TXMODE Position
Definition at line 939 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_SPPR_TXMODE_Pos 0 |
TPI SPPR: TXMODE Position
Definition at line 979 of file core_cm4.h.
| #define TPI_SPPR_TXMODE_Pos 0 |
TPI SPPR: TXMODE Position
Definition at line 1163 of file core_cm7.h.
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) |
TPI TRIGGER: TRIGGER Mask
Definition at line 944 of file core_sc300.h.
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) |
TPI TRIGGER: TRIGGER Mask
Definition at line 964 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) |
TPI TRIGGER: TRIGGER Mask
Definition at line 1004 of file core_cm4.h.
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) |
TPI TRIGGER: TRIGGER Mask
Definition at line 1188 of file core_cm7.h.
| #define TPI_TRIGGER_TRIGGER_Pos 0 |
TPI TRIGGER: TRIGGER Position
Definition at line 943 of file core_sc300.h.
| #define TPI_TRIGGER_TRIGGER_Pos 0 |
TPI TRIGGER: TRIGGER Position
Definition at line 963 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define TPI_TRIGGER_TRIGGER_Pos 0 |
TPI TRIGGER: TRIGGER Position
Definition at line 1003 of file core_cm4.h.
| #define TPI_TRIGGER_TRIGGER_Pos 0 |
TPI TRIGGER: TRIGGER Position
Definition at line 1187 of file core_cm7.h.