Classes | Macros
System Control Block (SCB)
Defines and Type Definitions

Type definitions for the System Control Block Registers. More...

Collaboration diagram for System Control Block (SCB):

Classes

struct  SCB_Type
 Structure type to access the System Control Block (SCB). More...
 

Macros

#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)
 
#define SCB_ABFSR_AHBP_Pos   2
 
#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)
 
#define SCB_ABFSR_AXIM_Pos   3
 
#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)
 
#define SCB_ABFSR_AXIMTYPE_Pos   8
 
#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)
 
#define SCB_ABFSR_DTCM_Pos   1
 
#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)
 
#define SCB_ABFSR_EPPB_Pos   4
 
#define SCB_ABFSR_ITCM_Msk   (1UL << SCB_ABFSR_ITCM_Pos)
 
#define SCB_ABFSR_ITCM_Pos   0
 
#define SCB_AHBPCR_EN_Msk   (1UL << SCB_AHBPCR_EN_Pos)
 
#define SCB_AHBPCR_EN_Pos   0
 
#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)
 
#define SCB_AHBPCR_SZ_Pos   1
 
#define SCB_AHBSCR_CTL_Msk   (3UL << SCB_AHBPCR_CTL_Pos)
 
#define SCB_AHBSCR_CTL_Pos   0
 
#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
 
#define SCB_AHBSCR_INITCOUNT_Pos   11
 
#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
 
#define SCB_AHBSCR_TPRI_Pos   2
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15
 
#define SCB_AIRCR_ENDIANESS_Pos   15
 
#define SCB_AIRCR_ENDIANESS_Pos   15
 
#define SCB_AIRCR_ENDIANESS_Pos   15
 
#define SCB_AIRCR_ENDIANESS_Pos   15
 
#define SCB_AIRCR_ENDIANESS_Pos   15
 
#define SCB_AIRCR_ENDIANESS_Pos   15
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8
 
#define SCB_AIRCR_PRIGROUP_Pos   8
 
#define SCB_AIRCR_PRIGROUP_Pos   8
 
#define SCB_AIRCR_PRIGROUP_Pos   8
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16
 
#define SCB_AIRCR_VECTKEY_Pos   16
 
#define SCB_AIRCR_VECTKEY_Pos   16
 
#define SCB_AIRCR_VECTKEY_Pos   16
 
#define SCB_AIRCR_VECTKEY_Pos   16
 
#define SCB_AIRCR_VECTKEY_Pos   16
 
#define SCB_AIRCR_VECTKEY_Pos   16
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL << SCB_AIRCR_VECTRESET_Pos)
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL << SCB_AIRCR_VECTRESET_Pos)
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL << SCB_AIRCR_VECTRESET_Pos)
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL << SCB_AIRCR_VECTRESET_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0
 
#define SCB_AIRCR_VECTRESET_Pos   0
 
#define SCB_AIRCR_VECTRESET_Pos   0
 
#define SCB_AIRCR_VECTRESET_Pos   0
 
#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
 
#define SCB_CACR_ECCEN_Pos   1
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_FORCEWT_Pos   2
 
#define SCB_CACR_SIWT_Msk   (1UL << SCB_CACR_SIWT_Pos)
 
#define SCB_CACR_SIWT_Pos   0
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8
 
#define SCB_CCR_BFHFNMIGN_Pos   8
 
#define SCB_CCR_BFHFNMIGN_Pos   8
 
#define SCB_CCR_BFHFNMIGN_Pos   8
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_BP_Pos   18
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_DC_Pos   16
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4
 
#define SCB_CCR_DIV_0_TRP_Pos   4
 
#define SCB_CCR_DIV_0_TRP_Pos   4
 
#define SCB_CCR_DIV_0_TRP_Pos   4
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_IC_Pos   17
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL << SCB_CCR_NONBASETHRDENA_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL << SCB_CCR_NONBASETHRDENA_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL << SCB_CCR_NONBASETHRDENA_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL << SCB_CCR_NONBASETHRDENA_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0
 
#define SCB_CCR_NONBASETHRDENA_Pos   0
 
#define SCB_CCR_NONBASETHRDENA_Pos   0
 
#define SCB_CCR_NONBASETHRDENA_Pos   0
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9
 
#define SCB_CCR_STKALIGN_Pos   9
 
#define SCB_CCR_STKALIGN_Pos   9
 
#define SCB_CCR_STKALIGN_Pos   9
 
#define SCB_CCR_STKALIGN_Pos   9
 
#define SCB_CCR_STKALIGN_Pos   9
 
#define SCB_CCR_STKALIGN_Pos   9
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3
 
#define SCB_CCR_UNALIGN_TRP_Pos   3
 
#define SCB_CCR_UNALIGN_TRP_Pos   3
 
#define SCB_CCR_UNALIGN_TRP_Pos   3
 
#define SCB_CCR_UNALIGN_TRP_Pos   3
 
#define SCB_CCR_UNALIGN_TRP_Pos   3
 
#define SCB_CCR_UNALIGN_TRP_Pos   3
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1
 
#define SCB_CCR_USERSETMPEND_Pos   1
 
#define SCB_CCR_USERSETMPEND_Pos   1
 
#define SCB_CCR_USERSETMPEND_Pos   1
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL << SCB_CCSIDR_LINESIZE_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13
 
#define SCB_CCSIDR_RA_Msk   (7UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_RA_Pos   29
 
#define SCB_CCSIDR_WA_Msk   (7UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28
 
#define SCB_CCSIDR_WB_Msk   (7UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_WB_Pos   30
 
#define SCB_CCSIDR_WT_Msk   (7UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WT_Pos   31
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8
 
#define SCB_CFSR_BUSFAULTSR_Pos   8
 
#define SCB_CFSR_BUSFAULTSR_Pos   8
 
#define SCB_CFSR_BUSFAULTSR_Pos   8
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0
 
#define SCB_CFSR_MEMFAULTSR_Pos   0
 
#define SCB_CFSR_MEMFAULTSR_Pos   0
 
#define SCB_CFSR_MEMFAULTSR_Pos   0
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_USGFAULTSR_Pos   16
 
#define SCB_CFSR_USGFAULTSR_Pos   16
 
#define SCB_CFSR_USGFAULTSR_Pos   16
 
#define SCB_CFSR_USGFAULTSR_Pos   16
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_FORMAT_Pos)
 
#define SCB_CLIDR_LOC_Pos   24
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOUU_Pos   27
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16
 
#define SCB_CPUID_ARCHITECTURE_Pos   16
 
#define SCB_CPUID_ARCHITECTURE_Pos   16
 
#define SCB_CPUID_ARCHITECTURE_Pos   16
 
#define SCB_CPUID_ARCHITECTURE_Pos   16
 
#define SCB_CPUID_ARCHITECTURE_Pos   16
 
#define SCB_CPUID_ARCHITECTURE_Pos   16
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24
 
#define SCB_CPUID_IMPLEMENTER_Pos   24
 
#define SCB_CPUID_IMPLEMENTER_Pos   24
 
#define SCB_CPUID_IMPLEMENTER_Pos   24
 
#define SCB_CPUID_IMPLEMENTER_Pos   24
 
#define SCB_CPUID_IMPLEMENTER_Pos   24
 
#define SCB_CPUID_IMPLEMENTER_Pos   24
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4
 
#define SCB_CPUID_PARTNO_Pos   4
 
#define SCB_CPUID_PARTNO_Pos   4
 
#define SCB_CPUID_PARTNO_Pos   4
 
#define SCB_CPUID_PARTNO_Pos   4
 
#define SCB_CPUID_PARTNO_Pos   4
 
#define SCB_CPUID_PARTNO_Pos   4
 
#define SCB_CPUID_REVISION_Msk   (0xFUL << SCB_CPUID_REVISION_Pos)
 
#define SCB_CPUID_REVISION_Msk   (0xFUL << SCB_CPUID_REVISION_Pos)
 
#define SCB_CPUID_REVISION_Msk   (0xFUL << SCB_CPUID_REVISION_Pos)
 
#define SCB_CPUID_REVISION_Msk   (0xFUL << SCB_CPUID_REVISION_Pos)
 
#define SCB_CPUID_REVISION_Msk   (0xFUL << SCB_CPUID_REVISION_Pos)
 
#define SCB_CPUID_REVISION_Msk   (0xFUL << SCB_CPUID_REVISION_Pos)
 
#define SCB_CPUID_REVISION_Msk   (0xFUL << SCB_CPUID_REVISION_Pos)
 
#define SCB_CPUID_REVISION_Pos   0
 
#define SCB_CPUID_REVISION_Pos   0
 
#define SCB_CPUID_REVISION_Pos   0
 
#define SCB_CPUID_REVISION_Pos   0
 
#define SCB_CPUID_REVISION_Pos   0
 
#define SCB_CPUID_REVISION_Pos   0
 
#define SCB_CPUID_REVISION_Pos   0
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20
 
#define SCB_CPUID_VARIANT_Pos   20
 
#define SCB_CPUID_VARIANT_Pos   20
 
#define SCB_CPUID_VARIANT_Pos   20
 
#define SCB_CPUID_VARIANT_Pos   20
 
#define SCB_CPUID_VARIANT_Pos   20
 
#define SCB_CPUID_VARIANT_Pos   20
 
#define SCB_CSSELR_IND_Msk   (1UL << SCB_CSSELR_IND_Pos)
 
#define SCB_CSSELR_IND_Pos   0
 
#define SCB_CSSELR_LEVEL_Msk   (1UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_LEVEL_Pos   0
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_CWG_Pos   24
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_ERG_Pos   20
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_FORMAT_Pos   29
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL << SCB_CTR_IMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_BKPT_Pos   1
 
#define SCB_DFSR_BKPT_Pos   1
 
#define SCB_DFSR_BKPT_Pos   1
 
#define SCB_DFSR_BKPT_Pos   1
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2
 
#define SCB_DFSR_DWTTRAP_Pos   2
 
#define SCB_DFSR_DWTTRAP_Pos   2
 
#define SCB_DFSR_DWTTRAP_Pos   2
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4
 
#define SCB_DFSR_EXTERNAL_Pos   4
 
#define SCB_DFSR_EXTERNAL_Pos   4
 
#define SCB_DFSR_EXTERNAL_Pos   4
 
#define SCB_DFSR_HALTED_Msk   (1UL << SCB_DFSR_HALTED_Pos)
 
#define SCB_DFSR_HALTED_Msk   (1UL << SCB_DFSR_HALTED_Pos)
 
#define SCB_DFSR_HALTED_Msk   (1UL << SCB_DFSR_HALTED_Pos)
 
#define SCB_DFSR_HALTED_Msk   (1UL << SCB_DFSR_HALTED_Pos)
 
#define SCB_DFSR_HALTED_Pos   0
 
#define SCB_DFSR_HALTED_Pos   0
 
#define SCB_DFSR_HALTED_Pos   0
 
#define SCB_DFSR_HALTED_Pos   0
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3
 
#define SCB_DFSR_VCATCH_Pos   3
 
#define SCB_DFSR_VCATCH_Pos   3
 
#define SCB_DFSR_VCATCH_Pos   3
 
#define SCB_DTCMCR_EN_Msk   (1UL << SCB_DTCMCR_EN_Pos)
 
#define SCB_DTCMCR_EN_Pos   0
 
#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)
 
#define SCB_DTCMCR_RETEN_Pos   2
 
#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)
 
#define SCB_DTCMCR_RMW_Pos   1
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_SZ_Pos   3
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31
 
#define SCB_HFSR_DEBUGEVT_Pos   31
 
#define SCB_HFSR_DEBUGEVT_Pos   31
 
#define SCB_HFSR_DEBUGEVT_Pos   31
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_FORCED_Pos   30
 
#define SCB_HFSR_FORCED_Pos   30
 
#define SCB_HFSR_FORCED_Pos   30
 
#define SCB_HFSR_FORCED_Pos   30
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1
 
#define SCB_HFSR_VECTTBL_Pos   1
 
#define SCB_HFSR_VECTTBL_Pos   1
 
#define SCB_HFSR_VECTTBL_Pos   1
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22
 
#define SCB_ICSR_ISRPENDING_Pos   22
 
#define SCB_ICSR_ISRPENDING_Pos   22
 
#define SCB_ICSR_ISRPENDING_Pos   22
 
#define SCB_ICSR_ISRPENDING_Pos   22
 
#define SCB_ICSR_ISRPENDING_Pos   22
 
#define SCB_ICSR_ISRPENDING_Pos   22
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23
 
#define SCB_ICSR_ISRPREEMPT_Pos   23
 
#define SCB_ICSR_ISRPREEMPT_Pos   23
 
#define SCB_ICSR_ISRPREEMPT_Pos   23
 
#define SCB_ICSR_ISRPREEMPT_Pos   23
 
#define SCB_ICSR_ISRPREEMPT_Pos   23
 
#define SCB_ICSR_ISRPREEMPT_Pos   23
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   31
 
#define SCB_ICSR_NMIPENDSET_Pos   31
 
#define SCB_ICSR_NMIPENDSET_Pos   31
 
#define SCB_ICSR_NMIPENDSET_Pos   31
 
#define SCB_ICSR_NMIPENDSET_Pos   31
 
#define SCB_ICSR_NMIPENDSET_Pos   31
 
#define SCB_ICSR_NMIPENDSET_Pos   31
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25
 
#define SCB_ICSR_PENDSTCLR_Pos   25
 
#define SCB_ICSR_PENDSTCLR_Pos   25
 
#define SCB_ICSR_PENDSTCLR_Pos   25
 
#define SCB_ICSR_PENDSTCLR_Pos   25
 
#define SCB_ICSR_PENDSTCLR_Pos   25
 
#define SCB_ICSR_PENDSTCLR_Pos   25
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26
 
#define SCB_ICSR_PENDSTSET_Pos   26
 
#define SCB_ICSR_PENDSTSET_Pos   26
 
#define SCB_ICSR_PENDSTSET_Pos   26
 
#define SCB_ICSR_PENDSTSET_Pos   26
 
#define SCB_ICSR_PENDSTSET_Pos   26
 
#define SCB_ICSR_PENDSTSET_Pos   26
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27
 
#define SCB_ICSR_PENDSVCLR_Pos   27
 
#define SCB_ICSR_PENDSVCLR_Pos   27
 
#define SCB_ICSR_PENDSVCLR_Pos   27
 
#define SCB_ICSR_PENDSVCLR_Pos   27
 
#define SCB_ICSR_PENDSVCLR_Pos   27
 
#define SCB_ICSR_PENDSVCLR_Pos   27
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28
 
#define SCB_ICSR_PENDSVSET_Pos   28
 
#define SCB_ICSR_PENDSVSET_Pos   28
 
#define SCB_ICSR_PENDSVSET_Pos   28
 
#define SCB_ICSR_PENDSVSET_Pos   28
 
#define SCB_ICSR_PENDSVSET_Pos   28
 
#define SCB_ICSR_PENDSVSET_Pos   28
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11
 
#define SCB_ICSR_RETTOBASE_Pos   11
 
#define SCB_ICSR_RETTOBASE_Pos   11
 
#define SCB_ICSR_RETTOBASE_Pos   11
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0
 
#define SCB_ICSR_VECTACTIVE_Pos   0
 
#define SCB_ICSR_VECTACTIVE_Pos   0
 
#define SCB_ICSR_VECTACTIVE_Pos   0
 
#define SCB_ICSR_VECTACTIVE_Pos   0
 
#define SCB_ICSR_VECTACTIVE_Pos   0
 
#define SCB_ICSR_VECTACTIVE_Pos   0
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12
 
#define SCB_ICSR_VECTPENDING_Pos   12
 
#define SCB_ICSR_VECTPENDING_Pos   12
 
#define SCB_ICSR_VECTPENDING_Pos   12
 
#define SCB_ICSR_VECTPENDING_Pos   12
 
#define SCB_ICSR_VECTPENDING_Pos   12
 
#define SCB_ICSR_VECTPENDING_Pos   12
 
#define SCB_ITCMCR_EN_Msk   (1FFUL << SCB_ITCMCR_EN_Pos)
 
#define SCB_ITCMCR_EN_Pos   0
 
#define SCB_ITCMCR_RETEN_Msk   (1FFUL << SCB_ITCMCR_RETEN_Pos)
 
#define SCB_ITCMCR_RETEN_Pos   2
 
#define SCB_ITCMCR_RMW_Msk   (1FFUL << SCB_ITCMCR_RMW_Pos)
 
#define SCB_ITCMCR_RMW_Pos   1
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4
 
#define SCB_SCR_SEVONPEND_Pos   4
 
#define SCB_SCR_SEVONPEND_Pos   4
 
#define SCB_SCR_SEVONPEND_Pos   4
 
#define SCB_SCR_SEVONPEND_Pos   4
 
#define SCB_SCR_SEVONPEND_Pos   4
 
#define SCB_SCR_SEVONPEND_Pos   4
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2
 
#define SCB_SCR_SLEEPDEEP_Pos   2
 
#define SCB_SCR_SLEEPDEEP_Pos   2
 
#define SCB_SCR_SLEEPDEEP_Pos   2
 
#define SCB_SCR_SLEEPDEEP_Pos   2
 
#define SCB_SCR_SLEEPDEEP_Pos   2
 
#define SCB_SCR_SLEEPDEEP_Pos   2
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1
 
#define SCB_SCR_SLEEPONEXIT_Pos   1
 
#define SCB_SCR_SLEEPONEXIT_Pos   1
 
#define SCB_SCR_SLEEPONEXIT_Pos   1
 
#define SCB_SCR_SLEEPONEXIT_Pos   1
 
#define SCB_SCR_SLEEPONEXIT_Pos   1
 
#define SCB_SCR_SLEEPONEXIT_Pos   1
 
#define SCB_SFCR_SECKEY_Msk   (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SFCR_SECKEY_Pos   16
 
#define SCB_SFCR_UNIBRTIMING_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SFCR_UNIBRTIMING_Pos   0
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL << SCB_SHCSR_MEMFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL << SCB_SHCSR_MEMFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL << SCB_SHCSR_MEMFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL << SCB_SHCSR_MEMFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8
 
#define SCB_SHCSR_MONITORACT_Pos   8
 
#define SCB_SHCSR_MONITORACT_Pos   8
 
#define SCB_SHCSR_MONITORACT_Pos   8
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10
 
#define SCB_SHCSR_PENDSVACT_Pos   10
 
#define SCB_SHCSR_PENDSVACT_Pos   10
 
#define SCB_SHCSR_PENDSVACT_Pos   10
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7
 
#define SCB_SHCSR_SVCALLACT_Pos   7
 
#define SCB_SHCSR_SVCALLACT_Pos   7
 
#define SCB_SHCSR_SVCALLACT_Pos   7
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11
 
#define SCB_SHCSR_SYSTICKACT_Pos   11
 
#define SCB_SHCSR_SYSTICKACT_Pos   11
 
#define SCB_SHCSR_SYSTICKACT_Pos   11
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3
 
#define SCB_SHCSR_USGFAULTACT_Pos   3
 
#define SCB_SHCSR_USGFAULTACT_Pos   3
 
#define SCB_SHCSR_USGFAULTACT_Pos   3
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18
 
#define SCB_SHCSR_USGFAULTENA_Pos   18
 
#define SCB_SHCSR_USGFAULTENA_Pos   18
 
#define SCB_SHCSR_USGFAULTENA_Pos   18
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12
 
#define SCB_STIR_INTID_Msk   (0x1FFUL << SCB_STIR_INTID_Pos)
 
#define SCB_STIR_INTID_Pos   0
 
#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)
 
#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)
 
#define SCB_VTOR_TBLBASE_Pos   29
 
#define SCB_VTOR_TBLBASE_Pos   29
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_VTOR_TBLOFF_Pos   7
 
#define SCB_VTOR_TBLOFF_Pos   7
 
#define SCB_VTOR_TBLOFF_Pos   7
 
#define SCB_VTOR_TBLOFF_Pos   7
 
#define SCB_VTOR_TBLOFF_Pos   7
 

Detailed Description

Type definitions for the System Control Block Registers.

Macro Definition Documentation

#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 774 of file core_cm7.h.

#define SCB_ABFSR_AHBP_Pos   2

SCB ABFSR: AHBP Position

Definition at line 773 of file core_cm7.h.

#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 771 of file core_cm7.h.

#define SCB_ABFSR_AXIM_Pos   3

SCB ABFSR: AXIM Position

Definition at line 770 of file core_cm7.h.

#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 765 of file core_cm7.h.

#define SCB_ABFSR_AXIMTYPE_Pos   8

SCB ABFSR: AXIMTYPE Position

Definition at line 764 of file core_cm7.h.

#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 777 of file core_cm7.h.

#define SCB_ABFSR_DTCM_Pos   1

SCB ABFSR: DTCM Position

Definition at line 776 of file core_cm7.h.

#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 768 of file core_cm7.h.

#define SCB_ABFSR_EPPB_Pos   4

SCB ABFSR: EPPB Position

Definition at line 767 of file core_cm7.h.

#define SCB_ABFSR_ITCM_Msk   (1UL << SCB_ABFSR_ITCM_Pos)

SCB ABFSR: ITCM Mask

Definition at line 780 of file core_cm7.h.

#define SCB_ABFSR_ITCM_Pos   0

SCB ABFSR: ITCM Position

Definition at line 779 of file core_cm7.h.

#define SCB_AHBPCR_EN_Msk   (1UL << SCB_AHBPCR_EN_Pos)

SCB AHBPCR: EN Mask

Definition at line 741 of file core_cm7.h.

#define SCB_AHBPCR_EN_Pos   0

SCB AHBPCR: EN Position

Definition at line 740 of file core_cm7.h.

#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 738 of file core_cm7.h.

#define SCB_AHBPCR_SZ_Pos   1

SCB AHBPCR: SZ Position

Definition at line 737 of file core_cm7.h.

#define SCB_AHBSCR_CTL_Msk   (3UL << SCB_AHBPCR_CTL_Pos)

SCB AHBSCR: CTL Mask

Definition at line 761 of file core_cm7.h.

#define SCB_AHBSCR_CTL_Pos   0

SCB AHBSCR: CTL Position

Definition at line 760 of file core_cm7.h.

#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 755 of file core_cm7.h.

#define SCB_AHBSCR_INITCOUNT_Pos   11

SCB AHBSCR: INITCOUNT Position

Definition at line 754 of file core_cm7.h.

#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 758 of file core_cm7.h.

#define SCB_AHBSCR_TPRI_Pos   2

SCB AHBSCR: TPRI Position

Definition at line 757 of file core_cm7.h.

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 399 of file core_cm0.h.

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 411 of file core_sc000.h.

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 420 of file core_cm0plus.h.

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 435 of file core_sc300.h.

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 440 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 479 of file core_cm4.h.

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 523 of file core_cm7.h.

#define SCB_AIRCR_ENDIANESS_Pos   15

SCB AIRCR: ENDIANESS Position

Definition at line 398 of file core_cm0.h.

#define SCB_AIRCR_ENDIANESS_Pos   15

SCB AIRCR: ENDIANESS Position

Definition at line 410 of file core_sc000.h.

#define SCB_AIRCR_ENDIANESS_Pos   15

SCB AIRCR: ENDIANESS Position

Definition at line 419 of file core_cm0plus.h.

#define SCB_AIRCR_ENDIANESS_Pos   15

SCB AIRCR: ENDIANESS Position

Definition at line 434 of file core_sc300.h.

#define SCB_AIRCR_ENDIANESS_Pos   15

SCB AIRCR: ENDIANESS Position

Definition at line 439 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_AIRCR_ENDIANESS_Pos   15

SCB AIRCR: ENDIANESS Position

Definition at line 478 of file core_cm4.h.

#define SCB_AIRCR_ENDIANESS_Pos   15

SCB AIRCR: ENDIANESS Position

Definition at line 522 of file core_cm7.h.

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 438 of file core_sc300.h.

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 443 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 482 of file core_cm4.h.

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 526 of file core_cm7.h.

#define SCB_AIRCR_PRIGROUP_Pos   8

SCB AIRCR: PRIGROUP Position

Definition at line 437 of file core_sc300.h.

#define SCB_AIRCR_PRIGROUP_Pos   8

SCB AIRCR: PRIGROUP Position

Definition at line 442 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_AIRCR_PRIGROUP_Pos   8

SCB AIRCR: PRIGROUP Position

Definition at line 481 of file core_cm4.h.

#define SCB_AIRCR_PRIGROUP_Pos   8

SCB AIRCR: PRIGROUP Position

Definition at line 525 of file core_cm7.h.

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 402 of file core_cm0.h.

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 414 of file core_sc000.h.

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 423 of file core_cm0plus.h.

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 441 of file core_sc300.h.

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 446 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 485 of file core_cm4.h.

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 529 of file core_cm7.h.

#define SCB_AIRCR_SYSRESETREQ_Pos   2

SCB AIRCR: SYSRESETREQ Position

Definition at line 401 of file core_cm0.h.

#define SCB_AIRCR_SYSRESETREQ_Pos   2

SCB AIRCR: SYSRESETREQ Position

Definition at line 413 of file core_sc000.h.

#define SCB_AIRCR_SYSRESETREQ_Pos   2

SCB AIRCR: SYSRESETREQ Position

Definition at line 422 of file core_cm0plus.h.

#define SCB_AIRCR_SYSRESETREQ_Pos   2

SCB AIRCR: SYSRESETREQ Position

Definition at line 440 of file core_sc300.h.

#define SCB_AIRCR_SYSRESETREQ_Pos   2

SCB AIRCR: SYSRESETREQ Position

Definition at line 445 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_AIRCR_SYSRESETREQ_Pos   2

SCB AIRCR: SYSRESETREQ Position

Definition at line 484 of file core_cm4.h.

#define SCB_AIRCR_SYSRESETREQ_Pos   2

SCB AIRCR: SYSRESETREQ Position

Definition at line 528 of file core_cm7.h.

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 405 of file core_cm0.h.

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 417 of file core_sc000.h.

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 426 of file core_cm0plus.h.

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 444 of file core_sc300.h.

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 449 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 488 of file core_cm4.h.

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 532 of file core_cm7.h.

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 404 of file core_cm0.h.

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 416 of file core_sc000.h.

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 425 of file core_cm0plus.h.

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 443 of file core_sc300.h.

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 448 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 487 of file core_cm4.h.

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 531 of file core_cm7.h.

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 393 of file core_cm0.h.

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 405 of file core_sc000.h.

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 414 of file core_cm0plus.h.

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 429 of file core_sc300.h.

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 434 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 473 of file core_cm4.h.

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 517 of file core_cm7.h.

#define SCB_AIRCR_VECTKEY_Pos   16

SCB AIRCR: VECTKEY Position

Definition at line 392 of file core_cm0.h.

#define SCB_AIRCR_VECTKEY_Pos   16

SCB AIRCR: VECTKEY Position

Definition at line 404 of file core_sc000.h.

#define SCB_AIRCR_VECTKEY_Pos   16

SCB AIRCR: VECTKEY Position

Definition at line 413 of file core_cm0plus.h.

#define SCB_AIRCR_VECTKEY_Pos   16

SCB AIRCR: VECTKEY Position

Definition at line 428 of file core_sc300.h.

#define SCB_AIRCR_VECTKEY_Pos   16

SCB AIRCR: VECTKEY Position

Definition at line 433 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_AIRCR_VECTKEY_Pos   16

SCB AIRCR: VECTKEY Position

Definition at line 472 of file core_cm4.h.

#define SCB_AIRCR_VECTKEY_Pos   16

SCB AIRCR: VECTKEY Position

Definition at line 516 of file core_cm7.h.

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 396 of file core_cm0.h.

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 408 of file core_sc000.h.

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 417 of file core_cm0plus.h.

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 432 of file core_sc300.h.

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 437 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 476 of file core_cm4.h.

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 520 of file core_cm7.h.

#define SCB_AIRCR_VECTKEYSTAT_Pos   16

SCB AIRCR: VECTKEYSTAT Position

Definition at line 395 of file core_cm0.h.

#define SCB_AIRCR_VECTKEYSTAT_Pos   16

SCB AIRCR: VECTKEYSTAT Position

Definition at line 407 of file core_sc000.h.

#define SCB_AIRCR_VECTKEYSTAT_Pos   16

SCB AIRCR: VECTKEYSTAT Position

Definition at line 416 of file core_cm0plus.h.

#define SCB_AIRCR_VECTKEYSTAT_Pos   16

SCB AIRCR: VECTKEYSTAT Position

Definition at line 431 of file core_sc300.h.

#define SCB_AIRCR_VECTKEYSTAT_Pos   16

SCB AIRCR: VECTKEYSTAT Position

Definition at line 436 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_AIRCR_VECTKEYSTAT_Pos   16

SCB AIRCR: VECTKEYSTAT Position

Definition at line 475 of file core_cm4.h.

#define SCB_AIRCR_VECTKEYSTAT_Pos   16

SCB AIRCR: VECTKEYSTAT Position

Definition at line 519 of file core_cm7.h.

#define SCB_AIRCR_VECTRESET_Msk   (1UL << SCB_AIRCR_VECTRESET_Pos)

SCB AIRCR: VECTRESET Mask

Definition at line 447 of file core_sc300.h.

#define SCB_AIRCR_VECTRESET_Msk   (1UL << SCB_AIRCR_VECTRESET_Pos)

SCB AIRCR: VECTRESET Mask

Definition at line 452 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_AIRCR_VECTRESET_Msk   (1UL << SCB_AIRCR_VECTRESET_Pos)

SCB AIRCR: VECTRESET Mask

Definition at line 491 of file core_cm4.h.

#define SCB_AIRCR_VECTRESET_Msk   (1UL << SCB_AIRCR_VECTRESET_Pos)

SCB AIRCR: VECTRESET Mask

Definition at line 535 of file core_cm7.h.

#define SCB_AIRCR_VECTRESET_Pos   0

SCB AIRCR: VECTRESET Position

Definition at line 446 of file core_sc300.h.

#define SCB_AIRCR_VECTRESET_Pos   0

SCB AIRCR: VECTRESET Position

Definition at line 451 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_AIRCR_VECTRESET_Pos   0

SCB AIRCR: VECTRESET Position

Definition at line 490 of file core_cm4.h.

#define SCB_AIRCR_VECTRESET_Pos   0

SCB AIRCR: VECTRESET Position

Definition at line 534 of file core_cm7.h.

#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

Definition at line 748 of file core_cm7.h.

#define SCB_CACR_ECCEN_Pos   1

SCB CACR: ECCEN Position

Definition at line 747 of file core_cm7.h.

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 745 of file core_cm7.h.

#define SCB_CACR_FORCEWT_Pos   2

SCB CACR: FORCEWT Position

Definition at line 744 of file core_cm7.h.

#define SCB_CACR_SIWT_Msk   (1UL << SCB_CACR_SIWT_Pos)

SCB CACR: SIWT Mask

Definition at line 751 of file core_cm7.h.

#define SCB_CACR_SIWT_Pos   0

SCB CACR: SIWT Position

Definition at line 750 of file core_cm7.h.

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 464 of file core_sc300.h.

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 469 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 508 of file core_cm4.h.

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 561 of file core_cm7.h.

#define SCB_CCR_BFHFNMIGN_Pos   8

SCB CCR: BFHFNMIGN Position

Definition at line 463 of file core_sc300.h.

#define SCB_CCR_BFHFNMIGN_Pos   8

SCB CCR: BFHFNMIGN Position

Definition at line 468 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CCR_BFHFNMIGN_Pos   8

SCB CCR: BFHFNMIGN Position

Definition at line 507 of file core_cm4.h.

#define SCB_CCR_BFHFNMIGN_Pos   8

SCB CCR: BFHFNMIGN Position

Definition at line 560 of file core_cm7.h.

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: Branch prediction enable bit Mask

Definition at line 549 of file core_cm7.h.

#define SCB_CCR_BP_Pos   18

SCB CCR: Branch prediction enable bit Position

Definition at line 548 of file core_cm7.h.

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: Cache enable bit Mask

Definition at line 555 of file core_cm7.h.

#define SCB_CCR_DC_Pos   16

SCB CCR: Cache enable bit Position

Definition at line 554 of file core_cm7.h.

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 467 of file core_sc300.h.

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 472 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 511 of file core_cm4.h.

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 564 of file core_cm7.h.

#define SCB_CCR_DIV_0_TRP_Pos   4

SCB CCR: DIV_0_TRP Position

Definition at line 466 of file core_sc300.h.

#define SCB_CCR_DIV_0_TRP_Pos   4

SCB CCR: DIV_0_TRP Position

Definition at line 471 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CCR_DIV_0_TRP_Pos   4

SCB CCR: DIV_0_TRP Position

Definition at line 510 of file core_cm4.h.

#define SCB_CCR_DIV_0_TRP_Pos   4

SCB CCR: DIV_0_TRP Position

Definition at line 563 of file core_cm7.h.

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: Instruction cache enable bit Mask

Definition at line 552 of file core_cm7.h.

#define SCB_CCR_IC_Pos   17

SCB CCR: Instruction cache enable bit Position

Definition at line 551 of file core_cm7.h.

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL << SCB_CCR_NONBASETHRDENA_Pos)

SCB CCR: NONBASETHRDENA Mask

Definition at line 476 of file core_sc300.h.

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL << SCB_CCR_NONBASETHRDENA_Pos)

SCB CCR: NONBASETHRDENA Mask

Definition at line 481 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL << SCB_CCR_NONBASETHRDENA_Pos)

SCB CCR: NONBASETHRDENA Mask

Definition at line 520 of file core_cm4.h.

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL << SCB_CCR_NONBASETHRDENA_Pos)

SCB CCR: NONBASETHRDENA Mask

Definition at line 573 of file core_cm7.h.

#define SCB_CCR_NONBASETHRDENA_Pos   0

SCB CCR: NONBASETHRDENA Position

Definition at line 475 of file core_sc300.h.

#define SCB_CCR_NONBASETHRDENA_Pos   0

SCB CCR: NONBASETHRDENA Position

Definition at line 480 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CCR_NONBASETHRDENA_Pos   0

SCB CCR: NONBASETHRDENA Position

Definition at line 519 of file core_cm4.h.

#define SCB_CCR_NONBASETHRDENA_Pos   0

SCB CCR: NONBASETHRDENA Position

Definition at line 572 of file core_cm7.h.

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 419 of file core_cm0.h.

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 431 of file core_sc000.h.

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 440 of file core_cm0plus.h.

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 461 of file core_sc300.h.

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 466 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 505 of file core_cm4.h.

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 558 of file core_cm7.h.

#define SCB_CCR_STKALIGN_Pos   9

SCB CCR: STKALIGN Position

Definition at line 418 of file core_cm0.h.

#define SCB_CCR_STKALIGN_Pos   9

SCB CCR: STKALIGN Position

Definition at line 430 of file core_sc000.h.

#define SCB_CCR_STKALIGN_Pos   9

SCB CCR: STKALIGN Position

Definition at line 439 of file core_cm0plus.h.

#define SCB_CCR_STKALIGN_Pos   9

SCB CCR: STKALIGN Position

Definition at line 460 of file core_sc300.h.

#define SCB_CCR_STKALIGN_Pos   9

SCB CCR: STKALIGN Position

Definition at line 465 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CCR_STKALIGN_Pos   9

SCB CCR: STKALIGN Position

Definition at line 504 of file core_cm4.h.

#define SCB_CCR_STKALIGN_Pos   9

SCB CCR: STKALIGN Position

Definition at line 557 of file core_cm7.h.

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 422 of file core_cm0.h.

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 434 of file core_sc000.h.

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 443 of file core_cm0plus.h.

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 470 of file core_sc300.h.

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 475 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 514 of file core_cm4.h.

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 567 of file core_cm7.h.

#define SCB_CCR_UNALIGN_TRP_Pos   3

SCB CCR: UNALIGN_TRP Position

Definition at line 421 of file core_cm0.h.

#define SCB_CCR_UNALIGN_TRP_Pos   3

SCB CCR: UNALIGN_TRP Position

Definition at line 433 of file core_sc000.h.

#define SCB_CCR_UNALIGN_TRP_Pos   3

SCB CCR: UNALIGN_TRP Position

Definition at line 442 of file core_cm0plus.h.

#define SCB_CCR_UNALIGN_TRP_Pos   3

SCB CCR: UNALIGN_TRP Position

Definition at line 469 of file core_sc300.h.

#define SCB_CCR_UNALIGN_TRP_Pos   3

SCB CCR: UNALIGN_TRP Position

Definition at line 474 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CCR_UNALIGN_TRP_Pos   3

SCB CCR: UNALIGN_TRP Position

Definition at line 513 of file core_cm4.h.

#define SCB_CCR_UNALIGN_TRP_Pos   3

SCB CCR: UNALIGN_TRP Position

Definition at line 566 of file core_cm7.h.

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 473 of file core_sc300.h.

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 478 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 517 of file core_cm4.h.

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 570 of file core_cm7.h.

#define SCB_CCR_USERSETMPEND_Pos   1

SCB CCR: USERSETMPEND Position

Definition at line 472 of file core_sc300.h.

#define SCB_CCR_USERSETMPEND_Pos   1

SCB CCR: USERSETMPEND Position

Definition at line 477 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CCR_USERSETMPEND_Pos   1

SCB CCR: USERSETMPEND Position

Definition at line 516 of file core_cm4.h.

#define SCB_CCR_USERSETMPEND_Pos   1

SCB CCR: USERSETMPEND Position

Definition at line 569 of file core_cm7.h.

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 694 of file core_cm7.h.

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3

SCB CCSIDR: Associativity Position

Definition at line 693 of file core_cm7.h.

#define SCB_CCSIDR_LINESIZE_Msk   (7UL << SCB_CCSIDR_LINESIZE_Pos)

SCB CCSIDR: LineSize Mask

Definition at line 697 of file core_cm7.h.

#define SCB_CCSIDR_LINESIZE_Pos   0

SCB CCSIDR: LineSize Position

Definition at line 696 of file core_cm7.h.

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 691 of file core_cm7.h.

#define SCB_CCSIDR_NUMSETS_Pos   13

SCB CCSIDR: NumSets Position

Definition at line 690 of file core_cm7.h.

#define SCB_CCSIDR_RA_Msk   (7UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 685 of file core_cm7.h.

#define SCB_CCSIDR_RA_Pos   29

SCB CCSIDR: RA Position

Definition at line 684 of file core_cm7.h.

#define SCB_CCSIDR_WA_Msk   (7UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 688 of file core_cm7.h.

#define SCB_CCSIDR_WA_Pos   28

SCB CCSIDR: WA Position

Definition at line 687 of file core_cm7.h.

#define SCB_CCSIDR_WB_Msk   (7UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 682 of file core_cm7.h.

#define SCB_CCSIDR_WB_Pos   30

SCB CCSIDR: WB Position

Definition at line 681 of file core_cm7.h.

#define SCB_CCSIDR_WT_Msk   (7UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 679 of file core_cm7.h.

#define SCB_CCSIDR_WT_Pos   31

SCB CCSIDR: WT Position

Definition at line 678 of file core_cm7.h.

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 526 of file core_sc300.h.

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 531 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 570 of file core_cm4.h.

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 623 of file core_cm7.h.

#define SCB_CFSR_BUSFAULTSR_Pos   8

SCB CFSR: Bus Fault Status Register Position

Definition at line 525 of file core_sc300.h.

#define SCB_CFSR_BUSFAULTSR_Pos   8

SCB CFSR: Bus Fault Status Register Position

Definition at line 530 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CFSR_BUSFAULTSR_Pos   8

SCB CFSR: Bus Fault Status Register Position

Definition at line 569 of file core_cm4.h.

#define SCB_CFSR_BUSFAULTSR_Pos   8

SCB CFSR: Bus Fault Status Register Position

Definition at line 622 of file core_cm7.h.

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 529 of file core_sc300.h.

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 534 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 573 of file core_cm4.h.

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 626 of file core_cm7.h.

#define SCB_CFSR_MEMFAULTSR_Pos   0

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 528 of file core_sc300.h.

#define SCB_CFSR_MEMFAULTSR_Pos   0

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 533 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CFSR_MEMFAULTSR_Pos   0

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 572 of file core_cm4.h.

#define SCB_CFSR_MEMFAULTSR_Pos   0

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 625 of file core_cm7.h.

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 523 of file core_sc300.h.

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 528 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 567 of file core_cm4.h.

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 620 of file core_cm7.h.

#define SCB_CFSR_USGFAULTSR_Pos   16

SCB CFSR: Usage Fault Status Register Position

Definition at line 522 of file core_sc300.h.

#define SCB_CFSR_USGFAULTSR_Pos   16

SCB CFSR: Usage Fault Status Register Position

Definition at line 527 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CFSR_USGFAULTSR_Pos   16

SCB CFSR: Usage Fault Status Register Position

Definition at line 566 of file core_cm4.h.

#define SCB_CFSR_USGFAULTSR_Pos   16

SCB CFSR: Usage Fault Status Register Position

Definition at line 619 of file core_cm7.h.

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_FORMAT_Pos)

SCB CLIDR: LoC Mask

Definition at line 659 of file core_cm7.h.

#define SCB_CLIDR_LOC_Pos   24

SCB CLIDR: LoC Position

Definition at line 658 of file core_cm7.h.

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 656 of file core_cm7.h.

#define SCB_CLIDR_LOUU_Pos   27

SCB CLIDR: LoUU Position

Definition at line 655 of file core_cm7.h.

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 355 of file core_cm0.h.

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 363 of file core_sc000.h.

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 370 of file core_cm0plus.h.

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 381 of file core_sc300.h.

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 381 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 428 of file core_cm4.h.

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 472 of file core_cm7.h.

#define SCB_CPUID_ARCHITECTURE_Pos   16

SCB CPUID: ARCHITECTURE Position

Definition at line 354 of file core_cm0.h.

#define SCB_CPUID_ARCHITECTURE_Pos   16

SCB CPUID: ARCHITECTURE Position

Definition at line 362 of file core_sc000.h.

#define SCB_CPUID_ARCHITECTURE_Pos   16

SCB CPUID: ARCHITECTURE Position

Definition at line 369 of file core_cm0plus.h.

#define SCB_CPUID_ARCHITECTURE_Pos   16

SCB CPUID: ARCHITECTURE Position

Definition at line 380 of file core_sc300.h.

#define SCB_CPUID_ARCHITECTURE_Pos   16

SCB CPUID: ARCHITECTURE Position

Definition at line 380 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CPUID_ARCHITECTURE_Pos   16

SCB CPUID: ARCHITECTURE Position

Definition at line 427 of file core_cm4.h.

#define SCB_CPUID_ARCHITECTURE_Pos   16

SCB CPUID: ARCHITECTURE Position

Definition at line 471 of file core_cm7.h.

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 349 of file core_cm0.h.

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 357 of file core_sc000.h.

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 364 of file core_cm0plus.h.

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 375 of file core_sc300.h.

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 375 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 422 of file core_cm4.h.

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 466 of file core_cm7.h.

#define SCB_CPUID_IMPLEMENTER_Pos   24

SCB CPUID: IMPLEMENTER Position

Definition at line 348 of file core_cm0.h.

#define SCB_CPUID_IMPLEMENTER_Pos   24

SCB CPUID: IMPLEMENTER Position

Definition at line 356 of file core_sc000.h.

#define SCB_CPUID_IMPLEMENTER_Pos   24

SCB CPUID: IMPLEMENTER Position

Definition at line 363 of file core_cm0plus.h.

#define SCB_CPUID_IMPLEMENTER_Pos   24

SCB CPUID: IMPLEMENTER Position

Definition at line 374 of file core_sc300.h.

#define SCB_CPUID_IMPLEMENTER_Pos   24

SCB CPUID: IMPLEMENTER Position

Definition at line 374 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CPUID_IMPLEMENTER_Pos   24

SCB CPUID: IMPLEMENTER Position

Definition at line 421 of file core_cm4.h.

#define SCB_CPUID_IMPLEMENTER_Pos   24

SCB CPUID: IMPLEMENTER Position

Definition at line 465 of file core_cm7.h.

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 358 of file core_cm0.h.

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 366 of file core_sc000.h.

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 373 of file core_cm0plus.h.

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 384 of file core_sc300.h.

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 384 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 431 of file core_cm4.h.

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 475 of file core_cm7.h.

#define SCB_CPUID_PARTNO_Pos   4

SCB CPUID: PARTNO Position

Definition at line 357 of file core_cm0.h.

#define SCB_CPUID_PARTNO_Pos   4

SCB CPUID: PARTNO Position

Definition at line 365 of file core_sc000.h.

#define SCB_CPUID_PARTNO_Pos   4

SCB CPUID: PARTNO Position

Definition at line 372 of file core_cm0plus.h.

#define SCB_CPUID_PARTNO_Pos   4

SCB CPUID: PARTNO Position

Definition at line 383 of file core_sc300.h.

#define SCB_CPUID_PARTNO_Pos   4

SCB CPUID: PARTNO Position

Definition at line 383 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CPUID_PARTNO_Pos   4

SCB CPUID: PARTNO Position

Definition at line 430 of file core_cm4.h.

#define SCB_CPUID_PARTNO_Pos   4

SCB CPUID: PARTNO Position

Definition at line 474 of file core_cm7.h.

#define SCB_CPUID_REVISION_Msk   (0xFUL << SCB_CPUID_REVISION_Pos)

SCB CPUID: REVISION Mask

Definition at line 361 of file core_cm0.h.

#define SCB_CPUID_REVISION_Msk   (0xFUL << SCB_CPUID_REVISION_Pos)

SCB CPUID: REVISION Mask

Definition at line 369 of file core_sc000.h.

#define SCB_CPUID_REVISION_Msk   (0xFUL << SCB_CPUID_REVISION_Pos)

SCB CPUID: REVISION Mask

Definition at line 376 of file core_cm0plus.h.

#define SCB_CPUID_REVISION_Msk   (0xFUL << SCB_CPUID_REVISION_Pos)

SCB CPUID: REVISION Mask

Definition at line 387 of file core_sc300.h.

#define SCB_CPUID_REVISION_Msk   (0xFUL << SCB_CPUID_REVISION_Pos)

SCB CPUID: REVISION Mask

Definition at line 387 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CPUID_REVISION_Msk   (0xFUL << SCB_CPUID_REVISION_Pos)

SCB CPUID: REVISION Mask

Definition at line 434 of file core_cm4.h.

#define SCB_CPUID_REVISION_Msk   (0xFUL << SCB_CPUID_REVISION_Pos)

SCB CPUID: REVISION Mask

Definition at line 478 of file core_cm7.h.

#define SCB_CPUID_REVISION_Pos   0

SCB CPUID: REVISION Position

Definition at line 360 of file core_cm0.h.

#define SCB_CPUID_REVISION_Pos   0

SCB CPUID: REVISION Position

Definition at line 368 of file core_sc000.h.

#define SCB_CPUID_REVISION_Pos   0

SCB CPUID: REVISION Position

Definition at line 375 of file core_cm0plus.h.

#define SCB_CPUID_REVISION_Pos   0

SCB CPUID: REVISION Position

Definition at line 386 of file core_sc300.h.

#define SCB_CPUID_REVISION_Pos   0

SCB CPUID: REVISION Position

Definition at line 386 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CPUID_REVISION_Pos   0

SCB CPUID: REVISION Position

Definition at line 433 of file core_cm4.h.

#define SCB_CPUID_REVISION_Pos   0

SCB CPUID: REVISION Position

Definition at line 477 of file core_cm7.h.

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 352 of file core_cm0.h.

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 360 of file core_sc000.h.

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 367 of file core_cm0plus.h.

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 378 of file core_sc300.h.

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 378 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 425 of file core_cm4.h.

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 469 of file core_cm7.h.

#define SCB_CPUID_VARIANT_Pos   20

SCB CPUID: VARIANT Position

Definition at line 351 of file core_cm0.h.

#define SCB_CPUID_VARIANT_Pos   20

SCB CPUID: VARIANT Position

Definition at line 359 of file core_sc000.h.

#define SCB_CPUID_VARIANT_Pos   20

SCB CPUID: VARIANT Position

Definition at line 366 of file core_cm0plus.h.

#define SCB_CPUID_VARIANT_Pos   20

SCB CPUID: VARIANT Position

Definition at line 377 of file core_sc300.h.

#define SCB_CPUID_VARIANT_Pos   20

SCB CPUID: VARIANT Position

Definition at line 377 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_CPUID_VARIANT_Pos   20

SCB CPUID: VARIANT Position

Definition at line 424 of file core_cm4.h.

#define SCB_CPUID_VARIANT_Pos   20

SCB CPUID: VARIANT Position

Definition at line 468 of file core_cm7.h.

#define SCB_CSSELR_IND_Msk   (1UL << SCB_CSSELR_IND_Pos)

SCB CSSELR: InD Mask

Definition at line 704 of file core_cm7.h.

#define SCB_CSSELR_IND_Pos   0

SCB CSSELR: InD Position

Definition at line 703 of file core_cm7.h.

#define SCB_CSSELR_LEVEL_Msk   (1UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 701 of file core_cm7.h.

#define SCB_CSSELR_LEVEL_Pos   0

SCB CSSELR: Level Position

Definition at line 700 of file core_cm7.h.

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 666 of file core_cm7.h.

#define SCB_CTR_CWG_Pos   24

SCB CTR: CWG Position

Definition at line 665 of file core_cm7.h.

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 672 of file core_cm7.h.

#define SCB_CTR_DMINLINE_Pos   16

SCB CTR: DminLine Position

Definition at line 671 of file core_cm7.h.

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 669 of file core_cm7.h.

#define SCB_CTR_ERG_Pos   20

SCB CTR: ERG Position

Definition at line 668 of file core_cm7.h.

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 663 of file core_cm7.h.

#define SCB_CTR_FORMAT_Pos   29

SCB CTR: Format Position

Definition at line 662 of file core_cm7.h.

#define SCB_CTR_IMINLINE_Msk   (0xFUL << SCB_CTR_IMINLINE_Pos)

SCB CTR: ImInLine Mask

Definition at line 675 of file core_cm7.h.

#define SCB_CTR_IMINLINE_Pos   0

SCB CTR: ImInLine Position

Definition at line 674 of file core_cm7.h.

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 552 of file core_sc300.h.

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 557 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 596 of file core_cm4.h.

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 649 of file core_cm7.h.

#define SCB_DFSR_BKPT_Pos   1

SCB DFSR: BKPT Position

Definition at line 551 of file core_sc300.h.

#define SCB_DFSR_BKPT_Pos   1

SCB DFSR: BKPT Position

Definition at line 556 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_DFSR_BKPT_Pos   1

SCB DFSR: BKPT Position

Definition at line 595 of file core_cm4.h.

#define SCB_DFSR_BKPT_Pos   1

SCB DFSR: BKPT Position

Definition at line 648 of file core_cm7.h.

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 549 of file core_sc300.h.

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 554 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 593 of file core_cm4.h.

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 646 of file core_cm7.h.

#define SCB_DFSR_DWTTRAP_Pos   2

SCB DFSR: DWTTRAP Position

Definition at line 548 of file core_sc300.h.

#define SCB_DFSR_DWTTRAP_Pos   2

SCB DFSR: DWTTRAP Position

Definition at line 553 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_DFSR_DWTTRAP_Pos   2

SCB DFSR: DWTTRAP Position

Definition at line 592 of file core_cm4.h.

#define SCB_DFSR_DWTTRAP_Pos   2

SCB DFSR: DWTTRAP Position

Definition at line 645 of file core_cm7.h.

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 543 of file core_sc300.h.

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 548 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 587 of file core_cm4.h.

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 640 of file core_cm7.h.

#define SCB_DFSR_EXTERNAL_Pos   4

SCB DFSR: EXTERNAL Position

Definition at line 542 of file core_sc300.h.

#define SCB_DFSR_EXTERNAL_Pos   4

SCB DFSR: EXTERNAL Position

Definition at line 547 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_DFSR_EXTERNAL_Pos   4

SCB DFSR: EXTERNAL Position

Definition at line 586 of file core_cm4.h.

#define SCB_DFSR_EXTERNAL_Pos   4

SCB DFSR: EXTERNAL Position

Definition at line 639 of file core_cm7.h.

#define SCB_DFSR_HALTED_Msk   (1UL << SCB_DFSR_HALTED_Pos)

SCB DFSR: HALTED Mask

Definition at line 555 of file core_sc300.h.

#define SCB_DFSR_HALTED_Msk   (1UL << SCB_DFSR_HALTED_Pos)

SCB DFSR: HALTED Mask

Definition at line 560 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_DFSR_HALTED_Msk   (1UL << SCB_DFSR_HALTED_Pos)

SCB DFSR: HALTED Mask

Definition at line 599 of file core_cm4.h.

#define SCB_DFSR_HALTED_Msk   (1UL << SCB_DFSR_HALTED_Pos)

SCB DFSR: HALTED Mask

Definition at line 652 of file core_cm7.h.

#define SCB_DFSR_HALTED_Pos   0

SCB DFSR: HALTED Position

Definition at line 554 of file core_sc300.h.

#define SCB_DFSR_HALTED_Pos   0

SCB DFSR: HALTED Position

Definition at line 559 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_DFSR_HALTED_Pos   0

SCB DFSR: HALTED Position

Definition at line 598 of file core_cm4.h.

#define SCB_DFSR_HALTED_Pos   0

SCB DFSR: HALTED Position

Definition at line 651 of file core_cm7.h.

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 546 of file core_sc300.h.

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 551 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 590 of file core_cm4.h.

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 643 of file core_cm7.h.

#define SCB_DFSR_VCATCH_Pos   3

SCB DFSR: VCATCH Position

Definition at line 545 of file core_sc300.h.

#define SCB_DFSR_VCATCH_Pos   3

SCB DFSR: VCATCH Position

Definition at line 550 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_DFSR_VCATCH_Pos   3

SCB DFSR: VCATCH Position

Definition at line 589 of file core_cm4.h.

#define SCB_DFSR_VCATCH_Pos   3

SCB DFSR: VCATCH Position

Definition at line 642 of file core_cm7.h.

#define SCB_DTCMCR_EN_Msk   (1UL << SCB_DTCMCR_EN_Pos)

SCB DTCMCR: EN Mask

Definition at line 734 of file core_cm7.h.

#define SCB_DTCMCR_EN_Pos   0

SCB DTCMCR: EN Position

Definition at line 733 of file core_cm7.h.

#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

Definition at line 728 of file core_cm7.h.

#define SCB_DTCMCR_RETEN_Pos   2

SCB DTCMCR: RETEN Position

Definition at line 727 of file core_cm7.h.

#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

Definition at line 731 of file core_cm7.h.

#define SCB_DTCMCR_RMW_Pos   1

SCB DTCMCR: RMW Position

Definition at line 730 of file core_cm7.h.

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 725 of file core_cm7.h.

#define SCB_DTCMCR_SZ_Pos   3

SCB DTCMCR: SZ Position

Definition at line 724 of file core_cm7.h.

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 533 of file core_sc300.h.

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 538 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 577 of file core_cm4.h.

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 630 of file core_cm7.h.

#define SCB_HFSR_DEBUGEVT_Pos   31

SCB HFSR: DEBUGEVT Position

Definition at line 532 of file core_sc300.h.

#define SCB_HFSR_DEBUGEVT_Pos   31

SCB HFSR: DEBUGEVT Position

Definition at line 537 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_HFSR_DEBUGEVT_Pos   31

SCB HFSR: DEBUGEVT Position

Definition at line 576 of file core_cm4.h.

#define SCB_HFSR_DEBUGEVT_Pos   31

SCB HFSR: DEBUGEVT Position

Definition at line 629 of file core_cm7.h.

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 536 of file core_sc300.h.

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 541 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 580 of file core_cm4.h.

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 633 of file core_cm7.h.

#define SCB_HFSR_FORCED_Pos   30

SCB HFSR: FORCED Position

Definition at line 535 of file core_sc300.h.

#define SCB_HFSR_FORCED_Pos   30

SCB HFSR: FORCED Position

Definition at line 540 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_HFSR_FORCED_Pos   30

SCB HFSR: FORCED Position

Definition at line 579 of file core_cm4.h.

#define SCB_HFSR_FORCED_Pos   30

SCB HFSR: FORCED Position

Definition at line 632 of file core_cm7.h.

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 539 of file core_sc300.h.

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 544 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 583 of file core_cm4.h.

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 636 of file core_cm7.h.

#define SCB_HFSR_VECTTBL_Pos   1

SCB HFSR: VECTTBL Position

Definition at line 538 of file core_sc300.h.

#define SCB_HFSR_VECTTBL_Pos   1

SCB HFSR: VECTTBL Position

Definition at line 543 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_HFSR_VECTTBL_Pos   1

SCB HFSR: VECTTBL Position

Definition at line 582 of file core_cm4.h.

#define SCB_HFSR_VECTTBL_Pos   1

SCB HFSR: VECTTBL Position

Definition at line 635 of file core_cm7.h.

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 383 of file core_cm0.h.

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 391 of file core_sc000.h.

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 398 of file core_cm0plus.h.

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 409 of file core_sc300.h.

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 409 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 456 of file core_cm4.h.

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 500 of file core_cm7.h.

#define SCB_ICSR_ISRPENDING_Pos   22

SCB ICSR: ISRPENDING Position

Definition at line 382 of file core_cm0.h.

#define SCB_ICSR_ISRPENDING_Pos   22

SCB ICSR: ISRPENDING Position

Definition at line 390 of file core_sc000.h.

#define SCB_ICSR_ISRPENDING_Pos   22

SCB ICSR: ISRPENDING Position

Definition at line 397 of file core_cm0plus.h.

#define SCB_ICSR_ISRPENDING_Pos   22

SCB ICSR: ISRPENDING Position

Definition at line 408 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_ISRPENDING_Pos   22

SCB ICSR: ISRPENDING Position

Definition at line 408 of file core_sc300.h.

#define SCB_ICSR_ISRPENDING_Pos   22

SCB ICSR: ISRPENDING Position

Definition at line 455 of file core_cm4.h.

#define SCB_ICSR_ISRPENDING_Pos   22

SCB ICSR: ISRPENDING Position

Definition at line 499 of file core_cm7.h.

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 380 of file core_cm0.h.

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 388 of file core_sc000.h.

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 395 of file core_cm0plus.h.

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 406 of file core_sc300.h.

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 406 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 453 of file core_cm4.h.

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 497 of file core_cm7.h.

#define SCB_ICSR_ISRPREEMPT_Pos   23

SCB ICSR: ISRPREEMPT Position

Definition at line 379 of file core_cm0.h.

#define SCB_ICSR_ISRPREEMPT_Pos   23

SCB ICSR: ISRPREEMPT Position

Definition at line 387 of file core_sc000.h.

#define SCB_ICSR_ISRPREEMPT_Pos   23

SCB ICSR: ISRPREEMPT Position

Definition at line 394 of file core_cm0plus.h.

#define SCB_ICSR_ISRPREEMPT_Pos   23

SCB ICSR: ISRPREEMPT Position

Definition at line 405 of file core_sc300.h.

#define SCB_ICSR_ISRPREEMPT_Pos   23

SCB ICSR: ISRPREEMPT Position

Definition at line 405 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_ISRPREEMPT_Pos   23

SCB ICSR: ISRPREEMPT Position

Definition at line 452 of file core_cm4.h.

#define SCB_ICSR_ISRPREEMPT_Pos   23

SCB ICSR: ISRPREEMPT Position

Definition at line 496 of file core_cm7.h.

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 365 of file core_cm0.h.

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 373 of file core_sc000.h.

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 380 of file core_cm0plus.h.

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 391 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 391 of file core_sc300.h.

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 438 of file core_cm4.h.

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 482 of file core_cm7.h.

#define SCB_ICSR_NMIPENDSET_Pos   31

SCB ICSR: NMIPENDSET Position

Definition at line 364 of file core_cm0.h.

#define SCB_ICSR_NMIPENDSET_Pos   31

SCB ICSR: NMIPENDSET Position

Definition at line 372 of file core_sc000.h.

#define SCB_ICSR_NMIPENDSET_Pos   31

SCB ICSR: NMIPENDSET Position

Definition at line 379 of file core_cm0plus.h.

#define SCB_ICSR_NMIPENDSET_Pos   31

SCB ICSR: NMIPENDSET Position

Definition at line 390 of file core_sc300.h.

#define SCB_ICSR_NMIPENDSET_Pos   31

SCB ICSR: NMIPENDSET Position

Definition at line 390 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_NMIPENDSET_Pos   31

SCB ICSR: NMIPENDSET Position

Definition at line 437 of file core_cm4.h.

#define SCB_ICSR_NMIPENDSET_Pos   31

SCB ICSR: NMIPENDSET Position

Definition at line 481 of file core_cm7.h.

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 377 of file core_cm0.h.

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 385 of file core_sc000.h.

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 392 of file core_cm0plus.h.

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 403 of file core_sc300.h.

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 403 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 450 of file core_cm4.h.

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 494 of file core_cm7.h.

#define SCB_ICSR_PENDSTCLR_Pos   25

SCB ICSR: PENDSTCLR Position

Definition at line 376 of file core_cm0.h.

#define SCB_ICSR_PENDSTCLR_Pos   25

SCB ICSR: PENDSTCLR Position

Definition at line 384 of file core_sc000.h.

#define SCB_ICSR_PENDSTCLR_Pos   25

SCB ICSR: PENDSTCLR Position

Definition at line 391 of file core_cm0plus.h.

#define SCB_ICSR_PENDSTCLR_Pos   25

SCB ICSR: PENDSTCLR Position

Definition at line 402 of file core_sc300.h.

#define SCB_ICSR_PENDSTCLR_Pos   25

SCB ICSR: PENDSTCLR Position

Definition at line 402 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_PENDSTCLR_Pos   25

SCB ICSR: PENDSTCLR Position

Definition at line 449 of file core_cm4.h.

#define SCB_ICSR_PENDSTCLR_Pos   25

SCB ICSR: PENDSTCLR Position

Definition at line 493 of file core_cm7.h.

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 374 of file core_cm0.h.

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 382 of file core_sc000.h.

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 389 of file core_cm0plus.h.

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 400 of file core_sc300.h.

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 400 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 447 of file core_cm4.h.

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 491 of file core_cm7.h.

#define SCB_ICSR_PENDSTSET_Pos   26

SCB ICSR: PENDSTSET Position

Definition at line 373 of file core_cm0.h.

#define SCB_ICSR_PENDSTSET_Pos   26

SCB ICSR: PENDSTSET Position

Definition at line 381 of file core_sc000.h.

#define SCB_ICSR_PENDSTSET_Pos   26

SCB ICSR: PENDSTSET Position

Definition at line 388 of file core_cm0plus.h.

#define SCB_ICSR_PENDSTSET_Pos   26

SCB ICSR: PENDSTSET Position

Definition at line 399 of file core_sc300.h.

#define SCB_ICSR_PENDSTSET_Pos   26

SCB ICSR: PENDSTSET Position

Definition at line 399 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_PENDSTSET_Pos   26

SCB ICSR: PENDSTSET Position

Definition at line 446 of file core_cm4.h.

#define SCB_ICSR_PENDSTSET_Pos   26

SCB ICSR: PENDSTSET Position

Definition at line 490 of file core_cm7.h.

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 371 of file core_cm0.h.

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 379 of file core_sc000.h.

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 386 of file core_cm0plus.h.

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 397 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 397 of file core_sc300.h.

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 444 of file core_cm4.h.

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 488 of file core_cm7.h.

#define SCB_ICSR_PENDSVCLR_Pos   27

SCB ICSR: PENDSVCLR Position

Definition at line 370 of file core_cm0.h.

#define SCB_ICSR_PENDSVCLR_Pos   27

SCB ICSR: PENDSVCLR Position

Definition at line 378 of file core_sc000.h.

#define SCB_ICSR_PENDSVCLR_Pos   27

SCB ICSR: PENDSVCLR Position

Definition at line 385 of file core_cm0plus.h.

#define SCB_ICSR_PENDSVCLR_Pos   27

SCB ICSR: PENDSVCLR Position

Definition at line 396 of file core_sc300.h.

#define SCB_ICSR_PENDSVCLR_Pos   27

SCB ICSR: PENDSVCLR Position

Definition at line 396 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_PENDSVCLR_Pos   27

SCB ICSR: PENDSVCLR Position

Definition at line 443 of file core_cm4.h.

#define SCB_ICSR_PENDSVCLR_Pos   27

SCB ICSR: PENDSVCLR Position

Definition at line 487 of file core_cm7.h.

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 368 of file core_cm0.h.

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 376 of file core_sc000.h.

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 383 of file core_cm0plus.h.

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 394 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 394 of file core_sc300.h.

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 441 of file core_cm4.h.

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 485 of file core_cm7.h.

#define SCB_ICSR_PENDSVSET_Pos   28

SCB ICSR: PENDSVSET Position

Definition at line 367 of file core_cm0.h.

#define SCB_ICSR_PENDSVSET_Pos   28

SCB ICSR: PENDSVSET Position

Definition at line 375 of file core_sc000.h.

#define SCB_ICSR_PENDSVSET_Pos   28

SCB ICSR: PENDSVSET Position

Definition at line 382 of file core_cm0plus.h.

#define SCB_ICSR_PENDSVSET_Pos   28

SCB ICSR: PENDSVSET Position

Definition at line 393 of file core_sc300.h.

#define SCB_ICSR_PENDSVSET_Pos   28

SCB ICSR: PENDSVSET Position

Definition at line 393 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_PENDSVSET_Pos   28

SCB ICSR: PENDSVSET Position

Definition at line 440 of file core_cm4.h.

#define SCB_ICSR_PENDSVSET_Pos   28

SCB ICSR: PENDSVSET Position

Definition at line 484 of file core_cm7.h.

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 415 of file core_sc300.h.

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 415 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 462 of file core_cm4.h.

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 506 of file core_cm7.h.

#define SCB_ICSR_RETTOBASE_Pos   11

SCB ICSR: RETTOBASE Position

Definition at line 414 of file core_sc300.h.

#define SCB_ICSR_RETTOBASE_Pos   11

SCB ICSR: RETTOBASE Position

Definition at line 414 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_RETTOBASE_Pos   11

SCB ICSR: RETTOBASE Position

Definition at line 461 of file core_cm4.h.

#define SCB_ICSR_RETTOBASE_Pos   11

SCB ICSR: RETTOBASE Position

Definition at line 505 of file core_cm7.h.

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)

SCB ICSR: VECTACTIVE Mask

Definition at line 389 of file core_cm0.h.

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)

SCB ICSR: VECTACTIVE Mask

Definition at line 397 of file core_sc000.h.

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)

SCB ICSR: VECTACTIVE Mask

Definition at line 404 of file core_cm0plus.h.

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)

SCB ICSR: VECTACTIVE Mask

Definition at line 418 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)

SCB ICSR: VECTACTIVE Mask

Definition at line 418 of file core_sc300.h.

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)

SCB ICSR: VECTACTIVE Mask

Definition at line 465 of file core_cm4.h.

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)

SCB ICSR: VECTACTIVE Mask

Definition at line 509 of file core_cm7.h.

#define SCB_ICSR_VECTACTIVE_Pos   0

SCB ICSR: VECTACTIVE Position

Definition at line 388 of file core_cm0.h.

#define SCB_ICSR_VECTACTIVE_Pos   0

SCB ICSR: VECTACTIVE Position

Definition at line 396 of file core_sc000.h.

#define SCB_ICSR_VECTACTIVE_Pos   0

SCB ICSR: VECTACTIVE Position

Definition at line 403 of file core_cm0plus.h.

#define SCB_ICSR_VECTACTIVE_Pos   0

SCB ICSR: VECTACTIVE Position

Definition at line 417 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_VECTACTIVE_Pos   0

SCB ICSR: VECTACTIVE Position

Definition at line 417 of file core_sc300.h.

#define SCB_ICSR_VECTACTIVE_Pos   0

SCB ICSR: VECTACTIVE Position

Definition at line 464 of file core_cm4.h.

#define SCB_ICSR_VECTACTIVE_Pos   0

SCB ICSR: VECTACTIVE Position

Definition at line 508 of file core_cm7.h.

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 386 of file core_cm0.h.

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 394 of file core_sc000.h.

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 401 of file core_cm0plus.h.

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 412 of file core_sc300.h.

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 412 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 459 of file core_cm4.h.

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 503 of file core_cm7.h.

#define SCB_ICSR_VECTPENDING_Pos   12

SCB ICSR: VECTPENDING Position

Definition at line 385 of file core_cm0.h.

#define SCB_ICSR_VECTPENDING_Pos   12

SCB ICSR: VECTPENDING Position

Definition at line 393 of file core_sc000.h.

#define SCB_ICSR_VECTPENDING_Pos   12

SCB ICSR: VECTPENDING Position

Definition at line 400 of file core_cm0plus.h.

#define SCB_ICSR_VECTPENDING_Pos   12

SCB ICSR: VECTPENDING Position

Definition at line 411 of file core_sc300.h.

#define SCB_ICSR_VECTPENDING_Pos   12

SCB ICSR: VECTPENDING Position

Definition at line 411 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_ICSR_VECTPENDING_Pos   12

SCB ICSR: VECTPENDING Position

Definition at line 458 of file core_cm4.h.

#define SCB_ICSR_VECTPENDING_Pos   12

SCB ICSR: VECTPENDING Position

Definition at line 502 of file core_cm7.h.

#define SCB_ITCMCR_EN_Msk   (1FFUL << SCB_ITCMCR_EN_Pos)

SCB ITCMCR: EN Mask

Definition at line 721 of file core_cm7.h.

#define SCB_ITCMCR_EN_Pos   0

SCB ITCMCR: EN Position

Definition at line 720 of file core_cm7.h.

#define SCB_ITCMCR_RETEN_Msk   (1FFUL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

Definition at line 715 of file core_cm7.h.

#define SCB_ITCMCR_RETEN_Pos   2

SCB ITCMCR: RETEN Position

Definition at line 714 of file core_cm7.h.

#define SCB_ITCMCR_RMW_Msk   (1FFUL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

Definition at line 718 of file core_cm7.h.

#define SCB_ITCMCR_RMW_Pos   1

SCB ITCMCR: RMW Position

Definition at line 717 of file core_cm7.h.

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 712 of file core_cm7.h.

#define SCB_ITCMCR_SZ_Pos   3

SCB ITCMCR: SZ Position

Definition at line 711 of file core_cm7.h.

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 409 of file core_cm0.h.

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 421 of file core_sc000.h.

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 430 of file core_cm0plus.h.

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 451 of file core_sc300.h.

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 456 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 495 of file core_cm4.h.

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 539 of file core_cm7.h.

#define SCB_SCR_SEVONPEND_Pos   4

SCB SCR: SEVONPEND Position

Definition at line 408 of file core_cm0.h.

#define SCB_SCR_SEVONPEND_Pos   4

SCB SCR: SEVONPEND Position

Definition at line 420 of file core_sc000.h.

#define SCB_SCR_SEVONPEND_Pos   4

SCB SCR: SEVONPEND Position

Definition at line 429 of file core_cm0plus.h.

#define SCB_SCR_SEVONPEND_Pos   4

SCB SCR: SEVONPEND Position

Definition at line 450 of file core_sc300.h.

#define SCB_SCR_SEVONPEND_Pos   4

SCB SCR: SEVONPEND Position

Definition at line 455 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SCR_SEVONPEND_Pos   4

SCB SCR: SEVONPEND Position

Definition at line 494 of file core_cm4.h.

#define SCB_SCR_SEVONPEND_Pos   4

SCB SCR: SEVONPEND Position

Definition at line 538 of file core_cm7.h.

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 412 of file core_cm0.h.

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 424 of file core_sc000.h.

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 433 of file core_cm0plus.h.

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 454 of file core_sc300.h.

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 459 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 498 of file core_cm4.h.

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 542 of file core_cm7.h.

#define SCB_SCR_SLEEPDEEP_Pos   2

SCB SCR: SLEEPDEEP Position

Definition at line 411 of file core_cm0.h.

#define SCB_SCR_SLEEPDEEP_Pos   2

SCB SCR: SLEEPDEEP Position

Definition at line 423 of file core_sc000.h.

#define SCB_SCR_SLEEPDEEP_Pos   2

SCB SCR: SLEEPDEEP Position

Definition at line 432 of file core_cm0plus.h.

#define SCB_SCR_SLEEPDEEP_Pos   2

SCB SCR: SLEEPDEEP Position

Definition at line 453 of file core_sc300.h.

#define SCB_SCR_SLEEPDEEP_Pos   2

SCB SCR: SLEEPDEEP Position

Definition at line 458 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SCR_SLEEPDEEP_Pos   2

SCB SCR: SLEEPDEEP Position

Definition at line 497 of file core_cm4.h.

#define SCB_SCR_SLEEPDEEP_Pos   2

SCB SCR: SLEEPDEEP Position

Definition at line 541 of file core_cm7.h.

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 415 of file core_cm0.h.

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 427 of file core_sc000.h.

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 436 of file core_cm0plus.h.

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 457 of file core_sc300.h.

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 462 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 501 of file core_cm4.h.

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 545 of file core_cm7.h.

#define SCB_SCR_SLEEPONEXIT_Pos   1

SCB SCR: SLEEPONEXIT Position

Definition at line 414 of file core_cm0.h.

#define SCB_SCR_SLEEPONEXIT_Pos   1

SCB SCR: SLEEPONEXIT Position

Definition at line 426 of file core_sc000.h.

#define SCB_SCR_SLEEPONEXIT_Pos   1

SCB SCR: SLEEPONEXIT Position

Definition at line 435 of file core_cm0plus.h.

#define SCB_SCR_SLEEPONEXIT_Pos   1

SCB SCR: SLEEPONEXIT Position

Definition at line 456 of file core_sc300.h.

#define SCB_SCR_SLEEPONEXIT_Pos   1

SCB SCR: SLEEPONEXIT Position

Definition at line 461 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SCR_SLEEPONEXIT_Pos   1

SCB SCR: SLEEPONEXIT Position

Definition at line 500 of file core_cm4.h.

#define SCB_SCR_SLEEPONEXIT_Pos   1

SCB SCR: SLEEPONEXIT Position

Definition at line 544 of file core_cm7.h.

#define SCB_SFCR_SECKEY_Msk   (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SFCR: SECKEY Mask

Definition at line 445 of file core_sc000.h.

#define SCB_SFCR_SECKEY_Pos   16

SCB SFCR: SECKEY Position

Definition at line 444 of file core_sc000.h.

#define SCB_SFCR_UNIBRTIMING_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SFCR: UNIBRTIMING Mask

Definition at line 442 of file core_sc000.h.

#define SCB_SFCR_UNIBRTIMING_Pos   0

SCB SFCR: UNIBRTIMING Position

Definition at line 441 of file core_sc000.h.

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 516 of file core_sc300.h.

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 521 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 560 of file core_cm4.h.

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 613 of file core_cm7.h.

#define SCB_SHCSR_BUSFAULTACT_Pos   1

SCB SHCSR: BUSFAULTACT Position

Definition at line 515 of file core_sc300.h.

#define SCB_SHCSR_BUSFAULTACT_Pos   1

SCB SHCSR: BUSFAULTACT Position

Definition at line 520 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_BUSFAULTACT_Pos   1

SCB SHCSR: BUSFAULTACT Position

Definition at line 559 of file core_cm4.h.

#define SCB_SHCSR_BUSFAULTACT_Pos   1

SCB SHCSR: BUSFAULTACT Position

Definition at line 612 of file core_cm7.h.

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 483 of file core_sc300.h.

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 488 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 527 of file core_cm4.h.

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 580 of file core_cm7.h.

#define SCB_SHCSR_BUSFAULTENA_Pos   17

SCB SHCSR: BUSFAULTENA Position

Definition at line 482 of file core_sc300.h.

#define SCB_SHCSR_BUSFAULTENA_Pos   17

SCB SHCSR: BUSFAULTENA Position

Definition at line 487 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_BUSFAULTENA_Pos   17

SCB SHCSR: BUSFAULTENA Position

Definition at line 526 of file core_cm4.h.

#define SCB_SHCSR_BUSFAULTENA_Pos   17

SCB SHCSR: BUSFAULTENA Position

Definition at line 579 of file core_cm7.h.

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 492 of file core_sc300.h.

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 497 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 536 of file core_cm4.h.

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 589 of file core_cm7.h.

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 491 of file core_sc300.h.

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 496 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 535 of file core_cm4.h.

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 588 of file core_cm7.h.

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL << SCB_SHCSR_MEMFAULTACT_Pos)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 519 of file core_sc300.h.

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL << SCB_SHCSR_MEMFAULTACT_Pos)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 524 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL << SCB_SHCSR_MEMFAULTACT_Pos)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 563 of file core_cm4.h.

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL << SCB_SHCSR_MEMFAULTACT_Pos)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 616 of file core_cm7.h.

#define SCB_SHCSR_MEMFAULTACT_Pos   0

SCB SHCSR: MEMFAULTACT Position

Definition at line 518 of file core_sc300.h.

#define SCB_SHCSR_MEMFAULTACT_Pos   0

SCB SHCSR: MEMFAULTACT Position

Definition at line 523 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_MEMFAULTACT_Pos   0

SCB SHCSR: MEMFAULTACT Position

Definition at line 562 of file core_cm4.h.

#define SCB_SHCSR_MEMFAULTACT_Pos   0

SCB SHCSR: MEMFAULTACT Position

Definition at line 615 of file core_cm7.h.

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 486 of file core_sc300.h.

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 491 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 530 of file core_cm4.h.

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 583 of file core_cm7.h.

#define SCB_SHCSR_MEMFAULTENA_Pos   16

SCB SHCSR: MEMFAULTENA Position

Definition at line 485 of file core_sc300.h.

#define SCB_SHCSR_MEMFAULTENA_Pos   16

SCB SHCSR: MEMFAULTENA Position

Definition at line 490 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_MEMFAULTENA_Pos   16

SCB SHCSR: MEMFAULTENA Position

Definition at line 529 of file core_cm4.h.

#define SCB_SHCSR_MEMFAULTENA_Pos   16

SCB SHCSR: MEMFAULTENA Position

Definition at line 582 of file core_cm7.h.

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 495 of file core_sc300.h.

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 500 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 539 of file core_cm4.h.

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 592 of file core_cm7.h.

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 494 of file core_sc300.h.

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 499 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 538 of file core_cm4.h.

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 591 of file core_cm7.h.

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 507 of file core_sc300.h.

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 512 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 551 of file core_cm4.h.

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 604 of file core_cm7.h.

#define SCB_SHCSR_MONITORACT_Pos   8

SCB SHCSR: MONITORACT Position

Definition at line 506 of file core_sc300.h.

#define SCB_SHCSR_MONITORACT_Pos   8

SCB SHCSR: MONITORACT Position

Definition at line 511 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_MONITORACT_Pos   8

SCB SHCSR: MONITORACT Position

Definition at line 550 of file core_cm4.h.

#define SCB_SHCSR_MONITORACT_Pos   8

SCB SHCSR: MONITORACT Position

Definition at line 603 of file core_cm7.h.

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 504 of file core_sc300.h.

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 509 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 548 of file core_cm4.h.

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 601 of file core_cm7.h.

#define SCB_SHCSR_PENDSVACT_Pos   10

SCB SHCSR: PENDSVACT Position

Definition at line 503 of file core_sc300.h.

#define SCB_SHCSR_PENDSVACT_Pos   10

SCB SHCSR: PENDSVACT Position

Definition at line 508 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_PENDSVACT_Pos   10

SCB SHCSR: PENDSVACT Position

Definition at line 547 of file core_cm4.h.

#define SCB_SHCSR_PENDSVACT_Pos   10

SCB SHCSR: PENDSVACT Position

Definition at line 600 of file core_cm7.h.

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 510 of file core_sc300.h.

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 515 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 554 of file core_cm4.h.

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 607 of file core_cm7.h.

#define SCB_SHCSR_SVCALLACT_Pos   7

SCB SHCSR: SVCALLACT Position

Definition at line 509 of file core_sc300.h.

#define SCB_SHCSR_SVCALLACT_Pos   7

SCB SHCSR: SVCALLACT Position

Definition at line 514 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_SVCALLACT_Pos   7

SCB SHCSR: SVCALLACT Position

Definition at line 553 of file core_cm4.h.

#define SCB_SHCSR_SVCALLACT_Pos   7

SCB SHCSR: SVCALLACT Position

Definition at line 606 of file core_cm7.h.

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 426 of file core_cm0.h.

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 438 of file core_sc000.h.

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 447 of file core_cm0plus.h.

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 489 of file core_sc300.h.

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 494 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 533 of file core_cm4.h.

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 586 of file core_cm7.h.

#define SCB_SHCSR_SVCALLPENDED_Pos   15

SCB SHCSR: SVCALLPENDED Position

Definition at line 425 of file core_cm0.h.

#define SCB_SHCSR_SVCALLPENDED_Pos   15

SCB SHCSR: SVCALLPENDED Position

Definition at line 437 of file core_sc000.h.

#define SCB_SHCSR_SVCALLPENDED_Pos   15

SCB SHCSR: SVCALLPENDED Position

Definition at line 446 of file core_cm0plus.h.

#define SCB_SHCSR_SVCALLPENDED_Pos   15

SCB SHCSR: SVCALLPENDED Position

Definition at line 488 of file core_sc300.h.

#define SCB_SHCSR_SVCALLPENDED_Pos   15

SCB SHCSR: SVCALLPENDED Position

Definition at line 493 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_SVCALLPENDED_Pos   15

SCB SHCSR: SVCALLPENDED Position

Definition at line 532 of file core_cm4.h.

#define SCB_SHCSR_SVCALLPENDED_Pos   15

SCB SHCSR: SVCALLPENDED Position

Definition at line 585 of file core_cm7.h.

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 501 of file core_sc300.h.

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 506 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 545 of file core_cm4.h.

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 598 of file core_cm7.h.

#define SCB_SHCSR_SYSTICKACT_Pos   11

SCB SHCSR: SYSTICKACT Position

Definition at line 500 of file core_sc300.h.

#define SCB_SHCSR_SYSTICKACT_Pos   11

SCB SHCSR: SYSTICKACT Position

Definition at line 505 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_SYSTICKACT_Pos   11

SCB SHCSR: SYSTICKACT Position

Definition at line 544 of file core_cm4.h.

#define SCB_SHCSR_SYSTICKACT_Pos   11

SCB SHCSR: SYSTICKACT Position

Definition at line 597 of file core_cm7.h.

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 513 of file core_sc300.h.

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 518 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 557 of file core_cm4.h.

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 610 of file core_cm7.h.

#define SCB_SHCSR_USGFAULTACT_Pos   3

SCB SHCSR: USGFAULTACT Position

Definition at line 512 of file core_sc300.h.

#define SCB_SHCSR_USGFAULTACT_Pos   3

SCB SHCSR: USGFAULTACT Position

Definition at line 517 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_USGFAULTACT_Pos   3

SCB SHCSR: USGFAULTACT Position

Definition at line 556 of file core_cm4.h.

#define SCB_SHCSR_USGFAULTACT_Pos   3

SCB SHCSR: USGFAULTACT Position

Definition at line 609 of file core_cm7.h.

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 480 of file core_sc300.h.

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 485 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 524 of file core_cm4.h.

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 577 of file core_cm7.h.

#define SCB_SHCSR_USGFAULTENA_Pos   18

SCB SHCSR: USGFAULTENA Position

Definition at line 479 of file core_sc300.h.

#define SCB_SHCSR_USGFAULTENA_Pos   18

SCB SHCSR: USGFAULTENA Position

Definition at line 484 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_USGFAULTENA_Pos   18

SCB SHCSR: USGFAULTENA Position

Definition at line 523 of file core_cm4.h.

#define SCB_SHCSR_USGFAULTENA_Pos   18

SCB SHCSR: USGFAULTENA Position

Definition at line 576 of file core_cm7.h.

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 498 of file core_sc300.h.

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 503 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 542 of file core_cm4.h.

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 595 of file core_cm7.h.

#define SCB_SHCSR_USGFAULTPENDED_Pos   12

SCB SHCSR: USGFAULTPENDED Position

Definition at line 497 of file core_sc300.h.

#define SCB_SHCSR_USGFAULTPENDED_Pos   12

SCB SHCSR: USGFAULTPENDED Position

Definition at line 502 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_SHCSR_USGFAULTPENDED_Pos   12

SCB SHCSR: USGFAULTPENDED Position

Definition at line 541 of file core_cm4.h.

#define SCB_SHCSR_USGFAULTPENDED_Pos   12

SCB SHCSR: USGFAULTPENDED Position

Definition at line 594 of file core_cm7.h.

#define SCB_STIR_INTID_Msk   (0x1FFUL << SCB_STIR_INTID_Pos)

SCB STIR: INTID Mask

Definition at line 708 of file core_cm7.h.

#define SCB_STIR_INTID_Pos   0

SCB STIR: INTID Position

Definition at line 707 of file core_cm7.h.

#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)

SCB VTOR: TBLBASE Mask

Definition at line 422 of file core_sc300.h.

#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)

SCB VTOR: TBLBASE Mask

Definition at line 423 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_VTOR_TBLBASE_Pos   29

SCB VTOR: TBLBASE Position

Definition at line 421 of file core_sc300.h.

#define SCB_VTOR_TBLBASE_Pos   29

SCB VTOR: TBLBASE Position

Definition at line 422 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 401 of file core_sc000.h.

#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 425 of file core_sc300.h.

#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 426 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 469 of file core_cm4.h.

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 513 of file core_cm7.h.

#define SCB_VTOR_TBLOFF_Pos   7

SCB VTOR: TBLOFF Position

Definition at line 400 of file core_sc000.h.

#define SCB_VTOR_TBLOFF_Pos   7

SCB VTOR: TBLOFF Position

Definition at line 424 of file core_sc300.h.

#define SCB_VTOR_TBLOFF_Pos   7

SCB VTOR: TBLOFF Position

Definition at line 425 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define SCB_VTOR_TBLOFF_Pos   7

SCB VTOR: TBLOFF Position

Definition at line 468 of file core_cm4.h.

#define SCB_VTOR_TBLOFF_Pos   7

SCB VTOR: TBLOFF Position

Definition at line 512 of file core_cm7.h.


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Apr 15 2021 05:07:53