Structure type to access the Core Debug Register (CoreDebug). More...
#include <core_cm3.h>
Public Attributes | |
__IO uint32_t | DCRDR |
__O uint32_t | DCRSR |
__IO uint32_t | DEMCR |
__IO uint32_t | DHCSR |
Structure type to access the Core Debug Register (CoreDebug).
Definition at line 1152 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
__IO uint32_t CoreDebug_Type::DCRDR |
Offset: 0x008 (R/W) Debug Core Register Data Register
Offset: 0x08 Debug Core Register Data Register
Definition at line 1156 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
__O uint32_t CoreDebug_Type::DCRSR |
Offset: 0x004 ( /W) Debug Core Register Selector Register
Offset: 0x04 Debug Core Register Selector Register
Definition at line 1155 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
__IO uint32_t CoreDebug_Type::DEMCR |
Offset: 0x00C (R/W) Debug Exception and Monitor Control Register
Offset: 0x0C Debug Exception and Monitor Control Register
Definition at line 1157 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
__IO uint32_t CoreDebug_Type::DHCSR |
Offset: 0x000 (R/W) Debug Halting Control and Status Register
Offset: 0x00 Debug Halting Control and Status Register
Definition at line 1154 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.