73 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) 76 #define CR_OFFSET (RCC_OFFSET + 0x00) 77 #define HSION_BitNumber 0x00 78 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) 80 #define CSSON_BitNumber 0x13 81 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) 83 #define PLLON_BitNumber 0x18 84 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) 86 #define PLLI2SON_BitNumber 0x1A 87 #define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) 90 #define PLLSAION_BitNumber 0x1C 91 #define CR_PLLSAION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4)) 95 #define CFGR_OFFSET (RCC_OFFSET + 0x08) 96 #define I2SSRC_BitNumber 0x17 97 #define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) 101 #define BDCR_OFFSET (RCC_OFFSET + 0x70) 102 #define RTCEN_BitNumber 0x0F 103 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) 105 #define BDRST_BitNumber 0x10 106 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) 110 #define CSR_OFFSET (RCC_OFFSET + 0x74) 111 #define LSION_BitNumber 0x00 112 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) 116 #define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C) 117 #define TIMPRE_BitNumber 0x18 118 #define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4)) 121 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08) 122 #if defined(STM32F410xx) 124 #define RCC_MCO1EN_BIT_NUMBER 0x8 125 #define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4)) 128 #define RCC_MCO2EN_BIT_NUMBER 0x9 129 #define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4)) 133 #define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF) 134 #define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF) 137 #define FLAG_MASK ((uint8_t)0x1F) 140 #define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) 143 #define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) 146 #define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) 149 #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) 153 static __I uint8_t
APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
228 RCC->CR |= (uint32_t)0x00000001;
231 RCC->CFGR = 0x00000000;
234 RCC->CR &= (uint32_t)0xEAF6FFFF;
237 RCC->PLLCFGR = 0x24003010;
239 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469_479xx) 241 RCC->PLLI2SCFGR = 0x20003000;
244 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) 246 RCC->PLLSAICFGR = 0x24003000;
250 RCC->CR &= (uint32_t)0xFFFBFFFF;
253 RCC->CIR = 0x00000000;
256 RCC->DCKCFGR = 0x00000000;
258 #if defined(STM32F410xx) 260 RCC->DCKCFGR2 = 0x00000000;
310 __IO uint32_t startupcounter = 0;
351 tmpreg |= (uint32_t)HSICalibrationValue << 3;
448 #if defined(STM32F410xx) || defined(STM32F446xx) || defined(STM32F469_479xx) 488 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR)
498 RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
499 (PLLQ << 24) | (PLLR << 28);
503 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) 539 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
548 RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
570 #if defined(STM32F40_41xxx) || defined(STM32F401xx) 599 RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
603 #if defined(STM32F411xE) 638 RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28) | PLLI2SM;
642 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) 674 RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SQ << 24) | (PLLI2SR << 28);
678 #if defined(STM32F446xx) 713 void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR)
722 RCC->PLLI2SCFGR = PLLI2SM | (PLLI2SN << 6) | (((PLLI2SP >> 1) -1) << 16) | (PLLI2SQ << 24) | (PLLI2SR << 28);
739 #if defined(STM32F469_479xx) 765 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR)
773 RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIP << 16) | (PLLSAIQ << 24) | (PLLSAIR << 28);
777 #if defined(STM32F446xx) 806 void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ)
814 RCC->PLLSAICFGR = PLLSAIM | (PLLSAIN << 6) | (((PLLSAIP >> 1) -1) << 16) | (PLLSAIQ << 24);
818 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) 841 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR)
848 RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIQ << 24) | (PLLSAIR << 28);
918 tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
923 #if defined(STM32F410xx) 963 tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
968 #if defined(STM32F410xx) 1151 uint32_t tmpreg = 0;
1162 tmpreg |= RCC_SYSCLKSource;
1205 uint32_t tmpreg = 0;
1216 tmpreg |= RCC_SYSCLK;
1236 uint32_t tmpreg = 0;
1267 uint32_t tmpreg = 0;
1278 tmpreg |= RCC_HCLK << 3;
1319 uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
1320 #if defined(STM32F446xx) 1358 #if defined(STM32F446xx) 1377 pllr = (((
RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2;
1472 uint32_t tmpreg = 0;
1477 if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
1485 tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);
1492 RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);
1526 #if defined(STM32F446xx) 1551 if(RCC_I2SAPBx == RCC_I2SBus_APB1)
1554 RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S1SRC;
1556 RCC->DCKCFGR |= RCC_I2SCLKSource;
1561 RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S2SRC;
1563 RCC->DCKCFGR |= (RCC_I2SCLKSource << 2);
1584 void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource)
1590 if(RCC_SAIInstance == RCC_SAIInstance_SAI1)
1593 RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI1SRC;
1595 RCC->DCKCFGR |= RCC_SAICLKSource;
1600 RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI2SRC;
1602 RCC->DCKCFGR |= (RCC_SAICLKSource << 2);
1607 #if defined(STM32F410xx) 1625 RCC->DCKCFGR &= ~RCC_DCKCFGR_I2SSRC;
1627 RCC->DCKCFGR |= RCC_I2SCLKSource;
1631 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx) 1651 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) 1669 void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource)
1671 uint32_t tmpreg = 0;
1674 assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource));
1676 tmpreg =
RCC->DCKCFGR;
1682 tmpreg |= RCC_SAIBlockACLKSource;
1685 RCC->DCKCFGR = tmpreg;
1705 void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource)
1707 uint32_t tmpreg = 0;
1710 assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource));
1712 tmpreg =
RCC->DCKCFGR;
1718 tmpreg |= RCC_SAIBlockBCLKSource;
1721 RCC->DCKCFGR = tmpreg;
1740 uint32_t tmpreg = 0;
1745 tmpreg =
RCC->DCKCFGR;
1751 tmpreg |= (RCC_PLLI2SDivQ - 1);
1754 RCC->DCKCFGR = tmpreg;
1772 uint32_t tmpreg = 0;
1777 tmpreg =
RCC->DCKCFGR;
1783 tmpreg |= ((RCC_PLLSAIDivQ - 1) << 8);
1786 RCC->DCKCFGR = tmpreg;
1808 uint32_t tmpreg = 0;
1813 tmpreg =
RCC->DCKCFGR;
1819 tmpreg |= RCC_PLLSAIDivR;
1822 RCC->DCKCFGR = tmpreg;
1893 RCC->AHB1ENR |= RCC_AHB1Periph;
1897 RCC->AHB1ENR &= ~RCC_AHB1Periph;
1925 RCC->AHB2ENR |= RCC_AHB2Periph;
1929 RCC->AHB2ENR &= ~RCC_AHB2Periph;
1933 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) 1955 RCC->AHB3ENR |= RCC_AHB3Periph;
1959 RCC->AHB3ENR &= ~RCC_AHB3Periph;
2012 RCC->APB1ENR |= RCC_APB1Periph;
2016 RCC->APB1ENR &= ~RCC_APB1Periph;
2059 RCC->APB2ENR |= RCC_APB2Periph;
2063 RCC->APB2ENR &= ~RCC_APB2Periph;
2102 RCC->AHB1RSTR |= RCC_AHB1Periph;
2106 RCC->AHB1RSTR &= ~RCC_AHB1Periph;
2131 RCC->AHB2RSTR |= RCC_AHB2Periph;
2135 RCC->AHB2RSTR &= ~RCC_AHB2Periph;
2139 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) 2158 RCC->AHB3RSTR |= RCC_AHB3Periph;
2162 RCC->AHB3RSTR &= ~RCC_AHB3Periph;
2211 RCC->APB1RSTR |= RCC_APB1Periph;
2215 RCC->APB1RSTR &= ~RCC_APB1Periph;
2254 RCC->APB2RSTR |= RCC_APB2Periph;
2258 RCC->APB2RSTR &= ~RCC_APB2Periph;
2303 RCC->AHB1LPENR |= RCC_AHB1Periph;
2307 RCC->AHB1LPENR &= ~RCC_AHB1Periph;
2335 RCC->AHB2LPENR |= RCC_AHB2Periph;
2339 RCC->AHB2LPENR &= ~RCC_AHB2Periph;
2343 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) 2365 RCC->AHB3LPENR |= RCC_AHB3Periph;
2369 RCC->AHB3LPENR &= ~RCC_AHB3Periph;
2422 RCC->APB1LPENR |= RCC_APB1Periph;
2426 RCC->APB1LPENR &= ~RCC_APB1Periph;
2469 RCC->APB2LPENR |= RCC_APB2Periph;
2473 RCC->APB2LPENR &= ~RCC_APB2Periph;
2501 #if defined(STM32F410xx) 2513 void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource)
2516 assert_param(IS_RCC_LPTIM1_CLOCKSOURCE(RCC_ClockSource));
2519 RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_LPTIM1SEL;
2521 RCC->DCKCFGR2 |= RCC_ClockSource;
2525 #if defined(STM32F469_479xx) 2535 void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource)
2540 if(RCC_ClockSource == RCC_DSICLKSource_PLLR)
2551 #if defined(STM32F446xx) || defined(STM32F469_479xx) 2561 void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource)
2564 assert_param(IS_RCC_48MHZ_CLOCKSOURCE(RCC_ClockSource));
2565 #if defined(STM32F469_479xx) 2566 if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI)
2574 #elif defined(STM32F446xx) 2575 if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI)
2577 SET_BIT(
RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL);
2596 void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource)
2599 assert_param(IS_RCC_SDIO_CLOCKSOURCE(RCC_ClockSource));
2600 #if defined(STM32F469_479xx) 2601 if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK)
2609 #elif defined(STM32F446xx) 2610 if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK)
2612 SET_BIT(
RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL);
2623 #if defined(STM32F446xx) 2640 void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating,
FunctionalState NewState)
2643 assert_param(IS_RCC_AHB1_CLOCKGATING(RCC_AHB1ClockGating));
2648 RCC->CKGATENR &= ~RCC_AHB1ClockGating;
2652 RCC->CKGATENR |= RCC_AHB1ClockGating;
2665 void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource)
2668 assert_param(IS_RCC_SPDIFRX_CLOCKSOURCE(RCC_ClockSource));
2670 if(RCC_ClockSource == RCC_SPDIFRXCLKSource_PLLI2SP)
2672 SET_BIT(
RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL);
2689 void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource)
2694 if(RCC_ClockSource == RCC_CECCLKSource_LSE)
2705 #if defined(STM32F410xx) || defined(STM32F446xx) 2716 void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource)
2719 assert_param(IS_RCC_FMPI2C1_CLOCKSOURCE(RCC_ClockSource));
2722 RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_FMPI2C1SEL;
2724 RCC->DCKCFGR2 |= RCC_ClockSource;
2731 #if defined(STM32F410xx) 2743 *(
__IO uint32_t *) RCC_CFGR_MCO1EN_BB = (uint32_t)NewState;
2757 *(
__IO uint32_t *) RCC_CFGR_MCO2EN_BB = (uint32_t)NewState;
2828 uint32_t statusreg = 0;
2835 tmp = RCC_FLAG >> 5;
2838 statusreg =
RCC->CR;
2842 statusreg =
RCC->BDCR;
2846 statusreg =
RCC->CSR;
2851 if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)
RESET)
2898 if ((
RCC->CIR & RCC_IT) != (uint32_t)
RESET)
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
#define IS_RCC_APB1_PERIPH(PERIPH)
#define RCC_DCKCFGR_PLLSAIDIVR
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
Selects the clock source to output on MCO2 pin(PC9).
#define IS_RCC_PLLI2SQ_VALUE(VALUE)
#define IS_RCC_PLLQ_VALUE(VALUE)
void RCC_PLLSAICmd(FunctionalState NewState)
Enables or disables the PLLSAI.
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the Low Speed APB (APB1) peripheral clock.
ErrorStatus RCC_WaitForHSEStartUp(void)
Waits for HSE start-up.
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
Configures the RTC clock (RTCCLK).
#define IS_RCC_HCLK(HCLK)
#define CIR_BYTE3_ADDRESS
#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH)
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
Configures the main PLL clock source, multiplication and division factors.
#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH)
#define IS_RCC_MCO2SOURCE(SOURCE)
#define IS_RCC_PLLM_VALUE(VALUE)
#define IS_RCC_RTCCLK_SOURCE(SOURCE)
#define IS_RCC_PLLSAIN_VALUE(VALUE)
#define RCC_DCKCFGR_SAI1BSRC
#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE)
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Forces or releases AHB1 peripheral reset.
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
Configures the system clock (SYSCLK).
void assert_param(int val)
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Enables or disables the AHB1 peripheral clock.
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the High Speed APB (APB2) peripheral clock.
#define IS_RCC_MCO2DIV(DIV)
void RCC_BackupResetCmd(FunctionalState NewState)
Forces or releases the Backup domain reset.
#define CFGR_MCO2_RESET_MASK
#define IS_RCC_CLEAR_IT(IT)
#define IS_FUNCTIONAL_STATE(STATE)
static volatile uint8_t * status
#define IS_RCC_PLLN_VALUE(VALUE)
#define IS_RCC_PLLSAIQ_VALUE(VALUE)
#define HSE_STARTUP_TIMEOUT
Comment the line below if you will not use the peripherals drivers. In this case, these drivers will ...
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
#define RCC_DCKCFGR_SAI1ASRC
void RCC_LSEModeConfig(uint8_t RCC_Mode)
Configures the External Low Speed oscillator mode (LSE mode).
#define IS_RCC_GET_IT(IT)
#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE)
void RCC_PLLCmd(FunctionalState NewState)
Enables or disables the main PLL.
#define RCC_PLLCFGR_PLLSRC
#define IS_RCC_CALIBRATION_VALUE(VALUE)
ITStatus RCC_GetITStatus(uint8_t RCC_IT)
Checks whether the specified RCC interrupt has occurred or not.
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Enables or disables the AHB2 peripheral clock.
#define IS_RCC_PLLP_VALUE(VALUE)
#define IS_RCC_APB2_RESET_PERIPH(PERIPH)
void RCC_LSEConfig(uint8_t RCC_LSE)
Configures the External Low Speed oscillator (LSE).
#define IS_RCC_PLLSAIR_VALUE(VALUE)
#define IS_RCC_APB2_PERIPH(PERIPH)
void RCC_RTCCLKCmd(FunctionalState NewState)
Enables or disables the RTC clock.
#define HSE_VALUE
Comment the line below if you will not use the peripherals drivers. In this case, these drivers will ...
#define DCKCFGR_TIMPRE_BB
void RCC_PCLK1Config(uint32_t RCC_HCLK)
Configures the Low Speed APB clock (PCLK1).
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
Configures the I2S clock source (I2SCLK).
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
Configures the PLLI2S clock multiplication and division factors.
void RCC_LSICmd(FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
#define IS_RCC_PLLI2SR_VALUE(VALUE)
static __I uint8_t APBAHBPrescTable[16]
void RCC_DeInit(void)
Resets the RCC clock configuration to the default reset state.
void RCC_HSICmd(FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Forces or releases AHB3 peripheral reset.
#define IS_RCC_MCO1DIV(DIV)
void RCC_PCLK2Config(uint32_t RCC_HCLK)
Configures the High Speed APB clock (PCLK2).
void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR)
Configures the LTDC clock Divider coming from PLLSAI.
#define IS_RCC_LSE_MODE(MODE)
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
#define IS_RCC_SYSCLK_SOURCE(SOURCE)
void RCC_ClearFlag(void)
Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
Enables or disables the Clock Security System.
void RCC_PLLI2SCmd(FunctionalState NewState)
Enables or disables the PLLI2S.
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Enables or disables the AHB3 peripheral clock.
#define CIR_BYTE2_ADDRESS
#define RCC_DCKCFGR_PLLSAIDIVQ
void RCC_HSEConfig(uint8_t RCC_HSE)
Configures the External High Speed oscillator (HSE).
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
#define IS_RCC_I2SCLK_SOURCE(SOURCE)
#define IS_RCC_TIMCLK_PRESCALER(VALUE)
void RCC_ClearITPendingBit(uint8_t RCC_IT)
Clears the RCC's interrupt pending bits.
#define IS_RCC_FLAG(FLAG)
#define IS_RCC_MCO1SOURCE(SOURCE)
#define IS_RCC_PCLK(PCLK)
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
Checks whether the specified RCC flag is set or not.
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
Enables or disables the specified RCC interrupts.
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
uint32_t SYSCLK_Frequency
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
Selects the clock source to output on MCO1 pin(PA8).
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.
#define RCC_LSE_HIGHDRIVE_MODE
uint8_t RCC_GetSYSCLKSource(void)
Returns the clock source used as system clock.
#define SET_BIT(REG, BIT)
#define IS_RCC_PLLI2SM_VALUE(VALUE)
#define IS_RCC_AHB3_PERIPH(PERIPH)
#define IS_RCC_AHB2_PERIPH(PERIPH)
#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE)
void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ)
Configures the SAI clock Divider coming from PLLSAI.
void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ)
Configures the SAI clock Divider coming from PLLI2S.
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Forces or releases AHB2 peripheral reset.
#define CLEAR_BIT(REG, BIT)
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
Configures the AHB clock (HCLK).
#define CFGR_MCO1_RESET_MASK
#define IS_RCC_PLLI2SN_VALUE(VALUE)
#define IS_RCC_PLL_SOURCE(SOURCE)
#define RCC_DCKCFGR_PLLI2SDIVQ
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
#define IS_RCC_AHB1_RESET_PERIPH(PERIPH)
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
Configures the Timers clocks prescalers selection.