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| #define | ADC ((ADC_Common_TypeDef *) ADC_BASE) |
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| #define | ADC1 ((ADC_TypeDef *) ADC1_BASE) |
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| #define | ADC1 ((ADC_TypeDef *) ADC1_BASE) |
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| #define | ADC2 ((ADC_TypeDef *) ADC2_BASE) |
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| #define | ADC2 ((ADC_TypeDef *) ADC2_BASE) |
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| #define | ADC3 ((ADC_TypeDef *) ADC3_BASE) |
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| #define | ADC3 ((ADC_TypeDef *) ADC3_BASE) |
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| #define | AFIO ((AFIO_TypeDef *) AFIO_BASE) |
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| #define | BKP ((BKP_TypeDef *) BKP_BASE) |
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| #define | CAN1 ((CAN_TypeDef *) CAN1_BASE) |
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| #define | CAN1 ((CAN_TypeDef *) CAN1_BASE) |
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| #define | CAN2 ((CAN_TypeDef *) CAN2_BASE) |
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| #define | CAN2 ((CAN_TypeDef *) CAN2_BASE) |
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| #define | CEC ((CEC_TypeDef *) CEC_BASE) |
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| #define | CRC ((CRC_TypeDef *) CRC_BASE) |
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| #define | CRC ((CRC_TypeDef *) CRC_BASE) |
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| #define | CRYP ((CRYP_TypeDef *) CRYP_BASE) |
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| #define | DAC ((DAC_TypeDef *) DAC_BASE) |
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| #define | DAC ((DAC_TypeDef *) DAC_BASE) |
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| #define | DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
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| #define | DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
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| #define | DCMI ((DCMI_TypeDef *) DCMI_BASE) |
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| #define | DMA1 ((DMA_TypeDef *) DMA1_BASE) |
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| #define | DMA1 ((DMA_TypeDef *) DMA1_BASE) |
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| #define | DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) |
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| #define | DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) |
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| #define | DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) |
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| #define | DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) |
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| #define | DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) |
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| #define | DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) |
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| #define | DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) |
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| #define | DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) |
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| #define | DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) |
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| #define | DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) |
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| #define | DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) |
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| #define | DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) |
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| #define | DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) |
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| #define | DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) |
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| #define | DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) |
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| #define | DMA2 ((DMA_TypeDef *) DMA2_BASE) |
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| #define | DMA2 ((DMA_TypeDef *) DMA2_BASE) |
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| #define | DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) |
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| #define | DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) |
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| #define | DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) |
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| #define | DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) |
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| #define | DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) |
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| #define | DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) |
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| #define | DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) |
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| #define | DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) |
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| #define | DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) |
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| #define | DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) |
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| #define | DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) |
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| #define | DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) |
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| #define | DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) |
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| #define | DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) |
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| #define | ETH ((ETH_TypeDef *) ETH_BASE) |
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| #define | ETH ((ETH_TypeDef *) ETH_BASE) |
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| #define | EXTI ((EXTI_TypeDef *) EXTI_BASE) |
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| #define | EXTI ((EXTI_TypeDef *) EXTI_BASE) |
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| #define | FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
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| #define | FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
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| #define | FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) |
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| #define | FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) |
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| #define | FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) |
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| #define | FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) |
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| #define | FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) |
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| #define | GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
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| #define | GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
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| #define | GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
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| #define | GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
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| #define | GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
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| #define | GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
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| #define | GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
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| #define | GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
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| #define | GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
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| #define | GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
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| #define | GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
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| #define | GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
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| #define | GPIOG ((GPIO_TypeDef *) GPIOG_BASE) |
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| #define | GPIOG ((GPIO_TypeDef *) GPIOG_BASE) |
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| #define | GPIOH ((GPIO_TypeDef *) GPIOH_BASE) |
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| #define | GPIOI ((GPIO_TypeDef *) GPIOI_BASE) |
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| #define | GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) |
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| #define | GPIOK ((GPIO_TypeDef *) GPIOK_BASE) |
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| #define | HASH ((HASH_TypeDef *) HASH_BASE) |
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| #define | HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) |
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| #define | I2C1 ((I2C_TypeDef *) I2C1_BASE) |
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| #define | I2C1 ((I2C_TypeDef *) I2C1_BASE) |
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| #define | I2C2 ((I2C_TypeDef *) I2C2_BASE) |
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| #define | I2C2 ((I2C_TypeDef *) I2C2_BASE) |
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| #define | I2C3 ((I2C_TypeDef *) I2C3_BASE) |
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| #define | I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) |
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| #define | I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) |
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| #define | IWDG ((IWDG_TypeDef *) IWDG_BASE) |
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| #define | IWDG ((IWDG_TypeDef *) IWDG_BASE) |
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| #define | LTDC ((LTDC_TypeDef *)LTDC_BASE) |
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| #define | LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) |
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| #define | LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) |
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| #define | OB ((OB_TypeDef *) OB_BASE) |
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| #define | PWR ((PWR_TypeDef *) PWR_BASE) |
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| #define | PWR ((PWR_TypeDef *) PWR_BASE) |
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| #define | RCC ((RCC_TypeDef *) RCC_BASE) |
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| #define | RCC ((RCC_TypeDef *) RCC_BASE) |
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| #define | RNG ((RNG_TypeDef *) RNG_BASE) |
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| #define | RTC ((RTC_TypeDef *) RTC_BASE) |
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| #define | RTC ((RTC_TypeDef *) RTC_BASE) |
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| #define | SAI1 ((SAI_TypeDef *) SAI1_BASE) |
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| #define | SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) |
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| #define | SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) |
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| #define | SDIO ((SDIO_TypeDef *) SDIO_BASE) |
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| #define | SDIO ((SDIO_TypeDef *) SDIO_BASE) |
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| #define | SPI1 ((SPI_TypeDef *) SPI1_BASE) |
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| #define | SPI1 ((SPI_TypeDef *) SPI1_BASE) |
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| #define | SPI2 ((SPI_TypeDef *) SPI2_BASE) |
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| #define | SPI2 ((SPI_TypeDef *) SPI2_BASE) |
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| #define | SPI3 ((SPI_TypeDef *) SPI3_BASE) |
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| #define | SPI3 ((SPI_TypeDef *) SPI3_BASE) |
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| #define | SPI4 ((SPI_TypeDef *) SPI4_BASE) |
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| #define | SPI5 ((SPI_TypeDef *) SPI5_BASE) |
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| #define | SPI6 ((SPI_TypeDef *) SPI6_BASE) |
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| #define | SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) |
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| #define | TIM1 ((TIM_TypeDef *) TIM1_BASE) |
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| #define | TIM1 ((TIM_TypeDef *) TIM1_BASE) |
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| #define | TIM10 ((TIM_TypeDef *) TIM10_BASE) |
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| #define | TIM10 ((TIM_TypeDef *) TIM10_BASE) |
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| #define | TIM11 ((TIM_TypeDef *) TIM11_BASE) |
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| #define | TIM11 ((TIM_TypeDef *) TIM11_BASE) |
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| #define | TIM12 ((TIM_TypeDef *) TIM12_BASE) |
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| #define | TIM12 ((TIM_TypeDef *) TIM12_BASE) |
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| #define | TIM13 ((TIM_TypeDef *) TIM13_BASE) |
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| #define | TIM13 ((TIM_TypeDef *) TIM13_BASE) |
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| #define | TIM14 ((TIM_TypeDef *) TIM14_BASE) |
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| #define | TIM14 ((TIM_TypeDef *) TIM14_BASE) |
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| #define | TIM15 ((TIM_TypeDef *) TIM15_BASE) |
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| #define | TIM16 ((TIM_TypeDef *) TIM16_BASE) |
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| #define | TIM17 ((TIM_TypeDef *) TIM17_BASE) |
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| #define | TIM2 ((TIM_TypeDef *) TIM2_BASE) |
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| #define | TIM2 ((TIM_TypeDef *) TIM2_BASE) |
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| #define | TIM3 ((TIM_TypeDef *) TIM3_BASE) |
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| #define | TIM3 ((TIM_TypeDef *) TIM3_BASE) |
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| #define | TIM4 ((TIM_TypeDef *) TIM4_BASE) |
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| #define | TIM4 ((TIM_TypeDef *) TIM4_BASE) |
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| #define | TIM5 ((TIM_TypeDef *) TIM5_BASE) |
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| #define | TIM5 ((TIM_TypeDef *) TIM5_BASE) |
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| #define | TIM6 ((TIM_TypeDef *) TIM6_BASE) |
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| #define | TIM6 ((TIM_TypeDef *) TIM6_BASE) |
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| #define | TIM7 ((TIM_TypeDef *) TIM7_BASE) |
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| #define | TIM7 ((TIM_TypeDef *) TIM7_BASE) |
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| #define | TIM8 ((TIM_TypeDef *) TIM8_BASE) |
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| #define | TIM8 ((TIM_TypeDef *) TIM8_BASE) |
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| #define | TIM9 ((TIM_TypeDef *) TIM9_BASE) |
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| #define | TIM9 ((TIM_TypeDef *) TIM9_BASE) |
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| #define | UART4 ((USART_TypeDef *) UART4_BASE) |
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| #define | UART4 ((USART_TypeDef *) UART4_BASE) |
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| #define | UART5 ((USART_TypeDef *) UART5_BASE) |
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| #define | UART5 ((USART_TypeDef *) UART5_BASE) |
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| #define | UART7 ((USART_TypeDef *) UART7_BASE) |
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| #define | UART8 ((USART_TypeDef *) UART8_BASE) |
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| #define | USART1 ((USART_TypeDef *) USART1_BASE) |
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| #define | USART1 ((USART_TypeDef *) USART1_BASE) |
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| #define | USART2 ((USART_TypeDef *) USART2_BASE) |
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| #define | USART2 ((USART_TypeDef *) USART2_BASE) |
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| #define | USART3 ((USART_TypeDef *) USART3_BASE) |
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| #define | USART3 ((USART_TypeDef *) USART3_BASE) |
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| #define | USART6 ((USART_TypeDef *) USART6_BASE) |
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| #define | WWDG ((WWDG_TypeDef *) WWDG_BASE) |
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| #define | WWDG ((WWDG_TypeDef *) WWDG_BASE) |
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