stm32f4xx_spi.c
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1 
158 /* Includes ------------------------------------------------------------------*/
159 #include "stm32f4xx_spi.h"
160 #include "stm32f4xx_rcc.h"
161 
171 /* Private typedef -----------------------------------------------------------*/
172 /* Private define ------------------------------------------------------------*/
173 
174 /* SPI registers Masks */
175 #define CR1_CLEAR_MASK ((uint16_t)0x3040)
176 #define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040)
177 
178 /* RCC PLLs masks */
179 #define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000)
180 #define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0)
181 
182 #define SPI_CR2_FRF ((uint16_t)0x0010)
183 #define SPI_SR_TIFRFE ((uint16_t)0x0100)
184 
185 /* Private macro -------------------------------------------------------------*/
186 /* Private variables ---------------------------------------------------------*/
187 /* Private function prototypes -----------------------------------------------*/
188 /* Private functions ---------------------------------------------------------*/
189 
225 {
226  /* Check the parameters */
228 
229  if (SPIx == SPI1)
230  {
231  /* Enable SPI1 reset state */
233  /* Release SPI1 from reset state */
235  }
236  else if (SPIx == SPI2)
237  {
238  /* Enable SPI2 reset state */
240  /* Release SPI2 from reset state */
242  }
243  else if (SPIx == SPI3)
244  {
245  /* Enable SPI3 reset state */
247  /* Release SPI3 from reset state */
249  }
250  else if (SPIx == SPI4)
251  {
252  /* Enable SPI4 reset state */
254  /* Release SPI4 from reset state */
256  }
257  else if (SPIx == SPI5)
258  {
259  /* Enable SPI5 reset state */
261  /* Release SPI5 from reset state */
263  }
264  else
265  {
266  if (SPIx == SPI6)
267  {
268  /* Enable SPI6 reset state */
270  /* Release SPI6 from reset state */
272  }
273  }
274 }
275 
284 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
285 {
286  uint16_t tmpreg = 0;
287 
288  /* check the parameters */
290 
291  /* Check the SPI parameters */
293  assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
294  assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
295  assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
296  assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
297  assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
299  assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
301 
302 /*---------------------------- SPIx CR1 Configuration ------------------------*/
303  /* Get the SPIx CR1 value */
304  tmpreg = SPIx->CR1;
305  /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
306  tmpreg &= CR1_CLEAR_MASK;
307  /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
308  master/salve mode, CPOL and CPHA */
309  /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
310  /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
311  /* Set LSBFirst bit according to SPI_FirstBit value */
312  /* Set BR bits according to SPI_BaudRatePrescaler value */
313  /* Set CPOL bit according to SPI_CPOL value */
314  /* Set CPHA bit according to SPI_CPHA value */
315  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
316  SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
317  SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
318  SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
319  /* Write to SPIx CR1 */
320  SPIx->CR1 = tmpreg;
321 
322  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
323  SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
324 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
325  /* Write to SPIx CRCPOLY */
326  SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
327 }
328 
348 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
349 {
350  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
351  uint32_t tmp = 0, i2sclk = 0;
352 #ifndef I2S_EXTERNAL_CLOCK_VAL
353  uint32_t pllm = 0, plln = 0, pllr = 0;
354 #endif /* I2S_EXTERNAL_CLOCK_VAL */
355 
356  /* Check the I2S parameters */
358  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
359  assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
362  assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
363  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
364 
365 /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
366  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
367  SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK;
368  SPIx->I2SPR = 0x0002;
369 
370  /* Get the I2SCFGR register value */
371  tmpreg = SPIx->I2SCFGR;
372 
373  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
374  if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
375  {
376  i2sodd = (uint16_t)0;
377  i2sdiv = (uint16_t)2;
378  }
379  /* If the requested audio frequency is not the default, compute the prescaler */
380  else
381  {
382  /* Check the frame length (For the Prescaler computing) *******************/
383  if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
384  {
385  /* Packet length is 16 bits */
386  packetlength = 1;
387  }
388  else
389  {
390  /* Packet length is 32 bits */
391  packetlength = 2;
392  }
393 
394  /* Get I2S source Clock frequency ****************************************/
395 
396  /* If an external I2S clock has to be used, this define should be set
397  in the project configuration or in the stm32f4xx_conf.h file */
398  #ifdef I2S_EXTERNAL_CLOCK_VAL
399  /* Set external clock as I2S clock source */
400  if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0)
401  {
402  RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
403  }
404 
405  /* Set the I2S clock to the external clock value */
406  i2sclk = I2S_EXTERNAL_CLOCK_VAL;
407 
408  #else /* There is no define for External I2S clock source */
409  /* Set PLLI2S as I2S clock source */
410  if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0)
411  {
412  RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;
413  }
414 
415  /* Get the PLLI2SN value */
416  plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \
417  (RCC_PLLI2SCFGR_PLLI2SN >> 6));
418 
419  /* Get the PLLI2SR value */
420  pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \
421  (RCC_PLLI2SCFGR_PLLI2SR >> 28));
422 
423  /* Get the PLLM value */
424  pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
425 
426  /* Get the I2S source clock value */
427  i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr);
428  #endif /* I2S_EXTERNAL_CLOCK_VAL */
429 
430  /* Compute the Real divider depending on the MCLK output state, with a floating point */
431  if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
432  {
433  /* MCLK output is enabled */
434  tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
435  }
436  else
437  {
438  /* MCLK output is disabled */
439  tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
440  }
441 
442  /* Remove the flatting point */
443  tmp = tmp / 10;
444 
445  /* Check the parity of the divider */
446  i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
447 
448  /* Compute the i2sdiv prescaler */
449  i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
450 
451  /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
452  i2sodd = (uint16_t) (i2sodd << 8);
453  }
454 
455  /* Test if the divider is 1 or 0 or greater than 0xFF */
456  if ((i2sdiv < 2) || (i2sdiv > 0xFF))
457  {
458  /* Set the default values */
459  i2sdiv = 2;
460  i2sodd = 0;
461  }
462 
463  /* Write to SPIx I2SPR register the computed value */
464  SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
465 
466  /* Configure the I2S with the SPI_InitStruct values */
467  tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
468  (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
469  (uint16_t)I2S_InitStruct->I2S_CPOL))));
470 
471  /* Write to SPIx I2SCFGR */
472  SPIx->I2SCFGR = tmpreg;
473 }
474 
480 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
481 {
482 /*--------------- Reset SPI init structure parameters values -----------------*/
483  /* Initialize the SPI_Direction member */
485  /* initialize the SPI_Mode member */
486  SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
487  /* initialize the SPI_DataSize member */
488  SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
489  /* Initialize the SPI_CPOL member */
490  SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
491  /* Initialize the SPI_CPHA member */
492  SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
493  /* Initialize the SPI_NSS member */
494  SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
495  /* Initialize the SPI_BaudRatePrescaler member */
497  /* Initialize the SPI_FirstBit member */
498  SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
499  /* Initialize the SPI_CRCPolynomial member */
500  SPI_InitStruct->SPI_CRCPolynomial = 7;
501 }
502 
508 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
509 {
510 /*--------------- Reset I2S init structure parameters values -----------------*/
511  /* Initialize the I2S_Mode member */
512  I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
513 
514  /* Initialize the I2S_Standard member */
515  I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
516 
517  /* Initialize the I2S_DataFormat member */
518  I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
519 
520  /* Initialize the I2S_MCLKOutput member */
521  I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
522 
523  /* Initialize the I2S_AudioFreq member */
524  I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
525 
526  /* Initialize the I2S_CPOL member */
527  I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
528 }
529 
537 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
538 {
539  /* Check the parameters */
542  if (NewState != DISABLE)
543  {
544  /* Enable the selected SPI peripheral */
545  SPIx->CR1 |= SPI_CR1_SPE;
546  }
547  else
548  {
549  /* Disable the selected SPI peripheral */
550  SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
551  }
552 }
553 
562 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
563 {
564  /* Check the parameters */
567 
568  if (NewState != DISABLE)
569  {
570  /* Enable the selected SPI peripheral (in I2S mode) */
571  SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
572  }
573  else
574  {
575  /* Disable the selected SPI peripheral in I2S mode */
576  SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
577  }
578 }
579 
589 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
590 {
591  /* Check the parameters */
593  assert_param(IS_SPI_DATASIZE(SPI_DataSize));
594  /* Clear DFF bit */
595  SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
596  /* Set new DFF bit value */
597  SPIx->CR1 |= SPI_DataSize;
598 }
599 
609 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
610 {
611  /* Check the parameters */
613  assert_param(IS_SPI_DIRECTION(SPI_Direction));
614  if (SPI_Direction == SPI_Direction_Tx)
615  {
616  /* Set the Tx only mode */
617  SPIx->CR1 |= SPI_Direction_Tx;
618  }
619  else
620  {
621  /* Set the Rx only mode */
622  SPIx->CR1 &= SPI_Direction_Rx;
623  }
624 }
625 
635 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
636 {
637  /* Check the parameters */
639  assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
640  if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
641  {
642  /* Set NSS pin internally by software */
643  SPIx->CR1 |= SPI_NSSInternalSoft_Set;
644  }
645  else
646  {
647  /* Reset NSS pin internally by software */
649  }
650 }
651 
660 {
661  /* Check the parameters */
664  if (NewState != DISABLE)
665  {
666  /* Enable the selected SPI SS output */
667  SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;
668  }
669  else
670  {
671  /* Disable the selected SPI SS output */
672  SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
673  }
674 }
675 
691 {
692  /* Check the parameters */
695 
696  if (NewState != DISABLE)
697  {
698  /* Enable the TI mode for the selected SPI peripheral */
699  SPIx->CR2 |= SPI_CR2_FRF;
700  }
701  else
702  {
703  /* Disable the TI mode for the selected SPI peripheral */
704  SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF;
705  }
706 }
707 
727 void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct)
728 {
729  uint16_t tmpreg = 0, tmp = 0;
730 
731  /* Check the I2S parameters */
733  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
734  assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
736  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
737 
738 /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
739  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
740  I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK;
741  I2Sxext->I2SPR = 0x0002;
742 
743  /* Get the I2SCFGR register value */
744  tmpreg = I2Sxext->I2SCFGR;
745 
746  /* Get the mode to be configured for the extended I2S */
747  if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx))
748  {
749  tmp = I2S_Mode_SlaveRx;
750  }
751  else
752  {
753  if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx))
754  {
755  tmp = I2S_Mode_SlaveTx;
756  }
757  }
758 
759 
760  /* Configure the I2S with the SPI_InitStruct values */
761  tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
762  (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
763  (uint16_t)I2S_InitStruct->I2S_CPOL))));
764 
765  /* Write to SPIx I2SCFGR */
766  I2Sxext->I2SCFGR = tmpreg;
767 }
768 
802 {
803  /* Check the parameters */
805 
806  /* Return the data in the DR register */
807  return SPIx->DR;
808 }
809 
817 void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
818 {
819  /* Check the parameters */
821 
822  /* Write in the DR register the data to be sent */
823  SPIx->DR = Data;
824 }
825 
908 {
909  /* Check the parameters */
912  if (NewState != DISABLE)
913  {
914  /* Enable the selected SPI CRC calculation */
915  SPIx->CR1 |= SPI_CR1_CRCEN;
916  }
917  else
918  {
919  /* Disable the selected SPI CRC calculation */
920  SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
921  }
922 }
923 
930 {
931  /* Check the parameters */
933 
934  /* Enable the selected SPI CRC transmission */
935  SPIx->CR1 |= SPI_CR1_CRCNEXT;
936 }
937 
947 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
948 {
949  uint16_t crcreg = 0;
950  /* Check the parameters */
952  assert_param(IS_SPI_CRC(SPI_CRC));
953  if (SPI_CRC != SPI_CRC_Rx)
954  {
955  /* Get the Tx CRC register */
956  crcreg = SPIx->TXCRCR;
957  }
958  else
959  {
960  /* Get the Rx CRC register */
961  crcreg = SPIx->RXCRCR;
962  }
963  /* Return the selected CRC register */
964  return crcreg;
965 }
966 
973 {
974  /* Check the parameters */
976 
977  /* Return the CRC polynomial register */
978  return SPIx->CRCPR;
979 }
980 
1009 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
1010 {
1011  /* Check the parameters */
1013  assert_param(IS_FUNCTIONAL_STATE(NewState));
1014  assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
1015 
1016  if (NewState != DISABLE)
1017  {
1018  /* Enable the selected SPI DMA requests */
1019  SPIx->CR2 |= SPI_I2S_DMAReq;
1020  }
1021  else
1022  {
1023  /* Disable the selected SPI DMA requests */
1024  SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
1025  }
1026 }
1027 
1117 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
1118 {
1119  uint16_t itpos = 0, itmask = 0 ;
1120 
1121  /* Check the parameters */
1123  assert_param(IS_FUNCTIONAL_STATE(NewState));
1124  assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
1125 
1126  /* Get the SPI IT index */
1127  itpos = SPI_I2S_IT >> 4;
1128 
1129  /* Set the IT mask */
1130  itmask = (uint16_t)1 << (uint16_t)itpos;
1131 
1132  if (NewState != DISABLE)
1133  {
1134  /* Enable the selected SPI interrupt */
1135  SPIx->CR2 |= itmask;
1136  }
1137  else
1138  {
1139  /* Disable the selected SPI interrupt */
1140  SPIx->CR2 &= (uint16_t)~itmask;
1141  }
1142 }
1143 
1161 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
1162 {
1163  FlagStatus bitstatus = RESET;
1164  /* Check the parameters */
1166  assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
1167 
1168  /* Check the status of the specified SPI flag */
1169  if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
1170  {
1171  /* SPI_I2S_FLAG is set */
1172  bitstatus = SET;
1173  }
1174  else
1175  {
1176  /* SPI_I2S_FLAG is reset */
1177  bitstatus = RESET;
1178  }
1179  /* Return the SPI_I2S_FLAG status */
1180  return bitstatus;
1181 }
1182 
1202 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
1203 {
1204  /* Check the parameters */
1206  assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
1207 
1208  /* Clear the selected SPI CRC Error (CRCERR) flag */
1209  SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
1210 }
1211 
1227 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
1228 {
1229  ITStatus bitstatus = RESET;
1230  uint16_t itpos = 0, itmask = 0, enablestatus = 0;
1231 
1232  /* Check the parameters */
1234  assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
1235 
1236  /* Get the SPI_I2S_IT index */
1237  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
1238 
1239  /* Get the SPI_I2S_IT IT mask */
1240  itmask = SPI_I2S_IT >> 4;
1241 
1242  /* Set the IT mask */
1243  itmask = 0x01 << itmask;
1244 
1245  /* Get the SPI_I2S_IT enable bit status */
1246  enablestatus = (SPIx->CR2 & itmask) ;
1247 
1248  /* Check the status of the specified SPI interrupt */
1249  if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
1250  {
1251  /* SPI_I2S_IT is set */
1252  bitstatus = SET;
1253  }
1254  else
1255  {
1256  /* SPI_I2S_IT is reset */
1257  bitstatus = RESET;
1258  }
1259  /* Return the SPI_I2S_IT status */
1260  return bitstatus;
1261 }
1262 
1282 void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
1283 {
1284  uint16_t itpos = 0;
1285  /* Check the parameters */
1287  assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
1288 
1289  /* Get the SPI_I2S IT index */
1290  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
1291 
1292  /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
1293  SPIx->SR = (uint16_t)~itpos;
1294 }
1295 
1312 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral (in I2S mode).
FlagStatus
Definition: stm32f4xx.h:706
#define I2S_DataFormat_16b
uint16_t SPI_DataSize
Definition: stm32f4xx_spi.h:62
#define I2S_Mode_SlaveTx
#define IS_SPI_NSS_INTERNAL(INTERNAL)
void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct.
void SPI_I2S_DeInit(SPI_TypeDef *SPIx)
De-initialize the SPIx peripheral registers to their default reset values.
#define SPI4
Definition: stm32f4xx.h:2088
uint16_t SPI_Mode
Definition: stm32f4xx_spi.h:59
#define IS_SPI_I2S_GET_IT(IT)
#define SPI2
Definition: stm32f4xx.h:2050
#define IS_SPI_ALL_PERIPH(PERIPH)
#define RCC_PLLI2SCFGR_PLLI2SN
Definition: stm32f4xx.h:9124
void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Clears the SPIx CRC Error (CRCERR) flag.
FunctionalState
Definition: stm32f4xx.h:708
#define IS_SPI_I2S_CLEAR_FLAG(FLAG)
#define SPI_Mode_Slave
#define I2SCFGR_CLEAR_MASK
#define SPI1
Definition: stm32f4xx.h:2087
#define SPI_DataSize_16b
#define IS_I2S_AUDIO_FREQ(FREQ)
#define SPI3
Definition: stm32f4xx.h:2051
void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
Enables or disables the specified SPI/I2S interrupts.
#define IS_SPI_I2S_DMAREQ(DMAREQ)
uint16_t SPI_BaudRatePrescaler
Definition: stm32f4xx_spi.h:75
void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
Enables or disables the SPIx/I2Sx DMA interface.
This file contains all the functions prototypes for the SPI firmware library.
#define I2S_MCLKOutput_Disable
uint16_t SPI_CPOL
Definition: stm32f4xx_spi.h:65
uint16_t I2S_Standard
Definition: stm32f4xx_spi.h:97
uint16_t SPI_Direction
Definition: stm32f4xx_spi.h:56
#define I2S_Mode_SlaveRx
#define SPI_Direction_Tx
void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
Configures the data size for the selected SPI.
uint16_t SPI_CRCPolynomial
Definition: stm32f4xx_spi.h:84
__IO uint16_t CRCPR
Definition: stm32f4xx.h:1590
void assert_param(int val)
#define RCC_CFGR_I2SSRC
Definition: stm32f4xx.h:8715
__IO uint16_t CR1
Definition: stm32f4xx.h:1582
#define RCC_PLLCFGR_PLLM
Definition: stm32f4xx.h:8590
#define CR1_CLEAR_MASK
uint16_t I2S_Mode
Definition: stm32f4xx_spi.h:94
#define IS_SPI_DIRECTION(DIRECTION)
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
Serial Peripheral Interface.
Definition: stm32f4xx.h:1580
__IO uint16_t RXCRCR
Definition: stm32f4xx.h:1592
#define SPI_CR1_SPE
Definition: stm32f4xx.h:10057
#define SPI6
Definition: stm32f4xx.h:2095
#define SPI_CR1_CRCNEXT
Definition: stm32f4xx.h:10063
#define SPI5
Definition: stm32f4xx.h:2094
Definition: stm32f4xx.h:706
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
Returns the CRC Polynomial register value for the specified SPI.
enum FlagStatus ITStatus
#define IS_SPI_FIRST_BIT(BIT)
#define RCC_PLLI2SCFGR_PLLI2SR
Definition: stm32f4xx.h:9147
void SPI_TIModeCmd(SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the SPIx/I2Sx DMA interface.
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction)
Selects the data transfer direction in bidirectional mode for the specified SPI.
#define SPI_CR1_CRCEN
Definition: stm32f4xx.h:10064
#define SPI_NSSInternalSoft_Set
#define IS_I2S_DATA_FORMAT(FORMAT)
#define I2S_CPOL_Low
#define IS_I2S_CPOL(CPOL)
void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data)
Transmits a Data through the SPIx/I2Sx peripheral.
uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC)
Returns the transmit or the receive CRC register value for the specified SPI.
uint32_t I2S_AudioFreq
#define I2S_Mode_MasterTx
uint16_t I2S_MCLKOutput
#define IS_SPI_DATASIZE(DATASIZE)
#define SPI_BaudRatePrescaler_2
void SPI_TransmitCRC(SPI_TypeDef *SPIx)
Transmit the SPIx CRC value.
#define SPI_Direction_Rx
#define HSE_VALUE
Comment the line below if you will not use the peripherals drivers. In this case, these drivers will ...
Definition: stm32f10x.h:119
void I2S_FullDuplexConfig(SPI_TypeDef *I2Sxext, I2S_InitTypeDef *I2S_InitStruct)
Configures the full duplex mode for the I2Sx peripheral using its extension I2Sxext according to the ...
#define IS_I2S_MODE(MODE)
SPI Init structure definition.
Definition: stm32f4xx_spi.h:54
uint16_t SPI_NSS
Definition: stm32f4xx_spi.h:71
#define SPI_CRC_Rx
#define SPI_Direction_2Lines_FullDuplex
#define RCC
Definition: stm32f4xx.h:2122
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
Configures internally by software the NSS pin for the selected SPI.
#define I2S_Mode_MasterRx
#define IS_SPI_MODE(MODE)
#define SPI_CPHA_1Edge
void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct)
Fills each I2S_InitStruct member with its default value.
#define I2S_Standard_Phillips
__IO uint16_t TXCRCR
Definition: stm32f4xx.h:1594
__IO uint16_t I2SPR
Definition: stm32f4xx.h:1598
#define IS_SPI_CPHA(CPHA)
#define SPI_NSSInternalSoft_Reset
#define SPI_CR2_FRF
#define SPI_DataSize_8b
#define IS_I2S_STANDARD(STANDARD)
#define IS_SPI_I2S_GET_FLAG(FLAG)
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx)
Returns the most recent received data by the SPIx/I2Sx peripheral.
#define IS_SPI_23_PERIPH(PERIPH)
#define IS_SPI_I2S_CONFIG_IT(IT)
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Checks whether the specified SPIx/I2Sx flag is set or not.
void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the SS output for the selected SPI.
uint16_t SPI_FirstBit
Definition: stm32f4xx_spi.h:81
#define SPI_I2SCFGR_I2SMOD
Definition: stm32f4xx.h:10118
__IO uint16_t SR
Definition: stm32f4xx.h:1586
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Checks whether the specified SPIx/I2Sx interrupt has occurred or not.
#define IS_SPI_CPOL(CPOL)
I2S Init structure definition.
Definition: stm32f4xx_spi.h:91
__IO uint16_t I2SCFGR
Definition: stm32f4xx.h:1596
#define SPI_CPOL_Low
uint16_t SPI_CPHA
Definition: stm32f4xx_spi.h:68
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define SPI_FirstBit_MSB
#define IS_I2S_EXT_PERIPH(PERIPH)
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct.
uint16_t I2S_DataFormat
#define I2S_MCLKOutput_Enable
#define SPI_CR2_SSOE
Definition: stm32f4xx.h:10071
#define IS_SPI_ALL_PERIPH_EXT(PERIPH)
#define IS_SPI_DIRECTION_MODE(MODE)
#define IS_SPI_NSS(NSS)
__IO uint16_t DR
Definition: stm32f4xx.h:1588
#define SPI_NSS_Hard
#define IS_SPI_CRC(CRC)
void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct)
Fills each SPI_InitStruct member with its default value.
#define IS_I2S_MCLK_OUTPUT(OUTPUT)
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL)
void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the CRC value calculation of the transferred bytes.
#define IS_SPI_23_PERIPH_EXT(PERIPH)
#define IS_SPI_I2S_CLEAR_IT(IT)
void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral.
#define I2S_AudioFreq_Default
__IO uint16_t CR2
Definition: stm32f4xx.h:1584
void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
#define SPI_I2SCFGR_I2SE
Definition: stm32f4xx.h:10117


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19