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21 #ifndef STM32F7xx_HAL_I2S_H
22 #define STM32F7xx_HAL_I2S_H
88 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
125 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
137 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
143 HAL_I2S_TX_COMPLETE_CB_ID = 0x00U,
144 HAL_I2S_RX_COMPLETE_CB_ID = 0x01U,
145 HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U,
146 HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U,
147 HAL_I2S_ERROR_CB_ID = 0x06U,
148 HAL_I2S_MSPINIT_CB_ID = 0x07U,
149 HAL_I2S_MSPDEINIT_CB_ID = 0x08U
151 } HAL_I2S_CallbackIDTypeDef;
170 #define HAL_I2S_ERROR_NONE (0x00000000U)
171 #define HAL_I2S_ERROR_TIMEOUT (0x00000001U)
172 #define HAL_I2S_ERROR_OVR (0x00000002U)
173 #define HAL_I2S_ERROR_UDR (0x00000004U)
174 #define HAL_I2S_ERROR_DMA (0x00000008U)
175 #define HAL_I2S_ERROR_PRESCALER (0x00000010U)
176 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
177 #define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U)
186 #define I2S_MODE_SLAVE_TX (0x00000000U)
187 #define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
188 #define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
189 #define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
197 #define I2S_STANDARD_PHILIPS (0x00000000U)
198 #define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
199 #define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
200 #define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
201 #define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
209 #define I2S_DATAFORMAT_16B (0x00000000U)
210 #define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
211 #define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
212 #define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
220 #define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)
221 #define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
229 #define I2S_AUDIOFREQ_192K (192000U)
230 #define I2S_AUDIOFREQ_96K (96000U)
231 #define I2S_AUDIOFREQ_48K (48000U)
232 #define I2S_AUDIOFREQ_44K (44100U)
233 #define I2S_AUDIOFREQ_32K (32000U)
234 #define I2S_AUDIOFREQ_22K (22050U)
235 #define I2S_AUDIOFREQ_16K (16000U)
236 #define I2S_AUDIOFREQ_11K (11025U)
237 #define I2S_AUDIOFREQ_8K (8000U)
238 #define I2S_AUDIOFREQ_DEFAULT (2U)
246 #define I2S_CPOL_LOW (0x00000000U)
247 #define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
255 #define I2S_IT_TXE SPI_CR2_TXEIE
256 #define I2S_IT_RXNE SPI_CR2_RXNEIE
257 #define I2S_IT_ERR SPI_CR2_ERRIE
265 #define I2S_FLAG_TXE SPI_SR_TXE
266 #define I2S_FLAG_RXNE SPI_SR_RXNE
268 #define I2S_FLAG_UDR SPI_SR_UDR
269 #define I2S_FLAG_OVR SPI_SR_OVR
270 #define I2S_FLAG_FRE SPI_SR_FRE
272 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
273 #define I2S_FLAG_BSY SPI_SR_BSY
275 #define I2S_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
283 #define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001U)
284 #define I2S_CLOCK_PLL ((uint32_t)0x00000002U)
301 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
302 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
303 (__HANDLE__)->State = HAL_I2S_STATE_RESET; \
304 (__HANDLE__)->MspInitCallback = NULL; \
305 (__HANDLE__)->MspDeInitCallback = NULL; \
308 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
315 #define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
321 #define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
332 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
343 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
355 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
370 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
376 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
377 __IO uint32_t tmpreg_ovr = 0x00U; \
378 tmpreg_ovr = (__HANDLE__)->Instance->DR; \
379 tmpreg_ovr = (__HANDLE__)->Instance->SR; \
380 UNUSED(tmpreg_ovr); \
386 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
387 __IO uint32_t tmpreg_udr = 0x00U;\
388 tmpreg_udr = ((__HANDLE__)->Instance->SR);\
389 UNUSED(tmpreg_udr); \
410 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
491 #define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
502 #define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
509 #define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
510 ((__MODE__) == I2S_MODE_SLAVE_RX) || \
511 ((__MODE__) == I2S_MODE_MASTER_TX) || \
512 ((__MODE__) == I2S_MODE_MASTER_RX))
514 #define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
515 ((__STANDARD__) == I2S_STANDARD_MSB) || \
516 ((__STANDARD__) == I2S_STANDARD_LSB) || \
517 ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
518 ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
520 #define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
521 ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
522 ((__FORMAT__) == I2S_DATAFORMAT_24B) || \
523 ((__FORMAT__) == I2S_DATAFORMAT_32B))
525 #define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
526 ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
528 #define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
529 ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
530 ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
537 #define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
538 ((__CPOL__) == I2S_CPOL_HIGH))
540 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
541 ((CLOCK) == I2S_CLOCK_PLL))
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
Serial Peripheral Interface.
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
Tx Half Transfer completed callbacks.
HAL_StatusTypeDef
HAL Status structures definition
DMA handle Structure definition.
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
I2S handle Structure definition.
DMA_HandleTypeDef * hdmatx
HAL_LockTypeDef
HAL Lock structures definition
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
struct __I2S_HandleTypeDef I2S_HandleTypeDef
I2S handle Structure definition.
I2S handle Structure definition.
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
Rx Half Transfer completed callbacks.
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
I2S error callbacks.
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
__IO HAL_I2S_StateTypeDef State
DMA_HandleTypeDef * hdmarx
__IO uint16_t RxXferCount
This file contains HAL common defines, enumeration, macros and structures definitions.
__IO uint16_t TxXferCount
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
I2S Init structure definition.
HAL_I2S_StateTypeDef
HAL State structures definition.
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
__IO HAL_I2C_ModeTypeDef Mode
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
__IO HAL_LockTypeDef Lock
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)