Macros
Peripheral_memory_map
CMSIS_Device » Stm32f407xxCMSIS_Device » | Stm32f411xeCMSIS_Device » | Stm32f469xx
Collaboration diagram for Peripheral_memory_map:

Macros

#define ADC123_COMMON_BASE   (APB2PERIPH_BASE + 0x2300UL)
 
#define ADC123_COMMON_BASE   (APB2PERIPH_BASE + 0x2300UL)
 
#define ADC12_COMMON_BASE   (D2_AHB1PERIPH_BASE + 0x2300UL)
 
#define ADC12_COMMON_BASE   (D2_AHB1PERIPH_BASE + 0x2300UL)
 
#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000UL)
 
#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000UL)
 
#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000UL)
 
#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000UL)
 
#define ADC1_BASE   (D2_AHB1PERIPH_BASE + 0x2000UL)
 
#define ADC1_BASE   (D2_AHB1PERIPH_BASE + 0x2000UL)
 
#define ADC1_COMMON_BASE   (APB2PERIPH_BASE + 0x2300UL)
 
#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100UL)
 
#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100UL)
 
#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100UL)
 
#define ADC2_BASE   (D2_AHB1PERIPH_BASE + 0x2100UL)
 
#define ADC2_BASE   (D2_AHB1PERIPH_BASE + 0x2100UL)
 
#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200UL)
 
#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200UL)
 
#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200UL)
 
#define ADC3_BASE   (D3_AHB1PERIPH_BASE + 0x6000UL)
 
#define ADC3_BASE   (D3_AHB1PERIPH_BASE + 0x6000UL)
 
#define ADC3_COMMON_BASE   (D3_AHB1PERIPH_BASE + 0x6300UL)
 
#define ADC3_COMMON_BASE   (D3_AHB1PERIPH_BASE + 0x6300UL)
 
#define ADC_BASE   ADC1_COMMON_BASE
 
#define ADC_BASE   ADC123_COMMON_BASE
 
#define ADC_BASE   ADC123_COMMON_BASE
 
#define ADC_BASE   (APB2PERIPH_BASE + 0x2300UL)
 
#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)
 
#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)
 
#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)
 
#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)
 
#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)
 
#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)
 
#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000UL)
 
#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000UL)
 
#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000UL)
 
#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000UL)
 
#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x08000000UL)
 
#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x08000000UL)
 
#define APB1PERIPH_BASE   PERIPH_BASE
 
#define APB1PERIPH_BASE   PERIPH_BASE
 
#define APB1PERIPH_BASE   PERIPH_BASE
 
#define APB1PERIPH_BASE   PERIPH_BASE
 
#define APB1PERIPH_BASE   PERIPH_BASE
 
#define APB1PERIPH_BASE   PERIPH_BASE
 
#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)
 
#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)
 
#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)
 
#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)
 
#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)
 
#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)
 
#define ART_BASE   (D2_AHB1PERIPH_BASE + 0x4400UL)
 
#define BDMA_BASE   (D3_AHB1PERIPH_BASE + 0x5400UL)
 
#define BDMA_BASE   (D3_AHB1PERIPH_BASE + 0x5400UL)
 
#define BDMA_Channel0_BASE   (BDMA_BASE + 0x0008UL)
 
#define BDMA_Channel0_BASE   (BDMA_BASE + 0x0008UL)
 
#define BDMA_Channel1_BASE   (BDMA_BASE + 0x001CUL)
 
#define BDMA_Channel1_BASE   (BDMA_BASE + 0x001CUL)
 
#define BDMA_Channel2_BASE   (BDMA_BASE + 0x0030UL)
 
#define BDMA_Channel2_BASE   (BDMA_BASE + 0x0030UL)
 
#define BDMA_Channel3_BASE   (BDMA_BASE + 0x0044UL)
 
#define BDMA_Channel3_BASE   (BDMA_BASE + 0x0044UL)
 
#define BDMA_Channel4_BASE   (BDMA_BASE + 0x0058UL)
 
#define BDMA_Channel4_BASE   (BDMA_BASE + 0x0058UL)
 
#define BDMA_Channel5_BASE   (BDMA_BASE + 0x006CUL)
 
#define BDMA_Channel5_BASE   (BDMA_BASE + 0x006CUL)
 
#define BDMA_Channel6_BASE   (BDMA_BASE + 0x0080UL)
 
#define BDMA_Channel6_BASE   (BDMA_BASE + 0x0080UL)
 
#define BDMA_Channel7_BASE   (BDMA_BASE + 0x0094UL)
 
#define BDMA_Channel7_BASE   (BDMA_BASE + 0x0094UL)
 
#define BKPSRAM_BASE   0x40024000UL
 
#define BKPSRAM_BASE   0x40024000UL
 
#define BKPSRAM_BASE   0x40024000UL
 
#define BKPSRAM_BB_BASE   0x42480000UL
 
#define BKPSRAM_BB_BASE   0x42480000UL
 
#define BKPSRAM_BB_BASE   0x42480000UL
 
#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400UL)
 
#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400UL)
 
#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400UL)
 
#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800UL)
 
#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800UL)
 
#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800UL)
 
#define CAN3_BASE   (APB1PERIPH_BASE + 0x3400UL)
 
#define CCMDATARAM_BASE   0x10000000UL
 
#define CCMDATARAM_BASE   0x10000000UL
 
#define CCMDATARAM_END   0x1000FFFFUL
 
#define CCMDATARAM_END   0x1000FFFFUL
 
#define CEC_BASE   (APB1PERIPH_BASE + 0x6C00UL)
 
#define CEC_BASE   (D2_APB1PERIPH_BASE + 0x6C00UL)
 
#define CEC_BASE   (D2_APB1PERIPH_BASE + 0x6C00UL)
 
#define COMP12_BASE   (D3_APB1PERIPH_BASE + 0x3800UL)
 
#define COMP12_BASE   (D3_APB1PERIPH_BASE + 0x3800UL)
 
#define COMP1_BASE   (COMP12_BASE + 0x0CUL)
 
#define COMP1_BASE   (COMP12_BASE + 0x0CUL)
 
#define COMP2_BASE   (COMP12_BASE + 0x10UL)
 
#define COMP2_BASE   (COMP12_BASE + 0x10UL)
 
#define CORDIC_BASE   (D2_AHB2PERIPH_BASE + 0x4400UL)
 
#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000UL)
 
#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000UL)
 
#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000UL)
 
#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000UL)
 
#define CRC_BASE   (D3_AHB1PERIPH_BASE + 0x4C00UL)
 
#define CRC_BASE   (D3_AHB1PERIPH_BASE + 0x4C00UL)
 
#define CRS_BASE   (D2_APB1PERIPH_BASE + 0x8400UL)
 
#define CRS_BASE   (D2_APB1PERIPH_BASE + 0x8400UL)
 
#define CRYP_BASE   (D2_AHB2PERIPH_BASE + 0x1000UL)
 
#define D1_AHB1PERIPH_BASE   (PERIPH_BASE + 0x12000000UL)
 
#define D1_AHB1PERIPH_BASE   (PERIPH_BASE + 0x12000000UL)
 
#define D1_APB1PERIPH_BASE   (PERIPH_BASE + 0x10000000UL)
 
#define D1_APB1PERIPH_BASE   (PERIPH_BASE + 0x10000000UL)
 
#define D1_AXIFLASH_BASE   (0x08000000UL)
 
#define D1_AXIFLASH_BASE   (0x08000000UL)
 
#define D1_AXIICP_BASE   (0x1FF00000UL)
 
#define D1_AXIICP_BASE   (0x1FF00000UL)
 
#define D1_AXISRAM1_BASE   (0x24000000UL)
 
#define D1_AXISRAM2_BASE   (0x24020000UL)
 
#define D1_AXISRAM_BASE   (0x24000000UL)
 
#define D1_AXISRAM_BASE   D1_AXISRAM1_BASE
 
#define D1_DTCMRAM_BASE   (0x20000000UL)
 
#define D1_DTCMRAM_BASE   (0x20000000UL)
 
#define D1_ITCMICP_BASE   (0x00100000UL)
 
#define D1_ITCMICP_BASE   (0x00100000UL)
 
#define D1_ITCMRAM_BASE   (0x00000000UL)
 
#define D1_ITCMRAM_BASE   (0x00000000UL)
 
#define D2_AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)
 
#define D2_AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)
 
#define D2_AHB2PERIPH_BASE   (PERIPH_BASE + 0x08020000UL)
 
#define D2_AHB2PERIPH_BASE   (PERIPH_BASE + 0x08020000UL)
 
#define D2_AHBSRAM1_BASE   (0x30000000UL)
 
#define D2_AHBSRAM2_BASE   (0x30004000UL)
 
#define D2_AHBSRAM_BASE   (0x30000000UL)
 
#define D2_AHBSRAM_BASE   D2_AHBSRAM1_BASE
 
#define D2_APB1PERIPH_BASE   PERIPH_BASE
 
#define D2_APB1PERIPH_BASE   PERIPH_BASE
 
#define D2_APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)
 
#define D2_APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)
 
#define D2_AXISRAM_BASE   (0x10000000UL)
 
#define D3_AHB1PERIPH_BASE   (PERIPH_BASE + 0x18020000UL)
 
#define D3_AHB1PERIPH_BASE   (PERIPH_BASE + 0x18020000UL)
 
#define D3_APB1PERIPH_BASE   (PERIPH_BASE + 0x18000000UL)
 
#define D3_APB1PERIPH_BASE   (PERIPH_BASE + 0x18000000UL)
 
#define D3_BKPSRAM_BASE   (0x38800000UL)
 
#define D3_BKPSRAM_BASE   (0x38800000UL)
 
#define D3_SRAM_BASE   (0x38000000UL)
 
#define D3_SRAM_BASE   (0x38000000UL)
 
#define DAC1_BASE   (D2_APB1PERIPH_BASE + 0x7400UL)
 
#define DAC1_BASE   (D2_APB1PERIPH_BASE + 0x7400UL)
 
#define DAC_BASE   (APB1PERIPH_BASE + 0x7400UL)
 
#define DAC_BASE   (APB1PERIPH_BASE + 0x7400UL)
 
#define DAC_BASE   (APB1PERIPH_BASE + 0x7400UL)
 
#define DBGMCU_BASE   0xE0042000UL
 
#define DBGMCU_BASE   0xE0042000UL
 
#define DBGMCU_BASE   0xE0042000UL
 
#define DBGMCU_BASE   0xE0042000UL
 
#define DBGMCU_BASE   (0x5C001000UL)
 
#define DBGMCU_BASE   (0x5C001000UL)
 
#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000UL)
 
#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000UL)
 
#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000UL)
 
#define DCMI_BASE   (D2_AHB2PERIPH_BASE + 0x0000UL)
 
#define DCMI_BASE   (D2_AHB2PERIPH_BASE + 0x0000UL)
 
#define DFSDM1_BASE   (APB2PERIPH_BASE + 0x7400UL)
 
#define DFSDM1_BASE   (D2_APB2PERIPH_BASE + 0x7000UL)
 
#define DFSDM1_BASE   (D2_APB2PERIPH_BASE + 0x7800UL)
 
#define DFSDM1_Channel0_BASE   (DFSDM1_BASE + 0x00UL)
 
#define DFSDM1_Channel0_BASE   (DFSDM1_BASE + 0x00UL)
 
#define DFSDM1_Channel0_BASE   (DFSDM1_BASE + 0x00UL)
 
#define DFSDM1_Channel1_BASE   (DFSDM1_BASE + 0x20UL)
 
#define DFSDM1_Channel1_BASE   (DFSDM1_BASE + 0x20UL)
 
#define DFSDM1_Channel1_BASE   (DFSDM1_BASE + 0x20UL)
 
#define DFSDM1_Channel2_BASE   (DFSDM1_BASE + 0x40UL)
 
#define DFSDM1_Channel2_BASE   (DFSDM1_BASE + 0x40UL)
 
#define DFSDM1_Channel2_BASE   (DFSDM1_BASE + 0x40UL)
 
#define DFSDM1_Channel3_BASE   (DFSDM1_BASE + 0x60UL)
 
#define DFSDM1_Channel3_BASE   (DFSDM1_BASE + 0x60UL)
 
#define DFSDM1_Channel3_BASE   (DFSDM1_BASE + 0x60UL)
 
#define DFSDM1_Channel4_BASE   (DFSDM1_BASE + 0x80UL)
 
#define DFSDM1_Channel4_BASE   (DFSDM1_BASE + 0x80UL)
 
#define DFSDM1_Channel4_BASE   (DFSDM1_BASE + 0x80UL)
 
#define DFSDM1_Channel5_BASE   (DFSDM1_BASE + 0xA0UL)
 
#define DFSDM1_Channel5_BASE   (DFSDM1_BASE + 0xA0UL)
 
#define DFSDM1_Channel5_BASE   (DFSDM1_BASE + 0xA0UL)
 
#define DFSDM1_Channel6_BASE   (DFSDM1_BASE + 0xC0UL)
 
#define DFSDM1_Channel6_BASE   (DFSDM1_BASE + 0xC0UL)
 
#define DFSDM1_Channel6_BASE   (DFSDM1_BASE + 0xC0UL)
 
#define DFSDM1_Channel7_BASE   (DFSDM1_BASE + 0xE0UL)
 
#define DFSDM1_Channel7_BASE   (DFSDM1_BASE + 0xE0UL)
 
#define DFSDM1_Channel7_BASE   (DFSDM1_BASE + 0xE0UL)
 
#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)
 
#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)
 
#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)
 
#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)
 
#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)
 
#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)
 
#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)
 
#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)
 
#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)
 
#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)
 
#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)
 
#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)
 
#define DLYB_OCTOSPI1_BASE   (D1_AHB1PERIPH_BASE + 0x6000UL)
 
#define DLYB_OCTOSPI2_BASE   (D1_AHB1PERIPH_BASE + 0xB000UL)
 
#define DLYB_QSPI_BASE   (D1_AHB1PERIPH_BASE + 0x6000UL)
 
#define DLYB_SDMMC1_BASE   (D1_AHB1PERIPH_BASE + 0x8000UL)
 
#define DLYB_SDMMC1_BASE   (D1_AHB1PERIPH_BASE + 0x8000UL)
 
#define DLYB_SDMMC2_BASE   (D2_AHB2PERIPH_BASE + 0x2800UL)
 
#define DLYB_SDMMC2_BASE   (D2_AHB2PERIPH_BASE + 0x2800UL)
 
#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000UL)
 
#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000UL)
 
#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000UL)
 
#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000UL)
 
#define DMA1_BASE   (D2_AHB1PERIPH_BASE + 0x0000UL)
 
#define DMA1_BASE   (D2_AHB1PERIPH_BASE + 0x0000UL)
 
#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010UL)
 
#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010UL)
 
#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010UL)
 
#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010UL)
 
#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010UL)
 
#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010UL)
 
#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028UL)
 
#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028UL)
 
#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028UL)
 
#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028UL)
 
#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028UL)
 
#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028UL)
 
#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040UL)
 
#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040UL)
 
#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040UL)
 
#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040UL)
 
#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040UL)
 
#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040UL)
 
#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058UL)
 
#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058UL)
 
#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058UL)
 
#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058UL)
 
#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058UL)
 
#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058UL)
 
#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070UL)
 
#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070UL)
 
#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070UL)
 
#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070UL)
 
#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070UL)
 
#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070UL)
 
#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088UL)
 
#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088UL)
 
#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088UL)
 
#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088UL)
 
#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088UL)
 
#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088UL)
 
#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0UL)
 
#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0UL)
 
#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0UL)
 
#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0UL)
 
#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0UL)
 
#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0UL)
 
#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8UL)
 
#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8UL)
 
#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8UL)
 
#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8UL)
 
#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8UL)
 
#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8UL)
 
#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400UL)
 
#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400UL)
 
#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400UL)
 
#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400UL)
 
#define DMA2_BASE   (D2_AHB1PERIPH_BASE + 0x0400UL)
 
#define DMA2_BASE   (D2_AHB1PERIPH_BASE + 0x0400UL)
 
#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010UL)
 
#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010UL)
 
#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010UL)
 
#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010UL)
 
#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010UL)
 
#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010UL)
 
#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028UL)
 
#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028UL)
 
#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028UL)
 
#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028UL)
 
#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028UL)
 
#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028UL)
 
#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040UL)
 
#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040UL)
 
#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040UL)
 
#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040UL)
 
#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040UL)
 
#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040UL)
 
#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058UL)
 
#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058UL)
 
#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058UL)
 
#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058UL)
 
#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058UL)
 
#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058UL)
 
#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070UL)
 
#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070UL)
 
#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070UL)
 
#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070UL)
 
#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070UL)
 
#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070UL)
 
#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088UL)
 
#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088UL)
 
#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088UL)
 
#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088UL)
 
#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088UL)
 
#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088UL)
 
#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0UL)
 
#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0UL)
 
#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0UL)
 
#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0UL)
 
#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0UL)
 
#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0UL)
 
#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8UL)
 
#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8UL)
 
#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8UL)
 
#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8UL)
 
#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8UL)
 
#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8UL)
 
#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000UL)
 
#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000UL)
 
#define DMA2D_BASE   (D1_AHB1PERIPH_BASE + 0x1000UL)
 
#define DMA2D_BASE   (D1_AHB1PERIPH_BASE + 0x1000UL)
 
#define DMAMUX1_BASE   (D2_AHB1PERIPH_BASE + 0x0800UL)
 
#define DMAMUX1_BASE   (D2_AHB1PERIPH_BASE + 0x0800UL)
 
#define DMAMUX1_Channel0_BASE   (DMAMUX1_BASE)
 
#define DMAMUX1_Channel0_BASE   (DMAMUX1_BASE)
 
#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)
 
#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)
 
#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)
 
#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)
 
#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)
 
#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)
 
#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)
 
#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)
 
#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)
 
#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)
 
#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)
 
#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)
 
#define DMAMUX1_Channel1_BASE   (DMAMUX1_BASE + 0x0004UL)
 
#define DMAMUX1_Channel1_BASE   (DMAMUX1_BASE + 0x0004UL)
 
#define DMAMUX1_Channel2_BASE   (DMAMUX1_BASE + 0x0008UL)
 
#define DMAMUX1_Channel2_BASE   (DMAMUX1_BASE + 0x0008UL)
 
#define DMAMUX1_Channel3_BASE   (DMAMUX1_BASE + 0x000CUL)
 
#define DMAMUX1_Channel3_BASE   (DMAMUX1_BASE + 0x000CUL)
 
#define DMAMUX1_Channel4_BASE   (DMAMUX1_BASE + 0x0010UL)
 
#define DMAMUX1_Channel4_BASE   (DMAMUX1_BASE + 0x0010UL)
 
#define DMAMUX1_Channel5_BASE   (DMAMUX1_BASE + 0x0014UL)
 
#define DMAMUX1_Channel5_BASE   (DMAMUX1_BASE + 0x0014UL)
 
#define DMAMUX1_Channel6_BASE   (DMAMUX1_BASE + 0x0018UL)
 
#define DMAMUX1_Channel6_BASE   (DMAMUX1_BASE + 0x0018UL)
 
#define DMAMUX1_Channel7_BASE   (DMAMUX1_BASE + 0x001CUL)
 
#define DMAMUX1_Channel7_BASE   (DMAMUX1_BASE + 0x001CUL)
 
#define DMAMUX1_Channel8_BASE   (DMAMUX1_BASE + 0x0020UL)
 
#define DMAMUX1_Channel8_BASE   (DMAMUX1_BASE + 0x0020UL)
 
#define DMAMUX1_Channel9_BASE   (DMAMUX1_BASE + 0x0024UL)
 
#define DMAMUX1_Channel9_BASE   (DMAMUX1_BASE + 0x0024UL)
 
#define DMAMUX1_ChannelStatus_BASE   (DMAMUX1_BASE + 0x0080UL)
 
#define DMAMUX1_ChannelStatus_BASE   (DMAMUX1_BASE + 0x0080UL)
 
#define DMAMUX1_RequestGenerator0_BASE   (DMAMUX1_BASE + 0x0100UL)
 
#define DMAMUX1_RequestGenerator0_BASE   (DMAMUX1_BASE + 0x0100UL)
 
#define DMAMUX1_RequestGenerator1_BASE   (DMAMUX1_BASE + 0x0104UL)
 
#define DMAMUX1_RequestGenerator1_BASE   (DMAMUX1_BASE + 0x0104UL)
 
#define DMAMUX1_RequestGenerator2_BASE   (DMAMUX1_BASE + 0x0108UL)
 
#define DMAMUX1_RequestGenerator2_BASE   (DMAMUX1_BASE + 0x0108UL)
 
#define DMAMUX1_RequestGenerator3_BASE   (DMAMUX1_BASE + 0x010CUL)
 
#define DMAMUX1_RequestGenerator3_BASE   (DMAMUX1_BASE + 0x010CUL)
 
#define DMAMUX1_RequestGenerator4_BASE   (DMAMUX1_BASE + 0x0110UL)
 
#define DMAMUX1_RequestGenerator4_BASE   (DMAMUX1_BASE + 0x0110UL)
 
#define DMAMUX1_RequestGenerator5_BASE   (DMAMUX1_BASE + 0x0114UL)
 
#define DMAMUX1_RequestGenerator5_BASE   (DMAMUX1_BASE + 0x0114UL)
 
#define DMAMUX1_RequestGenerator6_BASE   (DMAMUX1_BASE + 0x0118UL)
 
#define DMAMUX1_RequestGenerator6_BASE   (DMAMUX1_BASE + 0x0118UL)
 
#define DMAMUX1_RequestGenerator7_BASE   (DMAMUX1_BASE + 0x011CUL)
 
#define DMAMUX1_RequestGenerator7_BASE   (DMAMUX1_BASE + 0x011CUL)
 
#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)
 
#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)
 
#define DMAMUX2_BASE   (D3_AHB1PERIPH_BASE + 0x5800UL)
 
#define DMAMUX2_BASE   (D3_AHB1PERIPH_BASE + 0x5800UL)
 
#define DMAMUX2_Channel0_BASE   (DMAMUX2_BASE)
 
#define DMAMUX2_Channel0_BASE   (DMAMUX2_BASE)
 
#define DMAMUX2_Channel1_BASE   (DMAMUX2_BASE + 0x0004UL)
 
#define DMAMUX2_Channel1_BASE   (DMAMUX2_BASE + 0x0004UL)
 
#define DMAMUX2_Channel2_BASE   (DMAMUX2_BASE + 0x0008UL)
 
#define DMAMUX2_Channel2_BASE   (DMAMUX2_BASE + 0x0008UL)
 
#define DMAMUX2_Channel3_BASE   (DMAMUX2_BASE + 0x000CUL)
 
#define DMAMUX2_Channel3_BASE   (DMAMUX2_BASE + 0x000CUL)
 
#define DMAMUX2_Channel4_BASE   (DMAMUX2_BASE + 0x0010UL)
 
#define DMAMUX2_Channel4_BASE   (DMAMUX2_BASE + 0x0010UL)
 
#define DMAMUX2_Channel5_BASE   (DMAMUX2_BASE + 0x0014UL)
 
#define DMAMUX2_Channel5_BASE   (DMAMUX2_BASE + 0x0014UL)
 
#define DMAMUX2_Channel6_BASE   (DMAMUX2_BASE + 0x0018UL)
 
#define DMAMUX2_Channel6_BASE   (DMAMUX2_BASE + 0x0018UL)
 
#define DMAMUX2_Channel7_BASE   (DMAMUX2_BASE + 0x001CUL)
 
#define DMAMUX2_Channel7_BASE   (DMAMUX2_BASE + 0x001CUL)
 
#define DMAMUX2_ChannelStatus_BASE   (DMAMUX2_BASE + 0x0080UL)
 
#define DMAMUX2_ChannelStatus_BASE   (DMAMUX2_BASE + 0x0080UL)
 
#define DMAMUX2_RequestGenerator0_BASE   (DMAMUX2_BASE + 0x0100UL)
 
#define DMAMUX2_RequestGenerator0_BASE   (DMAMUX2_BASE + 0x0100UL)
 
#define DMAMUX2_RequestGenerator1_BASE   (DMAMUX2_BASE + 0x0104UL)
 
#define DMAMUX2_RequestGenerator1_BASE   (DMAMUX2_BASE + 0x0104UL)
 
#define DMAMUX2_RequestGenerator2_BASE   (DMAMUX2_BASE + 0x0108UL)
 
#define DMAMUX2_RequestGenerator2_BASE   (DMAMUX2_BASE + 0x0108UL)
 
#define DMAMUX2_RequestGenerator3_BASE   (DMAMUX2_BASE + 0x010CUL)
 
#define DMAMUX2_RequestGenerator3_BASE   (DMAMUX2_BASE + 0x010CUL)
 
#define DMAMUX2_RequestGenerator4_BASE   (DMAMUX2_BASE + 0x0110UL)
 
#define DMAMUX2_RequestGenerator4_BASE   (DMAMUX2_BASE + 0x0110UL)
 
#define DMAMUX2_RequestGenerator5_BASE   (DMAMUX2_BASE + 0x0114UL)
 
#define DMAMUX2_RequestGenerator5_BASE   (DMAMUX2_BASE + 0x0114UL)
 
#define DMAMUX2_RequestGenerator6_BASE   (DMAMUX2_BASE + 0x0118UL)
 
#define DMAMUX2_RequestGenerator6_BASE   (DMAMUX2_BASE + 0x0118UL)
 
#define DMAMUX2_RequestGenerator7_BASE   (DMAMUX2_BASE + 0x011CUL)
 
#define DMAMUX2_RequestGenerator7_BASE   (DMAMUX2_BASE + 0x011CUL)
 
#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)
 
#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)
 
#define DSI_BASE   (APB2PERIPH_BASE + 0x6C00UL)
 
#define DSI_BASE   (APB2PERIPH_BASE + 0x6C00UL)
 
#define DSI_BASE   (D1_APB1PERIPH_BASE)
 
#define DTS_BASE   (D3_APB1PERIPH_BASE + 0x6800UL)
 
#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000UL)
 
#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000UL)
 
#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000UL)
 
#define ETH_BASE   (D2_AHB1PERIPH_BASE + 0x8000UL)
 
#define ETH_BASE   (D2_AHB1PERIPH_BASE + 0x8000UL)
 
#define ETH_DMA_BASE   (ETH_BASE + 0x1000UL)
 
#define ETH_DMA_BASE   (ETH_BASE + 0x1000UL)
 
#define ETH_DMA_BASE   (ETH_BASE + 0x1000UL)
 
#define ETH_MAC_BASE   (ETH_BASE)
 
#define ETH_MAC_BASE   (ETH_BASE)
 
#define ETH_MAC_BASE   (ETH_BASE)
 
#define ETH_MAC_BASE   (ETH_BASE)
 
#define ETH_MAC_BASE   (ETH_BASE)
 
#define ETH_MMC_BASE   (ETH_BASE + 0x0100UL)
 
#define ETH_MMC_BASE   (ETH_BASE + 0x0100UL)
 
#define ETH_MMC_BASE   (ETH_BASE + 0x0100UL)
 
#define ETH_PTP_BASE   (ETH_BASE + 0x0700UL)
 
#define ETH_PTP_BASE   (ETH_BASE + 0x0700UL)
 
#define ETH_PTP_BASE   (ETH_BASE + 0x0700UL)
 
#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00UL)
 
#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00UL)
 
#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00UL)
 
#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00UL)
 
#define EXTI_BASE   (D3_APB1PERIPH_BASE + 0x0000UL)
 
#define EXTI_BASE   (D3_APB1PERIPH_BASE + 0x0000UL)
 
#define EXTI_D1_BASE   (EXTI_BASE + 0x0080UL)
 
#define EXTI_D1_BASE   (EXTI_BASE + 0x0080UL)
 
#define EXTI_D2_BASE   (EXTI_BASE + 0x00C0UL)
 
#define EXTI_D2_BASE   (EXTI_BASE + 0x00C0UL)
 
#define FDCAN1_BASE   (D2_APB1PERIPH_BASE + 0xA000UL)
 
#define FDCAN1_BASE   (D2_APB1PERIPH_BASE + 0xA000UL)
 
#define FDCAN2_BASE   (D2_APB1PERIPH_BASE + 0xA400UL)
 
#define FDCAN2_BASE   (D2_APB1PERIPH_BASE + 0xA400UL)
 
#define FDCAN3_BASE   (D2_APB1PERIPH_BASE + 0xD400UL)
 
#define FDCAN_CCU_BASE   (D2_APB1PERIPH_BASE + 0xA800UL)
 
#define FDCAN_CCU_BASE   (D2_APB1PERIPH_BASE + 0xA800UL)
 
#define FLASH_BANK1_BASE   (0x08000000UL)
 
#define FLASH_BANK1_BASE   (0x08000000UL)
 
#define FLASH_BANK2_BASE   (0x08100000UL)
 
#define FLASH_BASE   0x08000000UL
 
#define FLASH_BASE   0x08000000UL
 
#define FLASH_BASE   0x08000000UL
 
#define FLASH_BASE   FLASHAXI_BASE
 
#define FLASH_BASE   FLASH_BANK1_BASE
 
#define FLASH_BASE   FLASH_BANK1_BASE
 
#define FLASH_END   0x0807FFFFUL
 
#define FLASH_END   0x080FFFFFUL
 
#define FLASH_END   0x081FFFFFUL
 
#define FLASH_END   0x081FFFFFUL
 
#define FLASH_END   (0x081FFFFFUL)
 
#define FLASH_END   (0x080FFFFFUL)
 
#define FLASH_OTP_BASE   0x1FFF7800UL
 
#define FLASH_OTP_BASE   0x1FFF7800UL
 
#define FLASH_OTP_BASE   0x1FFF7800UL
 
#define FLASH_OTP_BASE   0x1FF0F000UL
 
#define FLASH_OTP_END   0x1FFF7A0FUL
 
#define FLASH_OTP_END   0x1FFF7A0FUL
 
#define FLASH_OTP_END   0x1FFF7A0FUL
 
#define FLASH_OTP_END   0x1FF0F41FUL
 
#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00UL)
 
#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00UL)
 
#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00UL)
 
#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00UL)
 
#define FLASH_R_BASE   (D1_AHB1PERIPH_BASE + 0x2000UL)
 
#define FLASH_R_BASE   (D1_AHB1PERIPH_BASE + 0x2000UL)
 
#define FLASHAXI_BASE   0x08000000UL
 
#define FLASHITCM_BASE   0x00200000UL
 
#define FLASHSIZE_BASE   0x1FFF7A22UL
 
#define FLASHSIZE_BASE   0x1FFF7A22UL
 
#define FLASHSIZE_BASE   0x1FFF7A22UL
 
#define FLASHSIZE_BASE   0x1FF0F442UL
 
#define FLASHSIZE_BASE   (0x1FF1E880UL)
 
#define FLASHSIZE_BASE   (0x1FF1E880UL)
 
#define FMAC_BASE   (D2_AHB2PERIPH_BASE + 0x4000UL)
 
#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000UL)
 
#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000UL)
 
#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000UL)
 
#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000UL)
 
#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104UL)
 
#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104UL)
 
#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104UL)
 
#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104UL)
 
#define FMC_Bank2_R_BASE   (FMC_R_BASE + 0x0060UL)
 
#define FMC_Bank2_R_BASE   (FMC_R_BASE + 0x0060UL)
 
#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080UL)
 
#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080UL)
 
#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080UL)
 
#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080UL)
 
#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140UL)
 
#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140UL)
 
#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140UL)
 
#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140UL)
 
#define FMC_R_BASE   0xA0000000UL
 
#define FMC_R_BASE   0xA0000000UL
 
#define FMC_R_BASE   (D1_AHB1PERIPH_BASE + 0x4000UL)
 
#define FMC_R_BASE   (D1_AHB1PERIPH_BASE + 0x4000UL)
 
#define FSMC_Bank1_R_BASE   (FSMC_R_BASE + 0x0000UL)
 
#define FSMC_Bank1E_R_BASE   (FSMC_R_BASE + 0x0104UL)
 
#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060UL)
 
#define FSMC_Bank4_R_BASE   (FSMC_R_BASE + 0x00A0UL)
 
#define FSMC_R_BASE   0xA0000000UL
 
#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000UL)
 
#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000UL)
 
#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000UL)
 
#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000UL)
 
#define GPIOA_BASE   (D3_AHB1PERIPH_BASE + 0x0000UL)
 
#define GPIOA_BASE   (D3_AHB1PERIPH_BASE + 0x0000UL)
 
#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400UL)
 
#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400UL)
 
#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400UL)
 
#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400UL)
 
#define GPIOB_BASE   (D3_AHB1PERIPH_BASE + 0x0400UL)
 
#define GPIOB_BASE   (D3_AHB1PERIPH_BASE + 0x0400UL)
 
#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800UL)
 
#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800UL)
 
#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800UL)
 
#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800UL)
 
#define GPIOC_BASE   (D3_AHB1PERIPH_BASE + 0x0800UL)
 
#define GPIOC_BASE   (D3_AHB1PERIPH_BASE + 0x0800UL)
 
#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00UL)
 
#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00UL)
 
#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00UL)
 
#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00UL)
 
#define GPIOD_BASE   (D3_AHB1PERIPH_BASE + 0x0C00UL)
 
#define GPIOD_BASE   (D3_AHB1PERIPH_BASE + 0x0C00UL)
 
#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000UL)
 
#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000UL)
 
#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000UL)
 
#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000UL)
 
#define GPIOE_BASE   (D3_AHB1PERIPH_BASE + 0x1000UL)
 
#define GPIOE_BASE   (D3_AHB1PERIPH_BASE + 0x1000UL)
 
#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400UL)
 
#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400UL)
 
#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400UL)
 
#define GPIOF_BASE   (D3_AHB1PERIPH_BASE + 0x1400UL)
 
#define GPIOF_BASE   (D3_AHB1PERIPH_BASE + 0x1400UL)
 
#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800UL)
 
#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800UL)
 
#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800UL)
 
#define GPIOG_BASE   (D3_AHB1PERIPH_BASE + 0x1800UL)
 
#define GPIOG_BASE   (D3_AHB1PERIPH_BASE + 0x1800UL)
 
#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00UL)
 
#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00UL)
 
#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00UL)
 
#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00UL)
 
#define GPIOH_BASE   (D3_AHB1PERIPH_BASE + 0x1C00UL)
 
#define GPIOH_BASE   (D3_AHB1PERIPH_BASE + 0x1C00UL)
 
#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000UL)
 
#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000UL)
 
#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000UL)
 
#define GPIOI_BASE   (D3_AHB1PERIPH_BASE + 0x2000UL)
 
#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400UL)
 
#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400UL)
 
#define GPIOJ_BASE   (D3_AHB1PERIPH_BASE + 0x2400UL)
 
#define GPIOJ_BASE   (D3_AHB1PERIPH_BASE + 0x2400UL)
 
#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800UL)
 
#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800UL)
 
#define GPIOK_BASE   (D3_AHB1PERIPH_BASE + 0x2800UL)
 
#define GPIOK_BASE   (D3_AHB1PERIPH_BASE + 0x2800UL)
 
#define GPV_BASE   (PERIPH_BASE + 0x11000000UL)
 
#define HASH_BASE   (D2_AHB2PERIPH_BASE + 0x1400UL)
 
#define HASH_DIGEST_BASE   (D2_AHB2PERIPH_BASE + 0x1710UL)
 
#define HRTIM1_BASE   (D2_APB2PERIPH_BASE + 0x7400UL)
 
#define HRTIM1_COMMON_BASE   (HRTIM1_BASE + 0x00000380UL)
 
#define HRTIM1_TIMA_BASE   (HRTIM1_BASE + 0x00000080UL)
 
#define HRTIM1_TIMB_BASE   (HRTIM1_BASE + 0x00000100UL)
 
#define HRTIM1_TIMC_BASE   (HRTIM1_BASE + 0x00000180UL)
 
#define HRTIM1_TIMD_BASE   (HRTIM1_BASE + 0x00000200UL)
 
#define HRTIM1_TIME_BASE   (HRTIM1_BASE + 0x00000280UL)
 
#define HSEM_BASE   (D3_AHB1PERIPH_BASE + 0x6400UL)
 
#define HSEM_BASE   (D3_AHB1PERIPH_BASE + 0x6400UL)
 
#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400UL)
 
#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400UL)
 
#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400UL)
 
#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400UL)
 
#define I2C1_BASE   (D2_APB1PERIPH_BASE + 0x5400UL)
 
#define I2C1_BASE   (D2_APB1PERIPH_BASE + 0x5400UL)
 
#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800UL)
 
#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800UL)
 
#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800UL)
 
#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800UL)
 
#define I2C2_BASE   (D2_APB1PERIPH_BASE + 0x5800UL)
 
#define I2C2_BASE   (D2_APB1PERIPH_BASE + 0x5800UL)
 
#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00UL)
 
#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00UL)
 
#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00UL)
 
#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00UL)
 
#define I2C3_BASE   (D2_APB1PERIPH_BASE + 0x5C00UL)
 
#define I2C3_BASE   (D2_APB1PERIPH_BASE + 0x5C00UL)
 
#define I2C4_BASE   (APB1PERIPH_BASE + 0x6000UL)
 
#define I2C4_BASE   (D3_APB1PERIPH_BASE + 0x1C00UL)
 
#define I2C4_BASE   (D3_APB1PERIPH_BASE + 0x1C00UL)
 
#define I2C5_BASE   (D2_APB1PERIPH_BASE + 0x6400UL)
 
#define I2S2ext_BASE   (APB1PERIPH_BASE + 0x3400UL)
 
#define I2S2ext_BASE   (APB1PERIPH_BASE + 0x3400UL)
 
#define I2S2ext_BASE   (APB1PERIPH_BASE + 0x3400UL)
 
#define I2S3ext_BASE   (APB1PERIPH_BASE + 0x4000UL)
 
#define I2S3ext_BASE   (APB1PERIPH_BASE + 0x4000UL)
 
#define I2S3ext_BASE   (APB1PERIPH_BASE + 0x4000UL)
 
#define IWDG1_BASE   (D3_APB1PERIPH_BASE + 0x4800UL)
 
#define IWDG1_BASE   (D3_APB1PERIPH_BASE + 0x4800UL)
 
#define IWDG2_BASE   (D3_APB1PERIPH_BASE + 0x4C00UL)
 
#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000UL)
 
#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000UL)
 
#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000UL)
 
#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000UL)
 
#define JPEG_BASE   (AHB2PERIPH_BASE + 0x51000UL)
 
#define JPGDEC_BASE   (D1_AHB1PERIPH_BASE + 0x3000UL)
 
#define LPTIM1_BASE   (APB1PERIPH_BASE + 0x2400UL)
 
#define LPTIM1_BASE   (D2_APB1PERIPH_BASE + 0x2400UL)
 
#define LPTIM1_BASE   (D2_APB1PERIPH_BASE + 0x2400UL)
 
#define LPTIM2_BASE   (D3_APB1PERIPH_BASE + 0x2400UL)
 
#define LPTIM2_BASE   (D3_APB1PERIPH_BASE + 0x2400UL)
 
#define LPTIM3_BASE   (D3_APB1PERIPH_BASE + 0x2800UL)
 
#define LPTIM3_BASE   (D3_APB1PERIPH_BASE + 0x2800UL)
 
#define LPTIM4_BASE   (D3_APB1PERIPH_BASE + 0x2C00UL)
 
#define LPTIM4_BASE   (D3_APB1PERIPH_BASE + 0x2C00UL)
 
#define LPTIM5_BASE   (D3_APB1PERIPH_BASE + 0x3000UL)
 
#define LPTIM5_BASE   (D3_APB1PERIPH_BASE + 0x3000UL)
 
#define LPUART1_BASE   (D3_APB1PERIPH_BASE + 0x0C00UL)
 
#define LPUART1_BASE   (D3_APB1PERIPH_BASE + 0x0C00UL)
 
#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800UL)
 
#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800UL)
 
#define LTDC_BASE   (D1_APB1PERIPH_BASE + 0x1000UL)
 
#define LTDC_BASE   (D1_APB1PERIPH_BASE + 0x1000UL)
 
#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84UL)
 
#define LTDC_Layer1_BASE   (LTDC_BASE + 0x0084UL)
 
#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84UL)
 
#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84UL)
 
#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104UL)
 
#define LTDC_Layer2_BASE   (LTDC_BASE + 0x0104UL)
 
#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104UL)
 
#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104UL)
 
#define MDIOS_BASE   (APB2PERIPH_BASE + 0x7800UL)
 
#define MDIOS_BASE   (D2_APB1PERIPH_BASE + 0x9400UL)
 
#define MDIOS_BASE   (D2_APB1PERIPH_BASE + 0x9400UL)
 
#define MDMA_BASE   (D1_AHB1PERIPH_BASE + 0x0000UL)
 
#define MDMA_BASE   (D1_AHB1PERIPH_BASE + 0x0000UL)
 
#define MDMA_Channel0_BASE   (MDMA_BASE + 0x00000040UL)
 
#define MDMA_Channel0_BASE   (MDMA_BASE + 0x00000040UL)
 
#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)
 
#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)
 
#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)
 
#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)
 
#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)
 
#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)
 
#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)
 
#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)
 
#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)
 
#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)
 
#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)
 
#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)
 
#define MDMA_Channel1_BASE   (MDMA_BASE + 0x00000080UL)
 
#define MDMA_Channel1_BASE   (MDMA_BASE + 0x00000080UL)
 
#define MDMA_Channel2_BASE   (MDMA_BASE + 0x000000C0UL)
 
#define MDMA_Channel2_BASE   (MDMA_BASE + 0x000000C0UL)
 
#define MDMA_Channel3_BASE   (MDMA_BASE + 0x00000100UL)
 
#define MDMA_Channel3_BASE   (MDMA_BASE + 0x00000100UL)
 
#define MDMA_Channel4_BASE   (MDMA_BASE + 0x00000140UL)
 
#define MDMA_Channel4_BASE   (MDMA_BASE + 0x00000140UL)
 
#define MDMA_Channel5_BASE   (MDMA_BASE + 0x00000180UL)
 
#define MDMA_Channel5_BASE   (MDMA_BASE + 0x00000180UL)
 
#define MDMA_Channel6_BASE   (MDMA_BASE + 0x000001C0UL)
 
#define MDMA_Channel6_BASE   (MDMA_BASE + 0x000001C0UL)
 
#define MDMA_Channel7_BASE   (MDMA_BASE + 0x00000200UL)
 
#define MDMA_Channel7_BASE   (MDMA_BASE + 0x00000200UL)
 
#define MDMA_Channel8_BASE   (MDMA_BASE + 0x00000240UL)
 
#define MDMA_Channel8_BASE   (MDMA_BASE + 0x00000240UL)
 
#define MDMA_Channel9_BASE   (MDMA_BASE + 0x00000280UL)
 
#define MDMA_Channel9_BASE   (MDMA_BASE + 0x00000280UL)
 
#define OCTOSPI1_BASE   (0x90000000UL)
 
#define OCTOSPI1_R_BASE   (D1_AHB1PERIPH_BASE + 0x5000UL)
 
#define OCTOSPI2_BASE   (0x70000000UL)
 
#define OCTOSPI2_R_BASE   (D1_AHB1PERIPH_BASE + 0xA000UL)
 
#define OCTOSPIM_BASE   (D1_AHB1PERIPH_BASE + 0xB400UL)
 
#define OPAMP1_BASE   (D2_APB1PERIPH_BASE + 0x9000UL)
 
#define OPAMP1_BASE   (D2_APB1PERIPH_BASE + 0x9000UL)
 
#define OPAMP2_BASE   (D2_APB1PERIPH_BASE + 0x9010UL)
 
#define OPAMP2_BASE   (D2_APB1PERIPH_BASE + 0x9010UL)
 
#define OPAMP_BASE   (D2_APB1PERIPH_BASE + 0x9000UL)
 
#define OPAMP_BASE   (D2_APB1PERIPH_BASE + 0x9000UL)
 
#define OTFDEC1_BASE   (D1_AHB1PERIPH_BASE + 0xB800UL)
 
#define OTFDEC1_REGION1_BASE   (OTFDEC1_BASE + 0x20UL)
 
#define OTFDEC1_REGION2_BASE   (OTFDEC1_BASE + 0x50UL)
 
#define OTFDEC1_REGION3_BASE   (OTFDEC1_BASE + 0x80UL)
 
#define OTFDEC1_REGION4_BASE   (OTFDEC1_BASE + 0xB0UL)
 
#define OTFDEC2_BASE   (D1_AHB1PERIPH_BASE + 0xBC00UL)
 
#define OTFDEC2_REGION1_BASE   (OTFDEC2_BASE + 0x20UL)
 
#define OTFDEC2_REGION2_BASE   (OTFDEC2_BASE + 0x50UL)
 
#define OTFDEC2_REGION3_BASE   (OTFDEC2_BASE + 0x80UL)
 
#define OTFDEC2_REGION4_BASE   (OTFDEC2_BASE + 0xB0UL)
 
#define PACKAGE_BASE   0x1FFF7BF0UL
 
#define PACKAGE_BASE   0x1FFF7BF0UL
 
#define PACKAGE_BASE   0x1FFF7BF0UL
 
#define PACKAGE_BASE   0x1FF0F7E0UL
 
#define PACKAGESIZE_BASE   PACKAGE_BASE
 
#define PERIPH_BASE   0x40000000UL
 
#define PERIPH_BASE   0x40000000UL
 
#define PERIPH_BASE   0x40000000UL
 
#define PERIPH_BASE   0x40000000UL
 
#define PERIPH_BASE   (0x40000000UL)
 
#define PERIPH_BASE   (0x40000000UL)
 
#define PERIPH_BB_BASE   0x42000000UL
 
#define PERIPH_BB_BASE   0x42000000UL
 
#define PERIPH_BB_BASE   0x42000000UL
 
#define PSSI_BASE   (D2_AHB2PERIPH_BASE + 0x0400UL)
 
#define PWR_BASE   (APB1PERIPH_BASE + 0x7000UL)
 
#define PWR_BASE   (APB1PERIPH_BASE + 0x7000UL)
 
#define PWR_BASE   (APB1PERIPH_BASE + 0x7000UL)
 
#define PWR_BASE   (APB1PERIPH_BASE + 0x7000UL)
 
#define PWR_BASE   (D3_AHB1PERIPH_BASE + 0x4800UL)
 
#define PWR_BASE   (D3_AHB1PERIPH_BASE + 0x4800UL)
 
#define QSPI_BASE   0x90000000UL
 
#define QSPI_BASE   (0x90000000UL)
 
#define QSPI_R_BASE   0xA0001000UL
 
#define QSPI_R_BASE   0xA0001000UL
 
#define QSPI_R_BASE   (D1_AHB1PERIPH_BASE + 0x5000UL)
 
#define RAMDTCM_BASE   0x20000000UL
 
#define RAMECC1_BASE   (D1_AHB1PERIPH_BASE + 0x9000UL)
 
#define RAMECC1_BASE   (D1_AHB1PERIPH_BASE + 0x9000UL)
 
#define RAMECC1_Monitor1_BASE   (RAMECC1_BASE + 0x20UL)
 
#define RAMECC1_Monitor1_BASE   (RAMECC1_BASE + 0x20UL)
 
#define RAMECC1_Monitor2_BASE   (RAMECC1_BASE + 0x40UL)
 
#define RAMECC1_Monitor2_BASE   (RAMECC1_BASE + 0x40UL)
 
#define RAMECC1_Monitor3_BASE   (RAMECC1_BASE + 0x60UL)
 
#define RAMECC1_Monitor3_BASE   (RAMECC1_BASE + 0x60UL)
 
#define RAMECC1_Monitor4_BASE   (RAMECC1_BASE + 0x80UL)
 
#define RAMECC1_Monitor4_BASE   (RAMECC1_BASE + 0x80UL)
 
#define RAMECC1_Monitor5_BASE   (RAMECC1_BASE + 0xA0UL)
 
#define RAMECC1_Monitor5_BASE   (RAMECC1_BASE + 0xA0UL)
 
#define RAMECC1_Monitor6_BASE   (RAMECC1_BASE + 0xC0UL)
 
#define RAMECC2_BASE   (D2_AHB2PERIPH_BASE + 0x3000UL)
 
#define RAMECC2_BASE   (D2_AHB2PERIPH_BASE + 0x3000UL)
 
#define RAMECC2_Monitor1_BASE   (RAMECC2_BASE + 0x20UL)
 
#define RAMECC2_Monitor1_BASE   (RAMECC2_BASE + 0x20UL)
 
#define RAMECC2_Monitor2_BASE   (RAMECC2_BASE + 0x40UL)
 
#define RAMECC2_Monitor2_BASE   (RAMECC2_BASE + 0x40UL)
 
#define RAMECC2_Monitor3_BASE   (RAMECC2_BASE + 0x60UL)
 
#define RAMECC2_Monitor3_BASE   (RAMECC2_BASE + 0x60UL)
 
#define RAMECC2_Monitor4_BASE   (RAMECC2_BASE + 0x80UL)
 
#define RAMECC2_Monitor5_BASE   (RAMECC2_BASE + 0xA0UL)
 
#define RAMECC3_BASE   (D3_AHB1PERIPH_BASE + 0x7000UL)
 
#define RAMECC3_BASE   (D3_AHB1PERIPH_BASE + 0x7000UL)
 
#define RAMECC3_Monitor1_BASE   (RAMECC3_BASE + 0x20UL)
 
#define RAMECC3_Monitor1_BASE   (RAMECC3_BASE + 0x20UL)
 
#define RAMECC3_Monitor2_BASE   (RAMECC3_BASE + 0x40UL)
 
#define RAMECC3_Monitor2_BASE   (RAMECC3_BASE + 0x40UL)
 
#define RAMITCM_BASE   0x00000000UL
 
#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800UL)
 
#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800UL)
 
#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800UL)
 
#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800UL)
 
#define RCC_BASE   (D3_AHB1PERIPH_BASE + 0x4400UL)
 
#define RCC_BASE   (D3_AHB1PERIPH_BASE + 0x4400UL)
 
#define RCC_C1_BASE   (RCC_BASE + 0x130UL)
 
#define RCC_C2_BASE   (RCC_BASE + 0x190UL)
 
#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800UL)
 
#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800UL)
 
#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800UL)
 
#define RNG_BASE   (D2_AHB2PERIPH_BASE + 0x1800UL)
 
#define RNG_BASE   (D2_AHB2PERIPH_BASE + 0x1800UL)
 
#define RTC_BASE   (APB1PERIPH_BASE + 0x2800UL)
 
#define RTC_BASE   (APB1PERIPH_BASE + 0x2800UL)
 
#define RTC_BASE   (APB1PERIPH_BASE + 0x2800UL)
 
#define RTC_BASE   (APB1PERIPH_BASE + 0x2800UL)
 
#define RTC_BASE   (D3_APB1PERIPH_BASE + 0x4000UL)
 
#define RTC_BASE   (D3_APB1PERIPH_BASE + 0x4000UL)
 
#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800UL)
 
#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800UL)
 
#define SAI1_BASE   (D2_APB2PERIPH_BASE + 0x5800UL)
 
#define SAI1_BASE   (D2_APB2PERIPH_BASE + 0x5800UL)
 
#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004UL)
 
#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004UL)
 
#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004UL)
 
#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004UL)
 
#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024UL)
 
#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024UL)
 
#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024UL)
 
#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024UL)
 
#define SAI2_BASE   (APB2PERIPH_BASE + 0x5C00UL)
 
#define SAI2_BASE   (D2_APB2PERIPH_BASE + 0x5C00UL)
 
#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004UL)
 
#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004UL)
 
#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024UL)
 
#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024UL)
 
#define SAI3_BASE   (D2_APB2PERIPH_BASE + 0x6000UL)
 
#define SAI3_Block_A_BASE   (SAI3_BASE + 0x004UL)
 
#define SAI3_Block_B_BASE   (SAI3_BASE + 0x024UL)
 
#define SAI4_BASE   (D3_APB1PERIPH_BASE + 0x5400UL)
 
#define SAI4_BASE   (D3_APB1PERIPH_BASE + 0x5400UL)
 
#define SAI4_Block_A_BASE   (SAI4_BASE + 0x004UL)
 
#define SAI4_Block_A_BASE   (SAI4_BASE + 0x004UL)
 
#define SAI4_Block_B_BASE   (SAI4_BASE + 0x024UL)
 
#define SAI4_Block_B_BASE   (SAI4_BASE + 0x024UL)
 
#define SDIO_BASE   (APB2PERIPH_BASE + 0x2C00UL)
 
#define SDIO_BASE   (APB2PERIPH_BASE + 0x2C00UL)
 
#define SDIO_BASE   (APB2PERIPH_BASE + 0x2C00UL)
 
#define SDMMC1_BASE   (APB2PERIPH_BASE + 0x2C00UL)
 
#define SDMMC1_BASE   (D1_AHB1PERIPH_BASE + 0x7000UL)
 
#define SDMMC1_BASE   (D1_AHB1PERIPH_BASE + 0x7000UL)
 
#define SDMMC2_BASE   (APB2PERIPH_BASE + 0x1C00UL)
 
#define SDMMC2_BASE   (D2_AHB2PERIPH_BASE + 0x2400UL)
 
#define SDMMC2_BASE   (D2_AHB2PERIPH_BASE + 0x2400UL)
 
#define SPDIFRX_BASE   (APB1PERIPH_BASE + 0x4000UL)
 
#define SPDIFRX_BASE   (D2_APB1PERIPH_BASE + 0x4000UL)
 
#define SPDIFRX_BASE   (D2_APB1PERIPH_BASE + 0x4000UL)
 
#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000UL)
 
#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000UL)
 
#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000UL)
 
#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000UL)
 
#define SPI1_BASE   (D2_APB2PERIPH_BASE + 0x3000UL)
 
#define SPI1_BASE   (D2_APB2PERIPH_BASE + 0x3000UL)
 
#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800UL)
 
#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800UL)
 
#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800UL)
 
#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800UL)
 
#define SPI2_BASE   (D2_APB1PERIPH_BASE + 0x3800UL)
 
#define SPI2_BASE   (D2_APB1PERIPH_BASE + 0x3800UL)
 
#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00UL)
 
#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00UL)
 
#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00UL)
 
#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00UL)
 
#define SPI3_BASE   (D2_APB1PERIPH_BASE + 0x3C00UL)
 
#define SPI3_BASE   (D2_APB1PERIPH_BASE + 0x3C00UL)
 
#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400UL)
 
#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400UL)
 
#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400UL)
 
#define SPI4_BASE   (D2_APB2PERIPH_BASE + 0x3400UL)
 
#define SPI4_BASE   (D2_APB2PERIPH_BASE + 0x3400UL)
 
#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000UL)
 
#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000UL)
 
#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000UL)
 
#define SPI5_BASE   (D2_APB2PERIPH_BASE + 0x5000UL)
 
#define SPI5_BASE   (D2_APB2PERIPH_BASE + 0x5000UL)
 
#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400UL)
 
#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400UL)
 
#define SPI6_BASE   (D3_APB1PERIPH_BASE + 0x1400UL)
 
#define SPI6_BASE   (D3_APB1PERIPH_BASE + 0x1400UL)
 
#define SRAM1_BASE   0x20000000UL
 
#define SRAM1_BASE   0x20000000UL
 
#define SRAM1_BASE   0x20000000UL
 
#define SRAM1_BASE   0x20020000UL
 
#define SRAM1_BB_BASE   0x22000000UL
 
#define SRAM1_BB_BASE   0x22000000UL
 
#define SRAM1_BB_BASE   0x22000000UL
 
#define SRAM2_BASE   0x2001C000UL
 
#define SRAM2_BASE   0x20028000UL
 
#define SRAM2_BASE   0x2007C000UL
 
#define SRAM2_BB_BASE   0x22380000UL
 
#define SRAM2_BB_BASE   0x22500000UL
 
#define SRAM3_BASE   0x20030000UL
 
#define SRAM3_BB_BASE   0x22600000UL
 
#define SRAM_BASE   SRAM1_BASE
 
#define SRAM_BASE   SRAM1_BASE
 
#define SRAM_BASE   SRAM1_BASE
 
#define SRAM_BB_BASE   SRAM1_BB_BASE
 
#define SRAM_BB_BASE   SRAM1_BB_BASE
 
#define SRAM_BB_BASE   SRAM1_BB_BASE
 
#define SRAMCAN_BASE   (D2_APB1PERIPH_BASE + 0xAC00UL)
 
#define SRAMCAN_BASE   (D2_APB1PERIPH_BASE + 0xAC00UL)
 
#define SWPMI1_BASE   (D2_APB1PERIPH_BASE + 0x8800UL)
 
#define SWPMI1_BASE   (D2_APB1PERIPH_BASE + 0x8800UL)
 
#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800UL)
 
#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800UL)
 
#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800UL)
 
#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800UL)
 
#define SYSCFG_BASE   (D3_APB1PERIPH_BASE + 0x0400UL)
 
#define SYSCFG_BASE   (D3_APB1PERIPH_BASE + 0x0400UL)
 
#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400UL)
 
#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400UL)
 
#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400UL)
 
#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400UL)
 
#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800UL)
 
#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800UL)
 
#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800UL)
 
#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800UL)
 
#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800UL)
 
#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800UL)
 
#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800UL)
 
#define TIM12_BASE   (D2_APB1PERIPH_BASE + 0x1800UL)
 
#define TIM12_BASE   (D2_APB1PERIPH_BASE + 0x1800UL)
 
#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00UL)
 
#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00UL)
 
#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00UL)
 
#define TIM13_BASE   (D2_APB1PERIPH_BASE + 0x1C00UL)
 
#define TIM13_BASE   (D2_APB1PERIPH_BASE + 0x1C00UL)
 
#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000UL)
 
#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000UL)
 
#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000UL)
 
#define TIM14_BASE   (D2_APB1PERIPH_BASE + 0x2000UL)
 
#define TIM14_BASE   (D2_APB1PERIPH_BASE + 0x2000UL)
 
#define TIM15_BASE   (D2_APB2PERIPH_BASE + 0x4000UL)
 
#define TIM15_BASE   (D2_APB2PERIPH_BASE + 0x4000UL)
 
#define TIM16_BASE   (D2_APB2PERIPH_BASE + 0x4400UL)
 
#define TIM16_BASE   (D2_APB2PERIPH_BASE + 0x4400UL)
 
#define TIM17_BASE   (D2_APB2PERIPH_BASE + 0x4800UL)
 
#define TIM17_BASE   (D2_APB2PERIPH_BASE + 0x4800UL)
 
#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000UL)
 
#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000UL)
 
#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000UL)
 
#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000UL)
 
#define TIM1_BASE   (D2_APB2PERIPH_BASE + 0x0000UL)
 
#define TIM1_BASE   (D2_APB2PERIPH_BASE + 0x0000UL)
 
#define TIM23_BASE   (D2_APB1PERIPH_BASE + 0xE000UL)
 
#define TIM24_BASE   (D2_APB1PERIPH_BASE + 0xE400UL)
 
#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000UL)
 
#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000UL)
 
#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000UL)
 
#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000UL)
 
#define TIM2_BASE   (D2_APB1PERIPH_BASE + 0x0000UL)
 
#define TIM2_BASE   (D2_APB1PERIPH_BASE + 0x0000UL)
 
#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400UL)
 
#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400UL)
 
#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400UL)
 
#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400UL)
 
#define TIM3_BASE   (D2_APB1PERIPH_BASE + 0x0400UL)
 
#define TIM3_BASE   (D2_APB1PERIPH_BASE + 0x0400UL)
 
#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800UL)
 
#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800UL)
 
#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800UL)
 
#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800UL)
 
#define TIM4_BASE   (D2_APB1PERIPH_BASE + 0x0800UL)
 
#define TIM4_BASE   (D2_APB1PERIPH_BASE + 0x0800UL)
 
#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00UL)
 
#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00UL)
 
#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00UL)
 
#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00UL)
 
#define TIM5_BASE   (D2_APB1PERIPH_BASE + 0x0C00UL)
 
#define TIM5_BASE   (D2_APB1PERIPH_BASE + 0x0C00UL)
 
#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000UL)
 
#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000UL)
 
#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000UL)
 
#define TIM6_BASE   (D2_APB1PERIPH_BASE + 0x1000UL)
 
#define TIM6_BASE   (D2_APB1PERIPH_BASE + 0x1000UL)
 
#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400UL)
 
#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400UL)
 
#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400UL)
 
#define TIM7_BASE   (D2_APB1PERIPH_BASE + 0x1400UL)
 
#define TIM7_BASE   (D2_APB1PERIPH_BASE + 0x1400UL)
 
#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400UL)
 
#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400UL)
 
#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400UL)
 
#define TIM8_BASE   (D2_APB2PERIPH_BASE + 0x0400UL)
 
#define TIM8_BASE   (D2_APB2PERIPH_BASE + 0x0400UL)
 
#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000UL)
 
#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000UL)
 
#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000UL)
 
#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000UL)
 
#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00UL)
 
#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00UL)
 
#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00UL)
 
#define UART4_BASE   (D2_APB1PERIPH_BASE + 0x4C00UL)
 
#define UART4_BASE   (D2_APB1PERIPH_BASE + 0x4C00UL)
 
#define UART5_BASE   (APB1PERIPH_BASE + 0x5000UL)
 
#define UART5_BASE   (APB1PERIPH_BASE + 0x5000UL)
 
#define UART5_BASE   (APB1PERIPH_BASE + 0x5000UL)
 
#define UART5_BASE   (D2_APB1PERIPH_BASE + 0x5000UL)
 
#define UART5_BASE   (D2_APB1PERIPH_BASE + 0x5000UL)
 
#define UART7_BASE   (APB1PERIPH_BASE + 0x7800UL)
 
#define UART7_BASE   (APB1PERIPH_BASE + 0x7800UL)
 
#define UART7_BASE   (D2_APB1PERIPH_BASE + 0x7800UL)
 
#define UART7_BASE   (D2_APB1PERIPH_BASE + 0x7800UL)
 
#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00UL)
 
#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00UL)
 
#define UART8_BASE   (D2_APB1PERIPH_BASE + 0x7C00UL)
 
#define UART8_BASE   (D2_APB1PERIPH_BASE + 0x7C00UL)
 
#define UART9_BASE   (D2_APB2PERIPH_BASE + 0x1800UL)
 
#define UID_BASE   0x1FFF7A10UL
 
#define UID_BASE   0x1FFF7A10UL
 
#define UID_BASE   0x1FFF7A10UL
 
#define UID_BASE   0x1FF0F420UL
 
#define UID_BASE   (0x1FF1E800UL)
 
#define UID_BASE   (0x1FF1E800UL)
 
#define USART10_BASE   (D2_APB2PERIPH_BASE + 0x1C00UL)
 
#define USART1_BASE   (APB2PERIPH_BASE + 0x1000UL)
 
#define USART1_BASE   (APB2PERIPH_BASE + 0x1000UL)
 
#define USART1_BASE   (APB2PERIPH_BASE + 0x1000UL)
 
#define USART1_BASE   (APB2PERIPH_BASE + 0x1000UL)
 
#define USART1_BASE   (D2_APB2PERIPH_BASE + 0x1000UL)
 
#define USART1_BASE   (D2_APB2PERIPH_BASE + 0x1000UL)
 
#define USART2_BASE   (APB1PERIPH_BASE + 0x4400UL)
 
#define USART2_BASE   (APB1PERIPH_BASE + 0x4400UL)
 
#define USART2_BASE   (APB1PERIPH_BASE + 0x4400UL)
 
#define USART2_BASE   (APB1PERIPH_BASE + 0x4400UL)
 
#define USART2_BASE   (D2_APB1PERIPH_BASE + 0x4400UL)
 
#define USART2_BASE   (D2_APB1PERIPH_BASE + 0x4400UL)
 
#define USART3_BASE   (APB1PERIPH_BASE + 0x4800UL)
 
#define USART3_BASE   (APB1PERIPH_BASE + 0x4800UL)
 
#define USART3_BASE   (APB1PERIPH_BASE + 0x4800UL)
 
#define USART3_BASE   (D2_APB1PERIPH_BASE + 0x4800UL)
 
#define USART3_BASE   (D2_APB1PERIPH_BASE + 0x4800UL)
 
#define USART6_BASE   (APB2PERIPH_BASE + 0x1400UL)
 
#define USART6_BASE   (APB2PERIPH_BASE + 0x1400UL)
 
#define USART6_BASE   (APB2PERIPH_BASE + 0x1400UL)
 
#define USART6_BASE   (APB2PERIPH_BASE + 0x1400UL)
 
#define USART6_BASE   (D2_APB2PERIPH_BASE + 0x1400UL)
 
#define USART6_BASE   (D2_APB2PERIPH_BASE + 0x1400UL)
 
#define USB1_OTG_HS_PERIPH_BASE   (0x40040000UL)
 
#define USB1_OTG_HS_PERIPH_BASE   (0x40040000UL)
 
#define USB2_OTG_FS_PERIPH_BASE   (0x40080000UL)
 
#define USB_OTG_DEVICE_BASE   0x800UL
 
#define USB_OTG_DEVICE_BASE   0x800UL
 
#define USB_OTG_DEVICE_BASE   0x800UL
 
#define USB_OTG_DEVICE_BASE   0x0800UL
 
#define USB_OTG_DEVICE_BASE   (0x800UL)
 
#define USB_OTG_DEVICE_BASE   (0x800UL)
 
#define USB_OTG_EP_REG_SIZE   0x20UL
 
#define USB_OTG_EP_REG_SIZE   0x20UL
 
#define USB_OTG_EP_REG_SIZE   0x20UL
 
#define USB_OTG_EP_REG_SIZE   0x0020UL
 
#define USB_OTG_EP_REG_SIZE   (0x20UL)
 
#define USB_OTG_EP_REG_SIZE   (0x20UL)
 
#define USB_OTG_FIFO_BASE   0x1000UL
 
#define USB_OTG_FIFO_BASE   0x1000UL
 
#define USB_OTG_FIFO_BASE   0x1000UL
 
#define USB_OTG_FIFO_BASE   0x1000UL
 
#define USB_OTG_FIFO_BASE   (0x1000UL)
 
#define USB_OTG_FIFO_BASE   (0x1000UL)
 
#define USB_OTG_FIFO_SIZE   0x1000UL
 
#define USB_OTG_FIFO_SIZE   0x1000UL
 
#define USB_OTG_FIFO_SIZE   0x1000UL
 
#define USB_OTG_FIFO_SIZE   0x1000UL
 
#define USB_OTG_FIFO_SIZE   (0x1000UL)
 
#define USB_OTG_FIFO_SIZE   (0x1000UL)
 
#define USB_OTG_FS_PERIPH_BASE   0x50000000UL
 
#define USB_OTG_FS_PERIPH_BASE   0x50000000UL
 
#define USB_OTG_FS_PERIPH_BASE   0x50000000UL
 
#define USB_OTG_FS_PERIPH_BASE   0x50000000UL
 
#define USB_OTG_GLOBAL_BASE   0x000UL
 
#define USB_OTG_GLOBAL_BASE   0x000UL
 
#define USB_OTG_GLOBAL_BASE   0x000UL
 
#define USB_OTG_GLOBAL_BASE   0x0000UL
 
#define USB_OTG_GLOBAL_BASE   (0x000UL)
 
#define USB_OTG_GLOBAL_BASE   (0x000UL)
 
#define USB_OTG_HOST_BASE   0x400UL
 
#define USB_OTG_HOST_BASE   0x400UL
 
#define USB_OTG_HOST_BASE   0x400UL
 
#define USB_OTG_HOST_BASE   0x0400UL
 
#define USB_OTG_HOST_BASE   (0x400UL)
 
#define USB_OTG_HOST_BASE   (0x400UL)
 
#define USB_OTG_HOST_CHANNEL_BASE   0x500UL
 
#define USB_OTG_HOST_CHANNEL_BASE   0x500UL
 
#define USB_OTG_HOST_CHANNEL_BASE   0x500UL
 
#define USB_OTG_HOST_CHANNEL_BASE   0x0500UL
 
#define USB_OTG_HOST_CHANNEL_BASE   (0x500UL)
 
#define USB_OTG_HOST_CHANNEL_BASE   (0x500UL)
 
#define USB_OTG_HOST_CHANNEL_SIZE   0x20UL
 
#define USB_OTG_HOST_CHANNEL_SIZE   0x20UL
 
#define USB_OTG_HOST_CHANNEL_SIZE   0x20UL
 
#define USB_OTG_HOST_CHANNEL_SIZE   0x0020UL
 
#define USB_OTG_HOST_CHANNEL_SIZE   (0x20UL)
 
#define USB_OTG_HOST_CHANNEL_SIZE   (0x20UL)
 
#define USB_OTG_HOST_PORT_BASE   0x440UL
 
#define USB_OTG_HOST_PORT_BASE   0x440UL
 
#define USB_OTG_HOST_PORT_BASE   0x440UL
 
#define USB_OTG_HOST_PORT_BASE   0x0440UL
 
#define USB_OTG_HOST_PORT_BASE   (0x440UL)
 
#define USB_OTG_HOST_PORT_BASE   (0x440UL)
 
#define USB_OTG_HS_PERIPH_BASE   0x40040000UL
 
#define USB_OTG_HS_PERIPH_BASE   0x40040000UL
 
#define USB_OTG_HS_PERIPH_BASE   0x40040000UL
 
#define USB_OTG_IN_ENDPOINT_BASE   0x900UL
 
#define USB_OTG_IN_ENDPOINT_BASE   0x900UL
 
#define USB_OTG_IN_ENDPOINT_BASE   0x900UL
 
#define USB_OTG_IN_ENDPOINT_BASE   0x0900UL
 
#define USB_OTG_IN_ENDPOINT_BASE   (0x900UL)
 
#define USB_OTG_IN_ENDPOINT_BASE   (0x900UL)
 
#define USB_OTG_OUT_ENDPOINT_BASE   0xB00UL
 
#define USB_OTG_OUT_ENDPOINT_BASE   0xB00UL
 
#define USB_OTG_OUT_ENDPOINT_BASE   0xB00UL
 
#define USB_OTG_OUT_ENDPOINT_BASE   0x0B00UL
 
#define USB_OTG_OUT_ENDPOINT_BASE   (0xB00UL)
 
#define USB_OTG_OUT_ENDPOINT_BASE   (0xB00UL)
 
#define USB_OTG_PCGCCTL_BASE   0xE00UL
 
#define USB_OTG_PCGCCTL_BASE   0xE00UL
 
#define USB_OTG_PCGCCTL_BASE   0xE00UL
 
#define USB_OTG_PCGCCTL_BASE   0x0E00UL
 
#define USB_OTG_PCGCCTL_BASE   (0xE00UL)
 
#define USB_OTG_PCGCCTL_BASE   (0xE00UL)
 
#define VREFBUF_BASE   (D3_APB1PERIPH_BASE + 0x3C00UL)
 
#define VREFBUF_BASE   (D3_APB1PERIPH_BASE + 0x3C00UL)
 
#define WWDG1_BASE   (D1_APB1PERIPH_BASE + 0x3000UL)
 
#define WWDG1_BASE   (D1_APB1PERIPH_BASE + 0x3000UL)
 
#define WWDG2_BASE   (D2_APB1PERIPH_BASE + 0x2C00UL)
 
#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00UL)
 
#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00UL)
 
#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00UL)
 
#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00UL)
 

Detailed Description

Macro Definition Documentation

◆ ADC123_COMMON_BASE [1/2]

#define ADC123_COMMON_BASE   (APB2PERIPH_BASE + 0x2300UL)

Definition at line 970 of file stm32f407xx.h.

◆ ADC123_COMMON_BASE [2/2]

#define ADC123_COMMON_BASE   (APB2PERIPH_BASE + 0x2300UL)

Definition at line 1182 of file stm32f469xx.h.

◆ ADC12_COMMON_BASE [1/2]

#define ADC12_COMMON_BASE   (D2_AHB1PERIPH_BASE + 0x2300UL)

Definition at line 2192 of file stm32h747xx.h.

◆ ADC12_COMMON_BASE [2/2]

#define ADC12_COMMON_BASE   (D2_AHB1PERIPH_BASE + 0x2300UL)

Definition at line 2246 of file stm32h735xx.h.

◆ ADC1_BASE [1/6]

#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000UL)

Definition at line 679 of file stm32f411xe.h.

◆ ADC1_BASE [2/6]

#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000UL)

Definition at line 967 of file stm32f407xx.h.

◆ ADC1_BASE [3/6]

#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000UL)

Definition at line 1179 of file stm32f469xx.h.

◆ ADC1_BASE [4/6]

#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000UL)

Definition at line 1436 of file stm32f769xx.h.

◆ ADC1_BASE [5/6]

#define ADC1_BASE   (D2_AHB1PERIPH_BASE + 0x2000UL)

Definition at line 2190 of file stm32h747xx.h.

◆ ADC1_BASE [6/6]

#define ADC1_BASE   (D2_AHB1PERIPH_BASE + 0x2000UL)

Definition at line 2244 of file stm32h735xx.h.

◆ ADC1_COMMON_BASE

#define ADC1_COMMON_BASE   (APB2PERIPH_BASE + 0x2300UL)

Definition at line 680 of file stm32f411xe.h.

◆ ADC2_BASE [1/5]

#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100UL)

Definition at line 968 of file stm32f407xx.h.

◆ ADC2_BASE [2/5]

#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100UL)

Definition at line 1180 of file stm32f469xx.h.

◆ ADC2_BASE [3/5]

#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100UL)

Definition at line 1437 of file stm32f769xx.h.

◆ ADC2_BASE [4/5]

#define ADC2_BASE   (D2_AHB1PERIPH_BASE + 0x2100UL)

Definition at line 2191 of file stm32h747xx.h.

◆ ADC2_BASE [5/5]

#define ADC2_BASE   (D2_AHB1PERIPH_BASE + 0x2100UL)

Definition at line 2245 of file stm32h735xx.h.

◆ ADC3_BASE [1/5]

#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200UL)

Definition at line 969 of file stm32f407xx.h.

◆ ADC3_BASE [2/5]

#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200UL)

Definition at line 1181 of file stm32f469xx.h.

◆ ADC3_BASE [3/5]

#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200UL)

Definition at line 1438 of file stm32f769xx.h.

◆ ADC3_BASE [4/5]

#define ADC3_BASE   (D3_AHB1PERIPH_BASE + 0x6000UL)

Definition at line 2240 of file stm32h747xx.h.

◆ ADC3_BASE [5/5]

#define ADC3_BASE   (D3_AHB1PERIPH_BASE + 0x6000UL)

Definition at line 2295 of file stm32h735xx.h.

◆ ADC3_COMMON_BASE [1/2]

#define ADC3_COMMON_BASE   (D3_AHB1PERIPH_BASE + 0x6300UL)

Definition at line 2241 of file stm32h747xx.h.

◆ ADC3_COMMON_BASE [2/2]

#define ADC3_COMMON_BASE   (D3_AHB1PERIPH_BASE + 0x6300UL)

Definition at line 2296 of file stm32h735xx.h.

◆ ADC_BASE [1/4]

#define ADC_BASE   ADC1_COMMON_BASE

Definition at line 682 of file stm32f411xe.h.

◆ ADC_BASE [2/4]

#define ADC_BASE   ADC123_COMMON_BASE

Definition at line 972 of file stm32f407xx.h.

◆ ADC_BASE [3/4]

#define ADC_BASE   ADC123_COMMON_BASE

Definition at line 1184 of file stm32f469xx.h.

◆ ADC_BASE [4/4]

#define ADC_BASE   (APB2PERIPH_BASE + 0x2300UL)

Definition at line 1439 of file stm32f769xx.h.

◆ AHB1PERIPH_BASE [1/6]

#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)

Definition at line 654 of file stm32f411xe.h.

◆ AHB1PERIPH_BASE [2/6]

#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)

Definition at line 930 of file stm32f407xx.h.

◆ AHB1PERIPH_BASE [3/6]

#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)

Definition at line 1140 of file stm32f469xx.h.

◆ AHB1PERIPH_BASE [4/6]

#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)

Definition at line 1393 of file stm32f769xx.h.

◆ AHB1PERIPH_BASE [5/6]

#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)

Definition at line 2168 of file stm32h747xx.h.

◆ AHB1PERIPH_BASE [6/6]

#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)

Definition at line 2209 of file stm32h735xx.h.

◆ AHB2PERIPH_BASE [1/6]

#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000UL)

APB1 peripherals

Definition at line 655 of file stm32f411xe.h.

◆ AHB2PERIPH_BASE [2/6]

#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000UL)

APB1 peripherals

Definition at line 931 of file stm32f407xx.h.

◆ AHB2PERIPH_BASE [3/6]

#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000UL)

APB1 peripherals

Definition at line 1141 of file stm32f469xx.h.

◆ AHB2PERIPH_BASE [4/6]

#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000UL)

APB1 peripherals

Definition at line 1394 of file stm32f769xx.h.

◆ AHB2PERIPH_BASE [5/6]

#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x08000000UL)

D1_AHB1PERIPH peripherals

Definition at line 2169 of file stm32h747xx.h.

◆ AHB2PERIPH_BASE [6/6]

#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x08000000UL)

D1_AHB1PERIPH peripherals

Definition at line 2210 of file stm32h735xx.h.

◆ APB1PERIPH_BASE [1/6]

#define APB1PERIPH_BASE   PERIPH_BASE

Definition at line 652 of file stm32f411xe.h.

◆ APB1PERIPH_BASE [2/6]

#define APB1PERIPH_BASE   PERIPH_BASE

Definition at line 928 of file stm32f407xx.h.

◆ APB1PERIPH_BASE [3/6]

#define APB1PERIPH_BASE   PERIPH_BASE

Definition at line 1138 of file stm32f469xx.h.

◆ APB1PERIPH_BASE [4/6]

#define APB1PERIPH_BASE   PERIPH_BASE

Definition at line 1391 of file stm32f769xx.h.

◆ APB1PERIPH_BASE [5/6]

#define APB1PERIPH_BASE   PERIPH_BASE

Definition at line 2166 of file stm32h747xx.h.

◆ APB1PERIPH_BASE [6/6]

#define APB1PERIPH_BASE   PERIPH_BASE

Definition at line 2207 of file stm32h735xx.h.

◆ APB2PERIPH_BASE [1/6]

#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)

Definition at line 653 of file stm32f411xe.h.

◆ APB2PERIPH_BASE [2/6]

#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)

Definition at line 929 of file stm32f407xx.h.

◆ APB2PERIPH_BASE [3/6]

#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)

Definition at line 1139 of file stm32f469xx.h.

◆ APB2PERIPH_BASE [4/6]

#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)

Definition at line 1392 of file stm32f769xx.h.

◆ APB2PERIPH_BASE [5/6]

#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)

Definition at line 2167 of file stm32h747xx.h.

◆ APB2PERIPH_BASE [6/6]

#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)

Definition at line 2208 of file stm32h735xx.h.

◆ ART_BASE

#define ART_BASE   (D2_AHB1PERIPH_BASE + 0x4400UL)

Definition at line 2193 of file stm32h747xx.h.

◆ BDMA_BASE [1/2]

#define BDMA_BASE   (D3_AHB1PERIPH_BASE + 0x5400UL)

Definition at line 2238 of file stm32h747xx.h.

◆ BDMA_BASE [2/2]

#define BDMA_BASE   (D3_AHB1PERIPH_BASE + 0x5400UL)

Definition at line 2293 of file stm32h735xx.h.

◆ BDMA_Channel0_BASE [1/2]

#define BDMA_Channel0_BASE   (BDMA_BASE + 0x0008UL)

Definition at line 2362 of file stm32h747xx.h.

◆ BDMA_Channel0_BASE [2/2]

#define BDMA_Channel0_BASE   (BDMA_BASE + 0x0008UL)

Definition at line 2408 of file stm32h735xx.h.

◆ BDMA_Channel1_BASE [1/2]

#define BDMA_Channel1_BASE   (BDMA_BASE + 0x001CUL)

Definition at line 2363 of file stm32h747xx.h.

◆ BDMA_Channel1_BASE [2/2]

#define BDMA_Channel1_BASE   (BDMA_BASE + 0x001CUL)

Definition at line 2409 of file stm32h735xx.h.

◆ BDMA_Channel2_BASE [1/2]

#define BDMA_Channel2_BASE   (BDMA_BASE + 0x0030UL)

Definition at line 2364 of file stm32h747xx.h.

◆ BDMA_Channel2_BASE [2/2]

#define BDMA_Channel2_BASE   (BDMA_BASE + 0x0030UL)

Definition at line 2410 of file stm32h735xx.h.

◆ BDMA_Channel3_BASE [1/2]

#define BDMA_Channel3_BASE   (BDMA_BASE + 0x0044UL)

Definition at line 2365 of file stm32h747xx.h.

◆ BDMA_Channel3_BASE [2/2]

#define BDMA_Channel3_BASE   (BDMA_BASE + 0x0044UL)

Definition at line 2411 of file stm32h735xx.h.

◆ BDMA_Channel4_BASE [1/2]

#define BDMA_Channel4_BASE   (BDMA_BASE + 0x0058UL)

Definition at line 2366 of file stm32h747xx.h.

◆ BDMA_Channel4_BASE [2/2]

#define BDMA_Channel4_BASE   (BDMA_BASE + 0x0058UL)

Definition at line 2412 of file stm32h735xx.h.

◆ BDMA_Channel5_BASE [1/2]

#define BDMA_Channel5_BASE   (BDMA_BASE + 0x006CUL)

Definition at line 2367 of file stm32h747xx.h.

◆ BDMA_Channel5_BASE [2/2]

#define BDMA_Channel5_BASE   (BDMA_BASE + 0x006CUL)

Definition at line 2413 of file stm32h735xx.h.

◆ BDMA_Channel6_BASE [1/2]

#define BDMA_Channel6_BASE   (BDMA_BASE + 0x0080UL)

Definition at line 2368 of file stm32h747xx.h.

◆ BDMA_Channel6_BASE [2/2]

#define BDMA_Channel6_BASE   (BDMA_BASE + 0x0080UL)

Definition at line 2414 of file stm32h735xx.h.

◆ BDMA_Channel7_BASE [1/2]

#define BDMA_Channel7_BASE   (BDMA_BASE + 0x0094UL)

Definition at line 2369 of file stm32h747xx.h.

◆ BDMA_Channel7_BASE [2/2]

#define BDMA_Channel7_BASE   (BDMA_BASE + 0x0094UL)

Definition at line 2415 of file stm32h735xx.h.

◆ BKPSRAM_BASE [1/3]

#define BKPSRAM_BASE   0x40024000UL

Backup SRAM(4 KB) base address in the alias region

Definition at line 912 of file stm32f407xx.h.

◆ BKPSRAM_BASE [2/3]

#define BKPSRAM_BASE   0x40024000UL

Backup SRAM(4 KB) base address in the alias region

Definition at line 1120 of file stm32f469xx.h.

◆ BKPSRAM_BASE [3/3]

#define BKPSRAM_BASE   0x40024000UL

Base address of : Backup SRAM(4 KB)

Definition at line 1377 of file stm32f769xx.h.

◆ BKPSRAM_BB_BASE [1/3]

#define BKPSRAM_BB_BASE   0x42480000UL

Backup SRAM(4 KB) base address in the bit-band region

Definition at line 642 of file stm32f411xe.h.

◆ BKPSRAM_BB_BASE [2/3]

#define BKPSRAM_BB_BASE   0x42480000UL

Backup SRAM(4 KB) base address in the bit-band region

Definition at line 917 of file stm32f407xx.h.

◆ BKPSRAM_BB_BASE [3/3]

#define BKPSRAM_BB_BASE   0x42480000UL

Backup SRAM(4 KB) base address in the bit-band region

Definition at line 1127 of file stm32f469xx.h.

◆ CAN1_BASE [1/3]

#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400UL)

Definition at line 957 of file stm32f407xx.h.

◆ CAN1_BASE [2/3]

#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400UL)

Definition at line 1167 of file stm32f469xx.h.

◆ CAN1_BASE [3/3]

#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400UL)

Definition at line 1422 of file stm32f769xx.h.

◆ CAN2_BASE [1/3]

#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800UL)

Definition at line 958 of file stm32f407xx.h.

◆ CAN2_BASE [2/3]

#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800UL)

Definition at line 1168 of file stm32f469xx.h.

◆ CAN2_BASE [3/3]

#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800UL)

Definition at line 1423 of file stm32f769xx.h.

◆ CAN3_BASE

#define CAN3_BASE   (APB1PERIPH_BASE + 0x3400UL)

Definition at line 1410 of file stm32f769xx.h.

◆ CCMDATARAM_BASE [1/2]

#define CCMDATARAM_BASE   0x10000000UL

CCM(core coupled memory) data RAM(64 KB) base address in the alias region

Definition at line 908 of file stm32f407xx.h.

◆ CCMDATARAM_BASE [2/2]

#define CCMDATARAM_BASE   0x10000000UL

CCM(core coupled memory) data RAM(64 KB) base address in the alias region

Definition at line 1115 of file stm32f469xx.h.

◆ CCMDATARAM_END [1/2]

#define CCMDATARAM_END   0x1000FFFFUL

CCM data RAM end address

Definition at line 921 of file stm32f407xx.h.

◆ CCMDATARAM_END [2/2]

#define CCMDATARAM_END   0x1000FFFFUL

CCM data RAM end address

Definition at line 1131 of file stm32f469xx.h.

◆ CEC_BASE [1/3]

#define CEC_BASE   (APB1PERIPH_BASE + 0x6C00UL)

Definition at line 1424 of file stm32f769xx.h.

◆ CEC_BASE [2/3]

#define CEC_BASE   (D2_APB1PERIPH_BASE + 0x6C00UL)

Definition at line 2276 of file stm32h747xx.h.

◆ CEC_BASE [3/3]

#define CEC_BASE   (D2_APB1PERIPH_BASE + 0x6C00UL)

Definition at line 2330 of file stm32h735xx.h.

◆ COMP12_BASE [1/2]

#define COMP12_BASE   (D3_APB1PERIPH_BASE + 0x3800UL)

Definition at line 2346 of file stm32h747xx.h.

◆ COMP12_BASE [2/2]

#define COMP12_BASE   (D3_APB1PERIPH_BASE + 0x3800UL)

Definition at line 2392 of file stm32h735xx.h.

◆ COMP1_BASE [1/2]

#define COMP1_BASE   (COMP12_BASE + 0x0CUL)

Definition at line 2347 of file stm32h747xx.h.

◆ COMP1_BASE [2/2]

#define COMP1_BASE   (COMP12_BASE + 0x0CUL)

Definition at line 2393 of file stm32h735xx.h.

◆ COMP2_BASE [1/2]

#define COMP2_BASE   (COMP12_BASE + 0x10UL)

Definition at line 2348 of file stm32h747xx.h.

◆ COMP2_BASE [2/2]

#define COMP2_BASE   (COMP12_BASE + 0x10UL)

Definition at line 2394 of file stm32h735xx.h.

◆ CORDIC_BASE

#define CORDIC_BASE   (D2_AHB2PERIPH_BASE + 0x4400UL)

D3_AHB1PERIPH peripherals

Definition at line 2277 of file stm32h735xx.h.

◆ CRC_BASE [1/6]

#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000UL)

Definition at line 700 of file stm32f411xe.h.

◆ CRC_BASE [2/6]

#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000UL)

Definition at line 991 of file stm32f407xx.h.

◆ CRC_BASE [3/6]

#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000UL)

Definition at line 1215 of file stm32f469xx.h.

◆ CRC_BASE [4/6]

#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000UL)

Definition at line 1486 of file stm32f769xx.h.

◆ CRC_BASE [5/6]

#define CRC_BASE   (D3_AHB1PERIPH_BASE + 0x4C00UL)

Definition at line 2237 of file stm32h747xx.h.

◆ CRC_BASE [6/6]

#define CRC_BASE   (D3_AHB1PERIPH_BASE + 0x4C00UL)

Definition at line 2292 of file stm32h735xx.h.

◆ CRS_BASE [1/2]

#define CRS_BASE   (D2_APB1PERIPH_BASE + 0x8400UL)

Definition at line 2280 of file stm32h747xx.h.

◆ CRS_BASE [2/2]

#define CRS_BASE   (D2_APB1PERIPH_BASE + 0x8400UL)

Definition at line 2334 of file stm32h735xx.h.

◆ CRYP_BASE

#define CRYP_BASE   (D2_AHB2PERIPH_BASE + 0x1000UL)

Definition at line 2269 of file stm32h735xx.h.

◆ D1_AHB1PERIPH_BASE [1/2]

#define D1_AHB1PERIPH_BASE   (PERIPH_BASE + 0x12000000UL)

Definition at line 2160 of file stm32h747xx.h.

◆ D1_AHB1PERIPH_BASE [2/2]

#define D1_AHB1PERIPH_BASE   (PERIPH_BASE + 0x12000000UL)

Definition at line 2201 of file stm32h735xx.h.

◆ D1_APB1PERIPH_BASE [1/2]

#define D1_APB1PERIPH_BASE   (PERIPH_BASE + 0x10000000UL)

Definition at line 2159 of file stm32h747xx.h.

◆ D1_APB1PERIPH_BASE [2/2]

#define D1_APB1PERIPH_BASE   (PERIPH_BASE + 0x10000000UL)

Definition at line 2200 of file stm32h735xx.h.

◆ D1_AXIFLASH_BASE [1/2]

#define D1_AXIFLASH_BASE   (0x08000000UL)

Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI

Definition at line 2128 of file stm32h747xx.h.

◆ D1_AXIFLASH_BASE [2/2]

#define D1_AXIFLASH_BASE   (0x08000000UL)

Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI

Definition at line 2165 of file stm32h735xx.h.

◆ D1_AXIICP_BASE [1/2]

#define D1_AXIICP_BASE   (0x1FF00000UL)

Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI

Definition at line 2129 of file stm32h747xx.h.

◆ D1_AXIICP_BASE [2/2]

#define D1_AXIICP_BASE   (0x1FF00000UL)

Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI

Definition at line 2166 of file stm32h735xx.h.

◆ D1_AXISRAM1_BASE

#define D1_AXISRAM1_BASE   (0x24000000UL)

Base address of : (up to 128KB) system data RAM1 accessible over over AXI

Definition at line 2167 of file stm32h735xx.h.

◆ D1_AXISRAM2_BASE

#define D1_AXISRAM2_BASE   (0x24020000UL)

Base address of : (up to 192KB) system data RAM2 accessible over over AXI to be shared with ITCM (64K granularity)

Definition at line 2168 of file stm32h735xx.h.

◆ D1_AXISRAM_BASE [1/2]

#define D1_AXISRAM_BASE   (0x24000000UL)

Base address of : (up to 512KB) system data RAM accessible over over AXI

Definition at line 2130 of file stm32h747xx.h.

◆ D1_AXISRAM_BASE [2/2]

#define D1_AXISRAM_BASE   D1_AXISRAM1_BASE

Base address of : (up to 320KB) system data RAM1/2 accessible over over AXI

Definition at line 2169 of file stm32h735xx.h.

◆ D1_DTCMRAM_BASE [1/2]

#define D1_DTCMRAM_BASE   (0x20000000UL)

Base address of : 128KB system data RAM accessible over DTCM

Definition at line 2127 of file stm32h747xx.h.

◆ D1_DTCMRAM_BASE [2/2]

#define D1_DTCMRAM_BASE   (0x20000000UL)

Base address of : 128KB system data RAM accessible over DTCM

Definition at line 2164 of file stm32h735xx.h.

◆ D1_ITCMICP_BASE [1/2]

#define D1_ITCMICP_BASE   (0x00100000UL)

Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM

Definition at line 2126 of file stm32h747xx.h.

◆ D1_ITCMICP_BASE [2/2]

#define D1_ITCMICP_BASE   (0x00100000UL)

Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM

Definition at line 2163 of file stm32h735xx.h.

◆ D1_ITCMRAM_BASE [1/2]

#define D1_ITCMRAM_BASE   (0x00000000UL)

Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM

Definition at line 2125 of file stm32h747xx.h.

◆ D1_ITCMRAM_BASE [2/2]

#define D1_ITCMRAM_BASE   (0x00000000UL)

Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM

Definition at line 2162 of file stm32h735xx.h.

◆ D2_AHB1PERIPH_BASE [1/2]

#define D2_AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)

Definition at line 2156 of file stm32h747xx.h.

◆ D2_AHB1PERIPH_BASE [2/2]

#define D2_AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)

Definition at line 2197 of file stm32h735xx.h.

◆ D2_AHB2PERIPH_BASE [1/2]

#define D2_AHB2PERIPH_BASE   (PERIPH_BASE + 0x08020000UL)

Definition at line 2157 of file stm32h747xx.h.

◆ D2_AHB2PERIPH_BASE [2/2]

#define D2_AHB2PERIPH_BASE   (PERIPH_BASE + 0x08020000UL)

Definition at line 2198 of file stm32h735xx.h.

◆ D2_AHBSRAM1_BASE

#define D2_AHBSRAM1_BASE   (0x30000000UL)

Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge

Definition at line 2171 of file stm32h735xx.h.

◆ D2_AHBSRAM2_BASE

#define D2_AHBSRAM2_BASE   (0x30004000UL)

Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge

Definition at line 2172 of file stm32h735xx.h.

◆ D2_AHBSRAM_BASE [1/2]

#define D2_AHBSRAM_BASE   (0x30000000UL)

Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge

Definition at line 2133 of file stm32h747xx.h.

◆ D2_AHBSRAM_BASE [2/2]

#define D2_AHBSRAM_BASE   D2_AHBSRAM1_BASE

Base address of : (up to 32KB) system data RAM1/2 accessible over over AXI->AHB Bridge

Definition at line 2173 of file stm32h735xx.h.

◆ D2_APB1PERIPH_BASE [1/2]

#define D2_APB1PERIPH_BASE   PERIPH_BASE

Definition at line 2154 of file stm32h747xx.h.

◆ D2_APB1PERIPH_BASE [2/2]

#define D2_APB1PERIPH_BASE   PERIPH_BASE

Definition at line 2195 of file stm32h735xx.h.

◆ D2_APB2PERIPH_BASE [1/2]

#define D2_APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)

Definition at line 2155 of file stm32h747xx.h.

◆ D2_APB2PERIPH_BASE [2/2]

#define D2_APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)

Definition at line 2196 of file stm32h735xx.h.

◆ D2_AXISRAM_BASE

#define D2_AXISRAM_BASE   (0x10000000UL)

Base address of : (up to 288KB) system data RAM accessible over over AXI

Definition at line 2132 of file stm32h747xx.h.

◆ D3_AHB1PERIPH_BASE [1/2]

#define D3_AHB1PERIPH_BASE   (PERIPH_BASE + 0x18020000UL)

Legacy Peripheral memory map

Definition at line 2163 of file stm32h747xx.h.

◆ D3_AHB1PERIPH_BASE [2/2]

#define D3_AHB1PERIPH_BASE   (PERIPH_BASE + 0x18020000UL)

Legacy Peripheral memory map

Definition at line 2204 of file stm32h735xx.h.

◆ D3_APB1PERIPH_BASE [1/2]

#define D3_APB1PERIPH_BASE   (PERIPH_BASE + 0x18000000UL)

Definition at line 2162 of file stm32h747xx.h.

◆ D3_APB1PERIPH_BASE [2/2]

#define D3_APB1PERIPH_BASE   (PERIPH_BASE + 0x18000000UL)

Definition at line 2203 of file stm32h735xx.h.

◆ D3_BKPSRAM_BASE [1/2]

#define D3_BKPSRAM_BASE   (0x38800000UL)

Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge

Definition at line 2135 of file stm32h747xx.h.

◆ D3_BKPSRAM_BASE [2/2]

#define D3_BKPSRAM_BASE   (0x38800000UL)

Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge

Definition at line 2175 of file stm32h735xx.h.

◆ D3_SRAM_BASE [1/2]

#define D3_SRAM_BASE   (0x38000000UL)

Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge

Definition at line 2136 of file stm32h747xx.h.

◆ D3_SRAM_BASE [2/2]

#define D3_SRAM_BASE   (0x38000000UL)

Base address of : Backup SRAM(16 KB) over AXI->AHB Bridge

Definition at line 2176 of file stm32h735xx.h.

◆ DAC1_BASE [1/2]

#define DAC1_BASE   (D2_APB1PERIPH_BASE + 0x7400UL)

Definition at line 2277 of file stm32h747xx.h.

◆ DAC1_BASE [2/2]

#define DAC1_BASE   (D2_APB1PERIPH_BASE + 0x7400UL)

Definition at line 2331 of file stm32h735xx.h.

◆ DAC_BASE [1/3]

#define DAC_BASE   (APB1PERIPH_BASE + 0x7400UL)

APB2 peripherals

Definition at line 960 of file stm32f407xx.h.

◆ DAC_BASE [2/3]

#define DAC_BASE   (APB1PERIPH_BASE + 0x7400UL)

Definition at line 1170 of file stm32f469xx.h.

◆ DAC_BASE [3/3]

#define DAC_BASE   (APB1PERIPH_BASE + 0x7400UL)

Definition at line 1426 of file stm32f769xx.h.

◆ DBGMCU_BASE [1/6]

#define DBGMCU_BASE   0xE0042000UL

USB registers base address

Definition at line 724 of file stm32f411xe.h.

◆ DBGMCU_BASE [2/6]

#define DBGMCU_BASE   0xE0042000UL

USB registers base address

Definition at line 1030 of file stm32f407xx.h.

◆ DBGMCU_BASE [3/6]

#define DBGMCU_BASE   0xE0042000UL

USB registers base address

Definition at line 1255 of file stm32f469xx.h.

◆ DBGMCU_BASE [4/6]

#define DBGMCU_BASE   0xE0042000UL

USB registers base address

Definition at line 1530 of file stm32f769xx.h.

◆ DBGMCU_BASE [5/6]

#define DBGMCU_BASE   (0x5C001000UL)

Definition at line 2447 of file stm32h747xx.h.

◆ DBGMCU_BASE [6/6]

#define DBGMCU_BASE   (0x5C001000UL)

Definition at line 2493 of file stm32h735xx.h.

◆ DCMI_BASE [1/5]

#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000UL)

Definition at line 1019 of file stm32f407xx.h.

◆ DCMI_BASE [2/5]

#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000UL)

Definition at line 1244 of file stm32f469xx.h.

◆ DCMI_BASE [3/5]

#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000UL)

Definition at line 1520 of file stm32f769xx.h.

◆ DCMI_BASE [4/5]

#define DCMI_BASE   (D2_AHB2PERIPH_BASE + 0x0000UL)

Definition at line 2215 of file stm32h747xx.h.

◆ DCMI_BASE [5/5]

#define DCMI_BASE   (D2_AHB2PERIPH_BASE + 0x0000UL)

Definition at line 2267 of file stm32h735xx.h.

◆ DFSDM1_BASE [1/3]

#define DFSDM1_BASE   (APB2PERIPH_BASE + 0x7400UL)

Definition at line 1460 of file stm32f769xx.h.

◆ DFSDM1_BASE [2/3]

#define DFSDM1_BASE   (D2_APB2PERIPH_BASE + 0x7000UL)

Definition at line 2312 of file stm32h747xx.h.

◆ DFSDM1_BASE [3/3]

#define DFSDM1_BASE   (D2_APB2PERIPH_BASE + 0x7800UL)

Definition at line 2365 of file stm32h735xx.h.

◆ DFSDM1_Channel0_BASE [1/3]

#define DFSDM1_Channel0_BASE   (DFSDM1_BASE + 0x00UL)

Definition at line 1461 of file stm32f769xx.h.

◆ DFSDM1_Channel0_BASE [2/3]

#define DFSDM1_Channel0_BASE   (DFSDM1_BASE + 0x00UL)

Definition at line 2313 of file stm32h747xx.h.

◆ DFSDM1_Channel0_BASE [3/3]

#define DFSDM1_Channel0_BASE   (DFSDM1_BASE + 0x00UL)

Definition at line 2366 of file stm32h735xx.h.

◆ DFSDM1_Channel1_BASE [1/3]

#define DFSDM1_Channel1_BASE   (DFSDM1_BASE + 0x20UL)

Definition at line 1462 of file stm32f769xx.h.

◆ DFSDM1_Channel1_BASE [2/3]

#define DFSDM1_Channel1_BASE   (DFSDM1_BASE + 0x20UL)

Definition at line 2314 of file stm32h747xx.h.

◆ DFSDM1_Channel1_BASE [3/3]

#define DFSDM1_Channel1_BASE   (DFSDM1_BASE + 0x20UL)

Definition at line 2367 of file stm32h735xx.h.

◆ DFSDM1_Channel2_BASE [1/3]

#define DFSDM1_Channel2_BASE   (DFSDM1_BASE + 0x40UL)

Definition at line 1463 of file stm32f769xx.h.

◆ DFSDM1_Channel2_BASE [2/3]

#define DFSDM1_Channel2_BASE   (DFSDM1_BASE + 0x40UL)

Definition at line 2315 of file stm32h747xx.h.

◆ DFSDM1_Channel2_BASE [3/3]

#define DFSDM1_Channel2_BASE   (DFSDM1_BASE + 0x40UL)

Definition at line 2368 of file stm32h735xx.h.

◆ DFSDM1_Channel3_BASE [1/3]

#define DFSDM1_Channel3_BASE   (DFSDM1_BASE + 0x60UL)

Definition at line 1464 of file stm32f769xx.h.

◆ DFSDM1_Channel3_BASE [2/3]

#define DFSDM1_Channel3_BASE   (DFSDM1_BASE + 0x60UL)

Definition at line 2316 of file stm32h747xx.h.

◆ DFSDM1_Channel3_BASE [3/3]

#define DFSDM1_Channel3_BASE   (DFSDM1_BASE + 0x60UL)

Definition at line 2369 of file stm32h735xx.h.

◆ DFSDM1_Channel4_BASE [1/3]

#define DFSDM1_Channel4_BASE   (DFSDM1_BASE + 0x80UL)

Definition at line 1465 of file stm32f769xx.h.

◆ DFSDM1_Channel4_BASE [2/3]

#define DFSDM1_Channel4_BASE   (DFSDM1_BASE + 0x80UL)

Definition at line 2317 of file stm32h747xx.h.

◆ DFSDM1_Channel4_BASE [3/3]

#define DFSDM1_Channel4_BASE   (DFSDM1_BASE + 0x80UL)

Definition at line 2370 of file stm32h735xx.h.

◆ DFSDM1_Channel5_BASE [1/3]

#define DFSDM1_Channel5_BASE   (DFSDM1_BASE + 0xA0UL)

Definition at line 1466 of file stm32f769xx.h.

◆ DFSDM1_Channel5_BASE [2/3]

#define DFSDM1_Channel5_BASE   (DFSDM1_BASE + 0xA0UL)

Definition at line 2318 of file stm32h747xx.h.

◆ DFSDM1_Channel5_BASE [3/3]

#define DFSDM1_Channel5_BASE   (DFSDM1_BASE + 0xA0UL)

Definition at line 2371 of file stm32h735xx.h.

◆ DFSDM1_Channel6_BASE [1/3]

#define DFSDM1_Channel6_BASE   (DFSDM1_BASE + 0xC0UL)

Definition at line 1467 of file stm32f769xx.h.

◆ DFSDM1_Channel6_BASE [2/3]

#define DFSDM1_Channel6_BASE   (DFSDM1_BASE + 0xC0UL)

Definition at line 2319 of file stm32h747xx.h.

◆ DFSDM1_Channel6_BASE [3/3]

#define DFSDM1_Channel6_BASE   (DFSDM1_BASE + 0xC0UL)

Definition at line 2372 of file stm32h735xx.h.

◆ DFSDM1_Channel7_BASE [1/3]

#define DFSDM1_Channel7_BASE   (DFSDM1_BASE + 0xE0UL)

Definition at line 1468 of file stm32f769xx.h.

◆ DFSDM1_Channel7_BASE [2/3]

#define DFSDM1_Channel7_BASE   (DFSDM1_BASE + 0xE0UL)

Definition at line 2320 of file stm32h747xx.h.

◆ DFSDM1_Channel7_BASE [3/3]

#define DFSDM1_Channel7_BASE   (DFSDM1_BASE + 0xE0UL)

Definition at line 2373 of file stm32h735xx.h.

◆ DFSDM1_Filter0_BASE [1/3]

#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)

Definition at line 1469 of file stm32f769xx.h.

◆ DFSDM1_Filter0_BASE [2/3]

#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)

Definition at line 2321 of file stm32h747xx.h.

◆ DFSDM1_Filter0_BASE [3/3]

#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)

Definition at line 2374 of file stm32h735xx.h.

◆ DFSDM1_Filter1_BASE [1/3]

#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)

Definition at line 1470 of file stm32f769xx.h.

◆ DFSDM1_Filter1_BASE [2/3]

#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)

Definition at line 2322 of file stm32h747xx.h.

◆ DFSDM1_Filter1_BASE [3/3]

#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)

Definition at line 2375 of file stm32h735xx.h.

◆ DFSDM1_Filter2_BASE [1/3]

#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)

Definition at line 1471 of file stm32f769xx.h.

◆ DFSDM1_Filter2_BASE [2/3]

#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)

Definition at line 2323 of file stm32h747xx.h.

◆ DFSDM1_Filter2_BASE [3/3]

#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)

Definition at line 2376 of file stm32h735xx.h.

◆ DFSDM1_Filter3_BASE [1/3]

#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)

Definition at line 1472 of file stm32f769xx.h.

◆ DFSDM1_Filter3_BASE [2/3]

#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)

Definition at line 2324 of file stm32h747xx.h.

◆ DFSDM1_Filter3_BASE [3/3]

#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)

D3_APB1PERIPH peripherals

Definition at line 2377 of file stm32h735xx.h.

◆ DLYB_OCTOSPI1_BASE

#define DLYB_OCTOSPI1_BASE   (D1_AHB1PERIPH_BASE + 0x6000UL)

Definition at line 2220 of file stm32h735xx.h.

◆ DLYB_OCTOSPI2_BASE

#define DLYB_OCTOSPI2_BASE   (D1_AHB1PERIPH_BASE + 0xB000UL)

Definition at line 2225 of file stm32h735xx.h.

◆ DLYB_QSPI_BASE

#define DLYB_QSPI_BASE   (D1_AHB1PERIPH_BASE + 0x6000UL)

Definition at line 2180 of file stm32h747xx.h.

◆ DLYB_SDMMC1_BASE [1/2]

#define DLYB_SDMMC1_BASE   (D1_AHB1PERIPH_BASE + 0x8000UL)

Definition at line 2182 of file stm32h747xx.h.

◆ DLYB_SDMMC1_BASE [2/2]

#define DLYB_SDMMC1_BASE   (D1_AHB1PERIPH_BASE + 0x8000UL)

Definition at line 2222 of file stm32h735xx.h.

◆ DLYB_SDMMC2_BASE [1/2]

#define DLYB_SDMMC2_BASE   (D2_AHB2PERIPH_BASE + 0x2800UL)

Definition at line 2218 of file stm32h747xx.h.

◆ DLYB_SDMMC2_BASE [2/2]

#define DLYB_SDMMC2_BASE   (D2_AHB2PERIPH_BASE + 0x2800UL)

Definition at line 2274 of file stm32h735xx.h.

◆ DMA1_BASE [1/6]

#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000UL)

Definition at line 703 of file stm32f411xe.h.

◆ DMA1_BASE [2/6]

#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000UL)

Definition at line 994 of file stm32f407xx.h.

◆ DMA1_BASE [3/6]

#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000UL)

Definition at line 1218 of file stm32f469xx.h.

◆ DMA1_BASE [4/6]

#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000UL)

Definition at line 1495 of file stm32f769xx.h.

◆ DMA1_BASE [5/6]

#define DMA1_BASE   (D2_AHB1PERIPH_BASE + 0x0000UL)

Definition at line 2187 of file stm32h747xx.h.

◆ DMA1_BASE [6/6]

#define DMA1_BASE   (D2_AHB1PERIPH_BASE + 0x0000UL)

Definition at line 2241 of file stm32h735xx.h.

◆ DMA1_Stream0_BASE [1/6]

#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010UL)

Definition at line 704 of file stm32f411xe.h.

◆ DMA1_Stream0_BASE [2/6]

#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010UL)

Definition at line 995 of file stm32f407xx.h.

◆ DMA1_Stream0_BASE [3/6]

#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010UL)

Definition at line 1219 of file stm32f469xx.h.

◆ DMA1_Stream0_BASE [4/6]

#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010UL)

Definition at line 1496 of file stm32f769xx.h.

◆ DMA1_Stream0_BASE [5/6]

#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010UL)

Definition at line 2392 of file stm32h747xx.h.

◆ DMA1_Stream0_BASE [6/6]

#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010UL)

Definition at line 2438 of file stm32h735xx.h.

◆ DMA1_Stream1_BASE [1/6]

#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028UL)

Definition at line 705 of file stm32f411xe.h.

◆ DMA1_Stream1_BASE [2/6]

#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028UL)

Definition at line 996 of file stm32f407xx.h.

◆ DMA1_Stream1_BASE [3/6]

#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028UL)

Definition at line 1220 of file stm32f469xx.h.

◆ DMA1_Stream1_BASE [4/6]

#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028UL)

Definition at line 1497 of file stm32f769xx.h.

◆ DMA1_Stream1_BASE [5/6]

#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028UL)

Definition at line 2393 of file stm32h747xx.h.

◆ DMA1_Stream1_BASE [6/6]

#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028UL)

Definition at line 2439 of file stm32h735xx.h.

◆ DMA1_Stream2_BASE [1/6]

#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040UL)

Definition at line 706 of file stm32f411xe.h.

◆ DMA1_Stream2_BASE [2/6]

#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040UL)

Definition at line 997 of file stm32f407xx.h.

◆ DMA1_Stream2_BASE [3/6]

#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040UL)

Definition at line 1221 of file stm32f469xx.h.

◆ DMA1_Stream2_BASE [4/6]

#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040UL)

Definition at line 1498 of file stm32f769xx.h.

◆ DMA1_Stream2_BASE [5/6]

#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040UL)

Definition at line 2394 of file stm32h747xx.h.

◆ DMA1_Stream2_BASE [6/6]

#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040UL)

Definition at line 2440 of file stm32h735xx.h.

◆ DMA1_Stream3_BASE [1/6]

#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058UL)

Definition at line 707 of file stm32f411xe.h.

◆ DMA1_Stream3_BASE [2/6]

#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058UL)

Definition at line 998 of file stm32f407xx.h.

◆ DMA1_Stream3_BASE [3/6]

#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058UL)

Definition at line 1222 of file stm32f469xx.h.

◆ DMA1_Stream3_BASE [4/6]

#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058UL)

Definition at line 1499 of file stm32f769xx.h.

◆ DMA1_Stream3_BASE [5/6]

#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058UL)

Definition at line 2395 of file stm32h747xx.h.

◆ DMA1_Stream3_BASE [6/6]

#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058UL)

Definition at line 2441 of file stm32h735xx.h.

◆ DMA1_Stream4_BASE [1/6]

#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070UL)

Definition at line 708 of file stm32f411xe.h.

◆ DMA1_Stream4_BASE [2/6]

#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070UL)

Definition at line 999 of file stm32f407xx.h.

◆ DMA1_Stream4_BASE [3/6]

#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070UL)

Definition at line 1223 of file stm32f469xx.h.

◆ DMA1_Stream4_BASE [4/6]

#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070UL)

Definition at line 1500 of file stm32f769xx.h.

◆ DMA1_Stream4_BASE [5/6]

#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070UL)

Definition at line 2396 of file stm32h747xx.h.

◆ DMA1_Stream4_BASE [6/6]

#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070UL)

Definition at line 2442 of file stm32h735xx.h.

◆ DMA1_Stream5_BASE [1/6]

#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088UL)

Definition at line 709 of file stm32f411xe.h.

◆ DMA1_Stream5_BASE [2/6]

#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088UL)

Definition at line 1000 of file stm32f407xx.h.

◆ DMA1_Stream5_BASE [3/6]

#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088UL)

Definition at line 1224 of file stm32f469xx.h.

◆ DMA1_Stream5_BASE [4/6]

#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088UL)

Definition at line 1501 of file stm32f769xx.h.

◆ DMA1_Stream5_BASE [5/6]

#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088UL)

Definition at line 2397 of file stm32h747xx.h.

◆ DMA1_Stream5_BASE [6/6]

#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088UL)

Definition at line 2443 of file stm32h735xx.h.

◆ DMA1_Stream6_BASE [1/6]

#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0UL)

Definition at line 710 of file stm32f411xe.h.

◆ DMA1_Stream6_BASE [2/6]

#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0UL)

Definition at line 1001 of file stm32f407xx.h.

◆ DMA1_Stream6_BASE [3/6]

#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0UL)

Definition at line 1225 of file stm32f469xx.h.

◆ DMA1_Stream6_BASE [4/6]

#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0UL)

Definition at line 1502 of file stm32f769xx.h.

◆ DMA1_Stream6_BASE [5/6]

#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0UL)

Definition at line 2398 of file stm32h747xx.h.

◆ DMA1_Stream6_BASE [6/6]

#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0UL)

Definition at line 2444 of file stm32h735xx.h.

◆ DMA1_Stream7_BASE [1/6]

#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8UL)

Definition at line 711 of file stm32f411xe.h.

◆ DMA1_Stream7_BASE [2/6]

#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8UL)

Definition at line 1002 of file stm32f407xx.h.

◆ DMA1_Stream7_BASE [3/6]

#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8UL)

Definition at line 1226 of file stm32f469xx.h.

◆ DMA1_Stream7_BASE [4/6]

#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8UL)

Definition at line 1503 of file stm32f769xx.h.

◆ DMA1_Stream7_BASE [5/6]

#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8UL)

Definition at line 2399 of file stm32h747xx.h.

◆ DMA1_Stream7_BASE [6/6]

#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8UL)

Definition at line 2445 of file stm32h735xx.h.

◆ DMA2_BASE [1/6]

#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400UL)

Definition at line 712 of file stm32f411xe.h.

◆ DMA2_BASE [2/6]

#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400UL)

Definition at line 1003 of file stm32f407xx.h.

◆ DMA2_BASE [3/6]

#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400UL)

Definition at line 1227 of file stm32f469xx.h.

◆ DMA2_BASE [4/6]

#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400UL)

Definition at line 1504 of file stm32f769xx.h.

◆ DMA2_BASE [5/6]

#define DMA2_BASE   (D2_AHB1PERIPH_BASE + 0x0400UL)

Definition at line 2188 of file stm32h747xx.h.

◆ DMA2_BASE [6/6]

#define DMA2_BASE   (D2_AHB1PERIPH_BASE + 0x0400UL)

Definition at line 2242 of file stm32h735xx.h.

◆ DMA2_Stream0_BASE [1/6]

#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010UL)

Definition at line 713 of file stm32f411xe.h.

◆ DMA2_Stream0_BASE [2/6]

#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010UL)

Definition at line 1004 of file stm32f407xx.h.

◆ DMA2_Stream0_BASE [3/6]

#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010UL)

Definition at line 1228 of file stm32f469xx.h.

◆ DMA2_Stream0_BASE [4/6]

#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010UL)

Definition at line 1505 of file stm32f769xx.h.

◆ DMA2_Stream0_BASE [5/6]

#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010UL)

Definition at line 2401 of file stm32h747xx.h.

◆ DMA2_Stream0_BASE [6/6]

#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010UL)

Definition at line 2447 of file stm32h735xx.h.

◆ DMA2_Stream1_BASE [1/6]

#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028UL)

Definition at line 714 of file stm32f411xe.h.

◆ DMA2_Stream1_BASE [2/6]

#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028UL)

Definition at line 1005 of file stm32f407xx.h.

◆ DMA2_Stream1_BASE [3/6]

#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028UL)

Definition at line 1229 of file stm32f469xx.h.

◆ DMA2_Stream1_BASE [4/6]

#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028UL)

Definition at line 1506 of file stm32f769xx.h.

◆ DMA2_Stream1_BASE [5/6]

#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028UL)

Definition at line 2402 of file stm32h747xx.h.

◆ DMA2_Stream1_BASE [6/6]

#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028UL)

Definition at line 2448 of file stm32h735xx.h.

◆ DMA2_Stream2_BASE [1/6]

#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040UL)

Definition at line 715 of file stm32f411xe.h.

◆ DMA2_Stream2_BASE [2/6]

#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040UL)

Definition at line 1006 of file stm32f407xx.h.

◆ DMA2_Stream2_BASE [3/6]

#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040UL)

Definition at line 1230 of file stm32f469xx.h.

◆ DMA2_Stream2_BASE [4/6]

#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040UL)

Definition at line 1507 of file stm32f769xx.h.

◆ DMA2_Stream2_BASE [5/6]

#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040UL)

Definition at line 2403 of file stm32h747xx.h.

◆ DMA2_Stream2_BASE [6/6]

#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040UL)

Definition at line 2449 of file stm32h735xx.h.

◆ DMA2_Stream3_BASE [1/6]

#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058UL)

Definition at line 716 of file stm32f411xe.h.

◆ DMA2_Stream3_BASE [2/6]

#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058UL)

Definition at line 1007 of file stm32f407xx.h.

◆ DMA2_Stream3_BASE [3/6]

#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058UL)

Definition at line 1231 of file stm32f469xx.h.

◆ DMA2_Stream3_BASE [4/6]

#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058UL)

Definition at line 1508 of file stm32f769xx.h.

◆ DMA2_Stream3_BASE [5/6]

#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058UL)

Definition at line 2404 of file stm32h747xx.h.

◆ DMA2_Stream3_BASE [6/6]

#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058UL)

Definition at line 2450 of file stm32h735xx.h.

◆ DMA2_Stream4_BASE [1/6]

#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070UL)

Definition at line 717 of file stm32f411xe.h.

◆ DMA2_Stream4_BASE [2/6]

#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070UL)

Definition at line 1008 of file stm32f407xx.h.

◆ DMA2_Stream4_BASE [3/6]

#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070UL)

Definition at line 1232 of file stm32f469xx.h.

◆ DMA2_Stream4_BASE [4/6]

#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070UL)

Definition at line 1509 of file stm32f769xx.h.

◆ DMA2_Stream4_BASE [5/6]

#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070UL)

Definition at line 2405 of file stm32h747xx.h.

◆ DMA2_Stream4_BASE [6/6]

#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070UL)

Definition at line 2451 of file stm32h735xx.h.

◆ DMA2_Stream5_BASE [1/6]

#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088UL)

Definition at line 718 of file stm32f411xe.h.

◆ DMA2_Stream5_BASE [2/6]

#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088UL)

Definition at line 1009 of file stm32f407xx.h.

◆ DMA2_Stream5_BASE [3/6]

#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088UL)

Definition at line 1233 of file stm32f469xx.h.

◆ DMA2_Stream5_BASE [4/6]

#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088UL)

Definition at line 1510 of file stm32f769xx.h.

◆ DMA2_Stream5_BASE [5/6]

#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088UL)

Definition at line 2406 of file stm32h747xx.h.

◆ DMA2_Stream5_BASE [6/6]

#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088UL)

Definition at line 2452 of file stm32h735xx.h.

◆ DMA2_Stream6_BASE [1/6]

#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0UL)

Definition at line 719 of file stm32f411xe.h.

◆ DMA2_Stream6_BASE [2/6]

#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0UL)

Definition at line 1010 of file stm32f407xx.h.

◆ DMA2_Stream6_BASE [3/6]

#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0UL)

Definition at line 1234 of file stm32f469xx.h.

◆ DMA2_Stream6_BASE [4/6]

#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0UL)

Definition at line 1511 of file stm32f769xx.h.

◆ DMA2_Stream6_BASE [5/6]

#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0UL)

Definition at line 2407 of file stm32h747xx.h.

◆ DMA2_Stream6_BASE [6/6]

#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0UL)

Definition at line 2453 of file stm32h735xx.h.

◆ DMA2_Stream7_BASE [1/6]

#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8UL)

Debug MCU registers base address

Definition at line 720 of file stm32f411xe.h.

◆ DMA2_Stream7_BASE [2/6]

#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8UL)

Definition at line 1011 of file stm32f407xx.h.

◆ DMA2_Stream7_BASE [3/6]

#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8UL)

Definition at line 1235 of file stm32f469xx.h.

◆ DMA2_Stream7_BASE [4/6]

#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8UL)

Definition at line 1512 of file stm32f769xx.h.

◆ DMA2_Stream7_BASE [5/6]

#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8UL)

Definition at line 2408 of file stm32h747xx.h.

◆ DMA2_Stream7_BASE [6/6]

#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8UL)

Definition at line 2454 of file stm32h735xx.h.

◆ DMA2D_BASE [1/4]

#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000UL)

AHB2 peripherals

Definition at line 1241 of file stm32f469xx.h.

◆ DMA2D_BASE [2/4]

#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000UL)

AHB2 peripherals

Definition at line 1518 of file stm32f769xx.h.

◆ DMA2D_BASE [3/4]

#define DMA2D_BASE   (D1_AHB1PERIPH_BASE + 0x1000UL)

Definition at line 2175 of file stm32h747xx.h.

◆ DMA2D_BASE [4/4]

#define DMA2D_BASE   (D1_AHB1PERIPH_BASE + 0x1000UL)

Definition at line 2216 of file stm32h735xx.h.

◆ DMAMUX1_BASE [1/2]

#define DMAMUX1_BASE   (D2_AHB1PERIPH_BASE + 0x0800UL)

Definition at line 2189 of file stm32h747xx.h.

◆ DMAMUX1_BASE [2/2]

#define DMAMUX1_BASE   (D2_AHB1PERIPH_BASE + 0x0800UL)

Definition at line 2243 of file stm32h735xx.h.

◆ DMAMUX1_Channel0_BASE [1/2]

#define DMAMUX1_Channel0_BASE   (DMAMUX1_BASE)

Definition at line 2410 of file stm32h747xx.h.

◆ DMAMUX1_Channel0_BASE [2/2]

#define DMAMUX1_Channel0_BASE   (DMAMUX1_BASE)

Definition at line 2456 of file stm32h735xx.h.

◆ DMAMUX1_Channel10_BASE [1/2]

#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)

Definition at line 2420 of file stm32h747xx.h.

◆ DMAMUX1_Channel10_BASE [2/2]

#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)

Definition at line 2466 of file stm32h735xx.h.

◆ DMAMUX1_Channel11_BASE [1/2]

#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)

Definition at line 2421 of file stm32h747xx.h.

◆ DMAMUX1_Channel11_BASE [2/2]

#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)

Definition at line 2467 of file stm32h735xx.h.

◆ DMAMUX1_Channel12_BASE [1/2]

#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)

Definition at line 2422 of file stm32h747xx.h.

◆ DMAMUX1_Channel12_BASE [2/2]

#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)

Definition at line 2468 of file stm32h735xx.h.

◆ DMAMUX1_Channel13_BASE [1/2]

#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)

Definition at line 2423 of file stm32h747xx.h.

◆ DMAMUX1_Channel13_BASE [2/2]

#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)

Definition at line 2469 of file stm32h735xx.h.

◆ DMAMUX1_Channel14_BASE [1/2]

#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)

Definition at line 2424 of file stm32h747xx.h.

◆ DMAMUX1_Channel14_BASE [2/2]

#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)

Definition at line 2470 of file stm32h735xx.h.

◆ DMAMUX1_Channel15_BASE [1/2]

#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)

Definition at line 2425 of file stm32h747xx.h.

◆ DMAMUX1_Channel15_BASE [2/2]

#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)

Definition at line 2471 of file stm32h735xx.h.

◆ DMAMUX1_Channel1_BASE [1/2]

#define DMAMUX1_Channel1_BASE   (DMAMUX1_BASE + 0x0004UL)

Definition at line 2411 of file stm32h747xx.h.

◆ DMAMUX1_Channel1_BASE [2/2]

#define DMAMUX1_Channel1_BASE   (DMAMUX1_BASE + 0x0004UL)

Definition at line 2457 of file stm32h735xx.h.

◆ DMAMUX1_Channel2_BASE [1/2]

#define DMAMUX1_Channel2_BASE   (DMAMUX1_BASE + 0x0008UL)

Definition at line 2412 of file stm32h747xx.h.

◆ DMAMUX1_Channel2_BASE [2/2]

#define DMAMUX1_Channel2_BASE   (DMAMUX1_BASE + 0x0008UL)

Definition at line 2458 of file stm32h735xx.h.

◆ DMAMUX1_Channel3_BASE [1/2]

#define DMAMUX1_Channel3_BASE   (DMAMUX1_BASE + 0x000CUL)

Definition at line 2413 of file stm32h747xx.h.

◆ DMAMUX1_Channel3_BASE [2/2]

#define DMAMUX1_Channel3_BASE   (DMAMUX1_BASE + 0x000CUL)

Definition at line 2459 of file stm32h735xx.h.

◆ DMAMUX1_Channel4_BASE [1/2]

#define DMAMUX1_Channel4_BASE   (DMAMUX1_BASE + 0x0010UL)

Definition at line 2414 of file stm32h747xx.h.

◆ DMAMUX1_Channel4_BASE [2/2]

#define DMAMUX1_Channel4_BASE   (DMAMUX1_BASE + 0x0010UL)

Definition at line 2460 of file stm32h735xx.h.

◆ DMAMUX1_Channel5_BASE [1/2]

#define DMAMUX1_Channel5_BASE   (DMAMUX1_BASE + 0x0014UL)

Definition at line 2415 of file stm32h747xx.h.

◆ DMAMUX1_Channel5_BASE [2/2]

#define DMAMUX1_Channel5_BASE   (DMAMUX1_BASE + 0x0014UL)

Definition at line 2461 of file stm32h735xx.h.

◆ DMAMUX1_Channel6_BASE [1/2]

#define DMAMUX1_Channel6_BASE   (DMAMUX1_BASE + 0x0018UL)

Definition at line 2416 of file stm32h747xx.h.

◆ DMAMUX1_Channel6_BASE [2/2]

#define DMAMUX1_Channel6_BASE   (DMAMUX1_BASE + 0x0018UL)

Definition at line 2462 of file stm32h735xx.h.

◆ DMAMUX1_Channel7_BASE [1/2]

#define DMAMUX1_Channel7_BASE   (DMAMUX1_BASE + 0x001CUL)

Definition at line 2417 of file stm32h747xx.h.

◆ DMAMUX1_Channel7_BASE [2/2]

#define DMAMUX1_Channel7_BASE   (DMAMUX1_BASE + 0x001CUL)

Definition at line 2463 of file stm32h735xx.h.

◆ DMAMUX1_Channel8_BASE [1/2]

#define DMAMUX1_Channel8_BASE   (DMAMUX1_BASE + 0x0020UL)

Definition at line 2418 of file stm32h747xx.h.

◆ DMAMUX1_Channel8_BASE [2/2]

#define DMAMUX1_Channel8_BASE   (DMAMUX1_BASE + 0x0020UL)

Definition at line 2464 of file stm32h735xx.h.

◆ DMAMUX1_Channel9_BASE [1/2]

#define DMAMUX1_Channel9_BASE   (DMAMUX1_BASE + 0x0024UL)

Definition at line 2419 of file stm32h747xx.h.

◆ DMAMUX1_Channel9_BASE [2/2]

#define DMAMUX1_Channel9_BASE   (DMAMUX1_BASE + 0x0024UL)

Definition at line 2465 of file stm32h735xx.h.

◆ DMAMUX1_ChannelStatus_BASE [1/2]

#define DMAMUX1_ChannelStatus_BASE   (DMAMUX1_BASE + 0x0080UL)

Definition at line 2436 of file stm32h747xx.h.

◆ DMAMUX1_ChannelStatus_BASE [2/2]

#define DMAMUX1_ChannelStatus_BASE   (DMAMUX1_BASE + 0x0080UL)

Definition at line 2482 of file stm32h735xx.h.

◆ DMAMUX1_RequestGenerator0_BASE [1/2]

#define DMAMUX1_RequestGenerator0_BASE   (DMAMUX1_BASE + 0x0100UL)

Definition at line 2427 of file stm32h747xx.h.

◆ DMAMUX1_RequestGenerator0_BASE [2/2]

#define DMAMUX1_RequestGenerator0_BASE   (DMAMUX1_BASE + 0x0100UL)

Definition at line 2473 of file stm32h735xx.h.

◆ DMAMUX1_RequestGenerator1_BASE [1/2]

#define DMAMUX1_RequestGenerator1_BASE   (DMAMUX1_BASE + 0x0104UL)

Definition at line 2428 of file stm32h747xx.h.

◆ DMAMUX1_RequestGenerator1_BASE [2/2]

#define DMAMUX1_RequestGenerator1_BASE   (DMAMUX1_BASE + 0x0104UL)

Definition at line 2474 of file stm32h735xx.h.

◆ DMAMUX1_RequestGenerator2_BASE [1/2]

#define DMAMUX1_RequestGenerator2_BASE   (DMAMUX1_BASE + 0x0108UL)

Definition at line 2429 of file stm32h747xx.h.

◆ DMAMUX1_RequestGenerator2_BASE [2/2]

#define DMAMUX1_RequestGenerator2_BASE   (DMAMUX1_BASE + 0x0108UL)

Definition at line 2475 of file stm32h735xx.h.

◆ DMAMUX1_RequestGenerator3_BASE [1/2]

#define DMAMUX1_RequestGenerator3_BASE   (DMAMUX1_BASE + 0x010CUL)

Definition at line 2430 of file stm32h747xx.h.

◆ DMAMUX1_RequestGenerator3_BASE [2/2]

#define DMAMUX1_RequestGenerator3_BASE   (DMAMUX1_BASE + 0x010CUL)

Definition at line 2476 of file stm32h735xx.h.

◆ DMAMUX1_RequestGenerator4_BASE [1/2]

#define DMAMUX1_RequestGenerator4_BASE   (DMAMUX1_BASE + 0x0110UL)

Definition at line 2431 of file stm32h747xx.h.

◆ DMAMUX1_RequestGenerator4_BASE [2/2]

#define DMAMUX1_RequestGenerator4_BASE   (DMAMUX1_BASE + 0x0110UL)

Definition at line 2477 of file stm32h735xx.h.

◆ DMAMUX1_RequestGenerator5_BASE [1/2]

#define DMAMUX1_RequestGenerator5_BASE   (DMAMUX1_BASE + 0x0114UL)

Definition at line 2432 of file stm32h747xx.h.

◆ DMAMUX1_RequestGenerator5_BASE [2/2]

#define DMAMUX1_RequestGenerator5_BASE   (DMAMUX1_BASE + 0x0114UL)

Definition at line 2478 of file stm32h735xx.h.

◆ DMAMUX1_RequestGenerator6_BASE [1/2]

#define DMAMUX1_RequestGenerator6_BASE   (DMAMUX1_BASE + 0x0118UL)

Definition at line 2433 of file stm32h747xx.h.

◆ DMAMUX1_RequestGenerator6_BASE [2/2]

#define DMAMUX1_RequestGenerator6_BASE   (DMAMUX1_BASE + 0x0118UL)

Definition at line 2479 of file stm32h735xx.h.

◆ DMAMUX1_RequestGenerator7_BASE [1/2]

#define DMAMUX1_RequestGenerator7_BASE   (DMAMUX1_BASE + 0x011CUL)

Definition at line 2434 of file stm32h747xx.h.

◆ DMAMUX1_RequestGenerator7_BASE [2/2]

#define DMAMUX1_RequestGenerator7_BASE   (DMAMUX1_BASE + 0x011CUL)

Definition at line 2480 of file stm32h735xx.h.

◆ DMAMUX1_RequestGenStatus_BASE [1/2]

#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)

FMC Banks registers base address

Definition at line 2437 of file stm32h747xx.h.

◆ DMAMUX1_RequestGenStatus_BASE [2/2]

#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)

FMC Banks registers base address

Definition at line 2483 of file stm32h735xx.h.

◆ DMAMUX2_BASE [1/2]

#define DMAMUX2_BASE   (D3_AHB1PERIPH_BASE + 0x5800UL)

Definition at line 2239 of file stm32h747xx.h.

◆ DMAMUX2_BASE [2/2]

#define DMAMUX2_BASE   (D3_AHB1PERIPH_BASE + 0x5800UL)

Definition at line 2294 of file stm32h735xx.h.

◆ DMAMUX2_Channel0_BASE [1/2]

#define DMAMUX2_Channel0_BASE   (DMAMUX2_BASE)

Definition at line 2371 of file stm32h747xx.h.

◆ DMAMUX2_Channel0_BASE [2/2]

#define DMAMUX2_Channel0_BASE   (DMAMUX2_BASE)

Definition at line 2417 of file stm32h735xx.h.

◆ DMAMUX2_Channel1_BASE [1/2]

#define DMAMUX2_Channel1_BASE   (DMAMUX2_BASE + 0x0004UL)

Definition at line 2372 of file stm32h747xx.h.

◆ DMAMUX2_Channel1_BASE [2/2]

#define DMAMUX2_Channel1_BASE   (DMAMUX2_BASE + 0x0004UL)

Definition at line 2418 of file stm32h735xx.h.

◆ DMAMUX2_Channel2_BASE [1/2]

#define DMAMUX2_Channel2_BASE   (DMAMUX2_BASE + 0x0008UL)

Definition at line 2373 of file stm32h747xx.h.

◆ DMAMUX2_Channel2_BASE [2/2]

#define DMAMUX2_Channel2_BASE   (DMAMUX2_BASE + 0x0008UL)

Definition at line 2419 of file stm32h735xx.h.

◆ DMAMUX2_Channel3_BASE [1/2]

#define DMAMUX2_Channel3_BASE   (DMAMUX2_BASE + 0x000CUL)

Definition at line 2374 of file stm32h747xx.h.

◆ DMAMUX2_Channel3_BASE [2/2]

#define DMAMUX2_Channel3_BASE   (DMAMUX2_BASE + 0x000CUL)

Definition at line 2420 of file stm32h735xx.h.

◆ DMAMUX2_Channel4_BASE [1/2]

#define DMAMUX2_Channel4_BASE   (DMAMUX2_BASE + 0x0010UL)

Definition at line 2375 of file stm32h747xx.h.

◆ DMAMUX2_Channel4_BASE [2/2]

#define DMAMUX2_Channel4_BASE   (DMAMUX2_BASE + 0x0010UL)

Definition at line 2421 of file stm32h735xx.h.

◆ DMAMUX2_Channel5_BASE [1/2]

#define DMAMUX2_Channel5_BASE   (DMAMUX2_BASE + 0x0014UL)

Definition at line 2376 of file stm32h747xx.h.

◆ DMAMUX2_Channel5_BASE [2/2]

#define DMAMUX2_Channel5_BASE   (DMAMUX2_BASE + 0x0014UL)

Definition at line 2422 of file stm32h735xx.h.

◆ DMAMUX2_Channel6_BASE [1/2]

#define DMAMUX2_Channel6_BASE   (DMAMUX2_BASE + 0x0018UL)

Definition at line 2377 of file stm32h747xx.h.

◆ DMAMUX2_Channel6_BASE [2/2]

#define DMAMUX2_Channel6_BASE   (DMAMUX2_BASE + 0x0018UL)

Definition at line 2423 of file stm32h735xx.h.

◆ DMAMUX2_Channel7_BASE [1/2]

#define DMAMUX2_Channel7_BASE   (DMAMUX2_BASE + 0x001CUL)

Definition at line 2378 of file stm32h747xx.h.

◆ DMAMUX2_Channel7_BASE [2/2]

#define DMAMUX2_Channel7_BASE   (DMAMUX2_BASE + 0x001CUL)

Definition at line 2424 of file stm32h735xx.h.

◆ DMAMUX2_ChannelStatus_BASE [1/2]

#define DMAMUX2_ChannelStatus_BASE   (DMAMUX2_BASE + 0x0080UL)

Definition at line 2389 of file stm32h747xx.h.

◆ DMAMUX2_ChannelStatus_BASE [2/2]

#define DMAMUX2_ChannelStatus_BASE   (DMAMUX2_BASE + 0x0080UL)

Definition at line 2435 of file stm32h735xx.h.

◆ DMAMUX2_RequestGenerator0_BASE [1/2]

#define DMAMUX2_RequestGenerator0_BASE   (DMAMUX2_BASE + 0x0100UL)

Definition at line 2380 of file stm32h747xx.h.

◆ DMAMUX2_RequestGenerator0_BASE [2/2]

#define DMAMUX2_RequestGenerator0_BASE   (DMAMUX2_BASE + 0x0100UL)

Definition at line 2426 of file stm32h735xx.h.

◆ DMAMUX2_RequestGenerator1_BASE [1/2]

#define DMAMUX2_RequestGenerator1_BASE   (DMAMUX2_BASE + 0x0104UL)

Definition at line 2381 of file stm32h747xx.h.

◆ DMAMUX2_RequestGenerator1_BASE [2/2]

#define DMAMUX2_RequestGenerator1_BASE   (DMAMUX2_BASE + 0x0104UL)

Definition at line 2427 of file stm32h735xx.h.

◆ DMAMUX2_RequestGenerator2_BASE [1/2]

#define DMAMUX2_RequestGenerator2_BASE   (DMAMUX2_BASE + 0x0108UL)

Definition at line 2382 of file stm32h747xx.h.

◆ DMAMUX2_RequestGenerator2_BASE [2/2]

#define DMAMUX2_RequestGenerator2_BASE   (DMAMUX2_BASE + 0x0108UL)

Definition at line 2428 of file stm32h735xx.h.

◆ DMAMUX2_RequestGenerator3_BASE [1/2]

#define DMAMUX2_RequestGenerator3_BASE   (DMAMUX2_BASE + 0x010CUL)

Definition at line 2383 of file stm32h747xx.h.

◆ DMAMUX2_RequestGenerator3_BASE [2/2]

#define DMAMUX2_RequestGenerator3_BASE   (DMAMUX2_BASE + 0x010CUL)

Definition at line 2429 of file stm32h735xx.h.

◆ DMAMUX2_RequestGenerator4_BASE [1/2]

#define DMAMUX2_RequestGenerator4_BASE   (DMAMUX2_BASE + 0x0110UL)

Definition at line 2384 of file stm32h747xx.h.

◆ DMAMUX2_RequestGenerator4_BASE [2/2]

#define DMAMUX2_RequestGenerator4_BASE   (DMAMUX2_BASE + 0x0110UL)

Definition at line 2430 of file stm32h735xx.h.

◆ DMAMUX2_RequestGenerator5_BASE [1/2]

#define DMAMUX2_RequestGenerator5_BASE   (DMAMUX2_BASE + 0x0114UL)

Definition at line 2385 of file stm32h747xx.h.

◆ DMAMUX2_RequestGenerator5_BASE [2/2]

#define DMAMUX2_RequestGenerator5_BASE   (DMAMUX2_BASE + 0x0114UL)

Definition at line 2431 of file stm32h735xx.h.

◆ DMAMUX2_RequestGenerator6_BASE [1/2]

#define DMAMUX2_RequestGenerator6_BASE   (DMAMUX2_BASE + 0x0118UL)

Definition at line 2386 of file stm32h747xx.h.

◆ DMAMUX2_RequestGenerator6_BASE [2/2]

#define DMAMUX2_RequestGenerator6_BASE   (DMAMUX2_BASE + 0x0118UL)

Definition at line 2432 of file stm32h735xx.h.

◆ DMAMUX2_RequestGenerator7_BASE [1/2]

#define DMAMUX2_RequestGenerator7_BASE   (DMAMUX2_BASE + 0x011CUL)

Definition at line 2387 of file stm32h747xx.h.

◆ DMAMUX2_RequestGenerator7_BASE [2/2]

#define DMAMUX2_RequestGenerator7_BASE   (DMAMUX2_BASE + 0x011CUL)

Definition at line 2433 of file stm32h735xx.h.

◆ DMAMUX2_RequestGenStatus_BASE [1/2]

#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)

Definition at line 2390 of file stm32h747xx.h.

◆ DMAMUX2_RequestGenStatus_BASE [2/2]

#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)

Definition at line 2436 of file stm32h735xx.h.

◆ DSI_BASE [1/3]

#define DSI_BASE   (APB2PERIPH_BASE + 0x6C00UL)

AHB1 peripherals

Definition at line 1201 of file stm32f469xx.h.

◆ DSI_BASE [2/3]

#define DSI_BASE   (APB2PERIPH_BASE + 0x6C00UL)

Definition at line 1459 of file stm32f769xx.h.

◆ DSI_BASE [3/3]

#define DSI_BASE   (D1_APB1PERIPH_BASE)

Definition at line 2249 of file stm32h747xx.h.

◆ DTS_BASE

#define DTS_BASE   (D3_APB1PERIPH_BASE + 0x6800UL)

Definition at line 2404 of file stm32h735xx.h.

◆ ETH_BASE [1/5]

#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000UL)

Definition at line 1012 of file stm32f407xx.h.

◆ ETH_BASE [2/5]

#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000UL)

Definition at line 1236 of file stm32f469xx.h.

◆ ETH_BASE [3/5]

#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000UL)

Definition at line 1513 of file stm32f769xx.h.

◆ ETH_BASE [4/5]

#define ETH_BASE   (D2_AHB1PERIPH_BASE + 0x8000UL)

Definition at line 2194 of file stm32h747xx.h.

◆ ETH_BASE [5/5]

#define ETH_BASE   (D2_AHB1PERIPH_BASE + 0x8000UL)

Definition at line 2247 of file stm32h735xx.h.

◆ ETH_DMA_BASE [1/3]

#define ETH_DMA_BASE   (ETH_BASE + 0x1000UL)

AHB2 peripherals

Definition at line 1016 of file stm32f407xx.h.

◆ ETH_DMA_BASE [2/3]

#define ETH_DMA_BASE   (ETH_BASE + 0x1000UL)

Definition at line 1240 of file stm32f469xx.h.

◆ ETH_DMA_BASE [3/3]

#define ETH_DMA_BASE   (ETH_BASE + 0x1000UL)

Definition at line 1517 of file stm32f769xx.h.

◆ ETH_MAC_BASE [1/5]

#define ETH_MAC_BASE   (ETH_BASE)

Definition at line 1013 of file stm32f407xx.h.

◆ ETH_MAC_BASE [2/5]

#define ETH_MAC_BASE   (ETH_BASE)

Definition at line 1237 of file stm32f469xx.h.

◆ ETH_MAC_BASE [3/5]

#define ETH_MAC_BASE   (ETH_BASE)

Definition at line 1514 of file stm32f769xx.h.

◆ ETH_MAC_BASE [4/5]

#define ETH_MAC_BASE   (ETH_BASE)

USB registers base address

Definition at line 2195 of file stm32h747xx.h.

◆ ETH_MAC_BASE [5/5]

#define ETH_MAC_BASE   (ETH_BASE)

USB registers base address

Definition at line 2248 of file stm32h735xx.h.

◆ ETH_MMC_BASE [1/3]

#define ETH_MMC_BASE   (ETH_BASE + 0x0100UL)

Definition at line 1014 of file stm32f407xx.h.

◆ ETH_MMC_BASE [2/3]

#define ETH_MMC_BASE   (ETH_BASE + 0x0100UL)

Definition at line 1238 of file stm32f469xx.h.

◆ ETH_MMC_BASE [3/3]

#define ETH_MMC_BASE   (ETH_BASE + 0x0100UL)

Definition at line 1515 of file stm32f769xx.h.

◆ ETH_PTP_BASE [1/3]

#define ETH_PTP_BASE   (ETH_BASE + 0x0700UL)

Definition at line 1015 of file stm32f407xx.h.

◆ ETH_PTP_BASE [2/3]

#define ETH_PTP_BASE   (ETH_BASE + 0x0700UL)

Definition at line 1239 of file stm32f469xx.h.

◆ ETH_PTP_BASE [3/3]

#define ETH_PTP_BASE   (ETH_BASE + 0x0700UL)

Definition at line 1516 of file stm32f769xx.h.

◆ EXTI_BASE [1/6]

#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00UL)

Definition at line 687 of file stm32f411xe.h.

◆ EXTI_BASE [2/6]

#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00UL)

Definition at line 976 of file stm32f407xx.h.

◆ EXTI_BASE [3/6]

#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00UL)

Definition at line 1189 of file stm32f469xx.h.

◆ EXTI_BASE [4/6]

#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00UL)

Definition at line 1444 of file stm32f769xx.h.

◆ EXTI_BASE [5/6]

#define EXTI_BASE   (D3_APB1PERIPH_BASE + 0x0000UL)

Definition at line 2335 of file stm32h747xx.h.

◆ EXTI_BASE [6/6]

#define EXTI_BASE   (D3_APB1PERIPH_BASE + 0x0000UL)

Definition at line 2381 of file stm32h735xx.h.

◆ EXTI_D1_BASE [1/2]

#define EXTI_D1_BASE   (EXTI_BASE + 0x0080UL)

Definition at line 2336 of file stm32h747xx.h.

◆ EXTI_D1_BASE [2/2]

#define EXTI_D1_BASE   (EXTI_BASE + 0x0080UL)

Definition at line 2382 of file stm32h735xx.h.

◆ EXTI_D2_BASE [1/2]

#define EXTI_D2_BASE   (EXTI_BASE + 0x00C0UL)

Definition at line 2337 of file stm32h747xx.h.

◆ EXTI_D2_BASE [2/2]

#define EXTI_D2_BASE   (EXTI_BASE + 0x00C0UL)

Definition at line 2383 of file stm32h735xx.h.

◆ FDCAN1_BASE [1/2]

#define FDCAN1_BASE   (D2_APB1PERIPH_BASE + 0xA000UL)

Definition at line 2286 of file stm32h747xx.h.

◆ FDCAN1_BASE [2/2]

#define FDCAN1_BASE   (D2_APB1PERIPH_BASE + 0xA000UL)

Definition at line 2340 of file stm32h735xx.h.

◆ FDCAN2_BASE [1/2]

#define FDCAN2_BASE   (D2_APB1PERIPH_BASE + 0xA400UL)

Definition at line 2287 of file stm32h747xx.h.

◆ FDCAN2_BASE [2/2]

#define FDCAN2_BASE   (D2_APB1PERIPH_BASE + 0xA400UL)

Definition at line 2341 of file stm32h735xx.h.

◆ FDCAN3_BASE

#define FDCAN3_BASE   (D2_APB1PERIPH_BASE + 0xD400UL)

Definition at line 2344 of file stm32h735xx.h.

◆ FDCAN_CCU_BASE [1/2]

#define FDCAN_CCU_BASE   (D2_APB1PERIPH_BASE + 0xA800UL)

Definition at line 2288 of file stm32h747xx.h.

◆ FDCAN_CCU_BASE [2/2]

#define FDCAN_CCU_BASE   (D2_APB1PERIPH_BASE + 0xA800UL)

Definition at line 2342 of file stm32h735xx.h.

◆ FLASH_BANK1_BASE [1/2]

#define FLASH_BANK1_BASE   (0x08000000UL)

Base address of : (up to 1 MB) Flash Bank1 accessible over AXI

Definition at line 2141 of file stm32h747xx.h.

◆ FLASH_BANK1_BASE [2/2]

#define FLASH_BANK1_BASE   (0x08000000UL)

Base address of : (up to 1 MB) Flash Bank1 accessible over AXI

Definition at line 2182 of file stm32h735xx.h.

◆ FLASH_BANK2_BASE

#define FLASH_BANK2_BASE   (0x08100000UL)

Base address of : (up to 1 MB) Flash Bank2 accessible over AXI

Definition at line 2142 of file stm32h747xx.h.

◆ FLASH_BASE [1/6]

#define FLASH_BASE   0x08000000UL

FLASH(up to 1 MB) base address in the alias region

Definition at line 637 of file stm32f411xe.h.

◆ FLASH_BASE [2/6]

#define FLASH_BASE   0x08000000UL

FLASH(up to 1 MB) base address in the alias region

Definition at line 907 of file stm32f407xx.h.

◆ FLASH_BASE [3/6]

#define FLASH_BASE   0x08000000UL

FLASH(up to 1 MB) base address in the alias region

Definition at line 1114 of file stm32f469xx.h.

◆ FLASH_BASE [4/6]

#define FLASH_BASE   FLASHAXI_BASE

Peripheral memory map

Definition at line 1388 of file stm32f769xx.h.

◆ FLASH_BASE [5/6]

#define FLASH_BASE   FLASH_BANK1_BASE

Device electronic signature memory map

Definition at line 2146 of file stm32h747xx.h.

◆ FLASH_BASE [6/6]

#define FLASH_BASE   FLASH_BANK1_BASE

Device electronic signature memory map

Definition at line 2187 of file stm32h735xx.h.

◆ FLASH_END [1/6]

#define FLASH_END   0x0807FFFFUL

FLASH end address

Definition at line 643 of file stm32f411xe.h.

◆ FLASH_END [2/6]

#define FLASH_END   0x080FFFFFUL

FLASH end address

Definition at line 918 of file stm32f407xx.h.

◆ FLASH_END [3/6]

#define FLASH_END   0x081FFFFFUL

FLASH end address

Definition at line 1128 of file stm32f469xx.h.

◆ FLASH_END [4/6]

#define FLASH_END   0x081FFFFFUL

FLASH end address

Definition at line 1383 of file stm32f769xx.h.

◆ FLASH_END [5/6]

#define FLASH_END   (0x081FFFFFUL)

FLASH end address

Definition at line 2143 of file stm32h747xx.h.

◆ FLASH_END [6/6]

#define FLASH_END   (0x080FFFFFUL)

FLASH end address

Definition at line 2183 of file stm32h735xx.h.

◆ FLASH_OTP_BASE [1/4]

#define FLASH_OTP_BASE   0x1FFF7800UL

Base address of : (up to 528 Bytes) embedded FLASH OTP Area

Definition at line 644 of file stm32f411xe.h.

◆ FLASH_OTP_BASE [2/4]

#define FLASH_OTP_BASE   0x1FFF7800UL

Base address of : (up to 528 Bytes) embedded FLASH OTP Area

Definition at line 919 of file stm32f407xx.h.

◆ FLASH_OTP_BASE [3/4]

#define FLASH_OTP_BASE   0x1FFF7800UL

Base address of : (up to 528 Bytes) embedded FLASH OTP Area

Definition at line 1129 of file stm32f469xx.h.

◆ FLASH_OTP_BASE [4/4]

#define FLASH_OTP_BASE   0x1FF0F000UL

Base address of : (up to 1024 Bytes) embedded FLASH OTP Area

Definition at line 1384 of file stm32f769xx.h.

◆ FLASH_OTP_END [1/4]

#define FLASH_OTP_END   0x1FFF7A0FUL

End address of : (up to 528 Bytes) embedded FLASH OTP Area

Definition at line 645 of file stm32f411xe.h.

◆ FLASH_OTP_END [2/4]

#define FLASH_OTP_END   0x1FFF7A0FUL

End address of : (up to 528 Bytes) embedded FLASH OTP Area

Definition at line 920 of file stm32f407xx.h.

◆ FLASH_OTP_END [3/4]

#define FLASH_OTP_END   0x1FFF7A0FUL

End address of : (up to 528 Bytes) embedded FLASH OTP Area

Definition at line 1130 of file stm32f469xx.h.

◆ FLASH_OTP_END [4/4]

#define FLASH_OTP_END   0x1FF0F41FUL

End address of : (up to 1024 Bytes) embedded FLASH OTP Area

Definition at line 1385 of file stm32f769xx.h.

◆ FLASH_R_BASE [1/6]

#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00UL)

Definition at line 702 of file stm32f411xe.h.

◆ FLASH_R_BASE [2/6]

#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00UL)

Definition at line 993 of file stm32f407xx.h.

◆ FLASH_R_BASE [3/6]

#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00UL)

Definition at line 1217 of file stm32f469xx.h.

◆ FLASH_R_BASE [4/6]

#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00UL)

Definition at line 1488 of file stm32f769xx.h.

◆ FLASH_R_BASE [5/6]

#define FLASH_R_BASE   (D1_AHB1PERIPH_BASE + 0x2000UL)

Definition at line 2177 of file stm32h747xx.h.

◆ FLASH_R_BASE [6/6]

#define FLASH_R_BASE   (D1_AHB1PERIPH_BASE + 0x2000UL)

Definition at line 2217 of file stm32h735xx.h.

◆ FLASHAXI_BASE

#define FLASHAXI_BASE   0x08000000UL

Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI

Definition at line 1374 of file stm32f769xx.h.

◆ FLASHITCM_BASE

#define FLASHITCM_BASE   0x00200000UL

Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM

Definition at line 1373 of file stm32f769xx.h.

◆ FLASHSIZE_BASE [1/6]

#define FLASHSIZE_BASE   0x1FFF7A22UL

FLASH Size register base address

Definition at line 742 of file stm32f411xe.h.

◆ FLASHSIZE_BASE [2/6]

#define FLASHSIZE_BASE   0x1FFF7A22UL

FLASH Size register base address

Definition at line 1049 of file stm32f407xx.h.

◆ FLASHSIZE_BASE [3/6]

#define FLASHSIZE_BASE   0x1FFF7A22UL

FLASH Size register base address

Definition at line 1274 of file stm32f469xx.h.

◆ FLASHSIZE_BASE [4/6]

#define FLASHSIZE_BASE   0x1FF0F442UL

FLASH Size register base address

Definition at line 1490 of file stm32f769xx.h.

◆ FLASHSIZE_BASE [5/6]

#define FLASHSIZE_BASE   (0x1FF1E880UL)

FLASH Size register base address Peripheral memory map

Definition at line 2150 of file stm32h747xx.h.

◆ FLASHSIZE_BASE [6/6]

#define FLASHSIZE_BASE   (0x1FF1E880UL)

FLASH Size register base address Peripheral memory map

Definition at line 2191 of file stm32h735xx.h.

◆ FMAC_BASE

#define FMAC_BASE   (D2_AHB2PERIPH_BASE + 0x4000UL)

Definition at line 2276 of file stm32h735xx.h.

◆ FMC_Bank1_R_BASE [1/4]

#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000UL)

Definition at line 1248 of file stm32f469xx.h.

◆ FMC_Bank1_R_BASE [2/4]

#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000UL)

Definition at line 1524 of file stm32f769xx.h.

◆ FMC_Bank1_R_BASE [3/4]

#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000UL)

Definition at line 2440 of file stm32h747xx.h.

◆ FMC_Bank1_R_BASE [4/4]

#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000UL)

Definition at line 2486 of file stm32h735xx.h.

◆ FMC_Bank1E_R_BASE [1/4]

#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104UL)

Definition at line 1249 of file stm32f469xx.h.

◆ FMC_Bank1E_R_BASE [2/4]

#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104UL)

Definition at line 1525 of file stm32f769xx.h.

◆ FMC_Bank1E_R_BASE [3/4]

#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104UL)

Definition at line 2441 of file stm32h747xx.h.

◆ FMC_Bank1E_R_BASE [4/4]

#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104UL)

Definition at line 2487 of file stm32h735xx.h.

◆ FMC_Bank2_R_BASE [1/2]

#define FMC_Bank2_R_BASE   (FMC_R_BASE + 0x0060UL)

Definition at line 2442 of file stm32h747xx.h.

◆ FMC_Bank2_R_BASE [2/2]

#define FMC_Bank2_R_BASE   (FMC_R_BASE + 0x0060UL)

Definition at line 2488 of file stm32h735xx.h.

◆ FMC_Bank3_R_BASE [1/4]

#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080UL)

Definition at line 1250 of file stm32f469xx.h.

◆ FMC_Bank3_R_BASE [2/4]

#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080UL)

Definition at line 1526 of file stm32f769xx.h.

◆ FMC_Bank3_R_BASE [3/4]

#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080UL)

Definition at line 2443 of file stm32h747xx.h.

◆ FMC_Bank3_R_BASE [4/4]

#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080UL)

Definition at line 2489 of file stm32h735xx.h.

◆ FMC_Bank5_6_R_BASE [1/4]

#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140UL)

Debug MCU registers base address

Definition at line 1251 of file stm32f469xx.h.

◆ FMC_Bank5_6_R_BASE [2/4]

#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140UL)

Definition at line 1527 of file stm32f769xx.h.

◆ FMC_Bank5_6_R_BASE [3/4]

#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140UL)

Definition at line 2444 of file stm32h747xx.h.

◆ FMC_Bank5_6_R_BASE [4/4]

#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140UL)

Definition at line 2490 of file stm32h735xx.h.

◆ FMC_R_BASE [1/4]

#define FMC_R_BASE   0xA0000000UL

FMC registers base address

Definition at line 1121 of file stm32f469xx.h.

◆ FMC_R_BASE [2/4]

#define FMC_R_BASE   0xA0000000UL

Base address of : FMC Control registers

Definition at line 1379 of file stm32f769xx.h.

◆ FMC_R_BASE [3/4]

#define FMC_R_BASE   (D1_AHB1PERIPH_BASE + 0x4000UL)

Definition at line 2178 of file stm32h747xx.h.

◆ FMC_R_BASE [4/4]

#define FMC_R_BASE   (D1_AHB1PERIPH_BASE + 0x4000UL)

Definition at line 2218 of file stm32h735xx.h.

◆ FSMC_Bank1_R_BASE

#define FSMC_Bank1_R_BASE   (FSMC_R_BASE + 0x0000UL)

Definition at line 1023 of file stm32f407xx.h.

◆ FSMC_Bank1E_R_BASE

#define FSMC_Bank1E_R_BASE   (FSMC_R_BASE + 0x0104UL)

Definition at line 1024 of file stm32f407xx.h.

◆ FSMC_Bank2_3_R_BASE

#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060UL)

Definition at line 1025 of file stm32f407xx.h.

◆ FSMC_Bank4_R_BASE

#define FSMC_Bank4_R_BASE   (FSMC_R_BASE + 0x00A0UL)

Debug MCU registers base address

Definition at line 1026 of file stm32f407xx.h.

◆ FSMC_R_BASE

#define FSMC_R_BASE   0xA0000000UL

FSMC registers base address

Definition at line 913 of file stm32f407xx.h.

◆ GPIOA_BASE [1/6]

#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000UL)

Definition at line 694 of file stm32f411xe.h.

◆ GPIOA_BASE [2/6]

#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000UL)

Definition at line 982 of file stm32f407xx.h.

◆ GPIOA_BASE [3/6]

#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000UL)

Definition at line 1204 of file stm32f469xx.h.

◆ GPIOA_BASE [4/6]

#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000UL)

Definition at line 1475 of file stm32f769xx.h.

◆ GPIOA_BASE [5/6]

#define GPIOA_BASE   (D3_AHB1PERIPH_BASE + 0x0000UL)

Definition at line 2222 of file stm32h747xx.h.

◆ GPIOA_BASE [6/6]

#define GPIOA_BASE   (D3_AHB1PERIPH_BASE + 0x0000UL)

Definition at line 2280 of file stm32h735xx.h.

◆ GPIOB_BASE [1/6]

#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400UL)

Definition at line 695 of file stm32f411xe.h.

◆ GPIOB_BASE [2/6]

#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400UL)

Definition at line 983 of file stm32f407xx.h.

◆ GPIOB_BASE [3/6]

#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400UL)

Definition at line 1205 of file stm32f469xx.h.

◆ GPIOB_BASE [4/6]

#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400UL)

Definition at line 1476 of file stm32f769xx.h.

◆ GPIOB_BASE [5/6]

#define GPIOB_BASE   (D3_AHB1PERIPH_BASE + 0x0400UL)

Definition at line 2223 of file stm32h747xx.h.

◆ GPIOB_BASE [6/6]

#define GPIOB_BASE   (D3_AHB1PERIPH_BASE + 0x0400UL)

Definition at line 2281 of file stm32h735xx.h.

◆ GPIOC_BASE [1/6]

#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800UL)

Definition at line 696 of file stm32f411xe.h.

◆ GPIOC_BASE [2/6]

#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800UL)

Definition at line 984 of file stm32f407xx.h.

◆ GPIOC_BASE [3/6]

#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800UL)

Definition at line 1206 of file stm32f469xx.h.

◆ GPIOC_BASE [4/6]

#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800UL)

Definition at line 1477 of file stm32f769xx.h.

◆ GPIOC_BASE [5/6]

#define GPIOC_BASE   (D3_AHB1PERIPH_BASE + 0x0800UL)

Definition at line 2224 of file stm32h747xx.h.

◆ GPIOC_BASE [6/6]

#define GPIOC_BASE   (D3_AHB1PERIPH_BASE + 0x0800UL)

Definition at line 2282 of file stm32h735xx.h.

◆ GPIOD_BASE [1/6]

#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00UL)

Definition at line 697 of file stm32f411xe.h.

◆ GPIOD_BASE [2/6]

#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00UL)

Definition at line 985 of file stm32f407xx.h.

◆ GPIOD_BASE [3/6]

#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00UL)

Definition at line 1207 of file stm32f469xx.h.

◆ GPIOD_BASE [4/6]

#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00UL)

Definition at line 1478 of file stm32f769xx.h.

◆ GPIOD_BASE [5/6]

#define GPIOD_BASE   (D3_AHB1PERIPH_BASE + 0x0C00UL)

Definition at line 2225 of file stm32h747xx.h.

◆ GPIOD_BASE [6/6]

#define GPIOD_BASE   (D3_AHB1PERIPH_BASE + 0x0C00UL)

Definition at line 2283 of file stm32h735xx.h.

◆ GPIOE_BASE [1/6]

#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000UL)

Definition at line 698 of file stm32f411xe.h.

◆ GPIOE_BASE [2/6]

#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000UL)

Definition at line 986 of file stm32f407xx.h.

◆ GPIOE_BASE [3/6]

#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000UL)

Definition at line 1208 of file stm32f469xx.h.

◆ GPIOE_BASE [4/6]

#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000UL)

Definition at line 1479 of file stm32f769xx.h.

◆ GPIOE_BASE [5/6]

#define GPIOE_BASE   (D3_AHB1PERIPH_BASE + 0x1000UL)

Definition at line 2226 of file stm32h747xx.h.

◆ GPIOE_BASE [6/6]

#define GPIOE_BASE   (D3_AHB1PERIPH_BASE + 0x1000UL)

Definition at line 2284 of file stm32h735xx.h.

◆ GPIOF_BASE [1/5]

#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400UL)

Definition at line 987 of file stm32f407xx.h.

◆ GPIOF_BASE [2/5]

#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400UL)

Definition at line 1209 of file stm32f469xx.h.

◆ GPIOF_BASE [3/5]

#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400UL)

Definition at line 1480 of file stm32f769xx.h.

◆ GPIOF_BASE [4/5]

#define GPIOF_BASE   (D3_AHB1PERIPH_BASE + 0x1400UL)

Definition at line 2227 of file stm32h747xx.h.

◆ GPIOF_BASE [5/5]

#define GPIOF_BASE   (D3_AHB1PERIPH_BASE + 0x1400UL)

Definition at line 2285 of file stm32h735xx.h.

◆ GPIOG_BASE [1/5]

#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800UL)

Definition at line 988 of file stm32f407xx.h.

◆ GPIOG_BASE [2/5]

#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800UL)

Definition at line 1210 of file stm32f469xx.h.

◆ GPIOG_BASE [3/5]

#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800UL)

Definition at line 1481 of file stm32f769xx.h.

◆ GPIOG_BASE [4/5]

#define GPIOG_BASE   (D3_AHB1PERIPH_BASE + 0x1800UL)

Definition at line 2228 of file stm32h747xx.h.

◆ GPIOG_BASE [5/5]

#define GPIOG_BASE   (D3_AHB1PERIPH_BASE + 0x1800UL)

Definition at line 2286 of file stm32h735xx.h.

◆ GPIOH_BASE [1/6]

#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00UL)

Definition at line 699 of file stm32f411xe.h.

◆ GPIOH_BASE [2/6]

#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00UL)

Definition at line 989 of file stm32f407xx.h.

◆ GPIOH_BASE [3/6]

#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00UL)

Definition at line 1211 of file stm32f469xx.h.

◆ GPIOH_BASE [4/6]

#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00UL)

Definition at line 1482 of file stm32f769xx.h.

◆ GPIOH_BASE [5/6]

#define GPIOH_BASE   (D3_AHB1PERIPH_BASE + 0x1C00UL)

Definition at line 2229 of file stm32h747xx.h.

◆ GPIOH_BASE [6/6]

#define GPIOH_BASE   (D3_AHB1PERIPH_BASE + 0x1C00UL)

Definition at line 2287 of file stm32h735xx.h.

◆ GPIOI_BASE [1/4]

#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000UL)

Definition at line 990 of file stm32f407xx.h.

◆ GPIOI_BASE [2/4]

#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000UL)

Definition at line 1212 of file stm32f469xx.h.

◆ GPIOI_BASE [3/4]

#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000UL)

Definition at line 1483 of file stm32f769xx.h.

◆ GPIOI_BASE [4/4]

#define GPIOI_BASE   (D3_AHB1PERIPH_BASE + 0x2000UL)

Definition at line 2230 of file stm32h747xx.h.

◆ GPIOJ_BASE [1/4]

#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400UL)

Definition at line 1213 of file stm32f469xx.h.

◆ GPIOJ_BASE [2/4]

#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400UL)

Definition at line 1484 of file stm32f769xx.h.

◆ GPIOJ_BASE [3/4]

#define GPIOJ_BASE   (D3_AHB1PERIPH_BASE + 0x2400UL)

Definition at line 2231 of file stm32h747xx.h.

◆ GPIOJ_BASE [4/4]

#define GPIOJ_BASE   (D3_AHB1PERIPH_BASE + 0x2400UL)

Definition at line 2288 of file stm32h735xx.h.

◆ GPIOK_BASE [1/4]

#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800UL)

Definition at line 1214 of file stm32f469xx.h.

◆ GPIOK_BASE [2/4]

#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800UL)

Definition at line 1485 of file stm32f769xx.h.

◆ GPIOK_BASE [3/4]

#define GPIOK_BASE   (D3_AHB1PERIPH_BASE + 0x2800UL)

Definition at line 2232 of file stm32h747xx.h.

◆ GPIOK_BASE [4/4]

#define GPIOK_BASE   (D3_AHB1PERIPH_BASE + 0x2800UL)

Definition at line 2289 of file stm32h735xx.h.

◆ GPV_BASE

#define GPV_BASE   (PERIPH_BASE + 0x11000000UL)

GPV_BASE (PERIPH_BASE + 0x11000000UL)

Definition at line 2528 of file stm32h735xx.h.

◆ HASH_BASE

#define HASH_BASE   (D2_AHB2PERIPH_BASE + 0x1400UL)

Definition at line 2270 of file stm32h735xx.h.

◆ HASH_DIGEST_BASE

#define HASH_DIGEST_BASE   (D2_AHB2PERIPH_BASE + 0x1710UL)

Definition at line 2271 of file stm32h735xx.h.

◆ HRTIM1_BASE

#define HRTIM1_BASE   (D2_APB2PERIPH_BASE + 0x7400UL)

Definition at line 2325 of file stm32h747xx.h.

◆ HRTIM1_COMMON_BASE

#define HRTIM1_COMMON_BASE   (HRTIM1_BASE + 0x00000380UL)

D3_APB1PERIPH peripherals

Definition at line 2331 of file stm32h747xx.h.

◆ HRTIM1_TIMA_BASE

#define HRTIM1_TIMA_BASE   (HRTIM1_BASE + 0x00000080UL)

Definition at line 2326 of file stm32h747xx.h.

◆ HRTIM1_TIMB_BASE

#define HRTIM1_TIMB_BASE   (HRTIM1_BASE + 0x00000100UL)

Definition at line 2327 of file stm32h747xx.h.

◆ HRTIM1_TIMC_BASE

#define HRTIM1_TIMC_BASE   (HRTIM1_BASE + 0x00000180UL)

Definition at line 2328 of file stm32h747xx.h.

◆ HRTIM1_TIMD_BASE

#define HRTIM1_TIMD_BASE   (HRTIM1_BASE + 0x00000200UL)

Definition at line 2329 of file stm32h747xx.h.

◆ HRTIM1_TIME_BASE

#define HRTIM1_TIME_BASE   (HRTIM1_BASE + 0x00000280UL)

Definition at line 2330 of file stm32h747xx.h.

◆ HSEM_BASE [1/2]

#define HSEM_BASE   (D3_AHB1PERIPH_BASE + 0x6400UL)

Definition at line 2242 of file stm32h747xx.h.

◆ HSEM_BASE [2/2]

#define HSEM_BASE   (D3_AHB1PERIPH_BASE + 0x6400UL)

Definition at line 2297 of file stm32h735xx.h.

◆ I2C1_BASE [1/6]

#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400UL)

Definition at line 670 of file stm32f411xe.h.

◆ I2C1_BASE [2/6]

#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400UL)

Definition at line 954 of file stm32f407xx.h.

◆ I2C1_BASE [3/6]

#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400UL)

Definition at line 1164 of file stm32f469xx.h.

◆ I2C1_BASE [4/6]

#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400UL)

Definition at line 1418 of file stm32f769xx.h.

◆ I2C1_BASE [5/6]

#define I2C1_BASE   (D2_APB1PERIPH_BASE + 0x5400UL)

Definition at line 2273 of file stm32h747xx.h.

◆ I2C1_BASE [6/6]

#define I2C1_BASE   (D2_APB1PERIPH_BASE + 0x5400UL)

Definition at line 2326 of file stm32h735xx.h.

◆ I2C2_BASE [1/6]

#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800UL)

Definition at line 671 of file stm32f411xe.h.

◆ I2C2_BASE [2/6]

#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800UL)

Definition at line 955 of file stm32f407xx.h.

◆ I2C2_BASE [3/6]

#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800UL)

Definition at line 1165 of file stm32f469xx.h.

◆ I2C2_BASE [4/6]

#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800UL)

Definition at line 1419 of file stm32f769xx.h.

◆ I2C2_BASE [5/6]

#define I2C2_BASE   (D2_APB1PERIPH_BASE + 0x5800UL)

Definition at line 2274 of file stm32h747xx.h.

◆ I2C2_BASE [6/6]

#define I2C2_BASE   (D2_APB1PERIPH_BASE + 0x5800UL)

Definition at line 2327 of file stm32h735xx.h.

◆ I2C3_BASE [1/6]

#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00UL)

Definition at line 672 of file stm32f411xe.h.

◆ I2C3_BASE [2/6]

#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00UL)

Definition at line 956 of file stm32f407xx.h.

◆ I2C3_BASE [3/6]

#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00UL)

Definition at line 1166 of file stm32f469xx.h.

◆ I2C3_BASE [4/6]

#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00UL)

Definition at line 1420 of file stm32f769xx.h.

◆ I2C3_BASE [5/6]

#define I2C3_BASE   (D2_APB1PERIPH_BASE + 0x5C00UL)

Definition at line 2275 of file stm32h747xx.h.

◆ I2C3_BASE [6/6]

#define I2C3_BASE   (D2_APB1PERIPH_BASE + 0x5C00UL)

Definition at line 2328 of file stm32h735xx.h.

◆ I2C4_BASE [1/3]

#define I2C4_BASE   (APB1PERIPH_BASE + 0x6000UL)

Definition at line 1421 of file stm32f769xx.h.

◆ I2C4_BASE [2/3]

#define I2C4_BASE   (D3_APB1PERIPH_BASE + 0x1C00UL)

Definition at line 2341 of file stm32h747xx.h.

◆ I2C4_BASE [3/3]

#define I2C4_BASE   (D3_APB1PERIPH_BASE + 0x1C00UL)

Definition at line 2387 of file stm32h735xx.h.

◆ I2C5_BASE

#define I2C5_BASE   (D2_APB1PERIPH_BASE + 0x6400UL)

Definition at line 2329 of file stm32h735xx.h.

◆ I2S2ext_BASE [1/3]

#define I2S2ext_BASE   (APB1PERIPH_BASE + 0x3400UL)

Definition at line 665 of file stm32f411xe.h.

◆ I2S2ext_BASE [2/3]

#define I2S2ext_BASE   (APB1PERIPH_BASE + 0x3400UL)

Definition at line 946 of file stm32f407xx.h.

◆ I2S2ext_BASE [3/3]

#define I2S2ext_BASE   (APB1PERIPH_BASE + 0x3400UL)

Definition at line 1156 of file stm32f469xx.h.

◆ I2S3ext_BASE [1/3]

#define I2S3ext_BASE   (APB1PERIPH_BASE + 0x4000UL)

Definition at line 668 of file stm32f411xe.h.

◆ I2S3ext_BASE [2/3]

#define I2S3ext_BASE   (APB1PERIPH_BASE + 0x4000UL)

Definition at line 949 of file stm32f407xx.h.

◆ I2S3ext_BASE [3/3]

#define I2S3ext_BASE   (APB1PERIPH_BASE + 0x4000UL)

Definition at line 1159 of file stm32f469xx.h.

◆ IWDG1_BASE [1/2]

#define IWDG1_BASE   (D3_APB1PERIPH_BASE + 0x4800UL)

Definition at line 2351 of file stm32h747xx.h.

◆ IWDG1_BASE [2/2]

#define IWDG1_BASE   (D3_APB1PERIPH_BASE + 0x4800UL)

Definition at line 2397 of file stm32h735xx.h.

◆ IWDG2_BASE

#define IWDG2_BASE   (D3_APB1PERIPH_BASE + 0x4C00UL)

Definition at line 2353 of file stm32h747xx.h.

◆ IWDG_BASE [1/4]

#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000UL)

Definition at line 664 of file stm32f411xe.h.

◆ IWDG_BASE [2/4]

#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000UL)

Definition at line 945 of file stm32f407xx.h.

◆ IWDG_BASE [3/4]

#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000UL)

Definition at line 1155 of file stm32f469xx.h.

◆ IWDG_BASE [4/4]

#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000UL)

Definition at line 1409 of file stm32f769xx.h.

◆ JPEG_BASE

#define JPEG_BASE   (AHB2PERIPH_BASE + 0x51000UL)

Definition at line 1521 of file stm32f769xx.h.

◆ JPGDEC_BASE

#define JPGDEC_BASE   (D1_AHB1PERIPH_BASE + 0x3000UL)

Definition at line 2176 of file stm32h747xx.h.

◆ LPTIM1_BASE [1/3]

#define LPTIM1_BASE   (APB1PERIPH_BASE + 0x2400UL)

Definition at line 1406 of file stm32f769xx.h.

◆ LPTIM1_BASE [2/3]

#define LPTIM1_BASE   (D2_APB1PERIPH_BASE + 0x2400UL)

Definition at line 2262 of file stm32h747xx.h.

◆ LPTIM1_BASE [3/3]

#define LPTIM1_BASE   (D2_APB1PERIPH_BASE + 0x2400UL)

Definition at line 2316 of file stm32h735xx.h.

◆ LPTIM2_BASE [1/2]

#define LPTIM2_BASE   (D3_APB1PERIPH_BASE + 0x2400UL)

Definition at line 2342 of file stm32h747xx.h.

◆ LPTIM2_BASE [2/2]

#define LPTIM2_BASE   (D3_APB1PERIPH_BASE + 0x2400UL)

Definition at line 2388 of file stm32h735xx.h.

◆ LPTIM3_BASE [1/2]

#define LPTIM3_BASE   (D3_APB1PERIPH_BASE + 0x2800UL)

Definition at line 2343 of file stm32h747xx.h.

◆ LPTIM3_BASE [2/2]

#define LPTIM3_BASE   (D3_APB1PERIPH_BASE + 0x2800UL)

Definition at line 2389 of file stm32h735xx.h.

◆ LPTIM4_BASE [1/2]

#define LPTIM4_BASE   (D3_APB1PERIPH_BASE + 0x2C00UL)

Definition at line 2344 of file stm32h747xx.h.

◆ LPTIM4_BASE [2/2]

#define LPTIM4_BASE   (D3_APB1PERIPH_BASE + 0x2C00UL)

Definition at line 2390 of file stm32h735xx.h.

◆ LPTIM5_BASE [1/2]

#define LPTIM5_BASE   (D3_APB1PERIPH_BASE + 0x3000UL)

Definition at line 2345 of file stm32h747xx.h.

◆ LPTIM5_BASE [2/2]

#define LPTIM5_BASE   (D3_APB1PERIPH_BASE + 0x3000UL)

Definition at line 2391 of file stm32h735xx.h.

◆ LPUART1_BASE [1/2]

#define LPUART1_BASE   (D3_APB1PERIPH_BASE + 0x0C00UL)

Definition at line 2339 of file stm32h747xx.h.

◆ LPUART1_BASE [2/2]

#define LPUART1_BASE   (D3_APB1PERIPH_BASE + 0x0C00UL)

Definition at line 2385 of file stm32h735xx.h.

◆ LTDC_BASE [1/4]

#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800UL)

Definition at line 1198 of file stm32f469xx.h.

◆ LTDC_BASE [2/4]

#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800UL)

Definition at line 1456 of file stm32f769xx.h.

◆ LTDC_BASE [3/4]

#define LTDC_BASE   (D1_APB1PERIPH_BASE + 0x1000UL)

Definition at line 2246 of file stm32h747xx.h.

◆ LTDC_BASE [4/4]

#define LTDC_BASE   (D1_APB1PERIPH_BASE + 0x1000UL)

Definition at line 2301 of file stm32h735xx.h.

◆ LTDC_Layer1_BASE [1/4]

#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84UL)

Definition at line 1199 of file stm32f469xx.h.

◆ LTDC_Layer1_BASE [2/4]

#define LTDC_Layer1_BASE   (LTDC_BASE + 0x0084UL)

Definition at line 1457 of file stm32f769xx.h.

◆ LTDC_Layer1_BASE [3/4]

#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84UL)

Definition at line 2247 of file stm32h747xx.h.

◆ LTDC_Layer1_BASE [4/4]

#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84UL)

Definition at line 2302 of file stm32h735xx.h.

◆ LTDC_Layer2_BASE [1/4]

#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104UL)

Definition at line 1200 of file stm32f469xx.h.

◆ LTDC_Layer2_BASE [2/4]

#define LTDC_Layer2_BASE   (LTDC_BASE + 0x0104UL)

Definition at line 1458 of file stm32f769xx.h.

◆ LTDC_Layer2_BASE [3/4]

#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104UL)

Definition at line 2248 of file stm32h747xx.h.

◆ LTDC_Layer2_BASE [4/4]

#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104UL)

Definition at line 2303 of file stm32h735xx.h.

◆ MDIOS_BASE [1/3]

#define MDIOS_BASE   (APB2PERIPH_BASE + 0x7800UL)

AHB1 peripherals

Definition at line 1473 of file stm32f769xx.h.

◆ MDIOS_BASE [2/3]

#define MDIOS_BASE   (D2_APB1PERIPH_BASE + 0x9400UL)

Definition at line 2285 of file stm32h747xx.h.

◆ MDIOS_BASE [3/3]

#define MDIOS_BASE   (D2_APB1PERIPH_BASE + 0x9400UL)

Definition at line 2339 of file stm32h735xx.h.

◆ MDMA_BASE [1/2]

#define MDMA_BASE   (D1_AHB1PERIPH_BASE + 0x0000UL)

Definition at line 2174 of file stm32h747xx.h.

◆ MDMA_BASE [2/2]

#define MDMA_BASE   (D1_AHB1PERIPH_BASE + 0x0000UL)

Definition at line 2215 of file stm32h735xx.h.

◆ MDMA_Channel0_BASE [1/2]

#define MDMA_Channel0_BASE   (MDMA_BASE + 0x00000040UL)

Definition at line 2449 of file stm32h747xx.h.

◆ MDMA_Channel0_BASE [2/2]

#define MDMA_Channel0_BASE   (MDMA_BASE + 0x00000040UL)

Definition at line 2495 of file stm32h735xx.h.

◆ MDMA_Channel10_BASE [1/2]

#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)

Definition at line 2459 of file stm32h747xx.h.

◆ MDMA_Channel10_BASE [2/2]

#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)

Definition at line 2505 of file stm32h735xx.h.

◆ MDMA_Channel11_BASE [1/2]

#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)

Definition at line 2460 of file stm32h747xx.h.

◆ MDMA_Channel11_BASE [2/2]

#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)

Definition at line 2506 of file stm32h735xx.h.

◆ MDMA_Channel12_BASE [1/2]

#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)

Definition at line 2461 of file stm32h747xx.h.

◆ MDMA_Channel12_BASE [2/2]

#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)

Definition at line 2507 of file stm32h735xx.h.

◆ MDMA_Channel13_BASE [1/2]

#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)

Definition at line 2462 of file stm32h747xx.h.

◆ MDMA_Channel13_BASE [2/2]

#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)

Definition at line 2508 of file stm32h735xx.h.

◆ MDMA_Channel14_BASE [1/2]

#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)

Definition at line 2463 of file stm32h747xx.h.

◆ MDMA_Channel14_BASE [2/2]

#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)

Definition at line 2509 of file stm32h735xx.h.

◆ MDMA_Channel15_BASE [1/2]

#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)

Definition at line 2464 of file stm32h747xx.h.

◆ MDMA_Channel15_BASE [2/2]

#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)

Definition at line 2510 of file stm32h735xx.h.

◆ MDMA_Channel1_BASE [1/2]

#define MDMA_Channel1_BASE   (MDMA_BASE + 0x00000080UL)

Definition at line 2450 of file stm32h747xx.h.

◆ MDMA_Channel1_BASE [2/2]

#define MDMA_Channel1_BASE   (MDMA_BASE + 0x00000080UL)

Definition at line 2496 of file stm32h735xx.h.

◆ MDMA_Channel2_BASE [1/2]

#define MDMA_Channel2_BASE   (MDMA_BASE + 0x000000C0UL)

Definition at line 2451 of file stm32h747xx.h.

◆ MDMA_Channel2_BASE [2/2]

#define MDMA_Channel2_BASE   (MDMA_BASE + 0x000000C0UL)

Definition at line 2497 of file stm32h735xx.h.

◆ MDMA_Channel3_BASE [1/2]

#define MDMA_Channel3_BASE   (MDMA_BASE + 0x00000100UL)

Definition at line 2452 of file stm32h747xx.h.

◆ MDMA_Channel3_BASE [2/2]

#define MDMA_Channel3_BASE   (MDMA_BASE + 0x00000100UL)

Definition at line 2498 of file stm32h735xx.h.

◆ MDMA_Channel4_BASE [1/2]

#define MDMA_Channel4_BASE   (MDMA_BASE + 0x00000140UL)

Definition at line 2453 of file stm32h747xx.h.

◆ MDMA_Channel4_BASE [2/2]

#define MDMA_Channel4_BASE   (MDMA_BASE + 0x00000140UL)

Definition at line 2499 of file stm32h735xx.h.

◆ MDMA_Channel5_BASE [1/2]

#define MDMA_Channel5_BASE   (MDMA_BASE + 0x00000180UL)

Definition at line 2454 of file stm32h747xx.h.

◆ MDMA_Channel5_BASE [2/2]

#define MDMA_Channel5_BASE   (MDMA_BASE + 0x00000180UL)

Definition at line 2500 of file stm32h735xx.h.

◆ MDMA_Channel6_BASE [1/2]

#define MDMA_Channel6_BASE   (MDMA_BASE + 0x000001C0UL)

Definition at line 2455 of file stm32h747xx.h.

◆ MDMA_Channel6_BASE [2/2]

#define MDMA_Channel6_BASE   (MDMA_BASE + 0x000001C0UL)

Definition at line 2501 of file stm32h735xx.h.

◆ MDMA_Channel7_BASE [1/2]

#define MDMA_Channel7_BASE   (MDMA_BASE + 0x00000200UL)

Definition at line 2456 of file stm32h747xx.h.

◆ MDMA_Channel7_BASE [2/2]

#define MDMA_Channel7_BASE   (MDMA_BASE + 0x00000200UL)

Definition at line 2502 of file stm32h735xx.h.

◆ MDMA_Channel8_BASE [1/2]

#define MDMA_Channel8_BASE   (MDMA_BASE + 0x00000240UL)

Definition at line 2457 of file stm32h747xx.h.

◆ MDMA_Channel8_BASE [2/2]

#define MDMA_Channel8_BASE   (MDMA_BASE + 0x00000240UL)

Definition at line 2503 of file stm32h735xx.h.

◆ MDMA_Channel9_BASE [1/2]

#define MDMA_Channel9_BASE   (MDMA_BASE + 0x00000280UL)

Definition at line 2458 of file stm32h747xx.h.

◆ MDMA_Channel9_BASE [2/2]

#define MDMA_Channel9_BASE   (MDMA_BASE + 0x00000280UL)

Definition at line 2504 of file stm32h735xx.h.

◆ OCTOSPI1_BASE

#define OCTOSPI1_BASE   (0x90000000UL)

Base address of : OCTOSPI1 memories accessible over AXI

Definition at line 2179 of file stm32h735xx.h.

◆ OCTOSPI1_R_BASE

#define OCTOSPI1_R_BASE   (D1_AHB1PERIPH_BASE + 0x5000UL)

Definition at line 2219 of file stm32h735xx.h.

◆ OCTOSPI2_BASE

#define OCTOSPI2_BASE   (0x70000000UL)

Base address of : OCTOSPI2 memories accessible over AXI

Definition at line 2180 of file stm32h735xx.h.

◆ OCTOSPI2_R_BASE

#define OCTOSPI2_R_BASE   (D1_AHB1PERIPH_BASE + 0xA000UL)

Definition at line 2224 of file stm32h735xx.h.

◆ OCTOSPIM_BASE

#define OCTOSPIM_BASE   (D1_AHB1PERIPH_BASE + 0xB400UL)

Definition at line 2226 of file stm32h735xx.h.

◆ OPAMP1_BASE [1/2]

#define OPAMP1_BASE   (D2_APB1PERIPH_BASE + 0x9000UL)

Definition at line 2283 of file stm32h747xx.h.

◆ OPAMP1_BASE [2/2]

#define OPAMP1_BASE   (D2_APB1PERIPH_BASE + 0x9000UL)

Definition at line 2337 of file stm32h735xx.h.

◆ OPAMP2_BASE [1/2]

#define OPAMP2_BASE   (D2_APB1PERIPH_BASE + 0x9010UL)

Definition at line 2284 of file stm32h747xx.h.

◆ OPAMP2_BASE [2/2]

#define OPAMP2_BASE   (D2_APB1PERIPH_BASE + 0x9010UL)

Definition at line 2338 of file stm32h735xx.h.

◆ OPAMP_BASE [1/2]

#define OPAMP_BASE   (D2_APB1PERIPH_BASE + 0x9000UL)

Definition at line 2282 of file stm32h747xx.h.

◆ OPAMP_BASE [2/2]

#define OPAMP_BASE   (D2_APB1PERIPH_BASE + 0x9000UL)

Definition at line 2336 of file stm32h735xx.h.

◆ OTFDEC1_BASE

#define OTFDEC1_BASE   (D1_AHB1PERIPH_BASE + 0xB800UL)

Definition at line 2228 of file stm32h735xx.h.

◆ OTFDEC1_REGION1_BASE

#define OTFDEC1_REGION1_BASE   (OTFDEC1_BASE + 0x20UL)

Definition at line 2229 of file stm32h735xx.h.

◆ OTFDEC1_REGION2_BASE

#define OTFDEC1_REGION2_BASE   (OTFDEC1_BASE + 0x50UL)

Definition at line 2230 of file stm32h735xx.h.

◆ OTFDEC1_REGION3_BASE

#define OTFDEC1_REGION3_BASE   (OTFDEC1_BASE + 0x80UL)

Definition at line 2231 of file stm32h735xx.h.

◆ OTFDEC1_REGION4_BASE

#define OTFDEC1_REGION4_BASE   (OTFDEC1_BASE + 0xB0UL)

Definition at line 2232 of file stm32h735xx.h.

◆ OTFDEC2_BASE

#define OTFDEC2_BASE   (D1_AHB1PERIPH_BASE + 0xBC00UL)

Definition at line 2233 of file stm32h735xx.h.

◆ OTFDEC2_REGION1_BASE

#define OTFDEC2_REGION1_BASE   (OTFDEC2_BASE + 0x20UL)

Definition at line 2234 of file stm32h735xx.h.

◆ OTFDEC2_REGION2_BASE

#define OTFDEC2_REGION2_BASE   (OTFDEC2_BASE + 0x50UL)

Definition at line 2235 of file stm32h735xx.h.

◆ OTFDEC2_REGION3_BASE

#define OTFDEC2_REGION3_BASE   (OTFDEC2_BASE + 0x80UL)

Definition at line 2236 of file stm32h735xx.h.

◆ OTFDEC2_REGION4_BASE

#define OTFDEC2_REGION4_BASE   (OTFDEC2_BASE + 0xB0UL)

D2_AHB1PERIPH peripherals

Definition at line 2237 of file stm32h735xx.h.

◆ PACKAGE_BASE [1/4]

#define PACKAGE_BASE   0x1FFF7BF0UL

Package size register base address

Definition at line 743 of file stm32f411xe.h.

◆ PACKAGE_BASE [2/4]

#define PACKAGE_BASE   0x1FFF7BF0UL

Package size register base address

Definition at line 1050 of file stm32f407xx.h.

◆ PACKAGE_BASE [3/4]

#define PACKAGE_BASE   0x1FFF7BF0UL

Package size register base address

Definition at line 1275 of file stm32f469xx.h.

◆ PACKAGE_BASE [4/4]

#define PACKAGE_BASE   0x1FF0F7E0UL

Package size register base address

Definition at line 1491 of file stm32f769xx.h.

◆ PACKAGESIZE_BASE

#define PACKAGESIZE_BASE   PACKAGE_BASE

Definition at line 1493 of file stm32f769xx.h.

◆ PERIPH_BASE [1/6]

#define PERIPH_BASE   0x40000000UL

Peripheral base address in the alias region

Definition at line 639 of file stm32f411xe.h.

◆ PERIPH_BASE [2/6]

#define PERIPH_BASE   0x40000000UL

Peripheral base address in the alias region

Definition at line 911 of file stm32f407xx.h.

◆ PERIPH_BASE [3/6]

#define PERIPH_BASE   0x40000000UL

Peripheral base address in the alias region

Definition at line 1119 of file stm32f469xx.h.

◆ PERIPH_BASE [4/6]

#define PERIPH_BASE   0x40000000UL

Base address of : AHB/ABP Peripherals

Definition at line 1376 of file stm32f769xx.h.

◆ PERIPH_BASE [5/6]

#define PERIPH_BASE   (0x40000000UL)

Base address of : AHB/APB Peripherals

Definition at line 2138 of file stm32h747xx.h.

◆ PERIPH_BASE [6/6]

#define PERIPH_BASE   (0x40000000UL)

Base address of : AHB/APB Peripherals

Definition at line 2178 of file stm32h735xx.h.

◆ PERIPH_BB_BASE [1/3]

#define PERIPH_BB_BASE   0x42000000UL

Peripheral base address in the bit-band region

Definition at line 641 of file stm32f411xe.h.

◆ PERIPH_BB_BASE [2/3]

#define PERIPH_BB_BASE   0x42000000UL

Peripheral base address in the bit-band region

Definition at line 916 of file stm32f407xx.h.

◆ PERIPH_BB_BASE [3/3]

#define PERIPH_BB_BASE   0x42000000UL

Peripheral base address in the bit-band region

Definition at line 1126 of file stm32f469xx.h.

◆ PSSI_BASE

#define PSSI_BASE   (D2_AHB2PERIPH_BASE + 0x0400UL)

Definition at line 2268 of file stm32h735xx.h.

◆ PWR_BASE [1/6]

#define PWR_BASE   (APB1PERIPH_BASE + 0x7000UL)

APB2 peripherals

Definition at line 673 of file stm32f411xe.h.

◆ PWR_BASE [2/6]

#define PWR_BASE   (APB1PERIPH_BASE + 0x7000UL)

Definition at line 959 of file stm32f407xx.h.

◆ PWR_BASE [3/6]

#define PWR_BASE   (APB1PERIPH_BASE + 0x7000UL)

Definition at line 1169 of file stm32f469xx.h.

◆ PWR_BASE [4/6]

#define PWR_BASE   (APB1PERIPH_BASE + 0x7000UL)

Definition at line 1425 of file stm32f769xx.h.

◆ PWR_BASE [5/6]

#define PWR_BASE   (D3_AHB1PERIPH_BASE + 0x4800UL)

Definition at line 2236 of file stm32h747xx.h.

◆ PWR_BASE [6/6]

#define PWR_BASE   (D3_AHB1PERIPH_BASE + 0x4800UL)

Definition at line 2291 of file stm32h735xx.h.

◆ QSPI_BASE [1/2]

#define QSPI_BASE   0x90000000UL

Base address of : QSPI memories accessible over AXI

Definition at line 1378 of file stm32f769xx.h.

◆ QSPI_BASE [2/2]

#define QSPI_BASE   (0x90000000UL)

Base address of : QSPI memories accessible over AXI

Definition at line 2139 of file stm32h747xx.h.

◆ QSPI_R_BASE [1/3]

#define QSPI_R_BASE   0xA0001000UL

QuadSPI registers base address

Definition at line 1122 of file stm32f469xx.h.

◆ QSPI_R_BASE [2/3]

#define QSPI_R_BASE   0xA0001000UL

Base address of : QSPI Control registers

Definition at line 1380 of file stm32f769xx.h.

◆ QSPI_R_BASE [3/3]

#define QSPI_R_BASE   (D1_AHB1PERIPH_BASE + 0x5000UL)

Definition at line 2179 of file stm32h747xx.h.

◆ RAMDTCM_BASE

#define RAMDTCM_BASE   0x20000000UL

Base address of : 128KB system data RAM accessible over DTCM

Definition at line 1375 of file stm32f769xx.h.

◆ RAMECC1_BASE [1/2]

#define RAMECC1_BASE   (D1_AHB1PERIPH_BASE + 0x9000UL)

D2_AHB1PERIPH peripherals

Definition at line 2183 of file stm32h747xx.h.

◆ RAMECC1_BASE [2/2]

#define RAMECC1_BASE   (D1_AHB1PERIPH_BASE + 0x9000UL)

Definition at line 2223 of file stm32h735xx.h.

◆ RAMECC1_Monitor1_BASE [1/2]

#define RAMECC1_Monitor1_BASE   (RAMECC1_BASE + 0x20UL)

Definition at line 2466 of file stm32h747xx.h.

◆ RAMECC1_Monitor1_BASE [2/2]

#define RAMECC1_Monitor1_BASE   (RAMECC1_BASE + 0x20UL)

Definition at line 2512 of file stm32h735xx.h.

◆ RAMECC1_Monitor2_BASE [1/2]

#define RAMECC1_Monitor2_BASE   (RAMECC1_BASE + 0x40UL)

Definition at line 2467 of file stm32h747xx.h.

◆ RAMECC1_Monitor2_BASE [2/2]

#define RAMECC1_Monitor2_BASE   (RAMECC1_BASE + 0x40UL)

Definition at line 2513 of file stm32h735xx.h.

◆ RAMECC1_Monitor3_BASE [1/2]

#define RAMECC1_Monitor3_BASE   (RAMECC1_BASE + 0x60UL)

Definition at line 2468 of file stm32h747xx.h.

◆ RAMECC1_Monitor3_BASE [2/2]

#define RAMECC1_Monitor3_BASE   (RAMECC1_BASE + 0x60UL)

Definition at line 2514 of file stm32h735xx.h.

◆ RAMECC1_Monitor4_BASE [1/2]

#define RAMECC1_Monitor4_BASE   (RAMECC1_BASE + 0x80UL)

Definition at line 2469 of file stm32h747xx.h.

◆ RAMECC1_Monitor4_BASE [2/2]

#define RAMECC1_Monitor4_BASE   (RAMECC1_BASE + 0x80UL)

Definition at line 2515 of file stm32h735xx.h.

◆ RAMECC1_Monitor5_BASE [1/2]

#define RAMECC1_Monitor5_BASE   (RAMECC1_BASE + 0xA0UL)

Definition at line 2470 of file stm32h747xx.h.

◆ RAMECC1_Monitor5_BASE [2/2]

#define RAMECC1_Monitor5_BASE   (RAMECC1_BASE + 0xA0UL)

Definition at line 2516 of file stm32h735xx.h.

◆ RAMECC1_Monitor6_BASE

#define RAMECC1_Monitor6_BASE   (RAMECC1_BASE + 0xC0UL)

Definition at line 2517 of file stm32h735xx.h.

◆ RAMECC2_BASE [1/2]

#define RAMECC2_BASE   (D2_AHB2PERIPH_BASE + 0x3000UL)

D3_AHB1PERIPH peripherals

Definition at line 2219 of file stm32h747xx.h.

◆ RAMECC2_BASE [2/2]

#define RAMECC2_BASE   (D2_AHB2PERIPH_BASE + 0x3000UL)

Definition at line 2275 of file stm32h735xx.h.

◆ RAMECC2_Monitor1_BASE [1/2]

#define RAMECC2_Monitor1_BASE   (RAMECC2_BASE + 0x20UL)

Definition at line 2472 of file stm32h747xx.h.

◆ RAMECC2_Monitor1_BASE [2/2]

#define RAMECC2_Monitor1_BASE   (RAMECC2_BASE + 0x20UL)

Definition at line 2519 of file stm32h735xx.h.

◆ RAMECC2_Monitor2_BASE [1/2]

#define RAMECC2_Monitor2_BASE   (RAMECC2_BASE + 0x40UL)

Definition at line 2473 of file stm32h747xx.h.

◆ RAMECC2_Monitor2_BASE [2/2]

#define RAMECC2_Monitor2_BASE   (RAMECC2_BASE + 0x40UL)

Definition at line 2520 of file stm32h735xx.h.

◆ RAMECC2_Monitor3_BASE [1/2]

#define RAMECC2_Monitor3_BASE   (RAMECC2_BASE + 0x60UL)

Definition at line 2474 of file stm32h747xx.h.

◆ RAMECC2_Monitor3_BASE [2/2]

#define RAMECC2_Monitor3_BASE   (RAMECC2_BASE + 0x60UL)

Definition at line 2521 of file stm32h735xx.h.

◆ RAMECC2_Monitor4_BASE

#define RAMECC2_Monitor4_BASE   (RAMECC2_BASE + 0x80UL)

Definition at line 2475 of file stm32h747xx.h.

◆ RAMECC2_Monitor5_BASE

#define RAMECC2_Monitor5_BASE   (RAMECC2_BASE + 0xA0UL)

Definition at line 2476 of file stm32h747xx.h.

◆ RAMECC3_BASE [1/2]

#define RAMECC3_BASE   (D3_AHB1PERIPH_BASE + 0x7000UL)

D1_APB1PERIPH peripherals

Definition at line 2243 of file stm32h747xx.h.

◆ RAMECC3_BASE [2/2]

#define RAMECC3_BASE   (D3_AHB1PERIPH_BASE + 0x7000UL)

D1_APB1PERIPH peripherals

Definition at line 2298 of file stm32h735xx.h.

◆ RAMECC3_Monitor1_BASE [1/2]

#define RAMECC3_Monitor1_BASE   (RAMECC3_BASE + 0x20UL)

Definition at line 2478 of file stm32h747xx.h.

◆ RAMECC3_Monitor1_BASE [2/2]

#define RAMECC3_Monitor1_BASE   (RAMECC3_BASE + 0x20UL)

Definition at line 2523 of file stm32h735xx.h.

◆ RAMECC3_Monitor2_BASE [1/2]

#define RAMECC3_Monitor2_BASE   (RAMECC3_BASE + 0x40UL)

Definition at line 2479 of file stm32h747xx.h.

◆ RAMECC3_Monitor2_BASE [2/2]

#define RAMECC3_Monitor2_BASE   (RAMECC3_BASE + 0x40UL)

Definition at line 2524 of file stm32h735xx.h.

◆ RAMITCM_BASE

#define RAMITCM_BASE   0x00000000UL

Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM

Definition at line 1372 of file stm32f769xx.h.

◆ RCC_BASE [1/6]

#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800UL)

Definition at line 701 of file stm32f411xe.h.

◆ RCC_BASE [2/6]

#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800UL)

Definition at line 992 of file stm32f407xx.h.

◆ RCC_BASE [3/6]

#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800UL)

Definition at line 1216 of file stm32f469xx.h.

◆ RCC_BASE [4/6]

#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800UL)

Definition at line 1487 of file stm32f769xx.h.

◆ RCC_BASE [5/6]

#define RCC_BASE   (D3_AHB1PERIPH_BASE + 0x4400UL)

Definition at line 2233 of file stm32h747xx.h.

◆ RCC_BASE [6/6]

#define RCC_BASE   (D3_AHB1PERIPH_BASE + 0x4400UL)

Definition at line 2290 of file stm32h735xx.h.

◆ RCC_C1_BASE

#define RCC_C1_BASE   (RCC_BASE + 0x130UL)

Definition at line 2234 of file stm32h747xx.h.

◆ RCC_C2_BASE

#define RCC_C2_BASE   (RCC_BASE + 0x190UL)

Definition at line 2235 of file stm32h747xx.h.

◆ RNG_BASE [1/5]

#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800UL)

FSMC Bankx registers base address

Definition at line 1020 of file stm32f407xx.h.

◆ RNG_BASE [2/5]

#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800UL)

FMC Bankx registers base address

Definition at line 1245 of file stm32f469xx.h.

◆ RNG_BASE [3/5]

#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800UL)

FMC Bankx registers base address

Definition at line 1522 of file stm32f769xx.h.

◆ RNG_BASE [4/5]

#define RNG_BASE   (D2_AHB2PERIPH_BASE + 0x1800UL)

Definition at line 2216 of file stm32h747xx.h.

◆ RNG_BASE [5/5]

#define RNG_BASE   (D2_AHB2PERIPH_BASE + 0x1800UL)

Definition at line 2272 of file stm32h735xx.h.

◆ RTC_BASE [1/6]

#define RTC_BASE   (APB1PERIPH_BASE + 0x2800UL)

Definition at line 662 of file stm32f411xe.h.

◆ RTC_BASE [2/6]

#define RTC_BASE   (APB1PERIPH_BASE + 0x2800UL)

Definition at line 943 of file stm32f407xx.h.

◆ RTC_BASE [3/6]

#define RTC_BASE   (APB1PERIPH_BASE + 0x2800UL)

Definition at line 1153 of file stm32f469xx.h.

◆ RTC_BASE [4/6]

#define RTC_BASE   (APB1PERIPH_BASE + 0x2800UL)

Definition at line 1407 of file stm32f769xx.h.

◆ RTC_BASE [5/6]

#define RTC_BASE   (D3_APB1PERIPH_BASE + 0x4000UL)

Definition at line 2350 of file stm32h747xx.h.

◆ RTC_BASE [6/6]

#define RTC_BASE   (D3_APB1PERIPH_BASE + 0x4000UL)

Definition at line 2396 of file stm32h735xx.h.

◆ SAI1_BASE [1/4]

#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800UL)

Definition at line 1195 of file stm32f469xx.h.

◆ SAI1_BASE [2/4]

#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800UL)

Definition at line 1450 of file stm32f769xx.h.

◆ SAI1_BASE [3/4]

#define SAI1_BASE   (D2_APB2PERIPH_BASE + 0x5800UL)

Definition at line 2303 of file stm32h747xx.h.

◆ SAI1_BASE [4/4]

#define SAI1_BASE   (D2_APB2PERIPH_BASE + 0x5800UL)

Definition at line 2362 of file stm32h735xx.h.

◆ SAI1_Block_A_BASE [1/4]

#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004UL)

Definition at line 1196 of file stm32f469xx.h.

◆ SAI1_Block_A_BASE [2/4]

#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004UL)

Definition at line 1452 of file stm32f769xx.h.

◆ SAI1_Block_A_BASE [3/4]

#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004UL)

Definition at line 2304 of file stm32h747xx.h.

◆ SAI1_Block_A_BASE [4/4]

#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004UL)

Definition at line 2363 of file stm32h735xx.h.

◆ SAI1_Block_B_BASE [1/4]

#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024UL)

Definition at line 1197 of file stm32f469xx.h.

◆ SAI1_Block_B_BASE [2/4]

#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024UL)

Definition at line 1453 of file stm32f769xx.h.

◆ SAI1_Block_B_BASE [3/4]

#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024UL)

Definition at line 2305 of file stm32h747xx.h.

◆ SAI1_Block_B_BASE [4/4]

#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024UL)

Definition at line 2364 of file stm32h735xx.h.

◆ SAI2_BASE [1/2]

#define SAI2_BASE   (APB2PERIPH_BASE + 0x5C00UL)

Definition at line 1451 of file stm32f769xx.h.

◆ SAI2_BASE [2/2]

#define SAI2_BASE   (D2_APB2PERIPH_BASE + 0x5C00UL)

Definition at line 2306 of file stm32h747xx.h.

◆ SAI2_Block_A_BASE [1/2]

#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004UL)

Definition at line 1454 of file stm32f769xx.h.

◆ SAI2_Block_A_BASE [2/2]

#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004UL)

Definition at line 2307 of file stm32h747xx.h.

◆ SAI2_Block_B_BASE [1/2]

#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024UL)

Definition at line 1455 of file stm32f769xx.h.

◆ SAI2_Block_B_BASE [2/2]

#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024UL)

Definition at line 2308 of file stm32h747xx.h.

◆ SAI3_BASE

#define SAI3_BASE   (D2_APB2PERIPH_BASE + 0x6000UL)

Definition at line 2309 of file stm32h747xx.h.

◆ SAI3_Block_A_BASE

#define SAI3_Block_A_BASE   (SAI3_BASE + 0x004UL)

Definition at line 2310 of file stm32h747xx.h.

◆ SAI3_Block_B_BASE

#define SAI3_Block_B_BASE   (SAI3_BASE + 0x024UL)

Definition at line 2311 of file stm32h747xx.h.

◆ SAI4_BASE [1/2]

#define SAI4_BASE   (D3_APB1PERIPH_BASE + 0x5400UL)

Definition at line 2355 of file stm32h747xx.h.

◆ SAI4_BASE [2/2]

#define SAI4_BASE   (D3_APB1PERIPH_BASE + 0x5400UL)

Definition at line 2400 of file stm32h735xx.h.

◆ SAI4_Block_A_BASE [1/2]

#define SAI4_Block_A_BASE   (SAI4_BASE + 0x004UL)

Definition at line 2356 of file stm32h747xx.h.

◆ SAI4_Block_A_BASE [2/2]

#define SAI4_Block_A_BASE   (SAI4_BASE + 0x004UL)

Definition at line 2401 of file stm32h735xx.h.

◆ SAI4_Block_B_BASE [1/2]

#define SAI4_Block_B_BASE   (SAI4_BASE + 0x024UL)

Definition at line 2357 of file stm32h747xx.h.

◆ SAI4_Block_B_BASE [2/2]

#define SAI4_Block_B_BASE   (SAI4_BASE + 0x024UL)

Definition at line 2402 of file stm32h735xx.h.

◆ SDIO_BASE [1/3]

#define SDIO_BASE   (APB2PERIPH_BASE + 0x2C00UL)

Definition at line 683 of file stm32f411xe.h.

◆ SDIO_BASE [2/3]

#define SDIO_BASE   (APB2PERIPH_BASE + 0x2C00UL)

Definition at line 973 of file stm32f407xx.h.

◆ SDIO_BASE [3/3]

#define SDIO_BASE   (APB2PERIPH_BASE + 0x2C00UL)

Definition at line 1185 of file stm32f469xx.h.

◆ SDMMC1_BASE [1/3]

#define SDMMC1_BASE   (APB2PERIPH_BASE + 0x2C00UL)

Definition at line 1440 of file stm32f769xx.h.

◆ SDMMC1_BASE [2/3]

#define SDMMC1_BASE   (D1_AHB1PERIPH_BASE + 0x7000UL)

Definition at line 2181 of file stm32h747xx.h.

◆ SDMMC1_BASE [3/3]

#define SDMMC1_BASE   (D1_AHB1PERIPH_BASE + 0x7000UL)

Definition at line 2221 of file stm32h735xx.h.

◆ SDMMC2_BASE [1/3]

#define SDMMC2_BASE   (APB2PERIPH_BASE + 0x1C00UL)

Definition at line 1435 of file stm32f769xx.h.

◆ SDMMC2_BASE [2/3]

#define SDMMC2_BASE   (D2_AHB2PERIPH_BASE + 0x2400UL)

Definition at line 2217 of file stm32h747xx.h.

◆ SDMMC2_BASE [3/3]

#define SDMMC2_BASE   (D2_AHB2PERIPH_BASE + 0x2400UL)

Definition at line 2273 of file stm32h735xx.h.

◆ SPDIFRX_BASE [1/3]

#define SPDIFRX_BASE   (APB1PERIPH_BASE + 0x4000UL)

Definition at line 1413 of file stm32f769xx.h.

◆ SPDIFRX_BASE [2/3]

#define SPDIFRX_BASE   (D2_APB1PERIPH_BASE + 0x4000UL)

Definition at line 2268 of file stm32h747xx.h.

◆ SPDIFRX_BASE [3/3]

#define SPDIFRX_BASE   (D2_APB1PERIPH_BASE + 0x4000UL)

Definition at line 2321 of file stm32h735xx.h.

◆ SPI1_BASE [1/6]

#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000UL)

Definition at line 684 of file stm32f411xe.h.

◆ SPI1_BASE [2/6]

#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000UL)

Definition at line 974 of file stm32f407xx.h.

◆ SPI1_BASE [3/6]

#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000UL)

Definition at line 1186 of file stm32f469xx.h.

◆ SPI1_BASE [4/6]

#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000UL)

Definition at line 1441 of file stm32f769xx.h.

◆ SPI1_BASE [5/6]

#define SPI1_BASE   (D2_APB2PERIPH_BASE + 0x3000UL)

Definition at line 2297 of file stm32h747xx.h.

◆ SPI1_BASE [6/6]

#define SPI1_BASE   (D2_APB2PERIPH_BASE + 0x3000UL)

Definition at line 2356 of file stm32h735xx.h.

◆ SPI2_BASE [1/6]

#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800UL)

Definition at line 666 of file stm32f411xe.h.

◆ SPI2_BASE [2/6]

#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800UL)

Definition at line 947 of file stm32f407xx.h.

◆ SPI2_BASE [3/6]

#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800UL)

Definition at line 1157 of file stm32f469xx.h.

◆ SPI2_BASE [4/6]

#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800UL)

Definition at line 1411 of file stm32f769xx.h.

◆ SPI2_BASE [5/6]

#define SPI2_BASE   (D2_APB1PERIPH_BASE + 0x3800UL)

Definition at line 2266 of file stm32h747xx.h.

◆ SPI2_BASE [6/6]

#define SPI2_BASE   (D2_APB1PERIPH_BASE + 0x3800UL)

Definition at line 2319 of file stm32h735xx.h.

◆ SPI3_BASE [1/6]

#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00UL)

Definition at line 667 of file stm32f411xe.h.

◆ SPI3_BASE [2/6]

#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00UL)

Definition at line 948 of file stm32f407xx.h.

◆ SPI3_BASE [3/6]

#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00UL)

Definition at line 1158 of file stm32f469xx.h.

◆ SPI3_BASE [4/6]

#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00UL)

Definition at line 1412 of file stm32f769xx.h.

◆ SPI3_BASE [5/6]

#define SPI3_BASE   (D2_APB1PERIPH_BASE + 0x3C00UL)

Definition at line 2267 of file stm32h747xx.h.

◆ SPI3_BASE [6/6]

#define SPI3_BASE   (D2_APB1PERIPH_BASE + 0x3C00UL)

Definition at line 2320 of file stm32h735xx.h.

◆ SPI4_BASE [1/5]

#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400UL)

Definition at line 685 of file stm32f411xe.h.

◆ SPI4_BASE [2/5]

#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400UL)

Definition at line 1187 of file stm32f469xx.h.

◆ SPI4_BASE [3/5]

#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400UL)

Definition at line 1442 of file stm32f769xx.h.

◆ SPI4_BASE [4/5]

#define SPI4_BASE   (D2_APB2PERIPH_BASE + 0x3400UL)

Definition at line 2298 of file stm32h747xx.h.

◆ SPI4_BASE [5/5]

#define SPI4_BASE   (D2_APB2PERIPH_BASE + 0x3400UL)

Definition at line 2357 of file stm32h735xx.h.

◆ SPI5_BASE [1/5]

#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000UL)

AHB1 peripherals

Definition at line 691 of file stm32f411xe.h.

◆ SPI5_BASE [2/5]

#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000UL)

Definition at line 1193 of file stm32f469xx.h.

◆ SPI5_BASE [3/5]

#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000UL)

Definition at line 1448 of file stm32f769xx.h.

◆ SPI5_BASE [4/5]

#define SPI5_BASE   (D2_APB2PERIPH_BASE + 0x5000UL)

Definition at line 2302 of file stm32h747xx.h.

◆ SPI5_BASE [5/5]

#define SPI5_BASE   (D2_APB2PERIPH_BASE + 0x5000UL)

Definition at line 2361 of file stm32h735xx.h.

◆ SPI6_BASE [1/4]

#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400UL)

Definition at line 1194 of file stm32f469xx.h.

◆ SPI6_BASE [2/4]

#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400UL)

Definition at line 1449 of file stm32f769xx.h.

◆ SPI6_BASE [3/4]

#define SPI6_BASE   (D3_APB1PERIPH_BASE + 0x1400UL)

Definition at line 2340 of file stm32h747xx.h.

◆ SPI6_BASE [4/4]

#define SPI6_BASE   (D3_APB1PERIPH_BASE + 0x1400UL)

Definition at line 2386 of file stm32h735xx.h.

◆ SRAM1_BASE [1/4]

#define SRAM1_BASE   0x20000000UL

SRAM1(128 KB) base address in the alias region

Definition at line 638 of file stm32f411xe.h.

◆ SRAM1_BASE [2/4]

#define SRAM1_BASE   0x20000000UL

SRAM1(112 KB) base address in the alias region

Definition at line 909 of file stm32f407xx.h.

◆ SRAM1_BASE [3/4]

#define SRAM1_BASE   0x20000000UL

SRAM1(160 KB) base address in the alias region

Definition at line 1116 of file stm32f469xx.h.

◆ SRAM1_BASE [4/4]

#define SRAM1_BASE   0x20020000UL

Base address of : 368KB RAM1 accessible over AXI/AHB

Definition at line 1381 of file stm32f769xx.h.

◆ SRAM1_BB_BASE [1/3]

#define SRAM1_BB_BASE   0x22000000UL

SRAM1(128 KB) base address in the bit-band region

Definition at line 640 of file stm32f411xe.h.

◆ SRAM1_BB_BASE [2/3]

#define SRAM1_BB_BASE   0x22000000UL

SRAM1(112 KB) base address in the bit-band region

Definition at line 914 of file stm32f407xx.h.

◆ SRAM1_BB_BASE [3/3]

#define SRAM1_BB_BASE   0x22000000UL

SRAM1(112 KB) base address in the bit-band region

Definition at line 1123 of file stm32f469xx.h.

◆ SRAM2_BASE [1/3]

#define SRAM2_BASE   0x2001C000UL

SRAM2(16 KB) base address in the alias region

Definition at line 910 of file stm32f407xx.h.

◆ SRAM2_BASE [2/3]

#define SRAM2_BASE   0x20028000UL

SRAM2(32 KB) base address in the alias region

Definition at line 1117 of file stm32f469xx.h.

◆ SRAM2_BASE [3/3]

#define SRAM2_BASE   0x2007C000UL

Base address of : 16KB RAM2 accessible over AXI/AHB

Definition at line 1382 of file stm32f769xx.h.

◆ SRAM2_BB_BASE [1/2]

#define SRAM2_BB_BASE   0x22380000UL

SRAM2(16 KB) base address in the bit-band region

Definition at line 915 of file stm32f407xx.h.

◆ SRAM2_BB_BASE [2/2]

#define SRAM2_BB_BASE   0x22500000UL

SRAM2(16 KB) base address in the bit-band region

Definition at line 1124 of file stm32f469xx.h.

◆ SRAM3_BASE

#define SRAM3_BASE   0x20030000UL

SRAM3(128 KB) base address in the alias region

Definition at line 1118 of file stm32f469xx.h.

◆ SRAM3_BB_BASE

#define SRAM3_BB_BASE   0x22600000UL

SRAM3(64 KB) base address in the bit-band region

Definition at line 1125 of file stm32f469xx.h.

◆ SRAM_BASE [1/3]

#define SRAM_BASE   SRAM1_BASE

Definition at line 648 of file stm32f411xe.h.

◆ SRAM_BASE [2/3]

#define SRAM_BASE   SRAM1_BASE

Definition at line 924 of file stm32f407xx.h.

◆ SRAM_BASE [3/3]

#define SRAM_BASE   SRAM1_BASE

Definition at line 1134 of file stm32f469xx.h.

◆ SRAM_BB_BASE [1/3]

#define SRAM_BB_BASE   SRAM1_BB_BASE

Peripheral memory map

Definition at line 649 of file stm32f411xe.h.

◆ SRAM_BB_BASE [2/3]

#define SRAM_BB_BASE   SRAM1_BB_BASE

Peripheral memory map

Definition at line 925 of file stm32f407xx.h.

◆ SRAM_BB_BASE [3/3]

#define SRAM_BB_BASE   SRAM1_BB_BASE

Peripheral memory map

Definition at line 1135 of file stm32f469xx.h.

◆ SRAMCAN_BASE [1/2]

#define SRAMCAN_BASE   (D2_APB1PERIPH_BASE + 0xAC00UL)

D2_APB2PERIPH peripherals

Definition at line 2289 of file stm32h747xx.h.

◆ SRAMCAN_BASE [2/2]

#define SRAMCAN_BASE   (D2_APB1PERIPH_BASE + 0xAC00UL)

Definition at line 2343 of file stm32h735xx.h.

◆ SWPMI1_BASE [1/2]

#define SWPMI1_BASE   (D2_APB1PERIPH_BASE + 0x8800UL)

Definition at line 2281 of file stm32h747xx.h.

◆ SWPMI1_BASE [2/2]

#define SWPMI1_BASE   (D2_APB1PERIPH_BASE + 0x8800UL)

Definition at line 2335 of file stm32h735xx.h.

◆ SYSCFG_BASE [1/6]

#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800UL)

Definition at line 686 of file stm32f411xe.h.

◆ SYSCFG_BASE [2/6]

#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800UL)

Definition at line 975 of file stm32f407xx.h.

◆ SYSCFG_BASE [3/6]

#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800UL)

Definition at line 1188 of file stm32f469xx.h.

◆ SYSCFG_BASE [4/6]

#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800UL)

Definition at line 1443 of file stm32f769xx.h.

◆ SYSCFG_BASE [5/6]

#define SYSCFG_BASE   (D3_APB1PERIPH_BASE + 0x0400UL)

Definition at line 2338 of file stm32h747xx.h.

◆ SYSCFG_BASE [6/6]

#define SYSCFG_BASE   (D3_APB1PERIPH_BASE + 0x0400UL)

Definition at line 2384 of file stm32h735xx.h.

◆ TIM10_BASE [1/4]

#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400UL)

Definition at line 689 of file stm32f411xe.h.

◆ TIM10_BASE [2/4]

#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400UL)

Definition at line 978 of file stm32f407xx.h.

◆ TIM10_BASE [3/4]

#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400UL)

Definition at line 1191 of file stm32f469xx.h.

◆ TIM10_BASE [4/4]

#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400UL)

Definition at line 1446 of file stm32f769xx.h.

◆ TIM11_BASE [1/4]

#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800UL)

Definition at line 690 of file stm32f411xe.h.

◆ TIM11_BASE [2/4]

#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800UL)

AHB1 peripherals

Definition at line 979 of file stm32f407xx.h.

◆ TIM11_BASE [3/4]

#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800UL)

Definition at line 1192 of file stm32f469xx.h.

◆ TIM11_BASE [4/4]

#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800UL)

Definition at line 1447 of file stm32f769xx.h.

◆ TIM12_BASE [1/5]

#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800UL)

Definition at line 940 of file stm32f407xx.h.

◆ TIM12_BASE [2/5]

#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800UL)

Definition at line 1150 of file stm32f469xx.h.

◆ TIM12_BASE [3/5]

#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800UL)

Definition at line 1403 of file stm32f769xx.h.

◆ TIM12_BASE [4/5]

#define TIM12_BASE   (D2_APB1PERIPH_BASE + 0x1800UL)

Definition at line 2259 of file stm32h747xx.h.

◆ TIM12_BASE [5/5]

#define TIM12_BASE   (D2_APB1PERIPH_BASE + 0x1800UL)

Definition at line 2313 of file stm32h735xx.h.

◆ TIM13_BASE [1/5]

#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00UL)

Definition at line 941 of file stm32f407xx.h.

◆ TIM13_BASE [2/5]

#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00UL)

Definition at line 1151 of file stm32f469xx.h.

◆ TIM13_BASE [3/5]

#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00UL)

Definition at line 1404 of file stm32f769xx.h.

◆ TIM13_BASE [4/5]

#define TIM13_BASE   (D2_APB1PERIPH_BASE + 0x1C00UL)

Definition at line 2260 of file stm32h747xx.h.

◆ TIM13_BASE [5/5]

#define TIM13_BASE   (D2_APB1PERIPH_BASE + 0x1C00UL)

Definition at line 2314 of file stm32h735xx.h.

◆ TIM14_BASE [1/5]

#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000UL)

Definition at line 942 of file stm32f407xx.h.

◆ TIM14_BASE [2/5]

#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000UL)

Definition at line 1152 of file stm32f469xx.h.

◆ TIM14_BASE [3/5]

#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000UL)

Definition at line 1405 of file stm32f769xx.h.

◆ TIM14_BASE [4/5]

#define TIM14_BASE   (D2_APB1PERIPH_BASE + 0x2000UL)

Definition at line 2261 of file stm32h747xx.h.

◆ TIM14_BASE [5/5]

#define TIM14_BASE   (D2_APB1PERIPH_BASE + 0x2000UL)

Definition at line 2315 of file stm32h735xx.h.

◆ TIM15_BASE [1/2]

#define TIM15_BASE   (D2_APB2PERIPH_BASE + 0x4000UL)

Definition at line 2299 of file stm32h747xx.h.

◆ TIM15_BASE [2/2]

#define TIM15_BASE   (D2_APB2PERIPH_BASE + 0x4000UL)

Definition at line 2358 of file stm32h735xx.h.

◆ TIM16_BASE [1/2]

#define TIM16_BASE   (D2_APB2PERIPH_BASE + 0x4400UL)

Definition at line 2300 of file stm32h747xx.h.

◆ TIM16_BASE [2/2]

#define TIM16_BASE   (D2_APB2PERIPH_BASE + 0x4400UL)

Definition at line 2359 of file stm32h735xx.h.

◆ TIM17_BASE [1/2]

#define TIM17_BASE   (D2_APB2PERIPH_BASE + 0x4800UL)

Definition at line 2301 of file stm32h747xx.h.

◆ TIM17_BASE [2/2]

#define TIM17_BASE   (D2_APB2PERIPH_BASE + 0x4800UL)

Definition at line 2360 of file stm32h735xx.h.

◆ TIM1_BASE [1/6]

#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000UL)

Definition at line 676 of file stm32f411xe.h.

◆ TIM1_BASE [2/6]

#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000UL)

Definition at line 963 of file stm32f407xx.h.

◆ TIM1_BASE [3/6]

#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000UL)

Definition at line 1175 of file stm32f469xx.h.

◆ TIM1_BASE [4/6]

#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000UL)

Definition at line 1431 of file stm32f769xx.h.

◆ TIM1_BASE [5/6]

#define TIM1_BASE   (D2_APB2PERIPH_BASE + 0x0000UL)

Definition at line 2293 of file stm32h747xx.h.

◆ TIM1_BASE [6/6]

#define TIM1_BASE   (D2_APB2PERIPH_BASE + 0x0000UL)

Definition at line 2350 of file stm32h735xx.h.

◆ TIM23_BASE

#define TIM23_BASE   (D2_APB1PERIPH_BASE + 0xE000UL)

Definition at line 2345 of file stm32h735xx.h.

◆ TIM24_BASE

#define TIM24_BASE   (D2_APB1PERIPH_BASE + 0xE400UL)

D2_APB2PERIPH peripherals

Definition at line 2346 of file stm32h735xx.h.

◆ TIM2_BASE [1/6]

#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000UL)

Definition at line 658 of file stm32f411xe.h.

◆ TIM2_BASE [2/6]

#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000UL)

Definition at line 934 of file stm32f407xx.h.

◆ TIM2_BASE [3/6]

#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000UL)

Definition at line 1144 of file stm32f469xx.h.

◆ TIM2_BASE [4/6]

#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000UL)

Definition at line 1397 of file stm32f769xx.h.

◆ TIM2_BASE [5/6]

#define TIM2_BASE   (D2_APB1PERIPH_BASE + 0x0000UL)

Definition at line 2253 of file stm32h747xx.h.

◆ TIM2_BASE [6/6]

#define TIM2_BASE   (D2_APB1PERIPH_BASE + 0x0000UL)

Definition at line 2307 of file stm32h735xx.h.

◆ TIM3_BASE [1/6]

#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400UL)

Definition at line 659 of file stm32f411xe.h.

◆ TIM3_BASE [2/6]

#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400UL)

Definition at line 935 of file stm32f407xx.h.

◆ TIM3_BASE [3/6]

#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400UL)

Definition at line 1145 of file stm32f469xx.h.

◆ TIM3_BASE [4/6]

#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400UL)

Definition at line 1398 of file stm32f769xx.h.

◆ TIM3_BASE [5/6]

#define TIM3_BASE   (D2_APB1PERIPH_BASE + 0x0400UL)

Definition at line 2254 of file stm32h747xx.h.

◆ TIM3_BASE [6/6]

#define TIM3_BASE   (D2_APB1PERIPH_BASE + 0x0400UL)

Definition at line 2308 of file stm32h735xx.h.

◆ TIM4_BASE [1/6]

#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800UL)

Definition at line 660 of file stm32f411xe.h.

◆ TIM4_BASE [2/6]

#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800UL)

Definition at line 936 of file stm32f407xx.h.

◆ TIM4_BASE [3/6]

#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800UL)

Definition at line 1146 of file stm32f469xx.h.

◆ TIM4_BASE [4/6]

#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800UL)

Definition at line 1399 of file stm32f769xx.h.

◆ TIM4_BASE [5/6]

#define TIM4_BASE   (D2_APB1PERIPH_BASE + 0x0800UL)

Definition at line 2255 of file stm32h747xx.h.

◆ TIM4_BASE [6/6]

#define TIM4_BASE   (D2_APB1PERIPH_BASE + 0x0800UL)

Definition at line 2309 of file stm32h735xx.h.

◆ TIM5_BASE [1/6]

#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00UL)

Definition at line 661 of file stm32f411xe.h.

◆ TIM5_BASE [2/6]

#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00UL)

Definition at line 937 of file stm32f407xx.h.

◆ TIM5_BASE [3/6]

#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00UL)

Definition at line 1147 of file stm32f469xx.h.

◆ TIM5_BASE [4/6]

#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00UL)

Definition at line 1400 of file stm32f769xx.h.

◆ TIM5_BASE [5/6]

#define TIM5_BASE   (D2_APB1PERIPH_BASE + 0x0C00UL)

Definition at line 2256 of file stm32h747xx.h.

◆ TIM5_BASE [6/6]

#define TIM5_BASE   (D2_APB1PERIPH_BASE + 0x0C00UL)

Definition at line 2310 of file stm32h735xx.h.

◆ TIM6_BASE [1/5]

#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000UL)

Definition at line 938 of file stm32f407xx.h.

◆ TIM6_BASE [2/5]

#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000UL)

Definition at line 1148 of file stm32f469xx.h.

◆ TIM6_BASE [3/5]

#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000UL)

Definition at line 1401 of file stm32f769xx.h.

◆ TIM6_BASE [4/5]

#define TIM6_BASE   (D2_APB1PERIPH_BASE + 0x1000UL)

Definition at line 2257 of file stm32h747xx.h.

◆ TIM6_BASE [5/5]

#define TIM6_BASE   (D2_APB1PERIPH_BASE + 0x1000UL)

Definition at line 2311 of file stm32h735xx.h.

◆ TIM7_BASE [1/5]

#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400UL)

Definition at line 939 of file stm32f407xx.h.

◆ TIM7_BASE [2/5]

#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400UL)

Definition at line 1149 of file stm32f469xx.h.

◆ TIM7_BASE [3/5]

#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400UL)

Definition at line 1402 of file stm32f769xx.h.

◆ TIM7_BASE [4/5]

#define TIM7_BASE   (D2_APB1PERIPH_BASE + 0x1400UL)

Definition at line 2258 of file stm32h747xx.h.

◆ TIM7_BASE [5/5]

#define TIM7_BASE   (D2_APB1PERIPH_BASE + 0x1400UL)

Definition at line 2312 of file stm32h735xx.h.

◆ TIM8_BASE [1/5]

#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400UL)

Definition at line 964 of file stm32f407xx.h.

◆ TIM8_BASE [2/5]

#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400UL)

Definition at line 1176 of file stm32f469xx.h.

◆ TIM8_BASE [3/5]

#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400UL)

Definition at line 1432 of file stm32f769xx.h.

◆ TIM8_BASE [4/5]

#define TIM8_BASE   (D2_APB2PERIPH_BASE + 0x0400UL)

Definition at line 2294 of file stm32h747xx.h.

◆ TIM8_BASE [5/5]

#define TIM8_BASE   (D2_APB2PERIPH_BASE + 0x0400UL)

Definition at line 2351 of file stm32h735xx.h.

◆ TIM9_BASE [1/4]

#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000UL)

Definition at line 688 of file stm32f411xe.h.

◆ TIM9_BASE [2/4]

#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000UL)

Definition at line 977 of file stm32f407xx.h.

◆ TIM9_BASE [3/4]

#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000UL)

Definition at line 1190 of file stm32f469xx.h.

◆ TIM9_BASE [4/4]

#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000UL)

Definition at line 1445 of file stm32f769xx.h.

◆ UART4_BASE [1/5]

#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00UL)

Definition at line 952 of file stm32f407xx.h.

◆ UART4_BASE [2/5]

#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00UL)

Definition at line 1162 of file stm32f469xx.h.

◆ UART4_BASE [3/5]

#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00UL)

Definition at line 1416 of file stm32f769xx.h.

◆ UART4_BASE [4/5]

#define UART4_BASE   (D2_APB1PERIPH_BASE + 0x4C00UL)

Definition at line 2271 of file stm32h747xx.h.

◆ UART4_BASE [5/5]

#define UART4_BASE   (D2_APB1PERIPH_BASE + 0x4C00UL)

Definition at line 2324 of file stm32h735xx.h.

◆ UART5_BASE [1/5]

#define UART5_BASE   (APB1PERIPH_BASE + 0x5000UL)

Definition at line 953 of file stm32f407xx.h.

◆ UART5_BASE [2/5]

#define UART5_BASE   (APB1PERIPH_BASE + 0x5000UL)

Definition at line 1163 of file stm32f469xx.h.

◆ UART5_BASE [3/5]

#define UART5_BASE   (APB1PERIPH_BASE + 0x5000UL)

Definition at line 1417 of file stm32f769xx.h.

◆ UART5_BASE [4/5]

#define UART5_BASE   (D2_APB1PERIPH_BASE + 0x5000UL)

Definition at line 2272 of file stm32h747xx.h.

◆ UART5_BASE [5/5]

#define UART5_BASE   (D2_APB1PERIPH_BASE + 0x5000UL)

Definition at line 2325 of file stm32h735xx.h.

◆ UART7_BASE [1/4]

#define UART7_BASE   (APB1PERIPH_BASE + 0x7800UL)

Definition at line 1171 of file stm32f469xx.h.

◆ UART7_BASE [2/4]

#define UART7_BASE   (APB1PERIPH_BASE + 0x7800UL)

Definition at line 1427 of file stm32f769xx.h.

◆ UART7_BASE [3/4]

#define UART7_BASE   (D2_APB1PERIPH_BASE + 0x7800UL)

Definition at line 2278 of file stm32h747xx.h.

◆ UART7_BASE [4/4]

#define UART7_BASE   (D2_APB1PERIPH_BASE + 0x7800UL)

Definition at line 2332 of file stm32h735xx.h.

◆ UART8_BASE [1/4]

#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00UL)

APB2 peripherals

Definition at line 1172 of file stm32f469xx.h.

◆ UART8_BASE [2/4]

#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00UL)

APB2 peripherals

Definition at line 1428 of file stm32f769xx.h.

◆ UART8_BASE [3/4]

#define UART8_BASE   (D2_APB1PERIPH_BASE + 0x7C00UL)

Definition at line 2279 of file stm32h747xx.h.

◆ UART8_BASE [4/4]

#define UART8_BASE   (D2_APB1PERIPH_BASE + 0x7C00UL)

Definition at line 2333 of file stm32h735xx.h.

◆ UART9_BASE

#define UART9_BASE   (D2_APB2PERIPH_BASE + 0x1800UL)

Definition at line 2354 of file stm32h735xx.h.

◆ UID_BASE [1/6]

#define UID_BASE   0x1FFF7A10UL

Unique device ID register base address

Definition at line 741 of file stm32f411xe.h.

◆ UID_BASE [2/6]

#define UID_BASE   0x1FFF7A10UL

Unique device ID register base address

Definition at line 1048 of file stm32f407xx.h.

◆ UID_BASE [3/6]

#define UID_BASE   0x1FFF7A10UL

Unique device ID register base address

Definition at line 1273 of file stm32f469xx.h.

◆ UID_BASE [4/6]

#define UID_BASE   0x1FF0F420UL

Unique device ID register base address

Definition at line 1489 of file stm32f769xx.h.

◆ UID_BASE [5/6]

#define UID_BASE   (0x1FF1E800UL)

Unique device ID register base address

Definition at line 2149 of file stm32h747xx.h.

◆ UID_BASE [6/6]

#define UID_BASE   (0x1FF1E800UL)

Unique device ID register base address

Definition at line 2190 of file stm32h735xx.h.

◆ USART10_BASE

#define USART10_BASE   (D2_APB2PERIPH_BASE + 0x1C00UL)

Definition at line 2355 of file stm32h735xx.h.

◆ USART1_BASE [1/6]

#define USART1_BASE   (APB2PERIPH_BASE + 0x1000UL)

Definition at line 677 of file stm32f411xe.h.

◆ USART1_BASE [2/6]

#define USART1_BASE   (APB2PERIPH_BASE + 0x1000UL)

Definition at line 965 of file stm32f407xx.h.

◆ USART1_BASE [3/6]

#define USART1_BASE   (APB2PERIPH_BASE + 0x1000UL)

Definition at line 1177 of file stm32f469xx.h.

◆ USART1_BASE [4/6]

#define USART1_BASE   (APB2PERIPH_BASE + 0x1000UL)

Definition at line 1433 of file stm32f769xx.h.

◆ USART1_BASE [5/6]

#define USART1_BASE   (D2_APB2PERIPH_BASE + 0x1000UL)

Definition at line 2295 of file stm32h747xx.h.

◆ USART1_BASE [6/6]

#define USART1_BASE   (D2_APB2PERIPH_BASE + 0x1000UL)

Definition at line 2352 of file stm32h735xx.h.

◆ USART2_BASE [1/6]

#define USART2_BASE   (APB1PERIPH_BASE + 0x4400UL)

Definition at line 669 of file stm32f411xe.h.

◆ USART2_BASE [2/6]

#define USART2_BASE   (APB1PERIPH_BASE + 0x4400UL)

Definition at line 950 of file stm32f407xx.h.

◆ USART2_BASE [3/6]

#define USART2_BASE   (APB1PERIPH_BASE + 0x4400UL)

Definition at line 1160 of file stm32f469xx.h.

◆ USART2_BASE [4/6]

#define USART2_BASE   (APB1PERIPH_BASE + 0x4400UL)

Definition at line 1414 of file stm32f769xx.h.

◆ USART2_BASE [5/6]

#define USART2_BASE   (D2_APB1PERIPH_BASE + 0x4400UL)

Definition at line 2269 of file stm32h747xx.h.

◆ USART2_BASE [6/6]

#define USART2_BASE   (D2_APB1PERIPH_BASE + 0x4400UL)

Definition at line 2322 of file stm32h735xx.h.

◆ USART3_BASE [1/5]

#define USART3_BASE   (APB1PERIPH_BASE + 0x4800UL)

Definition at line 951 of file stm32f407xx.h.

◆ USART3_BASE [2/5]

#define USART3_BASE   (APB1PERIPH_BASE + 0x4800UL)

Definition at line 1161 of file stm32f469xx.h.

◆ USART3_BASE [3/5]

#define USART3_BASE   (APB1PERIPH_BASE + 0x4800UL)

Definition at line 1415 of file stm32f769xx.h.

◆ USART3_BASE [4/5]

#define USART3_BASE   (D2_APB1PERIPH_BASE + 0x4800UL)

Definition at line 2270 of file stm32h747xx.h.

◆ USART3_BASE [5/5]

#define USART3_BASE   (D2_APB1PERIPH_BASE + 0x4800UL)

Definition at line 2323 of file stm32h735xx.h.

◆ USART6_BASE [1/6]

#define USART6_BASE   (APB2PERIPH_BASE + 0x1400UL)

Definition at line 678 of file stm32f411xe.h.

◆ USART6_BASE [2/6]

#define USART6_BASE   (APB2PERIPH_BASE + 0x1400UL)

Definition at line 966 of file stm32f407xx.h.

◆ USART6_BASE [3/6]

#define USART6_BASE   (APB2PERIPH_BASE + 0x1400UL)

Definition at line 1178 of file stm32f469xx.h.

◆ USART6_BASE [4/6]

#define USART6_BASE   (APB2PERIPH_BASE + 0x1400UL)

Definition at line 1434 of file stm32f769xx.h.

◆ USART6_BASE [5/6]

#define USART6_BASE   (D2_APB2PERIPH_BASE + 0x1400UL)

Definition at line 2296 of file stm32h747xx.h.

◆ USART6_BASE [6/6]

#define USART6_BASE   (D2_APB2PERIPH_BASE + 0x1400UL)

Definition at line 2353 of file stm32h735xx.h.

◆ USB1_OTG_HS_PERIPH_BASE [1/2]

#define USB1_OTG_HS_PERIPH_BASE   (0x40040000UL)

Definition at line 2198 of file stm32h747xx.h.

◆ USB1_OTG_HS_PERIPH_BASE [2/2]

#define USB1_OTG_HS_PERIPH_BASE   (0x40040000UL)

Definition at line 2251 of file stm32h735xx.h.

◆ USB2_OTG_FS_PERIPH_BASE

#define USB2_OTG_FS_PERIPH_BASE   (0x40080000UL)

Definition at line 2199 of file stm32h747xx.h.

◆ USB_OTG_DEVICE_BASE [1/6]

#define USB_OTG_DEVICE_BASE   0x800UL

Definition at line 729 of file stm32f411xe.h.

◆ USB_OTG_DEVICE_BASE [2/6]

#define USB_OTG_DEVICE_BASE   0x800UL

Definition at line 1036 of file stm32f407xx.h.

◆ USB_OTG_DEVICE_BASE [3/6]

#define USB_OTG_DEVICE_BASE   0x800UL

Definition at line 1261 of file stm32f469xx.h.

◆ USB_OTG_DEVICE_BASE [4/6]

#define USB_OTG_DEVICE_BASE   0x0800UL

Definition at line 1537 of file stm32f769xx.h.

◆ USB_OTG_DEVICE_BASE [5/6]

#define USB_OTG_DEVICE_BASE   (0x800UL)

Definition at line 2201 of file stm32h747xx.h.

◆ USB_OTG_DEVICE_BASE [6/6]

#define USB_OTG_DEVICE_BASE   (0x800UL)

Definition at line 2253 of file stm32h735xx.h.

◆ USB_OTG_EP_REG_SIZE [1/6]

#define USB_OTG_EP_REG_SIZE   0x20UL

Definition at line 732 of file stm32f411xe.h.

◆ USB_OTG_EP_REG_SIZE [2/6]

#define USB_OTG_EP_REG_SIZE   0x20UL

Definition at line 1039 of file stm32f407xx.h.

◆ USB_OTG_EP_REG_SIZE [3/6]

#define USB_OTG_EP_REG_SIZE   0x20UL

Definition at line 1264 of file stm32f469xx.h.

◆ USB_OTG_EP_REG_SIZE [4/6]

#define USB_OTG_EP_REG_SIZE   0x0020UL

Definition at line 1540 of file stm32f769xx.h.

◆ USB_OTG_EP_REG_SIZE [5/6]

#define USB_OTG_EP_REG_SIZE   (0x20UL)

Definition at line 2204 of file stm32h747xx.h.

◆ USB_OTG_EP_REG_SIZE [6/6]

#define USB_OTG_EP_REG_SIZE   (0x20UL)

Definition at line 2256 of file stm32h735xx.h.

◆ USB_OTG_FIFO_BASE [1/6]

#define USB_OTG_FIFO_BASE   0x1000UL

Definition at line 738 of file stm32f411xe.h.

◆ USB_OTG_FIFO_BASE [2/6]

#define USB_OTG_FIFO_BASE   0x1000UL

Definition at line 1045 of file stm32f407xx.h.

◆ USB_OTG_FIFO_BASE [3/6]

#define USB_OTG_FIFO_BASE   0x1000UL

Definition at line 1270 of file stm32f469xx.h.

◆ USB_OTG_FIFO_BASE [4/6]

#define USB_OTG_FIFO_BASE   0x1000UL

Definition at line 1546 of file stm32f769xx.h.

◆ USB_OTG_FIFO_BASE [5/6]

#define USB_OTG_FIFO_BASE   (0x1000UL)

Definition at line 2210 of file stm32h747xx.h.

◆ USB_OTG_FIFO_BASE [6/6]

#define USB_OTG_FIFO_BASE   (0x1000UL)

Definition at line 2262 of file stm32h735xx.h.

◆ USB_OTG_FIFO_SIZE [1/6]

#define USB_OTG_FIFO_SIZE   0x1000UL

Definition at line 739 of file stm32f411xe.h.

◆ USB_OTG_FIFO_SIZE [2/6]

#define USB_OTG_FIFO_SIZE   0x1000UL

Definition at line 1046 of file stm32f407xx.h.

◆ USB_OTG_FIFO_SIZE [3/6]

#define USB_OTG_FIFO_SIZE   0x1000UL

Definition at line 1271 of file stm32f469xx.h.

◆ USB_OTG_FIFO_SIZE [4/6]

#define USB_OTG_FIFO_SIZE   0x1000UL

Definition at line 1547 of file stm32f769xx.h.

◆ USB_OTG_FIFO_SIZE [5/6]

#define USB_OTG_FIFO_SIZE   (0x1000UL)

D2_AHB2PERIPH peripherals

Definition at line 2211 of file stm32h747xx.h.

◆ USB_OTG_FIFO_SIZE [6/6]

#define USB_OTG_FIFO_SIZE   (0x1000UL)

D2_AHB2PERIPH peripherals

Definition at line 2263 of file stm32h735xx.h.

◆ USB_OTG_FS_PERIPH_BASE [1/4]

#define USB_OTG_FS_PERIPH_BASE   0x50000000UL

Definition at line 726 of file stm32f411xe.h.

◆ USB_OTG_FS_PERIPH_BASE [2/4]

#define USB_OTG_FS_PERIPH_BASE   0x50000000UL

Definition at line 1033 of file stm32f407xx.h.

◆ USB_OTG_FS_PERIPH_BASE [3/4]

#define USB_OTG_FS_PERIPH_BASE   0x50000000UL

Definition at line 1258 of file stm32f469xx.h.

◆ USB_OTG_FS_PERIPH_BASE [4/4]

#define USB_OTG_FS_PERIPH_BASE   0x50000000UL

Definition at line 1534 of file stm32f769xx.h.

◆ USB_OTG_GLOBAL_BASE [1/6]

#define USB_OTG_GLOBAL_BASE   0x000UL

Definition at line 728 of file stm32f411xe.h.

◆ USB_OTG_GLOBAL_BASE [2/6]

#define USB_OTG_GLOBAL_BASE   0x000UL

Definition at line 1035 of file stm32f407xx.h.

◆ USB_OTG_GLOBAL_BASE [3/6]

#define USB_OTG_GLOBAL_BASE   0x000UL

Definition at line 1260 of file stm32f469xx.h.

◆ USB_OTG_GLOBAL_BASE [4/6]

#define USB_OTG_GLOBAL_BASE   0x0000UL

Definition at line 1536 of file stm32f769xx.h.

◆ USB_OTG_GLOBAL_BASE [5/6]

#define USB_OTG_GLOBAL_BASE   (0x000UL)

Definition at line 2200 of file stm32h747xx.h.

◆ USB_OTG_GLOBAL_BASE [6/6]

#define USB_OTG_GLOBAL_BASE   (0x000UL)

Definition at line 2252 of file stm32h735xx.h.

◆ USB_OTG_HOST_BASE [1/6]

#define USB_OTG_HOST_BASE   0x400UL

Definition at line 733 of file stm32f411xe.h.

◆ USB_OTG_HOST_BASE [2/6]

#define USB_OTG_HOST_BASE   0x400UL

Definition at line 1040 of file stm32f407xx.h.

◆ USB_OTG_HOST_BASE [3/6]

#define USB_OTG_HOST_BASE   0x400UL

Definition at line 1265 of file stm32f469xx.h.

◆ USB_OTG_HOST_BASE [4/6]

#define USB_OTG_HOST_BASE   0x0400UL

Definition at line 1541 of file stm32f769xx.h.

◆ USB_OTG_HOST_BASE [5/6]

#define USB_OTG_HOST_BASE   (0x400UL)

Definition at line 2205 of file stm32h747xx.h.

◆ USB_OTG_HOST_BASE [6/6]

#define USB_OTG_HOST_BASE   (0x400UL)

Definition at line 2257 of file stm32h735xx.h.

◆ USB_OTG_HOST_CHANNEL_BASE [1/6]

#define USB_OTG_HOST_CHANNEL_BASE   0x500UL

Definition at line 735 of file stm32f411xe.h.

◆ USB_OTG_HOST_CHANNEL_BASE [2/6]

#define USB_OTG_HOST_CHANNEL_BASE   0x500UL

Definition at line 1042 of file stm32f407xx.h.

◆ USB_OTG_HOST_CHANNEL_BASE [3/6]

#define USB_OTG_HOST_CHANNEL_BASE   0x500UL

Definition at line 1267 of file stm32f469xx.h.

◆ USB_OTG_HOST_CHANNEL_BASE [4/6]

#define USB_OTG_HOST_CHANNEL_BASE   0x0500UL

Definition at line 1543 of file stm32f769xx.h.

◆ USB_OTG_HOST_CHANNEL_BASE [5/6]

#define USB_OTG_HOST_CHANNEL_BASE   (0x500UL)

Definition at line 2207 of file stm32h747xx.h.

◆ USB_OTG_HOST_CHANNEL_BASE [6/6]

#define USB_OTG_HOST_CHANNEL_BASE   (0x500UL)

Definition at line 2259 of file stm32h735xx.h.

◆ USB_OTG_HOST_CHANNEL_SIZE [1/6]

#define USB_OTG_HOST_CHANNEL_SIZE   0x20UL

Definition at line 736 of file stm32f411xe.h.

◆ USB_OTG_HOST_CHANNEL_SIZE [2/6]

#define USB_OTG_HOST_CHANNEL_SIZE   0x20UL

Definition at line 1043 of file stm32f407xx.h.

◆ USB_OTG_HOST_CHANNEL_SIZE [3/6]

#define USB_OTG_HOST_CHANNEL_SIZE   0x20UL

Definition at line 1268 of file stm32f469xx.h.

◆ USB_OTG_HOST_CHANNEL_SIZE [4/6]

#define USB_OTG_HOST_CHANNEL_SIZE   0x0020UL

Definition at line 1544 of file stm32f769xx.h.

◆ USB_OTG_HOST_CHANNEL_SIZE [5/6]

#define USB_OTG_HOST_CHANNEL_SIZE   (0x20UL)

Definition at line 2208 of file stm32h747xx.h.

◆ USB_OTG_HOST_CHANNEL_SIZE [6/6]

#define USB_OTG_HOST_CHANNEL_SIZE   (0x20UL)

Definition at line 2260 of file stm32h735xx.h.

◆ USB_OTG_HOST_PORT_BASE [1/6]

#define USB_OTG_HOST_PORT_BASE   0x440UL

Definition at line 734 of file stm32f411xe.h.

◆ USB_OTG_HOST_PORT_BASE [2/6]

#define USB_OTG_HOST_PORT_BASE   0x440UL

Definition at line 1041 of file stm32f407xx.h.

◆ USB_OTG_HOST_PORT_BASE [3/6]

#define USB_OTG_HOST_PORT_BASE   0x440UL

Definition at line 1266 of file stm32f469xx.h.

◆ USB_OTG_HOST_PORT_BASE [4/6]

#define USB_OTG_HOST_PORT_BASE   0x0440UL

Definition at line 1542 of file stm32f769xx.h.

◆ USB_OTG_HOST_PORT_BASE [5/6]

#define USB_OTG_HOST_PORT_BASE   (0x440UL)

Definition at line 2206 of file stm32h747xx.h.

◆ USB_OTG_HOST_PORT_BASE [6/6]

#define USB_OTG_HOST_PORT_BASE   (0x440UL)

Definition at line 2258 of file stm32h735xx.h.

◆ USB_OTG_HS_PERIPH_BASE [1/3]

#define USB_OTG_HS_PERIPH_BASE   0x40040000UL

Definition at line 1032 of file stm32f407xx.h.

◆ USB_OTG_HS_PERIPH_BASE [2/3]

#define USB_OTG_HS_PERIPH_BASE   0x40040000UL

Definition at line 1257 of file stm32f469xx.h.

◆ USB_OTG_HS_PERIPH_BASE [3/3]

#define USB_OTG_HS_PERIPH_BASE   0x40040000UL

Definition at line 1533 of file stm32f769xx.h.

◆ USB_OTG_IN_ENDPOINT_BASE [1/6]

#define USB_OTG_IN_ENDPOINT_BASE   0x900UL

Definition at line 730 of file stm32f411xe.h.

◆ USB_OTG_IN_ENDPOINT_BASE [2/6]

#define USB_OTG_IN_ENDPOINT_BASE   0x900UL

Definition at line 1037 of file stm32f407xx.h.

◆ USB_OTG_IN_ENDPOINT_BASE [3/6]

#define USB_OTG_IN_ENDPOINT_BASE   0x900UL

Definition at line 1262 of file stm32f469xx.h.

◆ USB_OTG_IN_ENDPOINT_BASE [4/6]

#define USB_OTG_IN_ENDPOINT_BASE   0x0900UL

Definition at line 1538 of file stm32f769xx.h.

◆ USB_OTG_IN_ENDPOINT_BASE [5/6]

#define USB_OTG_IN_ENDPOINT_BASE   (0x900UL)

Definition at line 2202 of file stm32h747xx.h.

◆ USB_OTG_IN_ENDPOINT_BASE [6/6]

#define USB_OTG_IN_ENDPOINT_BASE   (0x900UL)

Definition at line 2254 of file stm32h735xx.h.

◆ USB_OTG_OUT_ENDPOINT_BASE [1/6]

#define USB_OTG_OUT_ENDPOINT_BASE   0xB00UL

Definition at line 731 of file stm32f411xe.h.

◆ USB_OTG_OUT_ENDPOINT_BASE [2/6]

#define USB_OTG_OUT_ENDPOINT_BASE   0xB00UL

Definition at line 1038 of file stm32f407xx.h.

◆ USB_OTG_OUT_ENDPOINT_BASE [3/6]

#define USB_OTG_OUT_ENDPOINT_BASE   0xB00UL

Definition at line 1263 of file stm32f469xx.h.

◆ USB_OTG_OUT_ENDPOINT_BASE [4/6]

#define USB_OTG_OUT_ENDPOINT_BASE   0x0B00UL

Definition at line 1539 of file stm32f769xx.h.

◆ USB_OTG_OUT_ENDPOINT_BASE [5/6]

#define USB_OTG_OUT_ENDPOINT_BASE   (0xB00UL)

Definition at line 2203 of file stm32h747xx.h.

◆ USB_OTG_OUT_ENDPOINT_BASE [6/6]

#define USB_OTG_OUT_ENDPOINT_BASE   (0xB00UL)

Definition at line 2255 of file stm32h735xx.h.

◆ USB_OTG_PCGCCTL_BASE [1/6]

#define USB_OTG_PCGCCTL_BASE   0xE00UL

Definition at line 737 of file stm32f411xe.h.

◆ USB_OTG_PCGCCTL_BASE [2/6]

#define USB_OTG_PCGCCTL_BASE   0xE00UL

Definition at line 1044 of file stm32f407xx.h.

◆ USB_OTG_PCGCCTL_BASE [3/6]

#define USB_OTG_PCGCCTL_BASE   0xE00UL

Definition at line 1269 of file stm32f469xx.h.

◆ USB_OTG_PCGCCTL_BASE [4/6]

#define USB_OTG_PCGCCTL_BASE   0x0E00UL

Definition at line 1545 of file stm32f769xx.h.

◆ USB_OTG_PCGCCTL_BASE [5/6]

#define USB_OTG_PCGCCTL_BASE   (0xE00UL)

Definition at line 2209 of file stm32h747xx.h.

◆ USB_OTG_PCGCCTL_BASE [6/6]

#define USB_OTG_PCGCCTL_BASE   (0xE00UL)

Definition at line 2261 of file stm32h735xx.h.

◆ VREFBUF_BASE [1/2]

#define VREFBUF_BASE   (D3_APB1PERIPH_BASE + 0x3C00UL)

Definition at line 2349 of file stm32h747xx.h.

◆ VREFBUF_BASE [2/2]

#define VREFBUF_BASE   (D3_APB1PERIPH_BASE + 0x3C00UL)

Definition at line 2395 of file stm32h735xx.h.

◆ WWDG1_BASE [1/2]

#define WWDG1_BASE   (D1_APB1PERIPH_BASE + 0x3000UL)

D2_APB1PERIPH peripherals

Definition at line 2250 of file stm32h747xx.h.

◆ WWDG1_BASE [2/2]

#define WWDG1_BASE   (D1_APB1PERIPH_BASE + 0x3000UL)

D2_APB1PERIPH peripherals

Definition at line 2304 of file stm32h735xx.h.

◆ WWDG2_BASE

#define WWDG2_BASE   (D2_APB1PERIPH_BASE + 0x2C00UL)

Definition at line 2264 of file stm32h747xx.h.

◆ WWDG_BASE [1/4]

#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00UL)

Definition at line 663 of file stm32f411xe.h.

◆ WWDG_BASE [2/4]

#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00UL)

Definition at line 944 of file stm32f407xx.h.

◆ WWDG_BASE [3/4]

#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00UL)

Definition at line 1154 of file stm32f469xx.h.

◆ WWDG_BASE [4/4]

#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00UL)

Definition at line 1408 of file stm32f769xx.h.


picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:15:11