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103 char **list_part, **list_byte;
104 int size_part, size_byte, size_data, size_insn;
105 int i,
count, count_noreg;
109 char **offset_opcode;
110 int size_offset_opcode;
114 list_part =
split(
line,
" = ", &size_part);
115 offset_opcode =
split(list_part[0],
": ", &size_offset_opcode);
116 if (size_offset_opcode > 1) {
117 offset = (
unsigned int)strtol(offset_opcode[0], NULL, 16);
118 list_byte =
split(offset_opcode[1],
",", &size_byte);
121 list_byte =
split(offset_opcode[0],
",", &size_byte);
124 code = (
unsigned char *)malloc(size_byte *
sizeof(
char));
125 for (
i = 0;
i < size_byte; ++
i) {
126 code[
i] = (
unsigned char)strtol(list_byte[
i], NULL, 16);
131 fprintf(
stderr,
"[ ERROR ] --- %s --- Failed to disassemble given code!\n", list_part[0]);
133 free_strs(offset_opcode, size_offset_opcode);
136 _fail(__FILE__, __LINE__);
139 fprintf(
stderr,
"[ ERROR ] --- %s --- Multiple instructions(%d) disassembling doesn't support!\n", list_part[0],
count);
141 free_strs(offset_opcode, size_offset_opcode);
144 _fail(__FILE__, __LINE__);
147 for (
p = list_part[1]; *
p; ++
p) *
p = tolower(*
p);
148 for (
p = list_part[1]; *
p; ++
p)
149 if (*
p ==
'\t') *
p =
' ';
151 strcpy(tmp_mc, list_part[1]);
155 strcpy(
tmp, insn[0].mnemonic);
156 if (strlen(insn[0].op_str) > 0) {
157 tmp[strlen(insn[0].mnemonic)] =
' ';
158 strcpy(
tmp + strlen(insn[0].mnemonic) + 1, insn[0].op_str);
168 strcpy(tmp_noreg, insn[0].mnemonic);
169 if (strlen(insn[0].op_str) > 0) {
170 tmp_noreg[strlen(insn[0].mnemonic)] =
' ';
171 strcpy(tmp_noreg + strlen(insn[0].mnemonic) + 1, insn[0].op_str);
178 if (strcmp(
tmp, tmp_mc) && strcmp(tmp_noreg, tmp_mc)) {
179 fprintf(
stderr,
"[ ERROR ] --- %s --- \"%s\" != \"%s\" ( \"%s\" != \"%s\" and \"%s\" != \"%s\" )\n", list_part[0],
origin, list_part[1],
tmp, tmp_mc, tmp_noreg, tmp_mc);
181 free_strs(offset_opcode, size_offset_opcode);
185 _fail(__FILE__, __LINE__);
190 }
else if (strcmp(
tmp, tmp_mc)) {
191 fprintf(
stderr,
"[ ERROR ] --- %s --- \"%s\" != \"%s\" ( \"%s\" != \"%s\" )\n", list_part[0],
origin, list_part[1],
tmp, tmp_mc);
193 free_strs(offset_opcode, size_offset_opcode);
197 _fail(__FILE__, __LINE__);
201 free_strs(offset_opcode, size_offset_opcode);
222 if (!strcmp(s,
d[
i].
str))
278 char **list_part, **list_byte, **list_part_cs_result, **list_part_issue_result;
279 int size_part, size_byte, size_part_cs_result, size_part_issue_result;
284 char *cs_result, *
tmp, *
p;
285 char **offset_opcode;
286 int size_offset_opcode;
289 cs_result = (
char *)malloc(
sizeof(
char));
292 list_part =
split(
line,
" == ", &size_part);
294 offset_opcode =
split(list_part[0],
": ", &size_offset_opcode);
295 if (size_offset_opcode > 1) {
296 offset = (
unsigned int)strtol(offset_opcode[0], NULL, 16);
297 list_byte =
split(offset_opcode[1],
",", &size_byte);
300 list_byte =
split(offset_opcode[0],
",", &size_byte);
303 code = (
unsigned char *)malloc(
sizeof(
char) * size_byte);
304 for (
i = 0;
i < size_byte; ++
i) {
305 code[
i] = (
unsigned char)strtol(list_byte[
i], NULL, 16);
310 tmp = (
char *)malloc(strlen(insn[
i].mnemonic) + strlen(insn[
i].op_str) + 100);
311 strcpy(
tmp, insn[
i].mnemonic);
312 if (strlen(insn[
i].op_str) > 0) {
313 tmp[strlen(insn[
i].mnemonic)] =
' ';
314 strcpy(
tmp + strlen(insn[
i].mnemonic) + 1, insn[
i].op_str);
325 if (insn->detail->groups_count) {
326 add_str(&cs_result,
" ; Groups: ");
327 for (j = 0; j < insn->detail->groups_count; j++) {
336 for (
p = list_part[1]; *
p; ++
p)
if (*
p ==
'\t') *
p =
' ';
337 list_part_issue_result =
split(list_part[1],
" ; ", &size_part_issue_result);
339 for (
i = 0;
i < size_part_issue_result; ++
i) {
343 tmptmp = (
char *)malloc(
sizeof(
char));
345 add_str(&tmptmp,
"%s", list_part_issue_result[
i]);
348 if ((strstr(cs_result, tmptmp)) == NULL) {
349 fprintf(
stderr,
"[ ERROR ] --- %s --- \"%s\" not in \"%s\"\n", list_part[0], list_part_issue_result[
i], cs_result);
355 free_strs(list_part_issue_result, size_part_issue_result);
357 _fail(__FILE__, __LINE__);
366 free_strs(list_part_issue_result, size_part_issue_result);
@ CS_MODE_MIPS2
Mips II ISA.
int set_function(int arch)
@ CS_OPT_SYNTAX_NOREGNAME
Prints register name with only number (CS_OPT_SYNTAX)
char * get_detail_m680x(csh *handle, cs_mode mode, cs_insn *ins)
@ CS_OPT_SYNTAX
Assembly output syntax.
@ CS_MODE_32
32-bit mode (X86)
@ CS_MODE_M680X_6800
M680X Motorola 6800,6802 mode.
return memset(p, 0, total)
char * get_detail_mos65xx(csh *handle, cs_mode mode, cs_insn *ins)
@ CS_MODE_LITTLE_ENDIAN
little-endian mode (default mode)
void free_strs(char **list_str, int size)
@ CS_MODE_M680X_6805
M680X Motorola/Freescale 6805 mode.
@ CS_ARCH_M68K
68K architecture
@ CS_ARCH_MOS65XX
MOS65XX architecture (including MOS6502)
CAPSTONE_EXPORT size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64_t offset, size_t count, cs_insn **insn)
@ CS_MODE_M680X_CPU12
used on M68HC12/HCS12
@ CS_ARCH_PPC
PowerPC architecture.
@ CS_MODE_M680X_6801
M680X Motorola 6801,6803 mode.
@ CS_OPT_UNSIGNED
print immediate operands in unsigned form
@ CS_OPT_SYNTAX_DEFAULT
Default asm syntax (CS_OPT_SYNTAX).
@ CS_OPT_DETAIL
Break down instruction structure into details.
@ CS_MODE_M68K_060
M68K 68060 mode.
@ CS_OPT_SYNTAX_INTEL
X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX).
@ CS_MODE_M68K_000
M68K 68000 mode.
@ CS_MODE_16
16-bit mode (X86)
@ CS_ARCH_EVM
Ethereum architecture.
@ CS_ARCH_M680X
680X architecture
@ CS_ARCH_TMS320C64X
TMS320C64x architecture.
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_option(csh ud, cs_opt_type type, size_t value)
@ CS_MODE_M68K_010
M68K 68010 mode.
@ CS_MODE_M680X_6808
M680X Motorola/Freescale/NXP 68HC08 mode.
char * get_detail_arm(csh *handle, cs_mode mode, cs_insn *ins)
@ CS_MODE_MICRO
MicroMips mode (MIPS)
char * get_detail_m68k(csh *handle, cs_mode mode, cs_insn *ins)
char * get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins)
void replace_hex(char *src)
@ CS_ARCH_SYSZ
SystemZ architecture.
void test_single_MC(csh *handle, int mc_mode, char *line)
@ CS_MODE_QPX
Quad Processing eXtensions mode (PPC)
@ CS_ARCH_X86
X86 architecture (including x86 & x86-64)
char * get_detail_mips(csh *handle, cs_mode mode, cs_insn *ins)
char * get_detail_ppc(csh *handle, cs_mode mode, cs_insn *ins)
int get_value(single_dict d[], unsigned int size, const char *str)
@ CS_OPT_SYNTAX_ATT
X86 ATT asm syntax (CS_OPT_SYNTAX).
@ CS_OPT_ON
Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA).
@ CS_MODE_M68K_020
M68K 68020 mode.
@ CS_MODE_M68K_040
M68K 68040 mode.
@ CS_MODE_THUMB
ARM's Thumb mode, including Thumb-2.
void add_str(char **src, const char *format,...)
void test_single_issue(csh *handle, cs_mode mode, char *line, int detail)
@ CS_MODE_BIG_ENDIAN
big-endian mode
@ CS_MODE_MIPS32R6
Mips32r6 ISA.
@ CS_OPT_SKIPDATA
Skip data when disassembling. Then engine is in SKIPDATA mode.
@ CS_MODE_M68K_030
M68K 68030 mode.
@ CS_MODE_MCLASS
ARM's Cortex-M series.
char * get_detail_sysz(csh *handle, cs_mode mode, cs_insn *ins)
@ CS_MODE_M680X_6809
M680X Motorola 6809 mode.
@ CS_MODE_M680X_6309
M680X Hitachi 6309 mode.
@ CS_ARCH_SPARC
Sparc architecture.
@ CS_ARCH_MIPS
Mips architecture.
@ CS_MODE_M680X_HCS08
M680X Freescale/NXP HCS08 mode.
char * get_detail_sparc(csh *handle, cs_mode mode, cs_insn *ins)
@ CS_MODE_MIPS64
Mips64 ISA (Mips)
@ CS_MODE_64
64-bit mode (X86, PPC)
@ CS_ARCH_ARM
ARM architecture (including Thumb, Thumb-2)
const CAPSTONE_EXPORT char *CAPSTONE_API cs_group_name(csh ud, unsigned int group)
void replace_negative(char *src, int mode)
char * get_detail_evm(csh *handle, cs_mode mode, cs_insn *ins)
char * get_detail_xcore(csh *handle, cs_mode mode, cs_insn *ins)
@ CS_MODE_MIPS3
Mips III ISA.
int get_index(double_dict d[], unsigned int size, const char *s)
CAPSTONE_EXPORT void CAPSTONE_API cs_free(cs_insn *insn, size_t count)
@ CS_MODE_V9
SparcV9 mode (Sparc)
@ CS_MODE_M680X_6301
M680X Hitachi 6301,6303 mode.
@ CS_OPT_MODE
Change engine's mode at run-time.
@ CS_ARCH_ARM64
ARM-64, also called AArch64.
char * get_detail_x86(csh *handle, cs_mode mode, cs_insn *ins)
@ CS_MODE_MIPS32
Mips32 ISA (Mips)
static void split(const char *s, char ***ss, size_t *ns)
@ CS_MODE_M680X_6811
M680X Motorola/Freescale/NXP 68HC11 mode.
@ CS_ARCH_XCORE
XCore architecture.
@ CS_MODE_V8
ARMv8 A32 encodings for ARM.
char * get_detail_tms320c64x(csh *handle, cs_mode mode, cs_insn *ins)
@ CS_OPT_SYNTAX_MASM
X86 Intel Masm syntax (CS_OPT_SYNTAX).
grpc
Author(s):
autogenerated on Thu Mar 13 2025 02:58:43