arm_detail.c
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1 /* Capstone testing regression */
2 /* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
3 
4 
5 #include "factory.h"
6 
7 char *get_detail_arm(csh *handle, cs_mode mode, cs_insn *ins)
8 {
9  cs_arm *arm;
10  int i;
11  cs_regs regs_read, regs_write;
12  uint8_t regs_read_count, regs_write_count;
13  char *result;
14 
15  result = (char *)malloc(sizeof(char));
16  result[0] = '\0';
17 
18  if (ins->detail == NULL)
19  return result;
20 
21  arm = &(ins->detail->arm);
22 
23  if (arm->op_count)
24  add_str(&result, " ; op_count: %u", arm->op_count);
25 
26  for (i = 0; i < arm->op_count; i++) {
27  cs_arm_op *op = &(arm->operands[i]);
28  switch((int)op->type) {
29  default:
30  break;
31  case ARM_OP_REG:
32  add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
33  break;
34  case ARM_OP_IMM:
35  add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm);
36  break;
37  case ARM_OP_FP:
38 #if defined(_KERNEL_MODE)
39  // Issue #681: Windows kernel does not support formatting float point
40  add_str(&result, " ; operands[%u].type: FP = <float_point_unsupported>", i);
41 #else
42  add_str(&result, " ; operands[%u].type: FP = %f", i, op->fp);
43 #endif
44  break;
45  case ARM_OP_MEM:
46  add_str(&result, " ; operands[%u].type: MEM", i);
47  if (op->mem.base != ARM_REG_INVALID)
48  add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
49  if (op->mem.index != ARM_REG_INVALID)
50  add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index));
51  if (op->mem.scale != 1)
52  add_str(&result, " ; operands[%u].mem.scale: %d", i, op->mem.scale);
53  if (op->mem.disp != 0)
54  add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
55  if (op->mem.lshift != 0)
56  add_str(&result, " ; operands[%u].mem.lshift: 0x%x", i, op->mem.lshift);
57 
58  break;
59  case ARM_OP_PIMM:
60  add_str(&result, " ; operands[%u].type: P-IMM = %u", i, op->imm);
61  break;
62  case ARM_OP_CIMM:
63  add_str(&result, " ; operands[%u].type: C-IMM = %u", i, op->imm);
64  break;
65  case ARM_OP_SETEND:
66  add_str(&result, " ; operands[%u].type: SETEND = %s", i, op->setend == ARM_SETEND_BE? "be" : "le");
67  break;
68  case ARM_OP_SYSREG:
69  add_str(&result, " ; operands[%u].type: SYSREG = %u", i, op->reg);
70  break;
71  }
72 
73  if (op->neon_lane != -1) {
74  add_str(&result, " ; operands[%u].neon_lane = %u", i, op->neon_lane);
75  }
76 
77  switch(op->access) {
78  default:
79  break;
80  case CS_AC_READ:
81  add_str(&result, " ; operands[%u].access: READ", i);
82  break;
83  case CS_AC_WRITE:
84  add_str(&result, " ; operands[%u].access: WRITE", i);
85  break;
86  case CS_AC_READ | CS_AC_WRITE:
87  add_str(&result, " ; operands[%u].access: READ | WRITE", i);
88  break;
89  }
90 
91  if (op->shift.type != ARM_SFT_INVALID && op->shift.value) {
92  if (op->shift.type < ARM_SFT_ASR_REG)
93  add_str(&result, " ; Shift: %u = %u", op->shift.type, op->shift.value);
94  else
95  add_str(&result, " ; Shift: %u = %s", op->shift.type, cs_reg_name(*handle, op->shift.value));
96  }
97 
98  if (op->vector_index != -1) {
99  add_str(&result, " ; operands[%u].vector_index = %u", i, op->vector_index);
100  }
101 
102  if (op->subtracted)
103  add_str(&result, " ; Subtracted: True");
104  }
105 
106  if (arm->cc != ARM_CC_AL && arm->cc != ARM_CC_INVALID)
107  add_str(&result, " ; Code condition: %u", arm->cc);
108 
109  if (arm->update_flags)
110  add_str(&result, " ; Update-flags: True");
111 
112  if (arm->writeback)
113  add_str(&result, " ; Write-back: True");
114 
115  if (arm->cps_mode)
116  add_str(&result, " ; CPSI-mode: %u", arm->cps_mode);
117 
118  if (arm->cps_flag)
119  add_str(&result, " ; CPSI-flag: %u", arm->cps_flag);
120 
121  if (arm->vector_data)
122  add_str(&result, " ; Vector-data: %u", arm->vector_data);
123 
124  if (arm->vector_size)
125  add_str(&result, " ; Vector-size: %u", arm->vector_size);
126 
127  if (arm->usermode)
128  add_str(&result, " ; User-mode: True");
129 
130  if (arm->mem_barrier)
131  add_str(&result, " ; Memory-barrier: %u", arm->mem_barrier);
132 
133  if (!cs_regs_access(*handle, ins, regs_read, &regs_read_count, regs_write, &regs_write_count)) {
134  if (regs_read_count) {
135  add_str(&result, " ; Registers read:");
136  for(i = 0; i < regs_read_count; i++) {
137  add_str(&result, " %s", cs_reg_name(*handle, regs_read[i]));
138  }
139  }
140 
141  if (regs_write_count) {
142  add_str(&result, " ; Registers modified:");
143  for(i = 0; i < regs_write_count; i++) {
144  add_str(&result, " %s", cs_reg_name(*handle, regs_write[i]));
145  }
146  }
147  }
148 
149  return result;
150 }
_gevent_test_main.result
result
Definition: _gevent_test_main.py:96
arm
Definition: test_winkernel.cpp:55
factory.h
mode
const char int mode
Definition: bloaty/third_party/zlib/contrib/minizip/ioapi.h:135
uint8_t
unsigned char uint8_t
Definition: stdint-msvc2008.h:78
CS_AC_READ
@ CS_AC_READ
Operand read from memory or register.
Definition: capstone.h:205
cs_regs_access
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_regs_access(csh ud, const cs_insn *insn, cs_regs regs_read, uint8_t *regs_read_count, cs_regs regs_write, uint8_t *regs_write_count)
Definition: cs.c:1539
cs_mode
cs_mode
Mode type.
Definition: capstone.h:103
ARM_REG_INVALID
@ ARM_REG_INVALID
Definition: arm.h:253
ARM_SFT_ASR_REG
@ ARM_SFT_ASR_REG
shift with register
Definition: arm.h:25
cs_reg_name
const CAPSTONE_EXPORT char *CAPSTONE_API cs_reg_name(csh ud, unsigned int reg)
Definition: cs.c:1176
ARM_SFT_INVALID
@ ARM_SFT_INVALID
Definition: arm.h:19
ARM_OP_PIMM
@ ARM_OP_PIMM
P-Immediate (coprocessor registers)
Definition: arm.h:168
cs_arm
Instruction structure.
Definition: arm.h:424
add_str
void add_str(char **src, const char *format,...)
Definition: helper.c:89
ARM_CC_INVALID
@ ARM_CC_INVALID
Definition: arm.h:34
ARM_OP_REG
@ ARM_OP_REG
= CS_OP_REG (Register operand).
Definition: arm.h:163
ARM_OP_SYSREG
@ ARM_OP_SYSREG
MSR/MRS special register operand.
Definition: arm.h:170
ARM_OP_FP
@ ARM_OP_FP
= CS_OP_FP (Floating-Point operand).
Definition: arm.h:166
csh
size_t csh
Definition: capstone.h:71
ARM_CC_AL
@ ARM_CC_AL
Always (unconditional) Always (unconditional)
Definition: arm.h:49
ARM_OP_IMM
@ ARM_OP_IMM
= CS_OP_IMM (Immediate operand).
Definition: arm.h:164
ARM_OP_CIMM
@ ARM_OP_CIMM
C-Immediate (coprocessor registers)
Definition: arm.h:167
handle
static csh handle
Definition: test_arm_regression.c:16
ARM_SETEND_BE
@ ARM_SETEND_BE
BE operand.
Definition: arm.h:176
ARM_OP_SETEND
@ ARM_OP_SETEND
operand for SETEND instruction
Definition: arm.h:169
ARM_OP_MEM
@ ARM_OP_MEM
= CS_OP_MEM (Memory operand).
Definition: arm.h:165
cs_arm_op
Instruction operand.
Definition: arm.h:391
op
static grpc_op * op
Definition: test/core/fling/client.cc:47
i
uint64_t i
Definition: abseil-cpp/absl/container/btree_benchmark.cc:230
get_detail_arm
char * get_detail_arm(csh *handle, cs_mode mode, cs_insn *ins)
Definition: arm_detail.c:7
CS_AC_WRITE
@ CS_AC_WRITE
Operand write to memory or register.
Definition: capstone.h:206

grpc
Author(s):
autogenerated on Fri May 16 2025 02:57:43