stm32f30x_dma.h
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1 
29 /* Define to prevent recursive inclusion -------------------------------------*/
30 #ifndef __STM32F30x_DMA_H
31 #define __STM32F30x_DMA_H
32 
33 #ifdef __cplusplus
34  extern "C" {
35 #endif
36 
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f30x.h"
39 
48 /* Exported types ------------------------------------------------------------*/
49 
53 typedef struct
54 {
55  uint32_t DMA_PeripheralBaseAddr;
57  uint32_t DMA_MemoryBaseAddr;
59  uint32_t DMA_DIR;
62  uint16_t DMA_BufferSize;
66  uint32_t DMA_PeripheralInc;
69  uint32_t DMA_MemoryInc;
72  uint32_t DMA_PeripheralDataSize;
75  uint32_t DMA_MemoryDataSize;
78  uint32_t DMA_Mode;
83  uint32_t DMA_Priority;
86  uint32_t DMA_M2M;
88 }DMA_InitTypeDef;
89 
90 /* Exported constants --------------------------------------------------------*/
91 
96 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
97  ((PERIPH) == DMA1_Channel2) || \
98  ((PERIPH) == DMA1_Channel3) || \
99  ((PERIPH) == DMA1_Channel4) || \
100  ((PERIPH) == DMA1_Channel5) || \
101  ((PERIPH) == DMA1_Channel6) || \
102  ((PERIPH) == DMA1_Channel7) || \
103  ((PERIPH) == DMA2_Channel1) || \
104  ((PERIPH) == DMA2_Channel2) || \
105  ((PERIPH) == DMA2_Channel3) || \
106  ((PERIPH) == DMA2_Channel4) || \
107  ((PERIPH) == DMA2_Channel5))
108 
113 #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
114 #define DMA_DIR_PeripheralDST DMA_CCR_DIR
115 
116 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
117  ((DIR) == DMA_DIR_PeripheralDST))
118 
127 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
128 #define DMA_PeripheralInc_Enable DMA_CCR_PINC
129 
130 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
131  ((STATE) == DMA_PeripheralInc_Enable))
132 
140 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
141 #define DMA_MemoryInc_Enable DMA_CCR_MINC
142 
143 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
144  ((STATE) == DMA_MemoryInc_Enable))
145 
153 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
154 #define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0
155 #define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1
156 
157 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
158  ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
159  ((SIZE) == DMA_PeripheralDataSize_Word))
160 
168 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
169 #define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0
170 #define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1
171 
172 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
173  ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
174  ((SIZE) == DMA_MemoryDataSize_Word))
175 
183 #define DMA_Mode_Normal ((uint32_t)0x00000000)
184 #define DMA_Mode_Circular DMA_CCR_CIRC
185 
186 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
187 
195 #define DMA_Priority_VeryHigh DMA_CCR_PL
196 #define DMA_Priority_High DMA_CCR_PL_1
197 #define DMA_Priority_Medium DMA_CCR_PL_0
198 #define DMA_Priority_Low ((uint32_t)0x00000000)
199 
200 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
201  ((PRIORITY) == DMA_Priority_High) || \
202  ((PRIORITY) == DMA_Priority_Medium) || \
203  ((PRIORITY) == DMA_Priority_Low))
204 
212 #define DMA_M2M_Disable ((uint32_t)0x00000000)
213 #define DMA_M2M_Enable DMA_CCR_MEM2MEM
214 
215 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
216 
225 #define DMA_IT_TC ((uint32_t)0x00000002)
226 #define DMA_IT_HT ((uint32_t)0x00000004)
227 #define DMA_IT_TE ((uint32_t)0x00000008)
228 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
229 
230 #define DMA1_IT_GL1 ((uint32_t)0x00000001)
231 #define DMA1_IT_TC1 ((uint32_t)0x00000002)
232 #define DMA1_IT_HT1 ((uint32_t)0x00000004)
233 #define DMA1_IT_TE1 ((uint32_t)0x00000008)
234 #define DMA1_IT_GL2 ((uint32_t)0x00000010)
235 #define DMA1_IT_TC2 ((uint32_t)0x00000020)
236 #define DMA1_IT_HT2 ((uint32_t)0x00000040)
237 #define DMA1_IT_TE2 ((uint32_t)0x00000080)
238 #define DMA1_IT_GL3 ((uint32_t)0x00000100)
239 #define DMA1_IT_TC3 ((uint32_t)0x00000200)
240 #define DMA1_IT_HT3 ((uint32_t)0x00000400)
241 #define DMA1_IT_TE3 ((uint32_t)0x00000800)
242 #define DMA1_IT_GL4 ((uint32_t)0x00001000)
243 #define DMA1_IT_TC4 ((uint32_t)0x00002000)
244 #define DMA1_IT_HT4 ((uint32_t)0x00004000)
245 #define DMA1_IT_TE4 ((uint32_t)0x00008000)
246 #define DMA1_IT_GL5 ((uint32_t)0x00010000)
247 #define DMA1_IT_TC5 ((uint32_t)0x00020000)
248 #define DMA1_IT_HT5 ((uint32_t)0x00040000)
249 #define DMA1_IT_TE5 ((uint32_t)0x00080000)
250 #define DMA1_IT_GL6 ((uint32_t)0x00100000)
251 #define DMA1_IT_TC6 ((uint32_t)0x00200000)
252 #define DMA1_IT_HT6 ((uint32_t)0x00400000)
253 #define DMA1_IT_TE6 ((uint32_t)0x00800000)
254 #define DMA1_IT_GL7 ((uint32_t)0x01000000)
255 #define DMA1_IT_TC7 ((uint32_t)0x02000000)
256 #define DMA1_IT_HT7 ((uint32_t)0x04000000)
257 #define DMA1_IT_TE7 ((uint32_t)0x08000000)
258 
259 #define DMA2_IT_GL1 ((uint32_t)0x10000001)
260 #define DMA2_IT_TC1 ((uint32_t)0x10000002)
261 #define DMA2_IT_HT1 ((uint32_t)0x10000004)
262 #define DMA2_IT_TE1 ((uint32_t)0x10000008)
263 #define DMA2_IT_GL2 ((uint32_t)0x10000010)
264 #define DMA2_IT_TC2 ((uint32_t)0x10000020)
265 #define DMA2_IT_HT2 ((uint32_t)0x10000040)
266 #define DMA2_IT_TE2 ((uint32_t)0x10000080)
267 #define DMA2_IT_GL3 ((uint32_t)0x10000100)
268 #define DMA2_IT_TC3 ((uint32_t)0x10000200)
269 #define DMA2_IT_HT3 ((uint32_t)0x10000400)
270 #define DMA2_IT_TE3 ((uint32_t)0x10000800)
271 #define DMA2_IT_GL4 ((uint32_t)0x10001000)
272 #define DMA2_IT_TC4 ((uint32_t)0x10002000)
273 #define DMA2_IT_HT4 ((uint32_t)0x10004000)
274 #define DMA2_IT_TE4 ((uint32_t)0x10008000)
275 #define DMA2_IT_GL5 ((uint32_t)0x10010000)
276 #define DMA2_IT_TC5 ((uint32_t)0x10020000)
277 #define DMA2_IT_HT5 ((uint32_t)0x10040000)
278 #define DMA2_IT_TE5 ((uint32_t)0x10080000)
279 
280 #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
281 
282 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
283  ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
284  ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
285  ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
286  ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
287  ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
288  ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
289  ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
290  ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
291  ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
292  ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
293  ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
294  ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
295  ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
296  ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
297  ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
298  ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
299  ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
300  ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
301  ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
302  ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
303  ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
304  ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
305  ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
306 
315 #define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
316 #define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
317 #define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
318 #define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
319 #define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
320 #define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
321 #define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
322 #define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
323 #define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
324 #define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
325 #define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
326 #define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
327 #define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
328 #define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
329 #define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
330 #define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
331 #define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
332 #define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
333 #define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
334 #define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
335 #define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
336 #define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
337 #define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
338 #define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
339 #define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
340 #define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
341 #define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
342 #define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
343 
344 #define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
345 #define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
346 #define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
347 #define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
348 #define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
349 #define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
350 #define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
351 #define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
352 #define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
353 #define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
354 #define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
355 #define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
356 #define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
357 #define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
358 #define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
359 #define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
360 #define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
361 #define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
362 #define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
363 #define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
364 
365 #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
366 
367 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
368  ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
369  ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
370  ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
371  ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
372  ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
373  ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
374  ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
375  ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
376  ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
377  ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
378  ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
379  ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
380  ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
381  ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
382  ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
383  ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
384  ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
385  ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
386  ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
387  ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
388  ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
389  ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
390  ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
391 
400 /* Exported macro ------------------------------------------------------------*/
401 /* Exported functions ------------------------------------------------------- */
402 
403 /* Function used to set the DMA configuration to the default reset state ******/
404 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
405 
406 /* Initialization and Configuration functions *********************************/
407 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
408 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
409 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
410 
411 /* Data Counter functions******************************************************/
412 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
413 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
414 
415 /* Interrupts and flags management functions **********************************/
416 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
417 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
418 void DMA_ClearFlag(uint32_t DMAy_FLAG);
419 ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
420 void DMA_ClearITPendingBit(uint32_t DMAy_IT);
421 
422 #ifdef __cplusplus
423 }
424 #endif
425 
426 #endif /*__STM32F30x_DMA_H */
427 
436 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
FlagStatus
FlagStatus
Definition: stm32f4xx.h:706
FunctionalState
FunctionalState
Definition: stm32f4xx.h:708
DMA_InitTypeDef
DMA Init structure definition.
Definition: stm32f4xx_dma.h:54
DMA_ClearITPendingBit
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
Clears the DMAy Channelx's interrupt pending bits.
Definition: stm32f10x_dma.c:684
DMA_Cmd
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
Enables or disables the specified DMAy Channelx.
Definition: stm32f10x_dma.c:294
DMA_InitTypeDef::DMA_BufferSize
uint16_t DMA_BufferSize
Definition: stm32f30x_dma.h:62
ITStatus
enum FlagStatus ITStatus
DMA_StructInit
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
Fills each DMA_InitStruct member with its default value.
Definition: stm32f30x_dma.c:293
DMA_GetITStatus
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
Checks whether the specified DMAy Channelx interrupt has occurred or not.
Definition: stm32f10x_dma.c:595
DMA_ClearFlag
void DMA_ClearFlag(uint32_t DMAy_FLAG)
Clears the DMAy Channelx's pending flags.
Definition: stm32f10x_dma.c:523
DMA_GetCurrDataCounter
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx)
Returns the number of remaining data units in the current DMAy Channelx transfer. ...
Definition: stm32f10x_dma.c:371
DMA_Channel_TypeDef
DMA Controller.
Definition: stm32f10x.h:798
DMA_DeInit
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx)
Deinitializes the DMAy Channelx registers to their default reset values.
Definition: stm32f10x_dma.c:108
DMA_Init
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
Initializes the DMAy Channelx according to the specified parameters in the DMA_InitStruct.
Definition: stm32f10x_dma.c:202
DMA_ITConfig
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
Enables or disables the specified DMAy Channelx interrupts.
Definition: stm32f10x_dma.c:326
DMA_SetCurrDataCounter
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
Sets the number of data units in the current DMAy Channelx transfer.
Definition: stm32f10x_dma.c:353
DMA_GetFlagStatus
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
Checks whether the specified DMAy Channelx flag is set or not.
Definition: stm32f10x_dma.c:433

rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Wed Jul 3 2019 19:59:25