stm32f10x.h
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1 
50 #ifndef __STM32F10x_H
51 #define __STM32F10x_H
52 
53 #ifdef __cplusplus
54  extern "C" {
55 #endif
56 
61 /* Uncomment the line below according to the target STM32 device used in your
62  application
63  */
64 
65 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
66  /* #define STM32F10X_LD */
67  /* #define STM32F10X_LD_VL */
68  /* #define STM32F10X_MD */
69  /* #define STM32F10X_MD_VL */
70  /* #define STM32F10X_HD */
71  /* #define STM32F10X_HD_VL */
72  /* #define STM32F10X_XL */
73  /* #define STM32F10X_CL */
74 #endif
75 /* Tip: To avoid modifying this file each time you need to switch between these
76  devices, you can define the device in your toolchain compiler preprocessor.
77 
78  - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
79  where the Flash memory density ranges between 16 and 32 Kbytes.
80  - Low-density value line devices are STM32F100xx microcontrollers where the Flash
81  memory density ranges between 16 and 32 Kbytes.
82  - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
83  where the Flash memory density ranges between 64 and 128 Kbytes.
84  - Medium-density value line devices are STM32F100xx microcontrollers where the
85  Flash memory density ranges between 64 and 128 Kbytes.
86  - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
87  the Flash memory density ranges between 256 and 512 Kbytes.
88  - High-density value line devices are STM32F100xx microcontrollers where the
89  Flash memory density ranges between 256 and 512 Kbytes.
90  - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
91  the Flash memory density ranges between 512 and 1024 Kbytes.
92  - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
93  */
94 
95 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
96  #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"
97 #endif
98 
99 #if !defined USE_STDPERIPH_DRIVER
100 
105  /*#define USE_STDPERIPH_DRIVER*/
106 #endif
107 
115 #if !defined HSE_VALUE
116  #ifdef STM32F10X_CL
117  #define HSE_VALUE ((uint32_t)25000000)
118  #else
119  #define HSE_VALUE ((uint32_t)8000000)
120  #endif /* STM32F10X_CL */
121 #endif /* HSE_VALUE */
122 
123 
128 #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500)
130 #define HSI_VALUE ((uint32_t)8000000)
135 #define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03)
136 #define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05)
137 #define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00)
138 #define __STM32F10X_STDPERIPH_VERSION_RC (0x00)
139 #define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
140  |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
141  |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
142  |(__STM32F10X_STDPERIPH_VERSION_RC))
143 
155 #ifdef STM32F10X_XL
156  #define __MPU_PRESENT 1
157 #else
158  #define __MPU_PRESENT 0
159 #endif /* STM32F10X_XL */
160 #define __NVIC_PRIO_BITS 4
161 #define __Vendor_SysTickConfig 0
167 typedef enum IRQn
168 {
169 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
170  NonMaskableInt_IRQn = -14,
171  MemoryManagement_IRQn = -12,
172  BusFault_IRQn = -11,
173  UsageFault_IRQn = -10,
174  SVCall_IRQn = -5,
175  DebugMonitor_IRQn = -4,
176  PendSV_IRQn = -2,
177  SysTick_IRQn = -1,
179 /****** STM32 specific Interrupt Numbers *********************************************************/
180  WWDG_IRQn = 0,
181  PVD_IRQn = 1,
182  TAMPER_IRQn = 2,
183  RTC_IRQn = 3,
184  FLASH_IRQn = 4,
185  RCC_IRQn = 5,
186  EXTI0_IRQn = 6,
187  EXTI1_IRQn = 7,
188  EXTI2_IRQn = 8,
189  EXTI3_IRQn = 9,
190  EXTI4_IRQn = 10,
191  DMA1_Channel1_IRQn = 11,
192  DMA1_Channel2_IRQn = 12,
193  DMA1_Channel3_IRQn = 13,
194  DMA1_Channel4_IRQn = 14,
195  DMA1_Channel5_IRQn = 15,
196  DMA1_Channel6_IRQn = 16,
197  DMA1_Channel7_IRQn = 17,
199 #ifdef STM32F10X_LD
200  ADC1_2_IRQn = 18,
201  USB_HP_CAN1_TX_IRQn = 19,
202  USB_LP_CAN1_RX0_IRQn = 20,
203  CAN1_RX1_IRQn = 21,
204  CAN1_SCE_IRQn = 22,
205  EXTI9_5_IRQn = 23,
206  TIM1_BRK_IRQn = 24,
207  TIM1_UP_IRQn = 25,
208  TIM1_TRG_COM_IRQn = 26,
209  TIM1_CC_IRQn = 27,
210  TIM2_IRQn = 28,
211  TIM3_IRQn = 29,
212  I2C1_EV_IRQn = 31,
213  I2C1_ER_IRQn = 32,
214  SPI1_IRQn = 35,
215  USART1_IRQn = 37,
216  USART2_IRQn = 38,
217  EXTI15_10_IRQn = 40,
218  RTCAlarm_IRQn = 41,
219  USBWakeUp_IRQn = 42
220 #endif /* STM32F10X_LD */
221 
222 #ifdef STM32F10X_LD_VL
223  ADC1_IRQn = 18,
224  EXTI9_5_IRQn = 23,
225  TIM1_BRK_TIM15_IRQn = 24,
226  TIM1_UP_TIM16_IRQn = 25,
227  TIM1_TRG_COM_TIM17_IRQn = 26,
228  TIM1_CC_IRQn = 27,
229  TIM2_IRQn = 28,
230  TIM3_IRQn = 29,
231  I2C1_EV_IRQn = 31,
232  I2C1_ER_IRQn = 32,
233  SPI1_IRQn = 35,
234  USART1_IRQn = 37,
235  USART2_IRQn = 38,
236  EXTI15_10_IRQn = 40,
237  RTCAlarm_IRQn = 41,
238  CEC_IRQn = 42,
239  TIM6_DAC_IRQn = 54,
240  TIM7_IRQn = 55
241 #endif /* STM32F10X_LD_VL */
242 
243 #ifdef STM32F10X_MD
244  ADC1_2_IRQn = 18,
245  USB_HP_CAN1_TX_IRQn = 19,
246  USB_LP_CAN1_RX0_IRQn = 20,
247  CAN1_RX1_IRQn = 21,
248  CAN1_SCE_IRQn = 22,
249  EXTI9_5_IRQn = 23,
250  TIM1_BRK_IRQn = 24,
251  TIM1_UP_IRQn = 25,
252  TIM1_TRG_COM_IRQn = 26,
253  TIM1_CC_IRQn = 27,
254  TIM2_IRQn = 28,
255  TIM3_IRQn = 29,
256  TIM4_IRQn = 30,
257  I2C1_EV_IRQn = 31,
258  I2C1_ER_IRQn = 32,
259  I2C2_EV_IRQn = 33,
260  I2C2_ER_IRQn = 34,
261  SPI1_IRQn = 35,
262  SPI2_IRQn = 36,
263  USART1_IRQn = 37,
264  USART2_IRQn = 38,
265  USART3_IRQn = 39,
266  EXTI15_10_IRQn = 40,
267  RTCAlarm_IRQn = 41,
268  USBWakeUp_IRQn = 42
269 #endif /* STM32F10X_MD */
270 
271 #ifdef STM32F10X_MD_VL
272  ADC1_IRQn = 18,
273  EXTI9_5_IRQn = 23,
274  TIM1_BRK_TIM15_IRQn = 24,
275  TIM1_UP_TIM16_IRQn = 25,
276  TIM1_TRG_COM_TIM17_IRQn = 26,
277  TIM1_CC_IRQn = 27,
278  TIM2_IRQn = 28,
279  TIM3_IRQn = 29,
280  TIM4_IRQn = 30,
281  I2C1_EV_IRQn = 31,
282  I2C1_ER_IRQn = 32,
283  I2C2_EV_IRQn = 33,
284  I2C2_ER_IRQn = 34,
285  SPI1_IRQn = 35,
286  SPI2_IRQn = 36,
287  USART1_IRQn = 37,
288  USART2_IRQn = 38,
289  USART3_IRQn = 39,
290  EXTI15_10_IRQn = 40,
291  RTCAlarm_IRQn = 41,
292  CEC_IRQn = 42,
293  TIM6_DAC_IRQn = 54,
294  TIM7_IRQn = 55
295 #endif /* STM32F10X_MD_VL */
296 
297 #ifdef STM32F10X_HD
298  ADC1_2_IRQn = 18,
299  USB_HP_CAN1_TX_IRQn = 19,
300  USB_LP_CAN1_RX0_IRQn = 20,
301  CAN1_RX1_IRQn = 21,
302  CAN1_SCE_IRQn = 22,
303  EXTI9_5_IRQn = 23,
304  TIM1_BRK_IRQn = 24,
305  TIM1_UP_IRQn = 25,
306  TIM1_TRG_COM_IRQn = 26,
307  TIM1_CC_IRQn = 27,
308  TIM2_IRQn = 28,
309  TIM3_IRQn = 29,
310  TIM4_IRQn = 30,
311  I2C1_EV_IRQn = 31,
312  I2C1_ER_IRQn = 32,
313  I2C2_EV_IRQn = 33,
314  I2C2_ER_IRQn = 34,
315  SPI1_IRQn = 35,
316  SPI2_IRQn = 36,
317  USART1_IRQn = 37,
318  USART2_IRQn = 38,
319  USART3_IRQn = 39,
320  EXTI15_10_IRQn = 40,
321  RTCAlarm_IRQn = 41,
322  USBWakeUp_IRQn = 42,
323  TIM8_BRK_IRQn = 43,
324  TIM8_UP_IRQn = 44,
325  TIM8_TRG_COM_IRQn = 45,
326  TIM8_CC_IRQn = 46,
327  ADC3_IRQn = 47,
328  FSMC_IRQn = 48,
329  SDIO_IRQn = 49,
330  TIM5_IRQn = 50,
331  SPI3_IRQn = 51,
332  UART4_IRQn = 52,
333  UART5_IRQn = 53,
334  TIM6_IRQn = 54,
335  TIM7_IRQn = 55,
336  DMA2_Channel1_IRQn = 56,
337  DMA2_Channel2_IRQn = 57,
338  DMA2_Channel3_IRQn = 58,
339  DMA2_Channel4_5_IRQn = 59
340 #endif /* STM32F10X_HD */
341 
342 #ifdef STM32F10X_HD_VL
343  ADC1_IRQn = 18,
344  EXTI9_5_IRQn = 23,
345  TIM1_BRK_TIM15_IRQn = 24,
346  TIM1_UP_TIM16_IRQn = 25,
347  TIM1_TRG_COM_TIM17_IRQn = 26,
348  TIM1_CC_IRQn = 27,
349  TIM2_IRQn = 28,
350  TIM3_IRQn = 29,
351  TIM4_IRQn = 30,
352  I2C1_EV_IRQn = 31,
353  I2C1_ER_IRQn = 32,
354  I2C2_EV_IRQn = 33,
355  I2C2_ER_IRQn = 34,
356  SPI1_IRQn = 35,
357  SPI2_IRQn = 36,
358  USART1_IRQn = 37,
359  USART2_IRQn = 38,
360  USART3_IRQn = 39,
361  EXTI15_10_IRQn = 40,
362  RTCAlarm_IRQn = 41,
363  CEC_IRQn = 42,
364  TIM12_IRQn = 43,
365  TIM13_IRQn = 44,
366  TIM14_IRQn = 45,
367  TIM5_IRQn = 50,
368  SPI3_IRQn = 51,
369  UART4_IRQn = 52,
370  UART5_IRQn = 53,
371  TIM6_DAC_IRQn = 54,
372  TIM7_IRQn = 55,
373  DMA2_Channel1_IRQn = 56,
374  DMA2_Channel2_IRQn = 57,
375  DMA2_Channel3_IRQn = 58,
376  DMA2_Channel4_5_IRQn = 59,
377  DMA2_Channel5_IRQn = 60
380 #endif /* STM32F10X_HD_VL */
381 
382 #ifdef STM32F10X_XL
383  ADC1_2_IRQn = 18,
384  USB_HP_CAN1_TX_IRQn = 19,
385  USB_LP_CAN1_RX0_IRQn = 20,
386  CAN1_RX1_IRQn = 21,
387  CAN1_SCE_IRQn = 22,
388  EXTI9_5_IRQn = 23,
389  TIM1_BRK_TIM9_IRQn = 24,
390  TIM1_UP_TIM10_IRQn = 25,
391  TIM1_TRG_COM_TIM11_IRQn = 26,
392  TIM1_CC_IRQn = 27,
393  TIM2_IRQn = 28,
394  TIM3_IRQn = 29,
395  TIM4_IRQn = 30,
396  I2C1_EV_IRQn = 31,
397  I2C1_ER_IRQn = 32,
398  I2C2_EV_IRQn = 33,
399  I2C2_ER_IRQn = 34,
400  SPI1_IRQn = 35,
401  SPI2_IRQn = 36,
402  USART1_IRQn = 37,
403  USART2_IRQn = 38,
404  USART3_IRQn = 39,
405  EXTI15_10_IRQn = 40,
406  RTCAlarm_IRQn = 41,
407  USBWakeUp_IRQn = 42,
408  TIM8_BRK_TIM12_IRQn = 43,
409  TIM8_UP_TIM13_IRQn = 44,
410  TIM8_TRG_COM_TIM14_IRQn = 45,
411  TIM8_CC_IRQn = 46,
412  ADC3_IRQn = 47,
413  FSMC_IRQn = 48,
414  SDIO_IRQn = 49,
415  TIM5_IRQn = 50,
416  SPI3_IRQn = 51,
417  UART4_IRQn = 52,
418  UART5_IRQn = 53,
419  TIM6_IRQn = 54,
420  TIM7_IRQn = 55,
421  DMA2_Channel1_IRQn = 56,
422  DMA2_Channel2_IRQn = 57,
423  DMA2_Channel3_IRQn = 58,
424  DMA2_Channel4_5_IRQn = 59
425 #endif /* STM32F10X_XL */
426 
427 #ifdef STM32F10X_CL
428  ADC1_2_IRQn = 18,
429  CAN1_TX_IRQn = 19,
430  CAN1_RX0_IRQn = 20,
431  CAN1_RX1_IRQn = 21,
432  CAN1_SCE_IRQn = 22,
433  EXTI9_5_IRQn = 23,
434  TIM1_BRK_IRQn = 24,
435  TIM1_UP_IRQn = 25,
436  TIM1_TRG_COM_IRQn = 26,
437  TIM1_CC_IRQn = 27,
438  TIM2_IRQn = 28,
439  TIM3_IRQn = 29,
440  TIM4_IRQn = 30,
441  I2C1_EV_IRQn = 31,
442  I2C1_ER_IRQn = 32,
443  I2C2_EV_IRQn = 33,
444  I2C2_ER_IRQn = 34,
445  SPI1_IRQn = 35,
446  SPI2_IRQn = 36,
447  USART1_IRQn = 37,
448  USART2_IRQn = 38,
449  USART3_IRQn = 39,
450  EXTI15_10_IRQn = 40,
451  RTCAlarm_IRQn = 41,
452  OTG_FS_WKUP_IRQn = 42,
453  TIM5_IRQn = 50,
454  SPI3_IRQn = 51,
455  UART4_IRQn = 52,
456  UART5_IRQn = 53,
457  TIM6_IRQn = 54,
458  TIM7_IRQn = 55,
459  DMA2_Channel1_IRQn = 56,
460  DMA2_Channel2_IRQn = 57,
461  DMA2_Channel3_IRQn = 58,
462  DMA2_Channel4_IRQn = 59,
463  DMA2_Channel5_IRQn = 60,
464  ETH_IRQn = 61,
465  ETH_WKUP_IRQn = 62,
466  CAN2_TX_IRQn = 63,
467  CAN2_RX0_IRQn = 64,
468  CAN2_RX1_IRQn = 65,
469  CAN2_SCE_IRQn = 66,
470  OTG_FS_IRQn = 67
471 #endif /* STM32F10X_CL */
472 } IRQn_Type;
473 
478 #include "core_cm3.h"
479 #include "system_stm32f10x.h"
480 #include <stdint.h>
481 
487 typedef int32_t s32;
488 typedef int16_t s16;
489 typedef int8_t s8;
490 
491 typedef const int32_t sc32;
492 typedef const int16_t sc16;
493 typedef const int8_t sc8;
495 typedef __IO int32_t vs32;
496 typedef __IO int16_t vs16;
497 typedef __IO int8_t vs8;
498 
499 typedef __I int32_t vsc32;
500 typedef __I int16_t vsc16;
501 typedef __I int8_t vsc8;
503 typedef uint32_t u32;
504 typedef uint16_t u16;
505 typedef uint8_t u8;
506 
507 typedef const uint32_t uc32;
508 typedef const uint16_t uc16;
509 typedef const uint8_t uc8;
511 typedef __IO uint32_t vu32;
512 typedef __IO uint16_t vu16;
513 typedef __IO uint8_t vu8;
514 
515 typedef __I uint32_t vuc32;
516 typedef __I uint16_t vuc16;
517 typedef __I uint8_t vuc8;
519 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
520 
521 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
522 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
523 
524 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
525 
527 #define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
528 #define HSE_Value HSE_VALUE
529 #define HSI_Value HSI_VALUE
530 
542 typedef struct
543 {
544  __IO uint32_t SR;
545  __IO uint32_t CR1;
546  __IO uint32_t CR2;
547  __IO uint32_t SMPR1;
548  __IO uint32_t SMPR2;
549  __IO uint32_t JOFR1;
550  __IO uint32_t JOFR2;
551  __IO uint32_t JOFR3;
552  __IO uint32_t JOFR4;
553  __IO uint32_t HTR;
554  __IO uint32_t LTR;
555  __IO uint32_t SQR1;
556  __IO uint32_t SQR2;
557  __IO uint32_t SQR3;
558  __IO uint32_t JSQR;
559  __IO uint32_t JDR1;
560  __IO uint32_t JDR2;
561  __IO uint32_t JDR3;
562  __IO uint32_t JDR4;
563  __IO uint32_t DR;
564 } ADC_TypeDef;
565 
570 typedef struct
571 {
572  uint32_t RESERVED0;
573  __IO uint16_t DR1;
574  uint16_t RESERVED1;
575  __IO uint16_t DR2;
576  uint16_t RESERVED2;
577  __IO uint16_t DR3;
578  uint16_t RESERVED3;
579  __IO uint16_t DR4;
580  uint16_t RESERVED4;
581  __IO uint16_t DR5;
582  uint16_t RESERVED5;
583  __IO uint16_t DR6;
584  uint16_t RESERVED6;
585  __IO uint16_t DR7;
586  uint16_t RESERVED7;
587  __IO uint16_t DR8;
588  uint16_t RESERVED8;
589  __IO uint16_t DR9;
590  uint16_t RESERVED9;
591  __IO uint16_t DR10;
592  uint16_t RESERVED10;
593  __IO uint16_t RTCCR;
594  uint16_t RESERVED11;
595  __IO uint16_t CR;
596  uint16_t RESERVED12;
597  __IO uint16_t CSR;
598  uint16_t RESERVED13[5];
599  __IO uint16_t DR11;
600  uint16_t RESERVED14;
601  __IO uint16_t DR12;
602  uint16_t RESERVED15;
603  __IO uint16_t DR13;
604  uint16_t RESERVED16;
605  __IO uint16_t DR14;
606  uint16_t RESERVED17;
607  __IO uint16_t DR15;
608  uint16_t RESERVED18;
609  __IO uint16_t DR16;
610  uint16_t RESERVED19;
611  __IO uint16_t DR17;
612  uint16_t RESERVED20;
613  __IO uint16_t DR18;
614  uint16_t RESERVED21;
615  __IO uint16_t DR19;
616  uint16_t RESERVED22;
617  __IO uint16_t DR20;
618  uint16_t RESERVED23;
619  __IO uint16_t DR21;
620  uint16_t RESERVED24;
621  __IO uint16_t DR22;
622  uint16_t RESERVED25;
623  __IO uint16_t DR23;
624  uint16_t RESERVED26;
625  __IO uint16_t DR24;
626  uint16_t RESERVED27;
627  __IO uint16_t DR25;
628  uint16_t RESERVED28;
629  __IO uint16_t DR26;
630  uint16_t RESERVED29;
631  __IO uint16_t DR27;
632  uint16_t RESERVED30;
633  __IO uint16_t DR28;
634  uint16_t RESERVED31;
635  __IO uint16_t DR29;
636  uint16_t RESERVED32;
637  __IO uint16_t DR30;
638  uint16_t RESERVED33;
639  __IO uint16_t DR31;
640  uint16_t RESERVED34;
641  __IO uint16_t DR32;
642  uint16_t RESERVED35;
643  __IO uint16_t DR33;
644  uint16_t RESERVED36;
645  __IO uint16_t DR34;
646  uint16_t RESERVED37;
647  __IO uint16_t DR35;
648  uint16_t RESERVED38;
649  __IO uint16_t DR36;
650  uint16_t RESERVED39;
651  __IO uint16_t DR37;
652  uint16_t RESERVED40;
653  __IO uint16_t DR38;
654  uint16_t RESERVED41;
655  __IO uint16_t DR39;
656  uint16_t RESERVED42;
657  __IO uint16_t DR40;
658  uint16_t RESERVED43;
659  __IO uint16_t DR41;
660  uint16_t RESERVED44;
661  __IO uint16_t DR42;
662  uint16_t RESERVED45;
663 } BKP_TypeDef;
664 
669 typedef struct
670 {
671  __IO uint32_t TIR;
672  __IO uint32_t TDTR;
673  __IO uint32_t TDLR;
674  __IO uint32_t TDHR;
675 } CAN_TxMailBox_TypeDef;
676 
681 typedef struct
682 {
683  __IO uint32_t RIR;
684  __IO uint32_t RDTR;
685  __IO uint32_t RDLR;
686  __IO uint32_t RDHR;
687 } CAN_FIFOMailBox_TypeDef;
688 
693 typedef struct
694 {
695  __IO uint32_t FR1;
696  __IO uint32_t FR2;
697 } CAN_FilterRegister_TypeDef;
698 
703 typedef struct
704 {
705  __IO uint32_t MCR;
706  __IO uint32_t MSR;
707  __IO uint32_t TSR;
708  __IO uint32_t RF0R;
709  __IO uint32_t RF1R;
710  __IO uint32_t IER;
711  __IO uint32_t ESR;
712  __IO uint32_t BTR;
713  uint32_t RESERVED0[88];
714  CAN_TxMailBox_TypeDef sTxMailBox[3];
715  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
716  uint32_t RESERVED1[12];
717  __IO uint32_t FMR;
718  __IO uint32_t FM1R;
719  uint32_t RESERVED2;
720  __IO uint32_t FS1R;
721  uint32_t RESERVED3;
722  __IO uint32_t FFA1R;
723  uint32_t RESERVED4;
724  __IO uint32_t FA1R;
725  uint32_t RESERVED5[8];
726 #ifndef STM32F10X_CL
727  CAN_FilterRegister_TypeDef sFilterRegister[14];
728 #else
729  CAN_FilterRegister_TypeDef sFilterRegister[28];
730 #endif /* STM32F10X_CL */
731 } CAN_TypeDef;
732 
736 typedef struct
737 {
738  __IO uint32_t CFGR;
739  __IO uint32_t OAR;
740  __IO uint32_t PRES;
741  __IO uint32_t ESR;
742  __IO uint32_t CSR;
743  __IO uint32_t TXD;
744  __IO uint32_t RXD;
745 } CEC_TypeDef;
746 
751 typedef struct
752 {
753  __IO uint32_t DR;
754  __IO uint8_t IDR;
755  uint8_t RESERVED0;
756  uint16_t RESERVED1;
757  __IO uint32_t CR;
758 } CRC_TypeDef;
759 
764 typedef struct
765 {
766  __IO uint32_t CR;
767  __IO uint32_t SWTRIGR;
768  __IO uint32_t DHR12R1;
769  __IO uint32_t DHR12L1;
770  __IO uint32_t DHR8R1;
771  __IO uint32_t DHR12R2;
772  __IO uint32_t DHR12L2;
773  __IO uint32_t DHR8R2;
774  __IO uint32_t DHR12RD;
775  __IO uint32_t DHR12LD;
776  __IO uint32_t DHR8RD;
777  __IO uint32_t DOR1;
778  __IO uint32_t DOR2;
779 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
780  __IO uint32_t SR;
781 #endif
782 } DAC_TypeDef;
783 
788 typedef struct
789 {
790  __IO uint32_t IDCODE;
791  __IO uint32_t CR;
792 }DBGMCU_TypeDef;
793 
798 typedef struct
799 {
800  __IO uint32_t CCR;
801  __IO uint32_t CNDTR;
802  __IO uint32_t CPAR;
803  __IO uint32_t CMAR;
804 } DMA_Channel_TypeDef;
805 
806 typedef struct
807 {
808  __IO uint32_t ISR;
809  __IO uint32_t IFCR;
810 } DMA_TypeDef;
811 
816 typedef struct
817 {
818  __IO uint32_t MACCR;
819  __IO uint32_t MACFFR;
820  __IO uint32_t MACHTHR;
821  __IO uint32_t MACHTLR;
822  __IO uint32_t MACMIIAR;
823  __IO uint32_t MACMIIDR;
824  __IO uint32_t MACFCR;
825  __IO uint32_t MACVLANTR; /* 8 */
826  uint32_t RESERVED0[2];
827  __IO uint32_t MACRWUFFR; /* 11 */
828  __IO uint32_t MACPMTCSR;
829  uint32_t RESERVED1[2];
830  __IO uint32_t MACSR; /* 15 */
831  __IO uint32_t MACIMR;
832  __IO uint32_t MACA0HR;
833  __IO uint32_t MACA0LR;
834  __IO uint32_t MACA1HR;
835  __IO uint32_t MACA1LR;
836  __IO uint32_t MACA2HR;
837  __IO uint32_t MACA2LR;
838  __IO uint32_t MACA3HR;
839  __IO uint32_t MACA3LR; /* 24 */
840  uint32_t RESERVED2[40];
841  __IO uint32_t MMCCR; /* 65 */
842  __IO uint32_t MMCRIR;
843  __IO uint32_t MMCTIR;
844  __IO uint32_t MMCRIMR;
845  __IO uint32_t MMCTIMR; /* 69 */
846  uint32_t RESERVED3[14];
847  __IO uint32_t MMCTGFSCCR; /* 84 */
848  __IO uint32_t MMCTGFMSCCR;
849  uint32_t RESERVED4[5];
850  __IO uint32_t MMCTGFCR;
851  uint32_t RESERVED5[10];
852  __IO uint32_t MMCRFCECR;
853  __IO uint32_t MMCRFAECR;
854  uint32_t RESERVED6[10];
855  __IO uint32_t MMCRGUFCR;
856  uint32_t RESERVED7[334];
857  __IO uint32_t PTPTSCR;
858  __IO uint32_t PTPSSIR;
859  __IO uint32_t PTPTSHR;
860  __IO uint32_t PTPTSLR;
861  __IO uint32_t PTPTSHUR;
862  __IO uint32_t PTPTSLUR;
863  __IO uint32_t PTPTSAR;
864  __IO uint32_t PTPTTHR;
865  __IO uint32_t PTPTTLR;
866  uint32_t RESERVED8[567];
867  __IO uint32_t DMABMR;
868  __IO uint32_t DMATPDR;
869  __IO uint32_t DMARPDR;
870  __IO uint32_t DMARDLAR;
871  __IO uint32_t DMATDLAR;
872  __IO uint32_t DMASR;
873  __IO uint32_t DMAOMR;
874  __IO uint32_t DMAIER;
875  __IO uint32_t DMAMFBOCR;
876  uint32_t RESERVED9[9];
877  __IO uint32_t DMACHTDR;
878  __IO uint32_t DMACHRDR;
879  __IO uint32_t DMACHTBAR;
880  __IO uint32_t DMACHRBAR;
881 } ETH_TypeDef;
882 
887 typedef struct
888 {
889  __IO uint32_t IMR;
890  __IO uint32_t EMR;
891  __IO uint32_t RTSR;
892  __IO uint32_t FTSR;
893  __IO uint32_t SWIER;
894  __IO uint32_t PR;
895 } EXTI_TypeDef;
896 
901 typedef struct
902 {
903  __IO uint32_t ACR;
904  __IO uint32_t KEYR;
905  __IO uint32_t OPTKEYR;
906  __IO uint32_t SR;
907  __IO uint32_t CR;
908  __IO uint32_t AR;
909  __IO uint32_t RESERVED;
910  __IO uint32_t OBR;
911  __IO uint32_t WRPR;
912 #ifdef STM32F10X_XL
913  uint32_t RESERVED1[8];
914  __IO uint32_t KEYR2;
915  uint32_t RESERVED2;
916  __IO uint32_t SR2;
917  __IO uint32_t CR2;
918  __IO uint32_t AR2;
919 #endif /* STM32F10X_XL */
920 } FLASH_TypeDef;
921 
926 typedef struct
927 {
928  __IO uint16_t RDP;
929  __IO uint16_t USER;
930  __IO uint16_t Data0;
931  __IO uint16_t Data1;
932  __IO uint16_t WRP0;
933  __IO uint16_t WRP1;
934  __IO uint16_t WRP2;
935  __IO uint16_t WRP3;
936 } OB_TypeDef;
937 
942 typedef struct
943 {
944  __IO uint32_t BTCR[8];
945 } FSMC_Bank1_TypeDef;
946 
951 typedef struct
952 {
953  __IO uint32_t BWTR[7];
954 } FSMC_Bank1E_TypeDef;
955 
960 typedef struct
961 {
962  __IO uint32_t PCR2;
963  __IO uint32_t SR2;
964  __IO uint32_t PMEM2;
965  __IO uint32_t PATT2;
966  uint32_t RESERVED0;
967  __IO uint32_t ECCR2;
968 } FSMC_Bank2_TypeDef;
969 
974 typedef struct
975 {
976  __IO uint32_t PCR3;
977  __IO uint32_t SR3;
978  __IO uint32_t PMEM3;
979  __IO uint32_t PATT3;
980  uint32_t RESERVED0;
981  __IO uint32_t ECCR3;
982 } FSMC_Bank3_TypeDef;
983 
988 typedef struct
989 {
990  __IO uint32_t PCR4;
991  __IO uint32_t SR4;
992  __IO uint32_t PMEM4;
993  __IO uint32_t PATT4;
994  __IO uint32_t PIO4;
995 } FSMC_Bank4_TypeDef;
996 
1001 typedef struct
1002 {
1003  __IO uint32_t CRL;
1004  __IO uint32_t CRH;
1005  __IO uint32_t IDR;
1006  __IO uint32_t ODR;
1007  __IO uint32_t BSRR;
1008  __IO uint32_t BRR;
1009  __IO uint32_t LCKR;
1010 } GPIO_TypeDef;
1011 
1016 typedef struct
1017 {
1018  __IO uint32_t EVCR;
1019  __IO uint32_t MAPR;
1020  __IO uint32_t EXTICR[4];
1021  uint32_t RESERVED0;
1022  __IO uint32_t MAPR2;
1023 } AFIO_TypeDef;
1028 typedef struct
1029 {
1030  __IO uint16_t CR1;
1031  uint16_t RESERVED0;
1032  __IO uint16_t CR2;
1033  uint16_t RESERVED1;
1034  __IO uint16_t OAR1;
1035  uint16_t RESERVED2;
1036  __IO uint16_t OAR2;
1037  uint16_t RESERVED3;
1038  __IO uint16_t DR;
1039  uint16_t RESERVED4;
1040  __IO uint16_t SR1;
1041  uint16_t RESERVED5;
1042  __IO uint16_t SR2;
1043  uint16_t RESERVED6;
1044  __IO uint16_t CCR;
1045  uint16_t RESERVED7;
1046  __IO uint16_t TRISE;
1047  uint16_t RESERVED8;
1048 } I2C_TypeDef;
1049 
1054 typedef struct
1055 {
1056  __IO uint32_t KR;
1057  __IO uint32_t PR;
1058  __IO uint32_t RLR;
1059  __IO uint32_t SR;
1060 } IWDG_TypeDef;
1061 
1066 typedef struct
1067 {
1068  __IO uint32_t CR;
1069  __IO uint32_t CSR;
1070 } PWR_TypeDef;
1071 
1076 typedef struct
1077 {
1078  __IO uint32_t CR;
1079  __IO uint32_t CFGR;
1080  __IO uint32_t CIR;
1081  __IO uint32_t APB2RSTR;
1082  __IO uint32_t APB1RSTR;
1083  __IO uint32_t AHBENR;
1084  __IO uint32_t APB2ENR;
1085  __IO uint32_t APB1ENR;
1086  __IO uint32_t BDCR;
1087  __IO uint32_t CSR;
1088 
1089 #ifdef STM32F10X_CL
1090  __IO uint32_t AHBRSTR;
1091  __IO uint32_t CFGR2;
1092 #endif /* STM32F10X_CL */
1093 
1094 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
1095  uint32_t RESERVED0;
1096  __IO uint32_t CFGR2;
1097 #endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */
1098 } RCC_TypeDef;
1099 
1104 typedef struct
1105 {
1106  __IO uint16_t CRH;
1107  uint16_t RESERVED0;
1108  __IO uint16_t CRL;
1109  uint16_t RESERVED1;
1110  __IO uint16_t PRLH;
1111  uint16_t RESERVED2;
1112  __IO uint16_t PRLL;
1113  uint16_t RESERVED3;
1114  __IO uint16_t DIVH;
1115  uint16_t RESERVED4;
1116  __IO uint16_t DIVL;
1117  uint16_t RESERVED5;
1118  __IO uint16_t CNTH;
1119  uint16_t RESERVED6;
1120  __IO uint16_t CNTL;
1121  uint16_t RESERVED7;
1122  __IO uint16_t ALRH;
1123  uint16_t RESERVED8;
1124  __IO uint16_t ALRL;
1125  uint16_t RESERVED9;
1126 } RTC_TypeDef;
1127 
1132 typedef struct
1133 {
1134  __IO uint32_t POWER;
1135  __IO uint32_t CLKCR;
1136  __IO uint32_t ARG;
1137  __IO uint32_t CMD;
1138  __I uint32_t RESPCMD;
1139  __I uint32_t RESP1;
1140  __I uint32_t RESP2;
1141  __I uint32_t RESP3;
1142  __I uint32_t RESP4;
1143  __IO uint32_t DTIMER;
1144  __IO uint32_t DLEN;
1145  __IO uint32_t DCTRL;
1146  __I uint32_t DCOUNT;
1147  __I uint32_t STA;
1148  __IO uint32_t ICR;
1149  __IO uint32_t MASK;
1150  uint32_t RESERVED0[2];
1151  __I uint32_t FIFOCNT;
1152  uint32_t RESERVED1[13];
1153  __IO uint32_t FIFO;
1154 } SDIO_TypeDef;
1155 
1160 typedef struct
1161 {
1162  __IO uint16_t CR1;
1163  uint16_t RESERVED0;
1164  __IO uint16_t CR2;
1165  uint16_t RESERVED1;
1166  __IO uint16_t SR;
1167  uint16_t RESERVED2;
1168  __IO uint16_t DR;
1169  uint16_t RESERVED3;
1170  __IO uint16_t CRCPR;
1171  uint16_t RESERVED4;
1172  __IO uint16_t RXCRCR;
1173  uint16_t RESERVED5;
1174  __IO uint16_t TXCRCR;
1175  uint16_t RESERVED6;
1176  __IO uint16_t I2SCFGR;
1177  uint16_t RESERVED7;
1178  __IO uint16_t I2SPR;
1179  uint16_t RESERVED8;
1180 } SPI_TypeDef;
1181 
1186 typedef struct
1187 {
1188  __IO uint16_t CR1;
1189  uint16_t RESERVED0;
1190  __IO uint16_t CR2;
1191  uint16_t RESERVED1;
1192  __IO uint16_t SMCR;
1193  uint16_t RESERVED2;
1194  __IO uint16_t DIER;
1195  uint16_t RESERVED3;
1196  __IO uint16_t SR;
1197  uint16_t RESERVED4;
1198  __IO uint16_t EGR;
1199  uint16_t RESERVED5;
1200  __IO uint16_t CCMR1;
1201  uint16_t RESERVED6;
1202  __IO uint16_t CCMR2;
1203  uint16_t RESERVED7;
1204  __IO uint16_t CCER;
1205  uint16_t RESERVED8;
1206  __IO uint16_t CNT;
1207  uint16_t RESERVED9;
1208  __IO uint16_t PSC;
1209  uint16_t RESERVED10;
1210  __IO uint16_t ARR;
1211  uint16_t RESERVED11;
1212  __IO uint16_t RCR;
1213  uint16_t RESERVED12;
1214  __IO uint16_t CCR1;
1215  uint16_t RESERVED13;
1216  __IO uint16_t CCR2;
1217  uint16_t RESERVED14;
1218  __IO uint16_t CCR3;
1219  uint16_t RESERVED15;
1220  __IO uint16_t CCR4;
1221  uint16_t RESERVED16;
1222  __IO uint16_t BDTR;
1223  uint16_t RESERVED17;
1224  __IO uint16_t DCR;
1225  uint16_t RESERVED18;
1226  __IO uint16_t DMAR;
1227  uint16_t RESERVED19;
1228 } TIM_TypeDef;
1229 
1234 typedef struct
1235 {
1236  __IO uint16_t SR;
1237  uint16_t RESERVED0;
1238  __IO uint16_t DR;
1239  uint16_t RESERVED1;
1240  __IO uint16_t BRR;
1241  uint16_t RESERVED2;
1242  __IO uint16_t CR1;
1243  uint16_t RESERVED3;
1244  __IO uint16_t CR2;
1245  uint16_t RESERVED4;
1246  __IO uint16_t CR3;
1247  uint16_t RESERVED5;
1248  __IO uint16_t GTPR;
1249  uint16_t RESERVED6;
1250 } USART_TypeDef;
1251 
1256 typedef struct
1257 {
1258  __IO uint32_t CR;
1259  __IO uint32_t CFR;
1260  __IO uint32_t SR;
1261 } WWDG_TypeDef;
1262 
1272 #define FLASH_BASE ((uint32_t)0x08000000)
1273 #define SRAM_BASE ((uint32_t)0x20000000)
1274 #define PERIPH_BASE ((uint32_t)0x40000000)
1276 #define SRAM_BB_BASE ((uint32_t)0x22000000)
1277 #define PERIPH_BB_BASE ((uint32_t)0x42000000)
1279 #define FSMC_R_BASE ((uint32_t)0xA0000000)
1282 #define APB1PERIPH_BASE PERIPH_BASE
1283 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
1284 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
1285 
1286 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
1287 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
1288 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
1289 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
1290 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
1291 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
1292 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
1293 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
1294 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
1295 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
1296 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
1297 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
1298 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
1299 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
1300 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
1301 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
1302 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
1303 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
1304 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
1305 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
1306 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
1307 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
1308 #define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
1309 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
1310 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
1311 #define CEC_BASE (APB1PERIPH_BASE + 0x7800)
1312 
1313 #define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
1314 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
1315 #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
1316 #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
1317 #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
1318 #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
1319 #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
1320 #define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
1321 #define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
1322 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
1323 #define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
1324 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
1325 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
1326 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
1327 #define USART1_BASE (APB2PERIPH_BASE + 0x3800)
1328 #define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
1329 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
1330 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
1331 #define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
1332 #define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)
1333 #define TIM10_BASE (APB2PERIPH_BASE + 0x5000)
1334 #define TIM11_BASE (APB2PERIPH_BASE + 0x5400)
1335 
1336 #define SDIO_BASE (PERIPH_BASE + 0x18000)
1337 
1338 #define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
1339 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
1340 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
1341 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
1342 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
1343 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
1344 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
1345 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
1346 #define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
1347 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
1348 #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
1349 #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
1350 #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
1351 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
1352 #define RCC_BASE (AHBPERIPH_BASE + 0x1000)
1353 #define CRC_BASE (AHBPERIPH_BASE + 0x3000)
1354 
1355 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
1356 #define OB_BASE ((uint32_t)0x1FFFF800)
1358 #define ETH_BASE (AHBPERIPH_BASE + 0x8000)
1359 #define ETH_MAC_BASE (ETH_BASE)
1360 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
1361 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
1362 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
1363 
1364 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
1365 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
1366 #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
1367 #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
1368 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
1370 #define DBGMCU_BASE ((uint32_t)0xE0042000)
1380 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1381 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1382 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1383 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1384 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1385 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1386 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1387 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1388 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1389 #define RTC ((RTC_TypeDef *) RTC_BASE)
1390 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1391 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1392 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1393 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1394 #define USART2 ((USART_TypeDef *) USART2_BASE)
1395 #define USART3 ((USART_TypeDef *) USART3_BASE)
1396 #define UART4 ((USART_TypeDef *) UART4_BASE)
1397 #define UART5 ((USART_TypeDef *) UART5_BASE)
1398 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1399 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1400 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1401 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1402 #define BKP ((BKP_TypeDef *) BKP_BASE)
1403 #define PWR ((PWR_TypeDef *) PWR_BASE)
1404 #define DAC ((DAC_TypeDef *) DAC_BASE)
1405 #define CEC ((CEC_TypeDef *) CEC_BASE)
1406 #define AFIO ((AFIO_TypeDef *) AFIO_BASE)
1407 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1408 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1409 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1410 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1411 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1412 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1413 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1414 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1415 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1416 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1417 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1418 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1419 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1420 #define USART1 ((USART_TypeDef *) USART1_BASE)
1421 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1422 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
1423 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
1424 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
1425 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1426 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1427 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1428 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1429 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1430 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1431 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1432 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1433 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1434 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1435 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1436 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1437 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1438 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1439 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1440 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1441 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1442 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1443 #define RCC ((RCC_TypeDef *) RCC_BASE)
1444 #define CRC ((CRC_TypeDef *) CRC_BASE)
1445 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1446 #define OB ((OB_TypeDef *) OB_BASE)
1447 #define ETH ((ETH_TypeDef *) ETH_BASE)
1448 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1449 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1450 #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
1451 #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
1452 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1453 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1454 
1467 /******************************************************************************/
1468 /* Peripheral Registers_Bits_Definition */
1469 /******************************************************************************/
1470 
1471 /******************************************************************************/
1472 /* */
1473 /* CRC calculation unit */
1474 /* */
1475 /******************************************************************************/
1476 
1477 /******************* Bit definition for CRC_DR register *********************/
1478 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF)
1481 /******************* Bit definition for CRC_IDR register ********************/
1482 #define CRC_IDR_IDR ((uint8_t)0xFF)
1485 /******************** Bit definition for CRC_CR register ********************/
1486 #define CRC_CR_RESET ((uint8_t)0x01)
1488 /******************************************************************************/
1489 /* */
1490 /* Power Control */
1491 /* */
1492 /******************************************************************************/
1493 
1494 /******************** Bit definition for PWR_CR register ********************/
1495 #define PWR_CR_LPDS ((uint16_t)0x0001)
1496 #define PWR_CR_PDDS ((uint16_t)0x0002)
1497 #define PWR_CR_CWUF ((uint16_t)0x0004)
1498 #define PWR_CR_CSBF ((uint16_t)0x0008)
1499 #define PWR_CR_PVDE ((uint16_t)0x0010)
1501 #define PWR_CR_PLS ((uint16_t)0x00E0)
1502 #define PWR_CR_PLS_0 ((uint16_t)0x0020)
1503 #define PWR_CR_PLS_1 ((uint16_t)0x0040)
1504 #define PWR_CR_PLS_2 ((uint16_t)0x0080)
1507 #define PWR_CR_PLS_2V2 ((uint16_t)0x0000)
1508 #define PWR_CR_PLS_2V3 ((uint16_t)0x0020)
1509 #define PWR_CR_PLS_2V4 ((uint16_t)0x0040)
1510 #define PWR_CR_PLS_2V5 ((uint16_t)0x0060)
1511 #define PWR_CR_PLS_2V6 ((uint16_t)0x0080)
1512 #define PWR_CR_PLS_2V7 ((uint16_t)0x00A0)
1513 #define PWR_CR_PLS_2V8 ((uint16_t)0x00C0)
1514 #define PWR_CR_PLS_2V9 ((uint16_t)0x00E0)
1516 #define PWR_CR_DBP ((uint16_t)0x0100)
1519 /******************* Bit definition for PWR_CSR register ********************/
1520 #define PWR_CSR_WUF ((uint16_t)0x0001)
1521 #define PWR_CSR_SBF ((uint16_t)0x0002)
1522 #define PWR_CSR_PVDO ((uint16_t)0x0004)
1523 #define PWR_CSR_EWUP ((uint16_t)0x0100)
1525 /******************************************************************************/
1526 /* */
1527 /* Backup registers */
1528 /* */
1529 /******************************************************************************/
1530 
1531 /******************* Bit definition for BKP_DR1 register ********************/
1532 #define BKP_DR1_D ((uint16_t)0xFFFF)
1534 /******************* Bit definition for BKP_DR2 register ********************/
1535 #define BKP_DR2_D ((uint16_t)0xFFFF)
1537 /******************* Bit definition for BKP_DR3 register ********************/
1538 #define BKP_DR3_D ((uint16_t)0xFFFF)
1540 /******************* Bit definition for BKP_DR4 register ********************/
1541 #define BKP_DR4_D ((uint16_t)0xFFFF)
1543 /******************* Bit definition for BKP_DR5 register ********************/
1544 #define BKP_DR5_D ((uint16_t)0xFFFF)
1546 /******************* Bit definition for BKP_DR6 register ********************/
1547 #define BKP_DR6_D ((uint16_t)0xFFFF)
1549 /******************* Bit definition for BKP_DR7 register ********************/
1550 #define BKP_DR7_D ((uint16_t)0xFFFF)
1552 /******************* Bit definition for BKP_DR8 register ********************/
1553 #define BKP_DR8_D ((uint16_t)0xFFFF)
1555 /******************* Bit definition for BKP_DR9 register ********************/
1556 #define BKP_DR9_D ((uint16_t)0xFFFF)
1558 /******************* Bit definition for BKP_DR10 register *******************/
1559 #define BKP_DR10_D ((uint16_t)0xFFFF)
1561 /******************* Bit definition for BKP_DR11 register *******************/
1562 #define BKP_DR11_D ((uint16_t)0xFFFF)
1564 /******************* Bit definition for BKP_DR12 register *******************/
1565 #define BKP_DR12_D ((uint16_t)0xFFFF)
1567 /******************* Bit definition for BKP_DR13 register *******************/
1568 #define BKP_DR13_D ((uint16_t)0xFFFF)
1570 /******************* Bit definition for BKP_DR14 register *******************/
1571 #define BKP_DR14_D ((uint16_t)0xFFFF)
1573 /******************* Bit definition for BKP_DR15 register *******************/
1574 #define BKP_DR15_D ((uint16_t)0xFFFF)
1576 /******************* Bit definition for BKP_DR16 register *******************/
1577 #define BKP_DR16_D ((uint16_t)0xFFFF)
1579 /******************* Bit definition for BKP_DR17 register *******************/
1580 #define BKP_DR17_D ((uint16_t)0xFFFF)
1582 /****************** Bit definition for BKP_DR18 register ********************/
1583 #define BKP_DR18_D ((uint16_t)0xFFFF)
1585 /******************* Bit definition for BKP_DR19 register *******************/
1586 #define BKP_DR19_D ((uint16_t)0xFFFF)
1588 /******************* Bit definition for BKP_DR20 register *******************/
1589 #define BKP_DR20_D ((uint16_t)0xFFFF)
1591 /******************* Bit definition for BKP_DR21 register *******************/
1592 #define BKP_DR21_D ((uint16_t)0xFFFF)
1594 /******************* Bit definition for BKP_DR22 register *******************/
1595 #define BKP_DR22_D ((uint16_t)0xFFFF)
1597 /******************* Bit definition for BKP_DR23 register *******************/
1598 #define BKP_DR23_D ((uint16_t)0xFFFF)
1600 /******************* Bit definition for BKP_DR24 register *******************/
1601 #define BKP_DR24_D ((uint16_t)0xFFFF)
1603 /******************* Bit definition for BKP_DR25 register *******************/
1604 #define BKP_DR25_D ((uint16_t)0xFFFF)
1606 /******************* Bit definition for BKP_DR26 register *******************/
1607 #define BKP_DR26_D ((uint16_t)0xFFFF)
1609 /******************* Bit definition for BKP_DR27 register *******************/
1610 #define BKP_DR27_D ((uint16_t)0xFFFF)
1612 /******************* Bit definition for BKP_DR28 register *******************/
1613 #define BKP_DR28_D ((uint16_t)0xFFFF)
1615 /******************* Bit definition for BKP_DR29 register *******************/
1616 #define BKP_DR29_D ((uint16_t)0xFFFF)
1618 /******************* Bit definition for BKP_DR30 register *******************/
1619 #define BKP_DR30_D ((uint16_t)0xFFFF)
1621 /******************* Bit definition for BKP_DR31 register *******************/
1622 #define BKP_DR31_D ((uint16_t)0xFFFF)
1624 /******************* Bit definition for BKP_DR32 register *******************/
1625 #define BKP_DR32_D ((uint16_t)0xFFFF)
1627 /******************* Bit definition for BKP_DR33 register *******************/
1628 #define BKP_DR33_D ((uint16_t)0xFFFF)
1630 /******************* Bit definition for BKP_DR34 register *******************/
1631 #define BKP_DR34_D ((uint16_t)0xFFFF)
1633 /******************* Bit definition for BKP_DR35 register *******************/
1634 #define BKP_DR35_D ((uint16_t)0xFFFF)
1636 /******************* Bit definition for BKP_DR36 register *******************/
1637 #define BKP_DR36_D ((uint16_t)0xFFFF)
1639 /******************* Bit definition for BKP_DR37 register *******************/
1640 #define BKP_DR37_D ((uint16_t)0xFFFF)
1642 /******************* Bit definition for BKP_DR38 register *******************/
1643 #define BKP_DR38_D ((uint16_t)0xFFFF)
1645 /******************* Bit definition for BKP_DR39 register *******************/
1646 #define BKP_DR39_D ((uint16_t)0xFFFF)
1648 /******************* Bit definition for BKP_DR40 register *******************/
1649 #define BKP_DR40_D ((uint16_t)0xFFFF)
1651 /******************* Bit definition for BKP_DR41 register *******************/
1652 #define BKP_DR41_D ((uint16_t)0xFFFF)
1654 /******************* Bit definition for BKP_DR42 register *******************/
1655 #define BKP_DR42_D ((uint16_t)0xFFFF)
1657 /****************** Bit definition for BKP_RTCCR register *******************/
1658 #define BKP_RTCCR_CAL ((uint16_t)0x007F)
1659 #define BKP_RTCCR_CCO ((uint16_t)0x0080)
1660 #define BKP_RTCCR_ASOE ((uint16_t)0x0100)
1661 #define BKP_RTCCR_ASOS ((uint16_t)0x0200)
1663 /******************** Bit definition for BKP_CR register ********************/
1664 #define BKP_CR_TPE ((uint8_t)0x01)
1665 #define BKP_CR_TPAL ((uint8_t)0x02)
1667 /******************* Bit definition for BKP_CSR register ********************/
1668 #define BKP_CSR_CTE ((uint16_t)0x0001)
1669 #define BKP_CSR_CTI ((uint16_t)0x0002)
1670 #define BKP_CSR_TPIE ((uint16_t)0x0004)
1671 #define BKP_CSR_TEF ((uint16_t)0x0100)
1672 #define BKP_CSR_TIF ((uint16_t)0x0200)
1674 /******************************************************************************/
1675 /* */
1676 /* Reset and Clock Control */
1677 /* */
1678 /******************************************************************************/
1679 
1680 /******************** Bit definition for RCC_CR register ********************/
1681 #define RCC_CR_HSION ((uint32_t)0x00000001)
1682 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
1683 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
1684 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
1685 #define RCC_CR_HSEON ((uint32_t)0x00010000)
1686 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
1687 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
1688 #define RCC_CR_CSSON ((uint32_t)0x00080000)
1689 #define RCC_CR_PLLON ((uint32_t)0x01000000)
1690 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
1692 #ifdef STM32F10X_CL
1693  #define RCC_CR_PLL2ON ((uint32_t)0x04000000)
1694  #define RCC_CR_PLL2RDY ((uint32_t)0x08000000)
1695  #define RCC_CR_PLL3ON ((uint32_t)0x10000000)
1696  #define RCC_CR_PLL3RDY ((uint32_t)0x20000000)
1697 #endif /* STM32F10X_CL */
1698 
1699 /******************* Bit definition for RCC_CFGR register *******************/
1701 #define RCC_CFGR_SW ((uint32_t)0x00000003)
1702 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001)
1703 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002)
1705 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000)
1706 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001)
1707 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002)
1710 #define RCC_CFGR_SWS ((uint32_t)0x0000000C)
1711 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004)
1712 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008)
1714 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000)
1715 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004)
1716 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008)
1719 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0)
1720 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010)
1721 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020)
1722 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040)
1723 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080)
1725 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000)
1726 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080)
1727 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090)
1728 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0)
1729 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0)
1730 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0)
1731 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0)
1732 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0)
1733 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0)
1736 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700)
1737 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100)
1738 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200)
1739 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400)
1741 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000)
1742 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400)
1743 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500)
1744 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600)
1745 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700)
1748 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800)
1749 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800)
1750 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000)
1751 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000)
1753 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000)
1754 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000)
1755 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800)
1756 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000)
1757 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800)
1760 #define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000)
1761 #define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000)
1762 #define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000)
1764 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000)
1765 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000)
1766 #define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000)
1767 #define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000)
1769 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000)
1771 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000)
1774 #define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000)
1775 #define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000)
1776 #define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000)
1777 #define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000)
1778 #define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000)
1780 #ifdef STM32F10X_CL
1781  #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000)
1782  #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000)
1784  #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000)
1785  #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000)
1787  #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000)
1788  #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000)
1789  #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000)
1790  #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000)
1791  #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000)
1792  #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000)
1793  #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000)
1795  #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000)
1798  #define RCC_CFGR_MCO ((uint32_t)0x0F000000)
1799  #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000)
1800  #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000)
1801  #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000)
1802  #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000)
1804  #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000)
1805  #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000)
1806  #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000)
1807  #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000)
1808  #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000)
1809  #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000)
1810  #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000)
1811  #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000)
1812  #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000)
1813 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
1814  #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000)
1815  #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000)
1817  #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000)
1818  #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000)
1820  #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000)
1821  #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000)
1822  #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000)
1823  #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000)
1824  #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000)
1825  #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000)
1826  #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000)
1827  #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000)
1828  #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000)
1829  #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000)
1830  #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000)
1831  #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000)
1832  #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000)
1833  #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000)
1834  #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000)
1837  #define RCC_CFGR_MCO ((uint32_t)0x07000000)
1838  #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000)
1839  #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000)
1840  #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000)
1842  #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000)
1843  #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000)
1844  #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000)
1845  #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000)
1846  #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000)
1847 #else
1848  #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000)
1849  #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000)
1851  #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000)
1852  #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000)
1854  #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000)
1855  #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000)
1856  #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000)
1857  #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000)
1858  #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000)
1859  #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000)
1860  #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000)
1861  #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000)
1862  #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000)
1863  #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000)
1864  #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000)
1865  #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000)
1866  #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000)
1867  #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000)
1868  #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000)
1869  #define RCC_CFGR_USBPRE ((uint32_t)0x00400000)
1872  #define RCC_CFGR_MCO ((uint32_t)0x07000000)
1873  #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000)
1874  #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000)
1875  #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000)
1877  #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000)
1878  #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000)
1879  #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000)
1880  #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000)
1881  #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000)
1882 #endif /* STM32F10X_CL */
1883 
1885 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
1886 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
1887 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
1888 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
1889 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
1890 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
1891 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
1892 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
1893 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
1894 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
1895 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
1896 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
1897 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
1898 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
1899 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
1900 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
1901 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
1903 #ifdef STM32F10X_CL
1904  #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020)
1905  #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040)
1906  #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000)
1907  #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000)
1908  #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000)
1909  #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000)
1910 #endif /* STM32F10X_CL */
1911 
1912 /***************** Bit definition for RCC_APB2RSTR register *****************/
1913 #define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001)
1914 #define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004)
1915 #define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008)
1916 #define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010)
1917 #define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020)
1918 #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200)
1920 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
1921 #define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400)
1922 #endif
1923 
1924 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800)
1925 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
1926 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000)
1928 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
1929 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000)
1930 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000)
1931 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000)
1932 #endif
1933 
1934 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
1935  #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040)
1936 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
1937 
1938 #if defined (STM32F10X_HD) || defined (STM32F10X_XL)
1939  #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080)
1940  #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100)
1941  #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000)
1942  #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000)
1943 #endif
1944 
1945 #if defined (STM32F10X_HD_VL)
1946  #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080)
1947  #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100)
1948 #endif
1949 
1950 #ifdef STM32F10X_XL
1951  #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000)
1952  #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000)
1953  #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000)
1954 #endif /* STM32F10X_XL */
1955 
1956 /***************** Bit definition for RCC_APB1RSTR register *****************/
1957 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
1958 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
1959 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
1960 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
1961 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
1963 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
1964 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
1965 #endif
1966 
1967 #define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000)
1968 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
1970 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
1971  #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
1972  #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
1973  #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
1974  #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
1975 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
1976 
1977 #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL)
1978  #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000)
1979 #endif
1980 
1981 #if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL)
1982  #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
1983  #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
1984  #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
1985  #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
1986  #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
1987  #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
1988  #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
1989 #endif
1990 
1991 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
1992  #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
1993  #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
1994  #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
1995  #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000)
1996 #endif
1997 
1998 #if defined (STM32F10X_HD_VL)
1999  #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
2000  #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
2001  #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
2002  #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
2003  #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
2004  #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
2005  #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
2006 #endif
2007 
2008 #ifdef STM32F10X_CL
2009  #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
2010 #endif /* STM32F10X_CL */
2011 
2012 #ifdef STM32F10X_XL
2013  #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
2014  #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
2015  #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
2016 #endif /* STM32F10X_XL */
2017 
2018 /****************** Bit definition for RCC_AHBENR register ******************/
2019 #define RCC_AHBENR_DMA1EN ((uint16_t)0x0001)
2020 #define RCC_AHBENR_SRAMEN ((uint16_t)0x0004)
2021 #define RCC_AHBENR_FLITFEN ((uint16_t)0x0010)
2022 #define RCC_AHBENR_CRCEN ((uint16_t)0x0040)
2024 #if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL)
2025  #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002)
2026 #endif
2027 
2028 #if defined (STM32F10X_HD) || defined (STM32F10X_XL)
2029  #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100)
2030  #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400)
2031 #endif
2032 
2033 #if defined (STM32F10X_HD_VL)
2034  #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100)
2035 #endif
2036 
2037 #ifdef STM32F10X_CL
2038  #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000)
2039  #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000)
2040  #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000)
2041  #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000)
2042 #endif /* STM32F10X_CL */
2043 
2044 /****************** Bit definition for RCC_APB2ENR register *****************/
2045 #define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001)
2046 #define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004)
2047 #define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008)
2048 #define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010)
2049 #define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020)
2050 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200)
2052 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
2053 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400)
2054 #endif
2055 
2056 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800)
2057 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
2058 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000)
2060 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
2061 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000)
2062 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000)
2063 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000)
2064 #endif
2065 
2066 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
2067  #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040)
2068 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
2069 
2070 #if defined (STM32F10X_HD) || defined (STM32F10X_XL)
2071  #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080)
2072  #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100)
2073  #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000)
2074  #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000)
2075 #endif
2076 
2077 #if defined (STM32F10X_HD_VL)
2078  #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080)
2079  #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100)
2080 #endif
2081 
2082 #ifdef STM32F10X_XL
2083  #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000)
2084  #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000)
2085  #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000)
2086 #endif
2087 
2088 /***************** Bit definition for RCC_APB1ENR register ******************/
2089 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
2090 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
2091 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
2092 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
2093 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
2095 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
2096 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
2097 #endif
2098 
2099 #define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000)
2100 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
2102 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
2103  #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
2104  #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
2105  #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
2106  #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
2107 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
2108 
2109 #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
2110  #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000)
2111 #endif
2112 
2113 #if defined (STM32F10X_HD) || defined (STM32F10X_CL)
2114  #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
2115  #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
2116  #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
2117  #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
2118  #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
2119  #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
2120  #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
2121 #endif
2122 
2123 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
2124  #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
2125  #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
2126  #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
2127  #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000)
2128 #endif
2129 
2130 #ifdef STM32F10X_HD_VL
2131  #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
2132  #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
2133  #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
2134  #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
2135  #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
2136  #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
2137  #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
2138 #endif /* STM32F10X_HD_VL */
2139 
2140 #ifdef STM32F10X_CL
2141  #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
2142 #endif /* STM32F10X_CL */
2143 
2144 #ifdef STM32F10X_XL
2145  #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
2146  #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
2147  #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
2148 #endif /* STM32F10X_XL */
2149 
2150 /******************* Bit definition for RCC_BDCR register *******************/
2151 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
2152 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
2153 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
2155 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
2156 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
2157 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
2160 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000)
2161 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100)
2162 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200)
2163 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300)
2165 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
2166 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
2168 /******************* Bit definition for RCC_CSR register ********************/
2169 #define RCC_CSR_LSION ((uint32_t)0x00000001)
2170 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
2171 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
2172 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000)
2173 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
2174 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
2175 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)
2176 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
2177 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
2179 #ifdef STM32F10X_CL
2180 /******************* Bit definition for RCC_AHBRSTR register ****************/
2181  #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000)
2182  #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000)
2184 /******************* Bit definition for RCC_CFGR2 register ******************/
2185 
2186  #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F)
2187  #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001)
2188  #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002)
2189  #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004)
2190  #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008)
2192  #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000)
2193  #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001)
2194  #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002)
2195  #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003)
2196  #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004)
2197  #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005)
2198  #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006)
2199  #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007)
2200  #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008)
2201  #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009)
2202  #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A)
2203  #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B)
2204  #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C)
2205  #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D)
2206  #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E)
2207  #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F)
2210  #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0)
2211  #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010)
2212  #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020)
2213  #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040)
2214  #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080)
2216  #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000)
2217  #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010)
2218  #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020)
2219  #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030)
2220  #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040)
2221  #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050)
2222  #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060)
2223  #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070)
2224  #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080)
2225  #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090)
2226  #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0)
2227  #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0)
2228  #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0)
2229  #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0)
2230  #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0)
2231  #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0)
2234  #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00)
2235  #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100)
2236  #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200)
2237  #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400)
2238  #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800)
2240  #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600)
2241  #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700)
2242  #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800)
2243  #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900)
2244  #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00)
2245  #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00)
2246  #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00)
2247  #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00)
2248  #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00)
2251  #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000)
2252  #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000)
2253  #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000)
2254  #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000)
2255  #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000)
2257  #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000)
2258  #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000)
2259  #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000)
2260  #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000)
2261  #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000)
2262  #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000)
2263  #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000)
2264  #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000)
2265  #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000)
2267  #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000)
2268  #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000)
2269  #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000)
2270  #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000)
2271  #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000)
2272 #endif /* STM32F10X_CL */
2273 
2274 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
2275 /******************* Bit definition for RCC_CFGR2 register ******************/
2277  #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F)
2278  #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001)
2279  #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002)
2280  #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004)
2281  #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008)
2283  #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000)
2284  #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001)
2285  #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002)
2286  #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003)
2287  #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004)
2288  #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005)
2289  #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006)
2290  #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007)
2291  #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008)
2292  #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009)
2293  #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A)
2294  #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B)
2295  #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C)
2296  #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D)
2297  #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E)
2298  #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F)
2299 #endif
2300 
2301 /******************************************************************************/
2302 /* */
2303 /* General Purpose and Alternate Function I/O */
2304 /* */
2305 /******************************************************************************/
2306 
2307 /******************* Bit definition for GPIO_CRL register *******************/
2308 #define GPIO_CRL_MODE ((uint32_t)0x33333333)
2310 #define GPIO_CRL_MODE0 ((uint32_t)0x00000003)
2311 #define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001)
2312 #define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002)
2314 #define GPIO_CRL_MODE1 ((uint32_t)0x00000030)
2315 #define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010)
2316 #define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020)
2318 #define GPIO_CRL_MODE2 ((uint32_t)0x00000300)
2319 #define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100)
2320 #define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200)
2322 #define GPIO_CRL_MODE3 ((uint32_t)0x00003000)
2323 #define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000)
2324 #define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000)
2326 #define GPIO_CRL_MODE4 ((uint32_t)0x00030000)
2327 #define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000)
2328 #define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000)
2330 #define GPIO_CRL_MODE5 ((uint32_t)0x00300000)
2331 #define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000)
2332 #define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000)
2334 #define GPIO_CRL_MODE6 ((uint32_t)0x03000000)
2335 #define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000)
2336 #define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000)
2338 #define GPIO_CRL_MODE7 ((uint32_t)0x30000000)
2339 #define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000)
2340 #define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000)
2342 #define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC)
2344 #define GPIO_CRL_CNF0 ((uint32_t)0x0000000C)
2345 #define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004)
2346 #define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008)
2348 #define GPIO_CRL_CNF1 ((uint32_t)0x000000C0)
2349 #define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040)
2350 #define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080)
2352 #define GPIO_CRL_CNF2 ((uint32_t)0x00000C00)
2353 #define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400)
2354 #define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800)
2356 #define GPIO_CRL_CNF3 ((uint32_t)0x0000C000)
2357 #define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000)
2358 #define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000)
2360 #define GPIO_CRL_CNF4 ((uint32_t)0x000C0000)
2361 #define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000)
2362 #define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000)
2364 #define GPIO_CRL_CNF5 ((uint32_t)0x00C00000)
2365 #define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000)
2366 #define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000)
2368 #define GPIO_CRL_CNF6 ((uint32_t)0x0C000000)
2369 #define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000)
2370 #define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000)
2372 #define GPIO_CRL_CNF7 ((uint32_t)0xC0000000)
2373 #define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000)
2374 #define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000)
2376 /******************* Bit definition for GPIO_CRH register *******************/
2377 #define GPIO_CRH_MODE ((uint32_t)0x33333333)
2379 #define GPIO_CRH_MODE8 ((uint32_t)0x00000003)
2380 #define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001)
2381 #define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002)
2383 #define GPIO_CRH_MODE9 ((uint32_t)0x00000030)
2384 #define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010)
2385 #define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020)
2387 #define GPIO_CRH_MODE10 ((uint32_t)0x00000300)
2388 #define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100)
2389 #define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200)
2391 #define GPIO_CRH_MODE11 ((uint32_t)0x00003000)
2392 #define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000)
2393 #define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000)
2395 #define GPIO_CRH_MODE12 ((uint32_t)0x00030000)
2396 #define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000)
2397 #define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000)
2399 #define GPIO_CRH_MODE13 ((uint32_t)0x00300000)
2400 #define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000)
2401 #define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000)
2403 #define GPIO_CRH_MODE14 ((uint32_t)0x03000000)
2404 #define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000)
2405 #define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000)
2407 #define GPIO_CRH_MODE15 ((uint32_t)0x30000000)
2408 #define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000)
2409 #define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000)
2411 #define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC)
2413 #define GPIO_CRH_CNF8 ((uint32_t)0x0000000C)
2414 #define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004)
2415 #define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008)
2417 #define GPIO_CRH_CNF9 ((uint32_t)0x000000C0)
2418 #define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040)
2419 #define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080)
2421 #define GPIO_CRH_CNF10 ((uint32_t)0x00000C00)
2422 #define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400)
2423 #define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800)
2425 #define GPIO_CRH_CNF11 ((uint32_t)0x0000C000)
2426 #define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000)
2427 #define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000)
2429 #define GPIO_CRH_CNF12 ((uint32_t)0x000C0000)
2430 #define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000)
2431 #define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000)
2433 #define GPIO_CRH_CNF13 ((uint32_t)0x00C00000)
2434 #define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000)
2435 #define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000)
2437 #define GPIO_CRH_CNF14 ((uint32_t)0x0C000000)
2438 #define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000)
2439 #define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000)
2441 #define GPIO_CRH_CNF15 ((uint32_t)0xC0000000)
2442 #define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000)
2443 #define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000)
2446 #define GPIO_IDR_IDR0 ((uint16_t)0x0001)
2447 #define GPIO_IDR_IDR1 ((uint16_t)0x0002)
2448 #define GPIO_IDR_IDR2 ((uint16_t)0x0004)
2449 #define GPIO_IDR_IDR3 ((uint16_t)0x0008)
2450 #define GPIO_IDR_IDR4 ((uint16_t)0x0010)
2451 #define GPIO_IDR_IDR5 ((uint16_t)0x0020)
2452 #define GPIO_IDR_IDR6 ((uint16_t)0x0040)
2453 #define GPIO_IDR_IDR7 ((uint16_t)0x0080)
2454 #define GPIO_IDR_IDR8 ((uint16_t)0x0100)
2455 #define GPIO_IDR_IDR9 ((uint16_t)0x0200)
2456 #define GPIO_IDR_IDR10 ((uint16_t)0x0400)
2457 #define GPIO_IDR_IDR11 ((uint16_t)0x0800)
2458 #define GPIO_IDR_IDR12 ((uint16_t)0x1000)
2459 #define GPIO_IDR_IDR13 ((uint16_t)0x2000)
2460 #define GPIO_IDR_IDR14 ((uint16_t)0x4000)
2461 #define GPIO_IDR_IDR15 ((uint16_t)0x8000)
2463 /******************* Bit definition for GPIO_ODR register *******************/
2464 #define GPIO_ODR_ODR0 ((uint16_t)0x0001)
2465 #define GPIO_ODR_ODR1 ((uint16_t)0x0002)
2466 #define GPIO_ODR_ODR2 ((uint16_t)0x0004)
2467 #define GPIO_ODR_ODR3 ((uint16_t)0x0008)
2468 #define GPIO_ODR_ODR4 ((uint16_t)0x0010)
2469 #define GPIO_ODR_ODR5 ((uint16_t)0x0020)
2470 #define GPIO_ODR_ODR6 ((uint16_t)0x0040)
2471 #define GPIO_ODR_ODR7 ((uint16_t)0x0080)
2472 #define GPIO_ODR_ODR8 ((uint16_t)0x0100)
2473 #define GPIO_ODR_ODR9 ((uint16_t)0x0200)
2474 #define GPIO_ODR_ODR10 ((uint16_t)0x0400)
2475 #define GPIO_ODR_ODR11 ((uint16_t)0x0800)
2476 #define GPIO_ODR_ODR12 ((uint16_t)0x1000)
2477 #define GPIO_ODR_ODR13 ((uint16_t)0x2000)
2478 #define GPIO_ODR_ODR14 ((uint16_t)0x4000)
2479 #define GPIO_ODR_ODR15 ((uint16_t)0x8000)
2481 /****************** Bit definition for GPIO_BSRR register *******************/
2482 #define GPIO_BSRR_BS0 ((uint32_t)0x00000001)
2483 #define GPIO_BSRR_BS1 ((uint32_t)0x00000002)
2484 #define GPIO_BSRR_BS2 ((uint32_t)0x00000004)
2485 #define GPIO_BSRR_BS3 ((uint32_t)0x00000008)
2486 #define GPIO_BSRR_BS4 ((uint32_t)0x00000010)
2487 #define GPIO_BSRR_BS5 ((uint32_t)0x00000020)
2488 #define GPIO_BSRR_BS6 ((uint32_t)0x00000040)
2489 #define GPIO_BSRR_BS7 ((uint32_t)0x00000080)
2490 #define GPIO_BSRR_BS8 ((uint32_t)0x00000100)
2491 #define GPIO_BSRR_BS9 ((uint32_t)0x00000200)
2492 #define GPIO_BSRR_BS10 ((uint32_t)0x00000400)
2493 #define GPIO_BSRR_BS11 ((uint32_t)0x00000800)
2494 #define GPIO_BSRR_BS12 ((uint32_t)0x00001000)
2495 #define GPIO_BSRR_BS13 ((uint32_t)0x00002000)
2496 #define GPIO_BSRR_BS14 ((uint32_t)0x00004000)
2497 #define GPIO_BSRR_BS15 ((uint32_t)0x00008000)
2499 #define GPIO_BSRR_BR0 ((uint32_t)0x00010000)
2500 #define GPIO_BSRR_BR1 ((uint32_t)0x00020000)
2501 #define GPIO_BSRR_BR2 ((uint32_t)0x00040000)
2502 #define GPIO_BSRR_BR3 ((uint32_t)0x00080000)
2503 #define GPIO_BSRR_BR4 ((uint32_t)0x00100000)
2504 #define GPIO_BSRR_BR5 ((uint32_t)0x00200000)
2505 #define GPIO_BSRR_BR6 ((uint32_t)0x00400000)
2506 #define GPIO_BSRR_BR7 ((uint32_t)0x00800000)
2507 #define GPIO_BSRR_BR8 ((uint32_t)0x01000000)
2508 #define GPIO_BSRR_BR9 ((uint32_t)0x02000000)
2509 #define GPIO_BSRR_BR10 ((uint32_t)0x04000000)
2510 #define GPIO_BSRR_BR11 ((uint32_t)0x08000000)
2511 #define GPIO_BSRR_BR12 ((uint32_t)0x10000000)
2512 #define GPIO_BSRR_BR13 ((uint32_t)0x20000000)
2513 #define GPIO_BSRR_BR14 ((uint32_t)0x40000000)
2514 #define GPIO_BSRR_BR15 ((uint32_t)0x80000000)
2516 /******************* Bit definition for GPIO_BRR register *******************/
2517 #define GPIO_BRR_BR0 ((uint16_t)0x0001)
2518 #define GPIO_BRR_BR1 ((uint16_t)0x0002)
2519 #define GPIO_BRR_BR2 ((uint16_t)0x0004)
2520 #define GPIO_BRR_BR3 ((uint16_t)0x0008)
2521 #define GPIO_BRR_BR4 ((uint16_t)0x0010)
2522 #define GPIO_BRR_BR5 ((uint16_t)0x0020)
2523 #define GPIO_BRR_BR6 ((uint16_t)0x0040)
2524 #define GPIO_BRR_BR7 ((uint16_t)0x0080)
2525 #define GPIO_BRR_BR8 ((uint16_t)0x0100)
2526 #define GPIO_BRR_BR9 ((uint16_t)0x0200)
2527 #define GPIO_BRR_BR10 ((uint16_t)0x0400)
2528 #define GPIO_BRR_BR11 ((uint16_t)0x0800)
2529 #define GPIO_BRR_BR12 ((uint16_t)0x1000)
2530 #define GPIO_BRR_BR13 ((uint16_t)0x2000)
2531 #define GPIO_BRR_BR14 ((uint16_t)0x4000)
2532 #define GPIO_BRR_BR15 ((uint16_t)0x8000)
2534 /****************** Bit definition for GPIO_LCKR register *******************/
2535 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
2536 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
2537 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
2538 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
2539 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
2540 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
2541 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
2542 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
2543 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
2544 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
2545 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
2546 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
2547 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
2548 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
2549 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
2550 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
2551 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
2553 /*----------------------------------------------------------------------------*/
2554 
2555 /****************** Bit definition for AFIO_EVCR register *******************/
2556 #define AFIO_EVCR_PIN ((uint8_t)0x0F)
2557 #define AFIO_EVCR_PIN_0 ((uint8_t)0x01)
2558 #define AFIO_EVCR_PIN_1 ((uint8_t)0x02)
2559 #define AFIO_EVCR_PIN_2 ((uint8_t)0x04)
2560 #define AFIO_EVCR_PIN_3 ((uint8_t)0x08)
2563 #define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00)
2564 #define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01)
2565 #define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02)
2566 #define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03)
2567 #define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04)
2568 #define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05)
2569 #define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06)
2570 #define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07)
2571 #define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08)
2572 #define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09)
2573 #define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A)
2574 #define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B)
2575 #define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C)
2576 #define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D)
2577 #define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E)
2578 #define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F)
2580 #define AFIO_EVCR_PORT ((uint8_t)0x70)
2581 #define AFIO_EVCR_PORT_0 ((uint8_t)0x10)
2582 #define AFIO_EVCR_PORT_1 ((uint8_t)0x20)
2583 #define AFIO_EVCR_PORT_2 ((uint8_t)0x40)
2586 #define AFIO_EVCR_PORT_PA ((uint8_t)0x00)
2587 #define AFIO_EVCR_PORT_PB ((uint8_t)0x10)
2588 #define AFIO_EVCR_PORT_PC ((uint8_t)0x20)
2589 #define AFIO_EVCR_PORT_PD ((uint8_t)0x30)
2590 #define AFIO_EVCR_PORT_PE ((uint8_t)0x40)
2592 #define AFIO_EVCR_EVOE ((uint8_t)0x80)
2594 /****************** Bit definition for AFIO_MAPR register *******************/
2595 #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001)
2596 #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002)
2597 #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004)
2598 #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008)
2600 #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030)
2601 #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010)
2602 #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020)
2604 /* USART3_REMAP configuration */
2605 #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000)
2606 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010)
2607 #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030)
2609 #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0)
2610 #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040)
2611 #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080)
2614 #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000)
2615 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040)
2616 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0)
2618 #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300)
2619 #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100)
2620 #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200)
2623 #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000)
2624 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100)
2625 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200)
2626 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300)
2628 #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00)
2629 #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400)
2630 #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800)
2633 #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000)
2634 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800)
2635 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00)
2637 #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000)
2639 #define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000)
2640 #define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000)
2641 #define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000)
2644 #define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000)
2645 #define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000)
2646 #define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000)
2648 #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000)
2649 #define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000)
2650 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000)
2651 #define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000)
2652 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000)
2653 #define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000)
2656 #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000)
2657 #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000)
2658 #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000)
2659 #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000)
2661 #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000)
2662 #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000)
2663 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000)
2664 #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000)
2666 #ifdef STM32F10X_CL
2667 
2668  #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000)
2671  #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000)
2674  #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000)
2677  #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000)
2680  #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000)
2683  #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000)
2684 #endif
2685 
2686 /***************** Bit definition for AFIO_EXTICR1 register *****************/
2687 #define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F)
2688 #define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0)
2689 #define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00)
2690 #define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000)
2693 #define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000)
2694 #define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001)
2695 #define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002)
2696 #define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003)
2697 #define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004)
2698 #define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005)
2699 #define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006)
2702 #define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000)
2703 #define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010)
2704 #define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020)
2705 #define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030)
2706 #define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040)
2707 #define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050)
2708 #define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060)
2711 #define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000)
2712 #define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100)
2713 #define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200)
2714 #define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300)
2715 #define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400)
2716 #define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500)
2717 #define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600)
2720 #define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000)
2721 #define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000)
2722 #define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000)
2723 #define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000)
2724 #define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000)
2725 #define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000)
2726 #define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000)
2728 /***************** Bit definition for AFIO_EXTICR2 register *****************/
2729 #define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F)
2730 #define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0)
2731 #define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00)
2732 #define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000)
2735 #define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000)
2736 #define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001)
2737 #define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002)
2738 #define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003)
2739 #define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004)
2740 #define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005)
2741 #define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006)
2743 /* EXTI5 configuration */
2744 #define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000)
2745 #define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010)
2746 #define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020)
2747 #define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030)
2748 #define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040)
2749 #define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050)
2750 #define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060)
2753 #define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000)
2754 #define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100)
2755 #define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200)
2756 #define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300)
2757 #define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400)
2758 #define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500)
2759 #define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600)
2762 #define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000)
2763 #define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000)
2764 #define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000)
2765 #define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000)
2766 #define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000)
2767 #define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000)
2768 #define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000)
2770 /***************** Bit definition for AFIO_EXTICR3 register *****************/
2771 #define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F)
2772 #define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0)
2773 #define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00)
2774 #define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000)
2777 #define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000)
2778 #define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001)
2779 #define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002)
2780 #define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003)
2781 #define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004)
2782 #define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005)
2783 #define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006)
2786 #define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000)
2787 #define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010)
2788 #define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020)
2789 #define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030)
2790 #define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040)
2791 #define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050)
2792 #define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060)
2795 #define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000)
2796 #define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100)
2797 #define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200)
2798 #define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300)
2799 #define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400)
2800 #define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500)
2801 #define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600)
2804 #define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000)
2805 #define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000)
2806 #define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000)
2807 #define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000)
2808 #define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000)
2809 #define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000)
2810 #define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000)
2812 /***************** Bit definition for AFIO_EXTICR4 register *****************/
2813 #define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F)
2814 #define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0)
2815 #define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00)
2816 #define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000)
2818 /* EXTI12 configuration */
2819 #define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000)
2820 #define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001)
2821 #define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002)
2822 #define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003)
2823 #define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004)
2824 #define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005)
2825 #define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006)
2827 /* EXTI13 configuration */
2828 #define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000)
2829 #define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010)
2830 #define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020)
2831 #define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030)
2832 #define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040)
2833 #define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050)
2834 #define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060)
2837 #define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000)
2838 #define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100)
2839 #define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200)
2840 #define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300)
2841 #define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400)
2842 #define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500)
2843 #define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600)
2846 #define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000)
2847 #define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000)
2848 #define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000)
2849 #define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000)
2850 #define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000)
2851 #define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000)
2852 #define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000)
2854 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
2855 /****************** Bit definition for AFIO_MAPR2 register ******************/
2856 #define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001)
2857 #define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002)
2858 #define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004)
2859 #define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008)
2860 #define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010)
2861 #endif
2862 
2863 #ifdef STM32F10X_HD_VL
2864 #define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100)
2865 #define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200)
2866 #define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400)
2867 #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800)
2868 #define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000)
2869 #define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000)
2870 #endif
2871 
2872 #ifdef STM32F10X_XL
2873 /****************** Bit definition for AFIO_MAPR2 register ******************/
2874 #define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020)
2875 #define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040)
2876 #define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080)
2877 #define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100)
2878 #define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200)
2879 #define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400)
2880 #endif
2881 
2882 /******************************************************************************/
2883 /* */
2884 /* SystemTick */
2885 /* */
2886 /******************************************************************************/
2887 
2888 /***************** Bit definition for SysTick_CTRL register *****************/
2889 #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001)
2890 #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002)
2891 #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004)
2892 #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000)
2894 /***************** Bit definition for SysTick_LOAD register *****************/
2895 #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF)
2897 /***************** Bit definition for SysTick_VAL register ******************/
2898 #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF)
2900 /***************** Bit definition for SysTick_CALIB register ****************/
2901 #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF)
2902 #define SysTick_CALIB_SKEW ((uint32_t)0x40000000)
2903 #define SysTick_CALIB_NOREF ((uint32_t)0x80000000)
2905 /******************************************************************************/
2906 /* */
2907 /* Nested Vectored Interrupt Controller */
2908 /* */
2909 /******************************************************************************/
2910 
2911 /****************** Bit definition for NVIC_ISER register *******************/
2912 #define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF)
2913 #define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001)
2914 #define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002)
2915 #define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004)
2916 #define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008)
2917 #define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010)
2918 #define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020)
2919 #define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040)
2920 #define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080)
2921 #define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100)
2922 #define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200)
2923 #define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400)
2924 #define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800)
2925 #define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000)
2926 #define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000)
2927 #define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000)
2928 #define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000)
2929 #define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000)
2930 #define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000)
2931 #define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000)
2932 #define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000)
2933 #define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000)
2934 #define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000)
2935 #define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000)
2936 #define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000)
2937 #define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000)
2938 #define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000)
2939 #define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000)
2940 #define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000)
2941 #define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000)
2942 #define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000)
2943 #define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000)
2944 #define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000)
2946 /****************** Bit definition for NVIC_ICER register *******************/
2947 #define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF)
2948 #define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001)
2949 #define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002)
2950 #define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004)
2951 #define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008)
2952 #define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010)
2953 #define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020)
2954 #define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040)
2955 #define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080)
2956 #define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100)
2957 #define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200)
2958 #define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400)
2959 #define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800)
2960 #define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000)
2961 #define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000)
2962 #define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000)
2963 #define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000)
2964 #define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000)
2965 #define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000)
2966 #define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000)
2967 #define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000)
2968 #define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000)
2969 #define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000)
2970 #define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000)
2971 #define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000)
2972 #define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000)
2973 #define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000)
2974 #define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000)
2975 #define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000)
2976 #define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000)
2977 #define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000)
2978 #define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000)
2979 #define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000)
2981 /****************** Bit definition for NVIC_ISPR register *******************/
2982 #define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF)
2983 #define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001)
2984 #define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002)
2985 #define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004)
2986 #define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008)
2987 #define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010)
2988 #define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020)
2989 #define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040)
2990 #define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080)
2991 #define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100)
2992 #define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200)
2993 #define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400)
2994 #define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800)
2995 #define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000)
2996 #define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000)
2997 #define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000)
2998 #define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000)
2999 #define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000)
3000 #define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000)
3001 #define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000)
3002 #define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000)
3003 #define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000)
3004 #define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000)
3005 #define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000)
3006 #define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000)
3007 #define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000)
3008 #define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000)
3009 #define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000)
3010 #define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000)
3011 #define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000)
3012 #define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000)
3013 #define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000)
3014 #define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000)
3016 /****************** Bit definition for NVIC_ICPR register *******************/
3017 #define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF)
3018 #define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001)
3019 #define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002)
3020 #define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004)
3021 #define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008)
3022 #define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010)
3023 #define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020)
3024 #define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040)
3025 #define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080)
3026 #define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100)
3027 #define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200)
3028 #define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400)
3029 #define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800)
3030 #define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000)
3031 #define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000)
3032 #define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000)
3033 #define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000)
3034 #define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000)
3035 #define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000)
3036 #define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000)
3037 #define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000)
3038 #define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000)
3039 #define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000)
3040 #define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000)
3041 #define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000)
3042 #define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000)
3043 #define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000)
3044 #define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000)
3045 #define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000)
3046 #define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000)
3047 #define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000)
3048 #define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000)
3049 #define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000)
3051 /****************** Bit definition for NVIC_IABR register *******************/
3052 #define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF)
3053 #define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001)
3054 #define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002)
3055 #define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004)
3056 #define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008)
3057 #define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010)
3058 #define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020)
3059 #define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040)
3060 #define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080)
3061 #define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100)
3062 #define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200)
3063 #define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400)
3064 #define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800)
3065 #define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000)
3066 #define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000)
3067 #define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000)
3068 #define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000)
3069 #define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000)
3070 #define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000)
3071 #define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000)
3072 #define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000)
3073 #define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000)
3074 #define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000)
3075 #define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000)
3076 #define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000)
3077 #define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000)
3078 #define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000)
3079 #define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000)
3080 #define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000)
3081 #define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000)
3082 #define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000)
3083 #define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000)
3084 #define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000)
3086 /****************** Bit definition for NVIC_PRI0 register *******************/
3087 #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF)
3088 #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00)
3089 #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000)
3090 #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000)
3092 /****************** Bit definition for NVIC_PRI1 register *******************/
3093 #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF)
3094 #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00)
3095 #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000)
3096 #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000)
3098 /****************** Bit definition for NVIC_PRI2 register *******************/
3099 #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF)
3100 #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00)
3101 #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000)
3102 #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000)
3104 /****************** Bit definition for NVIC_PRI3 register *******************/
3105 #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF)
3106 #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00)
3107 #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000)
3108 #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000)
3110 /****************** Bit definition for NVIC_PRI4 register *******************/
3111 #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF)
3112 #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00)
3113 #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000)
3114 #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000)
3116 /****************** Bit definition for NVIC_PRI5 register *******************/
3117 #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF)
3118 #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00)
3119 #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000)
3120 #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000)
3122 /****************** Bit definition for NVIC_PRI6 register *******************/
3123 #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF)
3124 #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00)
3125 #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000)
3126 #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000)
3128 /****************** Bit definition for NVIC_PRI7 register *******************/
3129 #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF)
3130 #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00)
3131 #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000)
3132 #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000)
3134 /****************** Bit definition for SCB_CPUID register *******************/
3135 #define SCB_CPUID_REVISION ((uint32_t)0x0000000F)
3136 #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0)
3137 #define SCB_CPUID_Constant ((uint32_t)0x000F0000)
3138 #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000)
3139 #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000)
3141 /******************* Bit definition for SCB_ICSR register *******************/
3142 #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF)
3143 #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800)
3144 #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000)
3145 #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000)
3146 #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000)
3147 #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000)
3148 #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000)
3149 #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000)
3150 #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000)
3151 #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000)
3153 /******************* Bit definition for SCB_VTOR register *******************/
3154 #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80)
3155 #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000)
3158 #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001)
3159 #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002)
3160 #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004)
3162 #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700)
3163 #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100)
3164 #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200)
3165 #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400)
3167 /* prority group configuration */
3168 #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000)
3169 #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100)
3170 #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200)
3171 #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300)
3172 #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400)
3173 #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500)
3174 #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600)
3175 #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700)
3177 #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000)
3178 #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000)
3180 /******************* Bit definition for SCB_SCR register ********************/
3181 #define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02)
3182 #define SCB_SCR_SLEEPDEEP ((uint8_t)0x04)
3183 #define SCB_SCR_SEVONPEND ((uint8_t)0x10)
3185 /******************** Bit definition for SCB_CCR register *******************/
3186 #define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001)
3187 #define SCB_CCR_USERSETMPEND ((uint16_t)0x0002)
3188 #define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008)
3189 #define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010)
3190 #define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100)
3191 #define SCB_CCR_STKALIGN ((uint16_t)0x0200)
3193 /******************* Bit definition for SCB_SHPR register ********************/
3194 #define SCB_SHPR_PRI_N ((uint32_t)0x000000FF)
3195 #define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00)
3196 #define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000)
3197 #define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000)
3199 /****************** Bit definition for SCB_SHCSR register *******************/
3200 #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001)
3201 #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002)
3202 #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008)
3203 #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080)
3204 #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100)
3205 #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400)
3206 #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800)
3207 #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000)
3208 #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000)
3209 #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000)
3210 #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000)
3211 #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000)
3212 #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000)
3213 #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000)
3215 /******************* Bit definition for SCB_CFSR register *******************/
3216 
3217 #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001)
3218 #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002)
3219 #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008)
3220 #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010)
3221 #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080)
3223 #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100)
3224 #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200)
3225 #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400)
3226 #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800)
3227 #define SCB_CFSR_STKERR ((uint32_t)0x00001000)
3228 #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000)
3230 #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000)
3231 #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000)
3232 #define SCB_CFSR_INVPC ((uint32_t)0x00040000)
3233 #define SCB_CFSR_NOCP ((uint32_t)0x00080000)
3234 #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000)
3235 #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000)
3237 /******************* Bit definition for SCB_HFSR register *******************/
3238 #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002)
3239 #define SCB_HFSR_FORCED ((uint32_t)0x40000000)
3240 #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000)
3242 /******************* Bit definition for SCB_DFSR register *******************/
3243 #define SCB_DFSR_HALTED ((uint8_t)0x01)
3244 #define SCB_DFSR_BKPT ((uint8_t)0x02)
3245 #define SCB_DFSR_DWTTRAP ((uint8_t)0x04)
3246 #define SCB_DFSR_VCATCH ((uint8_t)0x08)
3247 #define SCB_DFSR_EXTERNAL ((uint8_t)0x10)
3249 /******************* Bit definition for SCB_MMFAR register ******************/
3250 #define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF)
3252 /******************* Bit definition for SCB_BFAR register *******************/
3253 #define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF)
3255 /******************* Bit definition for SCB_afsr register *******************/
3256 #define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF)
3258 /******************************************************************************/
3259 /* */
3260 /* External Interrupt/Event Controller */
3261 /* */
3262 /******************************************************************************/
3263 
3264 /******************* Bit definition for EXTI_IMR register *******************/
3265 #define EXTI_IMR_MR0 ((uint32_t)0x00000001)
3266 #define EXTI_IMR_MR1 ((uint32_t)0x00000002)
3267 #define EXTI_IMR_MR2 ((uint32_t)0x00000004)
3268 #define EXTI_IMR_MR3 ((uint32_t)0x00000008)
3269 #define EXTI_IMR_MR4 ((uint32_t)0x00000010)
3270 #define EXTI_IMR_MR5 ((uint32_t)0x00000020)
3271 #define EXTI_IMR_MR6 ((uint32_t)0x00000040)
3272 #define EXTI_IMR_MR7 ((uint32_t)0x00000080)
3273 #define EXTI_IMR_MR8 ((uint32_t)0x00000100)
3274 #define EXTI_IMR_MR9 ((uint32_t)0x00000200)
3275 #define EXTI_IMR_MR10 ((uint32_t)0x00000400)
3276 #define EXTI_IMR_MR11 ((uint32_t)0x00000800)
3277 #define EXTI_IMR_MR12 ((uint32_t)0x00001000)
3278 #define EXTI_IMR_MR13 ((uint32_t)0x00002000)
3279 #define EXTI_IMR_MR14 ((uint32_t)0x00004000)
3280 #define EXTI_IMR_MR15 ((uint32_t)0x00008000)
3281 #define EXTI_IMR_MR16 ((uint32_t)0x00010000)
3282 #define EXTI_IMR_MR17 ((uint32_t)0x00020000)
3283 #define EXTI_IMR_MR18 ((uint32_t)0x00040000)
3284 #define EXTI_IMR_MR19 ((uint32_t)0x00080000)
3286 /******************* Bit definition for EXTI_EMR register *******************/
3287 #define EXTI_EMR_MR0 ((uint32_t)0x00000001)
3288 #define EXTI_EMR_MR1 ((uint32_t)0x00000002)
3289 #define EXTI_EMR_MR2 ((uint32_t)0x00000004)
3290 #define EXTI_EMR_MR3 ((uint32_t)0x00000008)
3291 #define EXTI_EMR_MR4 ((uint32_t)0x00000010)
3292 #define EXTI_EMR_MR5 ((uint32_t)0x00000020)
3293 #define EXTI_EMR_MR6 ((uint32_t)0x00000040)
3294 #define EXTI_EMR_MR7 ((uint32_t)0x00000080)
3295 #define EXTI_EMR_MR8 ((uint32_t)0x00000100)
3296 #define EXTI_EMR_MR9 ((uint32_t)0x00000200)
3297 #define EXTI_EMR_MR10 ((uint32_t)0x00000400)
3298 #define EXTI_EMR_MR11 ((uint32_t)0x00000800)
3299 #define EXTI_EMR_MR12 ((uint32_t)0x00001000)
3300 #define EXTI_EMR_MR13 ((uint32_t)0x00002000)
3301 #define EXTI_EMR_MR14 ((uint32_t)0x00004000)
3302 #define EXTI_EMR_MR15 ((uint32_t)0x00008000)
3303 #define EXTI_EMR_MR16 ((uint32_t)0x00010000)
3304 #define EXTI_EMR_MR17 ((uint32_t)0x00020000)
3305 #define EXTI_EMR_MR18 ((uint32_t)0x00040000)
3306 #define EXTI_EMR_MR19 ((uint32_t)0x00080000)
3308 /****************** Bit definition for EXTI_RTSR register *******************/
3309 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001)
3310 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002)
3311 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004)
3312 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008)
3313 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010)
3314 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020)
3315 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040)
3316 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080)
3317 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100)
3318 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200)
3319 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400)
3320 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800)
3321 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000)
3322 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000)
3323 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000)
3324 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000)
3325 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000)
3326 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000)
3327 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000)
3328 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000)
3330 /****************** Bit definition for EXTI_FTSR register *******************/
3331 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001)
3332 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002)
3333 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004)
3334 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008)
3335 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010)
3336 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020)
3337 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040)
3338 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080)
3339 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100)
3340 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200)
3341 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400)
3342 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800)
3343 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000)
3344 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000)
3345 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000)
3346 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000)
3347 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000)
3348 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000)
3349 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000)
3350 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000)
3352 /****************** Bit definition for EXTI_SWIER register ******************/
3353 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001)
3354 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002)
3355 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004)
3356 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008)
3357 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010)
3358 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020)
3359 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040)
3360 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080)
3361 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100)
3362 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200)
3363 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400)
3364 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800)
3365 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000)
3366 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000)
3367 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000)
3368 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000)
3369 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000)
3370 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000)
3371 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000)
3372 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000)
3374 /******************* Bit definition for EXTI_PR register ********************/
3375 #define EXTI_PR_PR0 ((uint32_t)0x00000001)
3376 #define EXTI_PR_PR1 ((uint32_t)0x00000002)
3377 #define EXTI_PR_PR2 ((uint32_t)0x00000004)
3378 #define EXTI_PR_PR3 ((uint32_t)0x00000008)
3379 #define EXTI_PR_PR4 ((uint32_t)0x00000010)
3380 #define EXTI_PR_PR5 ((uint32_t)0x00000020)
3381 #define EXTI_PR_PR6 ((uint32_t)0x00000040)
3382 #define EXTI_PR_PR7 ((uint32_t)0x00000080)
3383 #define EXTI_PR_PR8 ((uint32_t)0x00000100)
3384 #define EXTI_PR_PR9 ((uint32_t)0x00000200)
3385 #define EXTI_PR_PR10 ((uint32_t)0x00000400)
3386 #define EXTI_PR_PR11 ((uint32_t)0x00000800)
3387 #define EXTI_PR_PR12 ((uint32_t)0x00001000)
3388 #define EXTI_PR_PR13 ((uint32_t)0x00002000)
3389 #define EXTI_PR_PR14 ((uint32_t)0x00004000)
3390 #define EXTI_PR_PR15 ((uint32_t)0x00008000)
3391 #define EXTI_PR_PR16 ((uint32_t)0x00010000)
3392 #define EXTI_PR_PR17 ((uint32_t)0x00020000)
3393 #define EXTI_PR_PR18 ((uint32_t)0x00040000)
3394 #define EXTI_PR_PR19 ((uint32_t)0x00080000)
3396 /******************************************************************************/
3397 /* */
3398 /* DMA Controller */
3399 /* */
3400 /******************************************************************************/
3401 
3402 /******************* Bit definition for DMA_ISR register ********************/
3403 #define DMA_ISR_GIF1 ((uint32_t)0x00000001)
3404 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002)
3405 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004)
3406 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008)
3407 #define DMA_ISR_GIF2 ((uint32_t)0x00000010)
3408 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020)
3409 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040)
3410 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080)
3411 #define DMA_ISR_GIF3 ((uint32_t)0x00000100)
3412 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200)
3413 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400)
3414 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800)
3415 #define DMA_ISR_GIF4 ((uint32_t)0x00001000)
3416 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000)
3417 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000)
3418 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000)
3419 #define DMA_ISR_GIF5 ((uint32_t)0x00010000)
3420 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000)
3421 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000)
3422 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000)
3423 #define DMA_ISR_GIF6 ((uint32_t)0x00100000)
3424 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000)
3425 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000)
3426 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000)
3427 #define DMA_ISR_GIF7 ((uint32_t)0x01000000)
3428 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000)
3429 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000)
3430 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000)
3432 /******************* Bit definition for DMA_IFCR register *******************/
3433 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001)
3434 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002)
3435 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004)
3436 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008)
3437 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010)
3438 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020)
3439 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040)
3440 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080)
3441 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100)
3442 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200)
3443 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400)
3444 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800)
3445 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000)
3446 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000)
3447 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000)
3448 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000)
3449 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000)
3450 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000)
3451 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000)
3452 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000)
3453 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000)
3454 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000)
3455 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000)
3456 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000)
3457 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000)
3458 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000)
3459 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000)
3460 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000)
3462 /******************* Bit definition for DMA_CCR1 register *******************/
3463 #define DMA_CCR1_EN ((uint16_t)0x0001)
3464 #define DMA_CCR1_TCIE ((uint16_t)0x0002)
3465 #define DMA_CCR1_HTIE ((uint16_t)0x0004)
3466 #define DMA_CCR1_TEIE ((uint16_t)0x0008)
3467 #define DMA_CCR1_DIR ((uint16_t)0x0010)
3468 #define DMA_CCR1_CIRC ((uint16_t)0x0020)
3469 #define DMA_CCR1_PINC ((uint16_t)0x0040)
3470 #define DMA_CCR1_MINC ((uint16_t)0x0080)
3472 #define DMA_CCR1_PSIZE ((uint16_t)0x0300)
3473 #define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100)
3474 #define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200)
3476 #define DMA_CCR1_MSIZE ((uint16_t)0x0C00)
3477 #define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400)
3478 #define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800)
3480 #define DMA_CCR1_PL ((uint16_t)0x3000)
3481 #define DMA_CCR1_PL_0 ((uint16_t)0x1000)
3482 #define DMA_CCR1_PL_1 ((uint16_t)0x2000)
3484 #define DMA_CCR1_MEM2MEM ((uint16_t)0x4000)
3486 /******************* Bit definition for DMA_CCR2 register *******************/
3487 #define DMA_CCR2_EN ((uint16_t)0x0001)
3488 #define DMA_CCR2_TCIE ((uint16_t)0x0002)
3489 #define DMA_CCR2_HTIE ((uint16_t)0x0004)
3490 #define DMA_CCR2_TEIE ((uint16_t)0x0008)
3491 #define DMA_CCR2_DIR ((uint16_t)0x0010)
3492 #define DMA_CCR2_CIRC ((uint16_t)0x0020)
3493 #define DMA_CCR2_PINC ((uint16_t)0x0040)
3494 #define DMA_CCR2_MINC ((uint16_t)0x0080)
3496 #define DMA_CCR2_PSIZE ((uint16_t)0x0300)
3497 #define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100)
3498 #define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200)
3500 #define DMA_CCR2_MSIZE ((uint16_t)0x0C00)
3501 #define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400)
3502 #define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800)
3504 #define DMA_CCR2_PL ((uint16_t)0x3000)
3505 #define DMA_CCR2_PL_0 ((uint16_t)0x1000)
3506 #define DMA_CCR2_PL_1 ((uint16_t)0x2000)
3508 #define DMA_CCR2_MEM2MEM ((uint16_t)0x4000)
3510 /******************* Bit definition for DMA_CCR3 register *******************/
3511 #define DMA_CCR3_EN ((uint16_t)0x0001)
3512 #define DMA_CCR3_TCIE ((uint16_t)0x0002)
3513 #define DMA_CCR3_HTIE ((uint16_t)0x0004)
3514 #define DMA_CCR3_TEIE ((uint16_t)0x0008)
3515 #define DMA_CCR3_DIR ((uint16_t)0x0010)
3516 #define DMA_CCR3_CIRC ((uint16_t)0x0020)
3517 #define DMA_CCR3_PINC ((uint16_t)0x0040)
3518 #define DMA_CCR3_MINC ((uint16_t)0x0080)
3520 #define DMA_CCR3_PSIZE ((uint16_t)0x0300)
3521 #define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100)
3522 #define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200)
3524 #define DMA_CCR3_MSIZE ((uint16_t)0x0C00)
3525 #define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400)
3526 #define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800)
3528 #define DMA_CCR3_PL ((uint16_t)0x3000)
3529 #define DMA_CCR3_PL_0 ((uint16_t)0x1000)
3530 #define DMA_CCR3_PL_1 ((uint16_t)0x2000)
3532 #define DMA_CCR3_MEM2MEM ((uint16_t)0x4000)
3535 #define DMA_CCR4_EN ((uint16_t)0x0001)
3536 #define DMA_CCR4_TCIE ((uint16_t)0x0002)
3537 #define DMA_CCR4_HTIE ((uint16_t)0x0004)
3538 #define DMA_CCR4_TEIE ((uint16_t)0x0008)
3539 #define DMA_CCR4_DIR ((uint16_t)0x0010)
3540 #define DMA_CCR4_CIRC ((uint16_t)0x0020)
3541 #define DMA_CCR4_PINC ((uint16_t)0x0040)
3542 #define DMA_CCR4_MINC ((uint16_t)0x0080)
3544 #define DMA_CCR4_PSIZE ((uint16_t)0x0300)
3545 #define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100)
3546 #define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200)
3548 #define DMA_CCR4_MSIZE ((uint16_t)0x0C00)
3549 #define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400)
3550 #define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800)
3552 #define DMA_CCR4_PL ((uint16_t)0x3000)
3553 #define DMA_CCR4_PL_0 ((uint16_t)0x1000)
3554 #define DMA_CCR4_PL_1 ((uint16_t)0x2000)
3556 #define DMA_CCR4_MEM2MEM ((uint16_t)0x4000)
3558 /****************** Bit definition for DMA_CCR5 register *******************/
3559 #define DMA_CCR5_EN ((uint16_t)0x0001)
3560 #define DMA_CCR5_TCIE ((uint16_t)0x0002)
3561 #define DMA_CCR5_HTIE ((uint16_t)0x0004)
3562 #define DMA_CCR5_TEIE ((uint16_t)0x0008)
3563 #define DMA_CCR5_DIR ((uint16_t)0x0010)
3564 #define DMA_CCR5_CIRC ((uint16_t)0x0020)
3565 #define DMA_CCR5_PINC ((uint16_t)0x0040)
3566 #define DMA_CCR5_MINC ((uint16_t)0x0080)
3568 #define DMA_CCR5_PSIZE ((uint16_t)0x0300)
3569 #define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100)
3570 #define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200)
3572 #define DMA_CCR5_MSIZE ((uint16_t)0x0C00)
3573 #define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400)
3574 #define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800)
3576 #define DMA_CCR5_PL ((uint16_t)0x3000)
3577 #define DMA_CCR5_PL_0 ((uint16_t)0x1000)
3578 #define DMA_CCR5_PL_1 ((uint16_t)0x2000)
3580 #define DMA_CCR5_MEM2MEM ((uint16_t)0x4000)
3582 /******************* Bit definition for DMA_CCR6 register *******************/
3583 #define DMA_CCR6_EN ((uint16_t)0x0001)
3584 #define DMA_CCR6_TCIE ((uint16_t)0x0002)
3585 #define DMA_CCR6_HTIE ((uint16_t)0x0004)
3586 #define DMA_CCR6_TEIE ((uint16_t)0x0008)
3587 #define DMA_CCR6_DIR ((uint16_t)0x0010)
3588 #define DMA_CCR6_CIRC ((uint16_t)0x0020)
3589 #define DMA_CCR6_PINC ((uint16_t)0x0040)
3590 #define DMA_CCR6_MINC ((uint16_t)0x0080)
3592 #define DMA_CCR6_PSIZE ((uint16_t)0x0300)
3593 #define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100)
3594 #define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200)
3596 #define DMA_CCR6_MSIZE ((uint16_t)0x0C00)
3597 #define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400)
3598 #define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800)
3600 #define DMA_CCR6_PL ((uint16_t)0x3000)
3601 #define DMA_CCR6_PL_0 ((uint16_t)0x1000)
3602 #define DMA_CCR6_PL_1 ((uint16_t)0x2000)
3604 #define DMA_CCR6_MEM2MEM ((uint16_t)0x4000)
3606 /******************* Bit definition for DMA_CCR7 register *******************/
3607 #define DMA_CCR7_EN ((uint16_t)0x0001)
3608 #define DMA_CCR7_TCIE ((uint16_t)0x0002)
3609 #define DMA_CCR7_HTIE ((uint16_t)0x0004)
3610 #define DMA_CCR7_TEIE ((uint16_t)0x0008)
3611 #define DMA_CCR7_DIR ((uint16_t)0x0010)
3612 #define DMA_CCR7_CIRC ((uint16_t)0x0020)
3613 #define DMA_CCR7_PINC ((uint16_t)0x0040)
3614 #define DMA_CCR7_MINC ((uint16_t)0x0080)
3616 #define DMA_CCR7_PSIZE , ((uint16_t)0x0300)
3617 #define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100)
3618 #define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200)
3620 #define DMA_CCR7_MSIZE ((uint16_t)0x0C00)
3621 #define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400)
3622 #define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800)
3624 #define DMA_CCR7_PL ((uint16_t)0x3000)
3625 #define DMA_CCR7_PL_0 ((uint16_t)0x1000)
3626 #define DMA_CCR7_PL_1 ((uint16_t)0x2000)
3628 #define DMA_CCR7_MEM2MEM ((uint16_t)0x4000)
3630 /****************** Bit definition for DMA_CNDTR1 register ******************/
3631 #define DMA_CNDTR1_NDT ((uint16_t)0xFFFF)
3633 /****************** Bit definition for DMA_CNDTR2 register ******************/
3634 #define DMA_CNDTR2_NDT ((uint16_t)0xFFFF)
3636 /****************** Bit definition for DMA_CNDTR3 register ******************/
3637 #define DMA_CNDTR3_NDT ((uint16_t)0xFFFF)
3639 /****************** Bit definition for DMA_CNDTR4 register ******************/
3640 #define DMA_CNDTR4_NDT ((uint16_t)0xFFFF)
3642 /****************** Bit definition for DMA_CNDTR5 register ******************/
3643 #define DMA_CNDTR5_NDT ((uint16_t)0xFFFF)
3645 /****************** Bit definition for DMA_CNDTR6 register ******************/
3646 #define DMA_CNDTR6_NDT ((uint16_t)0xFFFF)
3648 /****************** Bit definition for DMA_CNDTR7 register ******************/
3649 #define DMA_CNDTR7_NDT ((uint16_t)0xFFFF)
3651 /****************** Bit definition for DMA_CPAR1 register *******************/
3652 #define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF)
3654 /****************** Bit definition for DMA_CPAR2 register *******************/
3655 #define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF)
3657 /****************** Bit definition for DMA_CPAR3 register *******************/
3658 #define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF)
3661 /****************** Bit definition for DMA_CPAR4 register *******************/
3662 #define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF)
3664 /****************** Bit definition for DMA_CPAR5 register *******************/
3665 #define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF)
3667 /****************** Bit definition for DMA_CPAR6 register *******************/
3668 #define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF)
3671 /****************** Bit definition for DMA_CPAR7 register *******************/
3672 #define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF)
3674 /****************** Bit definition for DMA_CMAR1 register *******************/
3675 #define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF)
3677 /****************** Bit definition for DMA_CMAR2 register *******************/
3678 #define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF)
3680 /****************** Bit definition for DMA_CMAR3 register *******************/
3681 #define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF)
3684 /****************** Bit definition for DMA_CMAR4 register *******************/
3685 #define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF)
3687 /****************** Bit definition for DMA_CMAR5 register *******************/
3688 #define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF)
3690 /****************** Bit definition for DMA_CMAR6 register *******************/
3691 #define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF)
3693 /****************** Bit definition for DMA_CMAR7 register *******************/
3694 #define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF)
3696 /******************************************************************************/
3697 /* */
3698 /* Analog to Digital Converter */
3699 /* */
3700 /******************************************************************************/
3701 
3702 /******************** Bit definition for ADC_SR register ********************/
3703 #define ADC_SR_AWD ((uint8_t)0x01)
3704 #define ADC_SR_EOC ((uint8_t)0x02)
3705 #define ADC_SR_JEOC ((uint8_t)0x04)
3706 #define ADC_SR_JSTRT ((uint8_t)0x08)
3707 #define ADC_SR_STRT ((uint8_t)0x10)
3709 /******************* Bit definition for ADC_CR1 register ********************/
3710 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F)
3711 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001)
3712 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002)
3713 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004)
3714 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008)
3715 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010)
3717 #define ADC_CR1_EOCIE ((uint32_t)0x00000020)
3718 #define ADC_CR1_AWDIE ((uint32_t)0x00000040)
3719 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080)
3720 #define ADC_CR1_SCAN ((uint32_t)0x00000100)
3721 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200)
3722 #define ADC_CR1_JAUTO ((uint32_t)0x00000400)
3723 #define ADC_CR1_DISCEN ((uint32_t)0x00000800)
3724 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000)
3726 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000)
3727 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000)
3728 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000)
3729 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000)
3731 #define ADC_CR1_DUALMOD ((uint32_t)0x000F0000)
3732 #define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000)
3733 #define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000)
3734 #define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000)
3735 #define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000)
3737 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000)
3738 #define ADC_CR1_AWDEN ((uint32_t)0x00800000)
3741 /******************* Bit definition for ADC_CR2 register ********************/
3742 #define ADC_CR2_ADON ((uint32_t)0x00000001)
3743 #define ADC_CR2_CONT ((uint32_t)0x00000002)
3744 #define ADC_CR2_CAL ((uint32_t)0x00000004)
3745 #define ADC_CR2_RSTCAL ((uint32_t)0x00000008)
3746 #define ADC_CR2_DMA ((uint32_t)0x00000100)
3747 #define ADC_CR2_ALIGN ((uint32_t)0x00000800)
3749 #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000)
3750 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000)
3751 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000)
3752 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000)
3754 #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000)
3756 #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000)
3757 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000)
3758 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000)
3759 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000)
3761 #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000)
3762 #define ADC_CR2_JSWSTART ((uint32_t)0x00200000)
3763 #define ADC_CR2_SWSTART ((uint32_t)0x00400000)
3764 #define ADC_CR2_TSVREFE ((uint32_t)0x00800000)
3766 /****************** Bit definition for ADC_SMPR1 register *******************/
3767 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007)
3768 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001)
3769 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002)
3770 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004)
3772 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038)
3773 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008)
3774 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010)
3775 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020)
3777 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0)
3778 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040)
3779 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080)
3780 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100)
3782 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00)
3783 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200)
3784 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400)
3785 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800)
3787 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000)
3788 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000)
3789 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000)
3790 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000)
3792 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000)
3793 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000)
3794 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000)
3795 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000)
3797 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000)
3798 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000)
3799 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000)
3800 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000)
3802 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000)
3803 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000)
3804 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000)
3805 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000)
3807 /****************** Bit definition for ADC_SMPR2 register *******************/
3808 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007)
3809 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001)
3810 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002)
3811 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004)
3813 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038)
3814 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008)
3815 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010)
3816 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020)
3818 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0)
3819 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040)
3820 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080)
3821 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100)
3823 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00)
3824 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200)
3825 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400)
3826 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800)
3828 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000)
3829 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000)
3830 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000)
3831 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000)
3833 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000)
3834 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000)
3835 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000)
3836 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000)
3838 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000)
3839 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000)
3840 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000)
3841 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000)
3843 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000)
3844 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000)
3845 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000)
3846 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000)
3848 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000)
3849 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000)
3850 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000)
3851 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000)
3853 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000)
3854 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000)
3855 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000)
3856 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000)
3858 /****************** Bit definition for ADC_JOFR1 register *******************/
3859 #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF)
3861 /****************** Bit definition for ADC_JOFR2 register *******************/
3862 #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF)
3864 /****************** Bit definition for ADC_JOFR3 register *******************/
3865 #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF)
3867 /****************** Bit definition for ADC_JOFR4 register *******************/
3868 #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF)
3870 /******************* Bit definition for ADC_HTR register ********************/
3871 #define ADC_HTR_HT ((uint16_t)0x0FFF)
3873 /******************* Bit definition for ADC_LTR register ********************/
3874 #define ADC_LTR_LT ((uint16_t)0x0FFF)
3876 /******************* Bit definition for ADC_SQR1 register *******************/
3877 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F)
3878 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001)
3879 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002)
3880 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004)
3881 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008)
3882 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010)
3884 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0)
3885 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020)
3886 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040)
3887 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080)
3888 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100)
3889 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200)
3891 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00)
3892 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400)
3893 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800)
3894 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000)
3895 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000)
3896 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000)
3898 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000)
3899 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000)
3900 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000)
3901 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000)
3902 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000)
3903 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000)
3905 #define ADC_SQR1_L ((uint32_t)0x00F00000)
3906 #define ADC_SQR1_L_0 ((uint32_t)0x00100000)
3907 #define ADC_SQR1_L_1 ((uint32_t)0x00200000)
3908 #define ADC_SQR1_L_2 ((uint32_t)0x00400000)
3909 #define ADC_SQR1_L_3 ((uint32_t)0x00800000)
3911 /******************* Bit definition for ADC_SQR2 register *******************/
3912 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F)
3913 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001)
3914 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002)
3915 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004)
3916 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008)
3917 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010)
3919 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0)
3920 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020)
3921 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040)
3922 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080)
3923 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100)
3924 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200)
3926 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00)
3927 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400)
3928 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800)
3929 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000)
3930 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000)
3931 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000)
3933 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000)
3934 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000)
3935 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000)
3936 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000)
3937 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000)
3938 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000)
3940 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000)
3941 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000)
3942 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000)
3943 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000)
3944 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000)
3945 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000)
3947 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000)
3948 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000)
3949 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000)
3950 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000)
3951 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000)
3952 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000)
3954 /******************* Bit definition for ADC_SQR3 register *******************/
3955 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F)
3956 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001)
3957 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002)
3958 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004)
3959 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008)
3960 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010)
3962 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0)
3963 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020)
3964 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040)
3965 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080)
3966 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100)
3967 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200)
3969 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00)
3970 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400)
3971 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800)
3972 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000)
3973 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000)
3974 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000)
3976 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000)
3977 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000)
3978 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000)
3979 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000)
3980 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000)
3981 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000)
3983 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000)
3984 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000)
3985 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000)
3986 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000)
3987 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000)
3988 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000)
3990 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000)
3991 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000)
3992 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000)
3993 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000)
3994 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000)
3995 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000)
3997 /******************* Bit definition for ADC_JSQR register *******************/
3998 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F)
3999 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001)
4000 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002)
4001 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004)
4002 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008)
4003 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010)
4005 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0)
4006 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020)
4007 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040)
4008 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080)
4009 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100)
4010 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200)
4012 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00)
4013 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400)
4014 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800)
4015 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000)
4016 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000)
4017 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000)
4019 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000)
4020 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000)
4021 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000)
4022 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000)
4023 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000)
4024 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000)
4026 #define ADC_JSQR_JL ((uint32_t)0x00300000)
4027 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000)
4028 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000)
4030 /******************* Bit definition for ADC_JDR1 register *******************/
4031 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF)
4033 /******************* Bit definition for ADC_JDR2 register *******************/
4034 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF)
4036 /******************* Bit definition for ADC_JDR3 register *******************/
4037 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF)
4039 /******************* Bit definition for ADC_JDR4 register *******************/
4040 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF)
4042 /******************** Bit definition for ADC_DR register ********************/
4043 #define ADC_DR_DATA ((uint32_t)0x0000FFFF)
4044 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000)
4046 /******************************************************************************/
4047 /* */
4048 /* Digital to Analog Converter */
4049 /* */
4050 /******************************************************************************/
4051 
4052 /******************** Bit definition for DAC_CR register ********************/
4053 #define DAC_CR_EN1 ((uint32_t)0x00000001)
4054 #define DAC_CR_BOFF1 ((uint32_t)0x00000002)
4055 #define DAC_CR_TEN1 ((uint32_t)0x00000004)
4057 #define DAC_CR_TSEL1 ((uint32_t)0x00000038)
4058 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008)
4059 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010)
4060 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020)
4062 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0)
4063 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040)
4064 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080)
4066 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00)
4067 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100)
4068 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200)
4069 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400)
4070 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800)
4072 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000)
4073 #define DAC_CR_EN2 ((uint32_t)0x00010000)
4074 #define DAC_CR_BOFF2 ((uint32_t)0x00020000)
4075 #define DAC_CR_TEN2 ((uint32_t)0x00040000)
4077 #define DAC_CR_TSEL2 ((uint32_t)0x00380000)
4078 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000)
4079 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000)
4080 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000)
4082 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000)
4083 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000)
4084 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000)
4086 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000)
4087 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000)
4088 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000)
4089 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000)
4090 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000)
4092 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000)
4094 /***************** Bit definition for DAC_SWTRIGR register ******************/
4095 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01)
4096 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02)
4098 /***************** Bit definition for DAC_DHR12R1 register ******************/
4099 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF)
4101 /***************** Bit definition for DAC_DHR12L1 register ******************/
4102 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0)
4104 /****************** Bit definition for DAC_DHR8R1 register ******************/
4105 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF)
4107 /***************** Bit definition for DAC_DHR12R2 register ******************/
4108 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF)
4110 /***************** Bit definition for DAC_DHR12L2 register ******************/
4111 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0)
4113 /****************** Bit definition for DAC_DHR8R2 register ******************/
4114 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF)
4116 /***************** Bit definition for DAC_DHR12RD register ******************/
4117 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF)
4118 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000)
4120 /***************** Bit definition for DAC_DHR12LD register ******************/
4121 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0)
4122 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000)
4124 /****************** Bit definition for DAC_DHR8RD register ******************/
4125 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF)
4126 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00)
4128 /******************* Bit definition for DAC_DOR1 register *******************/
4129 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF)
4131 /******************* Bit definition for DAC_DOR2 register *******************/
4132 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF)
4134 /******************** Bit definition for DAC_SR register ********************/
4135 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000)
4136 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000)
4138 /******************************************************************************/
4139 /* */
4140 /* CEC */
4141 /* */
4142 /******************************************************************************/
4143 /******************** Bit definition for CEC_CFGR register ******************/
4144 #define CEC_CFGR_PE ((uint16_t)0x0001)
4145 #define CEC_CFGR_IE ((uint16_t)0x0002)
4146 #define CEC_CFGR_BTEM ((uint16_t)0x0004)
4147 #define CEC_CFGR_BPEM ((uint16_t)0x0008)
4149 /******************** Bit definition for CEC_OAR register ******************/
4150 #define CEC_OAR_OA ((uint16_t)0x000F)
4151 #define CEC_OAR_OA_0 ((uint16_t)0x0001)
4152 #define CEC_OAR_OA_1 ((uint16_t)0x0002)
4153 #define CEC_OAR_OA_2 ((uint16_t)0x0004)
4154 #define CEC_OAR_OA_3 ((uint16_t)0x0008)
4156 /******************** Bit definition for CEC_PRES register ******************/
4157 #define CEC_PRES_PRES ((uint16_t)0x3FFF)
4159 /******************** Bit definition for CEC_ESR register ******************/
4160 #define CEC_ESR_BTE ((uint16_t)0x0001)
4161 #define CEC_ESR_BPE ((uint16_t)0x0002)
4162 #define CEC_ESR_RBTFE ((uint16_t)0x0004)
4163 #define CEC_ESR_SBE ((uint16_t)0x0008)
4164 #define CEC_ESR_ACKE ((uint16_t)0x0010)
4165 #define CEC_ESR_LINE ((uint16_t)0x0020)
4166 #define CEC_ESR_TBTFE ((uint16_t)0x0040)
4168 /******************** Bit definition for CEC_CSR register ******************/
4169 #define CEC_CSR_TSOM ((uint16_t)0x0001)
4170 #define CEC_CSR_TEOM ((uint16_t)0x0002)
4171 #define CEC_CSR_TERR ((uint16_t)0x0004)
4172 #define CEC_CSR_TBTRF ((uint16_t)0x0008)
4173 #define CEC_CSR_RSOM ((uint16_t)0x0010)
4174 #define CEC_CSR_REOM ((uint16_t)0x0020)
4175 #define CEC_CSR_RERR ((uint16_t)0x0040)
4176 #define CEC_CSR_RBTF ((uint16_t)0x0080)
4178 /******************** Bit definition for CEC_TXD register ******************/
4179 #define CEC_TXD_TXD ((uint16_t)0x00FF)
4181 /******************** Bit definition for CEC_RXD register ******************/
4182 #define CEC_RXD_RXD ((uint16_t)0x00FF)
4184 /******************************************************************************/
4185 /* */
4186 /* TIM */
4187 /* */
4188 /******************************************************************************/
4189 
4190 /******************* Bit definition for TIM_CR1 register ********************/
4191 #define TIM_CR1_CEN ((uint16_t)0x0001)
4192 #define TIM_CR1_UDIS ((uint16_t)0x0002)
4193 #define TIM_CR1_URS ((uint16_t)0x0004)
4194 #define TIM_CR1_OPM ((uint16_t)0x0008)
4195 #define TIM_CR1_DIR ((uint16_t)0x0010)
4197 #define TIM_CR1_CMS ((uint16_t)0x0060)
4198 #define TIM_CR1_CMS_0 ((uint16_t)0x0020)
4199 #define TIM_CR1_CMS_1 ((uint16_t)0x0040)
4201 #define TIM_CR1_ARPE ((uint16_t)0x0080)
4203 #define TIM_CR1_CKD ((uint16_t)0x0300)
4204 #define TIM_CR1_CKD_0 ((uint16_t)0x0100)
4205 #define TIM_CR1_CKD_1 ((uint16_t)0x0200)
4207 /******************* Bit definition for TIM_CR2 register ********************/
4208 #define TIM_CR2_CCPC ((uint16_t)0x0001)
4209 #define TIM_CR2_CCUS ((uint16_t)0x0004)
4210 #define TIM_CR2_CCDS ((uint16_t)0x0008)
4212 #define TIM_CR2_MMS ((uint16_t)0x0070)
4213 #define TIM_CR2_MMS_0 ((uint16_t)0x0010)
4214 #define TIM_CR2_MMS_1 ((uint16_t)0x0020)
4215 #define TIM_CR2_MMS_2 ((uint16_t)0x0040)
4217 #define TIM_CR2_TI1S ((uint16_t)0x0080)
4218 #define TIM_CR2_OIS1 ((uint16_t)0x0100)
4219 #define TIM_CR2_OIS1N ((uint16_t)0x0200)
4220 #define TIM_CR2_OIS2 ((uint16_t)0x0400)
4221 #define TIM_CR2_OIS2N ((uint16_t)0x0800)
4222 #define TIM_CR2_OIS3 ((uint16_t)0x1000)
4223 #define TIM_CR2_OIS3N ((uint16_t)0x2000)
4224 #define TIM_CR2_OIS4 ((uint16_t)0x4000)
4226 /******************* Bit definition for TIM_SMCR register *******************/
4227 #define TIM_SMCR_SMS ((uint16_t)0x0007)
4228 #define TIM_SMCR_SMS_0 ((uint16_t)0x0001)
4229 #define TIM_SMCR_SMS_1 ((uint16_t)0x0002)
4230 #define TIM_SMCR_SMS_2 ((uint16_t)0x0004)
4232 #define TIM_SMCR_TS ((uint16_t)0x0070)
4233 #define TIM_SMCR_TS_0 ((uint16_t)0x0010)
4234 #define TIM_SMCR_TS_1 ((uint16_t)0x0020)
4235 #define TIM_SMCR_TS_2 ((uint16_t)0x0040)
4237 #define TIM_SMCR_MSM ((uint16_t)0x0080)
4239 #define TIM_SMCR_ETF ((uint16_t)0x0F00)
4240 #define TIM_SMCR_ETF_0 ((uint16_t)0x0100)
4241 #define TIM_SMCR_ETF_1 ((uint16_t)0x0200)
4242 #define TIM_SMCR_ETF_2 ((uint16_t)0x0400)
4243 #define TIM_SMCR_ETF_3 ((uint16_t)0x0800)
4245 #define TIM_SMCR_ETPS ((uint16_t)0x3000)
4246 #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000)
4247 #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000)
4249 #define TIM_SMCR_ECE ((uint16_t)0x4000)
4250 #define TIM_SMCR_ETP ((uint16_t)0x8000)
4252 /******************* Bit definition for TIM_DIER register *******************/
4253 #define TIM_DIER_UIE ((uint16_t)0x0001)
4254 #define TIM_DIER_CC1IE ((uint16_t)0x0002)
4255 #define TIM_DIER_CC2IE ((uint16_t)0x0004)
4256 #define TIM_DIER_CC3IE ((uint16_t)0x0008)
4257 #define TIM_DIER_CC4IE ((uint16_t)0x0010)
4258 #define TIM_DIER_COMIE ((uint16_t)0x0020)
4259 #define TIM_DIER_TIE ((uint16_t)0x0040)
4260 #define TIM_DIER_BIE ((uint16_t)0x0080)
4261 #define TIM_DIER_UDE ((uint16_t)0x0100)
4262 #define TIM_DIER_CC1DE ((uint16_t)0x0200)
4263 #define TIM_DIER_CC2DE ((uint16_t)0x0400)
4264 #define TIM_DIER_CC3DE ((uint16_t)0x0800)
4265 #define TIM_DIER_CC4DE ((uint16_t)0x1000)
4266 #define TIM_DIER_COMDE ((uint16_t)0x2000)
4267 #define TIM_DIER_TDE ((uint16_t)0x4000)
4269 /******************** Bit definition for TIM_SR register ********************/
4270 #define TIM_SR_UIF ((uint16_t)0x0001)
4271 #define TIM_SR_CC1IF ((uint16_t)0x0002)
4272 #define TIM_SR_CC2IF ((uint16_t)0x0004)
4273 #define TIM_SR_CC3IF ((uint16_t)0x0008)
4274 #define TIM_SR_CC4IF ((uint16_t)0x0010)
4275 #define TIM_SR_COMIF ((uint16_t)0x0020)
4276 #define TIM_SR_TIF ((uint16_t)0x0040)
4277 #define TIM_SR_BIF ((uint16_t)0x0080)
4278 #define TIM_SR_CC1OF ((uint16_t)0x0200)
4279 #define TIM_SR_CC2OF ((uint16_t)0x0400)
4280 #define TIM_SR_CC3OF ((uint16_t)0x0800)
4281 #define TIM_SR_CC4OF ((uint16_t)0x1000)
4283 /******************* Bit definition for TIM_EGR register ********************/
4284 #define TIM_EGR_UG ((uint8_t)0x01)
4285 #define TIM_EGR_CC1G ((uint8_t)0x02)
4286 #define TIM_EGR_CC2G ((uint8_t)0x04)
4287 #define TIM_EGR_CC3G ((uint8_t)0x08)
4288 #define TIM_EGR_CC4G ((uint8_t)0x10)
4289 #define TIM_EGR_COMG ((uint8_t)0x20)
4290 #define TIM_EGR_TG ((uint8_t)0x40)
4291 #define TIM_EGR_BG ((uint8_t)0x80)
4293 /****************** Bit definition for TIM_CCMR1 register *******************/
4294 #define TIM_CCMR1_CC1S ((uint16_t)0x0003)
4295 #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001)
4296 #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002)
4298 #define TIM_CCMR1_OC1FE ((uint16_t)0x0004)
4299 #define TIM_CCMR1_OC1PE ((uint16_t)0x0008)
4301 #define TIM_CCMR1_OC1M ((uint16_t)0x0070)
4302 #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010)
4303 #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020)
4304 #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040)
4306 #define TIM_CCMR1_OC1CE ((uint16_t)0x0080)
4308 #define TIM_CCMR1_CC2S ((uint16_t)0x0300)
4309 #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100)
4310 #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200)
4312 #define TIM_CCMR1_OC2FE ((uint16_t)0x0400)
4313 #define TIM_CCMR1_OC2PE ((uint16_t)0x0800)
4315 #define TIM_CCMR1_OC2M ((uint16_t)0x7000)
4316 #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000)
4317 #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000)
4318 #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000)
4320 #define TIM_CCMR1_OC2CE ((uint16_t)0x8000)
4322 /*----------------------------------------------------------------------------*/
4323 
4324 #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C)
4325 #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004)
4326 #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008)
4328 #define TIM_CCMR1_IC1F ((uint16_t)0x00F0)
4329 #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010)
4330 #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020)
4331 #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040)
4332 #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080)
4334 #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00)
4335 #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400)
4336 #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800)
4338 #define TIM_CCMR1_IC2F ((uint16_t)0xF000)
4339 #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000)
4340 #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000)
4341 #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000)
4342 #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000)
4344 /****************** Bit definition for TIM_CCMR2 register *******************/
4345 #define TIM_CCMR2_CC3S ((uint16_t)0x0003)
4346 #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001)
4347 #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002)
4349 #define TIM_CCMR2_OC3FE ((uint16_t)0x0004)
4350 #define TIM_CCMR2_OC3PE ((uint16_t)0x0008)
4352 #define TIM_CCMR2_OC3M ((uint16_t)0x0070)
4353 #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010)
4354 #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020)
4355 #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040)
4357 #define TIM_CCMR2_OC3CE ((uint16_t)0x0080)
4359 #define TIM_CCMR2_CC4S ((uint16_t)0x0300)
4360 #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100)
4361 #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200)
4363 #define TIM_CCMR2_OC4FE ((uint16_t)0x0400)
4364 #define TIM_CCMR2_OC4PE ((uint16_t)0x0800)
4366 #define TIM_CCMR2_OC4M ((uint16_t)0x7000)
4367 #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000)
4368 #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000)
4369 #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000)
4371 #define TIM_CCMR2_OC4CE ((uint16_t)0x8000)
4373 /*----------------------------------------------------------------------------*/
4374 
4375 #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C)
4376 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004)
4377 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008)
4379 #define TIM_CCMR2_IC3F ((uint16_t)0x00F0)
4380 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010)
4381 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020)
4382 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040)
4383 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080)
4385 #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00)
4386 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400)
4387 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800)
4389 #define TIM_CCMR2_IC4F ((uint16_t)0xF000)
4390 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000)
4391 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000)
4392 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000)
4393 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000)
4395 /******************* Bit definition for TIM_CCER register *******************/
4396 #define TIM_CCER_CC1E ((uint16_t)0x0001)
4397 #define TIM_CCER_CC1P ((uint16_t)0x0002)
4398 #define TIM_CCER_CC1NE ((uint16_t)0x0004)
4399 #define TIM_CCER_CC1NP ((uint16_t)0x0008)
4400 #define TIM_CCER_CC2E ((uint16_t)0x0010)
4401 #define TIM_CCER_CC2P ((uint16_t)0x0020)
4402 #define TIM_CCER_CC2NE ((uint16_t)0x0040)
4403 #define TIM_CCER_CC2NP ((uint16_t)0x0080)
4404 #define TIM_CCER_CC3E ((uint16_t)0x0100)
4405 #define TIM_CCER_CC3P ((uint16_t)0x0200)
4406 #define TIM_CCER_CC3NE ((uint16_t)0x0400)
4407 #define TIM_CCER_CC3NP ((uint16_t)0x0800)
4408 #define TIM_CCER_CC4E ((uint16_t)0x1000)
4409 #define TIM_CCER_CC4P ((uint16_t)0x2000)
4410 #define TIM_CCER_CC4NP ((uint16_t)0x8000)
4412 /******************* Bit definition for TIM_CNT register ********************/
4413 #define TIM_CNT_CNT ((uint16_t)0xFFFF)
4415 /******************* Bit definition for TIM_PSC register ********************/
4416 #define TIM_PSC_PSC ((uint16_t)0xFFFF)
4418 /******************* Bit definition for TIM_ARR register ********************/
4419 #define TIM_ARR_ARR ((uint16_t)0xFFFF)
4421 /******************* Bit definition for TIM_RCR register ********************/
4422 #define TIM_RCR_REP ((uint8_t)0xFF)
4424 /******************* Bit definition for TIM_CCR1 register *******************/
4425 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF)
4427 /******************* Bit definition for TIM_CCR2 register *******************/
4428 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF)
4430 /******************* Bit definition for TIM_CCR3 register *******************/
4431 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF)
4433 /******************* Bit definition for TIM_CCR4 register *******************/
4434 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF)
4436 /******************* Bit definition for TIM_BDTR register *******************/
4437 #define TIM_BDTR_DTG ((uint16_t)0x00FF)
4438 #define TIM_BDTR_DTG_0 ((uint16_t)0x0001)
4439 #define TIM_BDTR_DTG_1 ((uint16_t)0x0002)
4440 #define TIM_BDTR_DTG_2 ((uint16_t)0x0004)
4441 #define TIM_BDTR_DTG_3 ((uint16_t)0x0008)
4442 #define TIM_BDTR_DTG_4 ((uint16_t)0x0010)
4443 #define TIM_BDTR_DTG_5 ((uint16_t)0x0020)
4444 #define TIM_BDTR_DTG_6 ((uint16_t)0x0040)
4445 #define TIM_BDTR_DTG_7 ((uint16_t)0x0080)
4447 #define TIM_BDTR_LOCK ((uint16_t)0x0300)
4448 #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100)
4449 #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200)
4451 #define TIM_BDTR_OSSI ((uint16_t)0x0400)
4452 #define TIM_BDTR_OSSR ((uint16_t)0x0800)
4453 #define TIM_BDTR_BKE ((uint16_t)0x1000)
4454 #define TIM_BDTR_BKP ((uint16_t)0x2000)
4455 #define TIM_BDTR_AOE ((uint16_t)0x4000)
4456 #define TIM_BDTR_MOE ((uint16_t)0x8000)
4458 /******************* Bit definition for TIM_DCR register ********************/
4459 #define TIM_DCR_DBA ((uint16_t)0x001F)
4460 #define TIM_DCR_DBA_0 ((uint16_t)0x0001)
4461 #define TIM_DCR_DBA_1 ((uint16_t)0x0002)
4462 #define TIM_DCR_DBA_2 ((uint16_t)0x0004)
4463 #define TIM_DCR_DBA_3 ((uint16_t)0x0008)
4464 #define TIM_DCR_DBA_4 ((uint16_t)0x0010)
4466 #define TIM_DCR_DBL ((uint16_t)0x1F00)
4467 #define TIM_DCR_DBL_0 ((uint16_t)0x0100)
4468 #define TIM_DCR_DBL_1 ((uint16_t)0x0200)
4469 #define TIM_DCR_DBL_2 ((uint16_t)0x0400)
4470 #define TIM_DCR_DBL_3 ((uint16_t)0x0800)
4471 #define TIM_DCR_DBL_4 ((uint16_t)0x1000)
4473 /******************* Bit definition for TIM_DMAR register *******************/
4474 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF)
4476 /******************************************************************************/
4477 /* */
4478 /* Real-Time Clock */
4479 /* */
4480 /******************************************************************************/
4481 
4482 /******************* Bit definition for RTC_CRH register ********************/
4483 #define RTC_CRH_SECIE ((uint8_t)0x01)
4484 #define RTC_CRH_ALRIE ((uint8_t)0x02)
4485 #define RTC_CRH_OWIE ((uint8_t)0x04)
4487 /******************* Bit definition for RTC_CRL register ********************/
4488 #define RTC_CRL_SECF ((uint8_t)0x01)
4489 #define RTC_CRL_ALRF ((uint8_t)0x02)
4490 #define RTC_CRL_OWF ((uint8_t)0x04)
4491 #define RTC_CRL_RSF ((uint8_t)0x08)
4492 #define RTC_CRL_CNF ((uint8_t)0x10)
4493 #define RTC_CRL_RTOFF ((uint8_t)0x20)
4495 /******************* Bit definition for RTC_PRLH register *******************/
4496 #define RTC_PRLH_PRL ((uint16_t)0x000F)
4498 /******************* Bit definition for RTC_PRLL register *******************/
4499 #define RTC_PRLL_PRL ((uint16_t)0xFFFF)
4501 /******************* Bit definition for RTC_DIVH register *******************/
4502 #define RTC_DIVH_RTC_DIV ((uint16_t)0x000F)
4504 /******************* Bit definition for RTC_DIVL register *******************/
4505 #define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF)
4507 /******************* Bit definition for RTC_CNTH register *******************/
4508 #define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF)
4510 /******************* Bit definition for RTC_CNTL register *******************/
4511 #define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF)
4513 /******************* Bit definition for RTC_ALRH register *******************/
4514 #define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF)
4516 /******************* Bit definition for RTC_ALRL register *******************/
4517 #define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF)
4519 /******************************************************************************/
4520 /* */
4521 /* Independent WATCHDOG */
4522 /* */
4523 /******************************************************************************/
4524 
4525 /******************* Bit definition for IWDG_KR register ********************/
4526 #define IWDG_KR_KEY ((uint16_t)0xFFFF)
4528 /******************* Bit definition for IWDG_PR register ********************/
4529 #define IWDG_PR_PR ((uint8_t)0x07)
4530 #define IWDG_PR_PR_0 ((uint8_t)0x01)
4531 #define IWDG_PR_PR_1 ((uint8_t)0x02)
4532 #define IWDG_PR_PR_2 ((uint8_t)0x04)
4534 /******************* Bit definition for IWDG_RLR register *******************/
4535 #define IWDG_RLR_RL ((uint16_t)0x0FFF)
4537 /******************* Bit definition for IWDG_SR register ********************/
4538 #define IWDG_SR_PVU ((uint8_t)0x01)
4539 #define IWDG_SR_RVU ((uint8_t)0x02)
4541 /******************************************************************************/
4542 /* */
4543 /* Window WATCHDOG */
4544 /* */
4545 /******************************************************************************/
4546 
4547 /******************* Bit definition for WWDG_CR register ********************/
4548 #define WWDG_CR_T ((uint8_t)0x7F)
4549 #define WWDG_CR_T0 ((uint8_t)0x01)
4550 #define WWDG_CR_T1 ((uint8_t)0x02)
4551 #define WWDG_CR_T2 ((uint8_t)0x04)
4552 #define WWDG_CR_T3 ((uint8_t)0x08)
4553 #define WWDG_CR_T4 ((uint8_t)0x10)
4554 #define WWDG_CR_T5 ((uint8_t)0x20)
4555 #define WWDG_CR_T6 ((uint8_t)0x40)
4557 #define WWDG_CR_WDGA ((uint8_t)0x80)
4559 /******************* Bit definition for WWDG_CFR register *******************/
4560 #define WWDG_CFR_W ((uint16_t)0x007F)
4561 #define WWDG_CFR_W0 ((uint16_t)0x0001)
4562 #define WWDG_CFR_W1 ((uint16_t)0x0002)
4563 #define WWDG_CFR_W2 ((uint16_t)0x0004)
4564 #define WWDG_CFR_W3 ((uint16_t)0x0008)
4565 #define WWDG_CFR_W4 ((uint16_t)0x0010)
4566 #define WWDG_CFR_W5 ((uint16_t)0x0020)
4567 #define WWDG_CFR_W6 ((uint16_t)0x0040)
4569 #define WWDG_CFR_WDGTB ((uint16_t)0x0180)
4570 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080)
4571 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100)
4573 #define WWDG_CFR_EWI ((uint16_t)0x0200)
4575 /******************* Bit definition for WWDG_SR register ********************/
4576 #define WWDG_SR_EWIF ((uint8_t)0x01)
4578 /******************************************************************************/
4579 /* */
4580 /* Flexible Static Memory Controller */
4581 /* */
4582 /******************************************************************************/
4583 
4584 /****************** Bit definition for FSMC_BCR1 register *******************/
4585 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001)
4586 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002)
4588 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C)
4589 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004)
4590 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008)
4592 #define FSMC_BCR1_MWID ((uint32_t)0x00000030)
4593 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010)
4594 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020)
4596 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040)
4597 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100)
4598 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200)
4599 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400)
4600 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800)
4601 #define FSMC_BCR1_WREN ((uint32_t)0x00001000)
4602 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000)
4603 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000)
4604 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000)
4605 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000)
4607 /****************** Bit definition for FSMC_BCR2 register *******************/
4608 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001)
4609 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002)
4611 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C)
4612 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004)
4613 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008)
4615 #define FSMC_BCR2_MWID ((uint32_t)0x00000030)
4616 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010)
4617 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020)
4619 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040)
4620 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100)
4621 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200)
4622 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400)
4623 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800)
4624 #define FSMC_BCR2_WREN ((uint32_t)0x00001000)
4625 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000)
4626 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000)
4627 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000)
4628 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000)
4630 /****************** Bit definition for FSMC_BCR3 register *******************/
4631 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001)
4632 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002)
4634 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C)
4635 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004)
4636 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008)
4638 #define FSMC_BCR3_MWID ((uint32_t)0x00000030)
4639 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010)
4640 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020)
4642 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040)
4643 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100)
4644 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200)
4645 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400)
4646 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800)
4647 #define FSMC_BCR3_WREN ((uint32_t)0x00001000)
4648 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000)
4649 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000)
4650 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000)
4651 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000)
4653 /****************** Bit definition for FSMC_BCR4 register *******************/
4654 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001)
4655 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002)
4657 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C)
4658 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004)
4659 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008)
4661 #define FSMC_BCR4_MWID ((uint32_t)0x00000030)
4662 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010)
4663 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020)
4665 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040)
4666 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100)
4667 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200)
4668 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400)
4669 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800)
4670 #define FSMC_BCR4_WREN ((uint32_t)0x00001000)
4671 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000)
4672 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000)
4673 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000)
4674 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000)
4676 /****************** Bit definition for FSMC_BTR1 register ******************/
4677 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F)
4678 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001)
4679 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002)
4680 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004)
4681 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008)
4683 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0)
4684 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010)
4685 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020)
4686 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040)
4687 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080)
4689 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00)
4690 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100)
4691 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200)
4692 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400)
4693 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800)
4695 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000)
4696 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000)
4697 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000)
4698 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000)
4699 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000)
4701 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000)
4702 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000)
4703 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000)
4704 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000)
4705 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000)
4707 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000)
4708 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000)
4709 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000)
4710 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000)
4711 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000)
4713 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000)
4714 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000)
4715 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000)
4717 /****************** Bit definition for FSMC_BTR2 register *******************/
4718 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F)
4719 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001)
4720 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002)
4721 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004)
4722 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008)
4724 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0)
4725 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010)
4726 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020)
4727 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040)
4728 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080)
4730 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00)
4731 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100)
4732 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200)
4733 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400)
4734 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800)
4736 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000)
4737 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000)
4738 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000)
4739 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000)
4740 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000)
4742 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000)
4743 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000)
4744 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000)
4745 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000)
4746 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000)
4748 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000)
4749 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000)
4750 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000)
4751 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000)
4752 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000)
4754 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000)
4755 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000)
4756 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000)
4758 /******************* Bit definition for FSMC_BTR3 register *******************/
4759 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F)
4760 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001)
4761 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002)
4762 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004)
4763 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008)
4765 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0)
4766 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010)
4767 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020)
4768 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040)
4769 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080)
4771 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00)
4772 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100)
4773 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200)
4774 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400)
4775 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800)
4777 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000)
4778 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000)
4779 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000)
4780 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000)
4781 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000)
4783 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000)
4784 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000)
4785 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000)
4786 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000)
4787 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000)
4789 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000)
4790 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000)
4791 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000)
4792 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000)
4793 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000)
4795 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000)
4796 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000)
4797 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000)
4799 /****************** Bit definition for FSMC_BTR4 register *******************/
4800 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F)
4801 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001)
4802 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002)
4803 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004)
4804 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008)
4806 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0)
4807 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010)
4808 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020)
4809 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040)
4810 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080)
4812 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00)
4813 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100)
4814 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200)
4815 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400)
4816 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800)
4818 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000)
4819 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000)
4820 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000)
4821 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000)
4822 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000)
4824 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000)
4825 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000)
4826 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000)
4827 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000)
4828 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000)
4830 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000)
4831 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000)
4832 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000)
4833 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000)
4834 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000)
4836 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000)
4837 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000)
4838 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000)
4840 /****************** Bit definition for FSMC_BWTR1 register ******************/
4841 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F)
4842 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001)
4843 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002)
4844 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004)
4845 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008)
4847 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0)
4848 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010)
4849 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020)
4850 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040)
4851 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080)
4853 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00)
4854 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100)
4855 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200)
4856 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400)
4857 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800)
4859 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000)
4860 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000)
4861 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000)
4862 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000)
4863 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000)
4865 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000)
4866 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000)
4867 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000)
4868 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000)
4869 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000)
4871 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000)
4872 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000)
4873 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000)
4875 /****************** Bit definition for FSMC_BWTR2 register ******************/
4876 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F)
4877 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001)
4878 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002)
4879 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004)
4880 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008)
4882 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0)
4883 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010)
4884 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020)
4885 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040)
4886 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080)
4888 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00)
4889 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100)
4890 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200)
4891 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400)
4892 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800)
4894 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000)
4895 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000)
4896 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000)
4897 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000)
4898 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000)
4900 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000)
4901 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000)
4902 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000)
4903 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000)
4904 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000)
4906 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000)
4907 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000)
4908 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000)
4910 /****************** Bit definition for FSMC_BWTR3 register ******************/
4911 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F)
4912 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001)
4913 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002)
4914 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004)
4915 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008)
4917 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0)
4918 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010)
4919 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020)
4920 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040)
4921 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080)
4923 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00)
4924 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100)
4925 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200)
4926 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400)
4927 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800)
4929 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000)
4930 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000)
4931 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000)
4932 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000)
4933 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000)
4935 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000)
4936 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000)
4937 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000)
4938 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000)
4939 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000)
4941 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000)
4942 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000)
4943 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000)
4945 /****************** Bit definition for FSMC_BWTR4 register ******************/
4946 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F)
4947 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001)
4948 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002)
4949 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004)
4950 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008)
4952 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0)
4953 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010)
4954 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020)
4955 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040)
4956 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080)
4958 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00)
4959 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100)
4960 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200)
4961 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400)
4962 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800)
4964 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000)
4965 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000)
4966 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000)
4967 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000)
4968 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000)
4970 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000)
4971 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000)
4972 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000)
4973 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000)
4974 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000)
4976 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000)
4977 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000)
4978 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000)
4980 /****************** Bit definition for FSMC_PCR2 register *******************/
4981 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002)
4982 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004)
4983 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008)
4985 #define FSMC_PCR2_PWID ((uint32_t)0x00000030)
4986 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010)
4987 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020)
4989 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040)
4991 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00)
4992 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200)
4993 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400)
4994 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800)
4995 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000)
4997 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000)
4998 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000)
4999 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000)
5000 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000)
5001 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000)
5003 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000)
5004 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000)
5005 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000)
5006 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000)
5008 /****************** Bit definition for FSMC_PCR3 register *******************/
5009 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002)
5010 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004)
5011 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008)
5013 #define FSMC_PCR3_PWID ((uint32_t)0x00000030)
5014 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010)
5015 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020)
5017 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040)
5019 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00)
5020 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200)
5021 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400)
5022 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800)
5023 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000)
5025 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000)
5026 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000)
5027 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000)
5028 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000)
5029 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000)
5031 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000)
5032 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000)
5033 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000)
5034 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000)
5036 /****************** Bit definition for FSMC_PCR4 register *******************/
5037 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002)
5038 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004)
5039 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008)
5041 #define FSMC_PCR4_PWID ((uint32_t)0x00000030)
5042 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010)
5043 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020)
5045 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040)
5047 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00)
5048 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200)
5049 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400)
5050 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800)
5051 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000)
5053 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000)
5054 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000)
5055 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000)
5056 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000)
5057 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000)
5059 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000)
5060 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000)
5061 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000)
5062 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000)
5064 /******************* Bit definition for FSMC_SR2 register *******************/
5065 #define FSMC_SR2_IRS ((uint8_t)0x01)
5066 #define FSMC_SR2_ILS ((uint8_t)0x02)
5067 #define FSMC_SR2_IFS ((uint8_t)0x04)
5068 #define FSMC_SR2_IREN ((uint8_t)0x08)
5069 #define FSMC_SR2_ILEN ((uint8_t)0x10)
5070 #define FSMC_SR2_IFEN ((uint8_t)0x20)
5071 #define FSMC_SR2_FEMPT ((uint8_t)0x40)
5073 /******************* Bit definition for FSMC_SR3 register *******************/
5074 #define FSMC_SR3_IRS ((uint8_t)0x01)
5075 #define FSMC_SR3_ILS ((uint8_t)0x02)
5076 #define FSMC_SR3_IFS ((uint8_t)0x04)
5077 #define FSMC_SR3_IREN ((uint8_t)0x08)
5078 #define FSMC_SR3_ILEN ((uint8_t)0x10)
5079 #define FSMC_SR3_IFEN ((uint8_t)0x20)
5080 #define FSMC_SR3_FEMPT ((uint8_t)0x40)
5082 /******************* Bit definition for FSMC_SR4 register *******************/
5083 #define FSMC_SR4_IRS ((uint8_t)0x01)
5084 #define FSMC_SR4_ILS ((uint8_t)0x02)
5085 #define FSMC_SR4_IFS ((uint8_t)0x04)
5086 #define FSMC_SR4_IREN ((uint8_t)0x08)
5087 #define FSMC_SR4_ILEN ((uint8_t)0x10)
5088 #define FSMC_SR4_IFEN ((uint8_t)0x20)
5089 #define FSMC_SR4_FEMPT ((uint8_t)0x40)
5091 /****************** Bit definition for FSMC_PMEM2 register ******************/
5092 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF)
5093 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001)
5094 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002)
5095 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004)
5096 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008)
5097 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010)
5098 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020)
5099 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040)
5100 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080)
5102 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00)
5103 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100)
5104 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200)
5105 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400)
5106 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800)
5107 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000)
5108 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000)
5109 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000)
5110 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000)
5112 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000)
5113 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000)
5114 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000)
5115 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000)
5116 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000)
5117 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000)
5118 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000)
5119 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000)
5120 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000)
5122 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000)
5123 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000)
5124 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000)
5125 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000)
5126 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000)
5127 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000)
5128 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000)
5129 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000)
5130 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000)
5132 /****************** Bit definition for FSMC_PMEM3 register ******************/
5133 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF)
5134 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001)
5135 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002)
5136 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004)
5137 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008)
5138 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010)
5139 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020)
5140 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040)
5141 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080)
5143 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00)
5144 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100)
5145 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200)
5146 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400)
5147 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800)
5148 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000)
5149 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000)
5150 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000)
5151 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000)
5153 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000)
5154 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000)
5155 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000)
5156 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000)
5157 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000)
5158 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000)
5159 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000)
5160 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000)
5161 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000)
5163 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000)
5164 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000)
5165 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000)
5166 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000)
5167 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000)
5168 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000)
5169 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000)
5170 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000)
5171 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000)
5173 /****************** Bit definition for FSMC_PMEM4 register ******************/
5174 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF)
5175 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001)
5176 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002)
5177 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004)
5178 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008)
5179 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010)
5180 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020)
5181 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040)
5182 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080)
5184 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00)
5185 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100)
5186 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200)
5187 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400)
5188 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800)
5189 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000)
5190 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000)
5191 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000)
5192 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000)
5194 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000)
5195 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000)
5196 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000)
5197 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000)
5198 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000)
5199 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000)
5200 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000)
5201 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000)
5202 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000)
5204 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000)
5205 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000)
5206 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000)
5207 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000)
5208 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000)
5209 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000)
5210 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000)
5211 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000)
5212 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000)
5214 /****************** Bit definition for FSMC_PATT2 register ******************/
5215 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF)
5216 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001)
5217 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002)
5218 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004)
5219 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008)
5220 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010)
5221 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020)
5222 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040)
5223 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080)
5225 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00)
5226 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100)
5227 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200)
5228 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400)
5229 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800)
5230 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000)
5231 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000)
5232 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000)
5233 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000)
5235 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000)
5236 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000)
5237 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000)
5238 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000)
5239 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000)
5240 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000)
5241 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000)
5242 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000)
5243 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000)
5245 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000)
5246 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000)
5247 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000)
5248 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000)
5249 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000)
5250 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000)
5251 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000)
5252 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000)
5253 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000)
5255 /****************** Bit definition for FSMC_PATT3 register ******************/
5256 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF)
5257 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001)
5258 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002)
5259 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004)
5260 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008)
5261 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010)
5262 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020)
5263 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040)
5264 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080)
5266 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00)
5267 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100)
5268 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200)
5269 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400)
5270 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800)
5271 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000)
5272 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000)
5273 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000)
5274 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000)
5276 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000)
5277 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000)
5278 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000)
5279 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000)
5280 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000)
5281 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000)
5282 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000)
5283 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000)
5284 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000)
5286 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000)
5287 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000)
5288 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000)
5289 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000)
5290 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000)
5291 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000)
5292 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000)
5293 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000)
5294 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000)
5296 /****************** Bit definition for FSMC_PATT4 register ******************/
5297 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF)
5298 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001)
5299 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002)
5300 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004)
5301 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008)
5302 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010)
5303 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020)
5304 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040)
5305 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080)
5307 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00)
5308 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100)
5309 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200)
5310 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400)
5311 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800)
5312 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000)
5313 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000)
5314 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000)
5315 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000)
5317 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000)
5318 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000)
5319 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000)
5320 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000)
5321 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000)
5322 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000)
5323 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000)
5324 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000)
5325 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000)
5327 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000)
5328 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000)
5329 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000)
5330 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000)
5331 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000)
5332 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000)
5333 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000)
5334 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000)
5335 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000)
5337 /****************** Bit definition for FSMC_PIO4 register *******************/
5338 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF)
5339 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001)
5340 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002)
5341 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004)
5342 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008)
5343 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010)
5344 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020)
5345 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040)
5346 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080)
5348 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00)
5349 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100)
5350 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200)
5351 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400)
5352 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800)
5353 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000)
5354 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000)
5355 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000)
5356 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000)
5358 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000)
5359 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000)
5360 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000)
5361 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000)
5362 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000)
5363 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000)
5364 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000)
5365 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000)
5366 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000)
5368 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000)
5369 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000)
5370 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000)
5371 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000)
5372 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000)
5373 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000)
5374 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000)
5375 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000)
5376 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000)
5378 /****************** Bit definition for FSMC_ECCR2 register ******************/
5379 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF)
5381 /****************** Bit definition for FSMC_ECCR3 register ******************/
5382 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF)
5384 /******************************************************************************/
5385 /* */
5386 /* SD host Interface */
5387 /* */
5388 /******************************************************************************/
5389 
5390 /****************** Bit definition for SDIO_POWER register ******************/
5391 #define SDIO_POWER_PWRCTRL ((uint8_t)0x03)
5392 #define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01)
5393 #define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02)
5395 /****************** Bit definition for SDIO_CLKCR register ******************/
5396 #define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF)
5397 #define SDIO_CLKCR_CLKEN ((uint16_t)0x0100)
5398 #define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200)
5399 #define SDIO_CLKCR_BYPASS ((uint16_t)0x0400)
5401 #define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800)
5402 #define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800)
5403 #define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000)
5405 #define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000)
5406 #define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000)
5408 /******************* Bit definition for SDIO_ARG register *******************/
5409 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF)
5411 /******************* Bit definition for SDIO_CMD register *******************/
5412 #define SDIO_CMD_CMDINDEX ((uint16_t)0x003F)
5414 #define SDIO_CMD_WAITRESP ((uint16_t)0x00C0)
5415 #define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040)
5416 #define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080)
5418 #define SDIO_CMD_WAITINT ((uint16_t)0x0100)
5419 #define SDIO_CMD_WAITPEND ((uint16_t)0x0200)
5420 #define SDIO_CMD_CPSMEN ((uint16_t)0x0400)
5421 #define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800)
5422 #define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000)
5423 #define SDIO_CMD_NIEN ((uint16_t)0x2000)
5424 #define SDIO_CMD_CEATACMD ((uint16_t)0x4000)
5426 /***************** Bit definition for SDIO_RESPCMD register *****************/
5427 #define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F)
5429 /****************** Bit definition for SDIO_RESP0 register ******************/
5430 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF)
5432 /****************** Bit definition for SDIO_RESP1 register ******************/
5433 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF)
5435 /****************** Bit definition for SDIO_RESP2 register ******************/
5436 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF)
5438 /****************** Bit definition for SDIO_RESP3 register ******************/
5439 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF)
5441 /****************** Bit definition for SDIO_RESP4 register ******************/
5442 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF)
5444 /****************** Bit definition for SDIO_DTIMER register *****************/
5445 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF)
5447 /****************** Bit definition for SDIO_DLEN register *******************/
5448 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF)
5450 /****************** Bit definition for SDIO_DCTRL register ******************/
5451 #define SDIO_DCTRL_DTEN ((uint16_t)0x0001)
5452 #define SDIO_DCTRL_DTDIR ((uint16_t)0x0002)
5453 #define SDIO_DCTRL_DTMODE ((uint16_t)0x0004)
5454 #define SDIO_DCTRL_DMAEN ((uint16_t)0x0008)
5456 #define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0)
5457 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010)
5458 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020)
5459 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040)
5460 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080)
5462 #define SDIO_DCTRL_RWSTART ((uint16_t)0x0100)
5463 #define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200)
5464 #define SDIO_DCTRL_RWMOD ((uint16_t)0x0400)
5465 #define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800)
5467 /****************** Bit definition for SDIO_DCOUNT register *****************/
5468 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF)
5470 /****************** Bit definition for SDIO_STA register ********************/
5471 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001)
5472 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002)
5473 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004)
5474 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008)
5475 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010)
5476 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020)
5477 #define SDIO_STA_CMDREND ((uint32_t)0x00000040)
5478 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080)
5479 #define SDIO_STA_DATAEND ((uint32_t)0x00000100)
5480 #define SDIO_STA_STBITERR ((uint32_t)0x00000200)
5481 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400)
5482 #define SDIO_STA_CMDACT ((uint32_t)0x00000800)
5483 #define SDIO_STA_TXACT ((uint32_t)0x00001000)
5484 #define SDIO_STA_RXACT ((uint32_t)0x00002000)
5485 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000)
5486 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000)
5487 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000)
5488 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000)
5489 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000)
5490 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000)
5491 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000)
5492 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000)
5493 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000)
5494 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000)
5496 /******************* Bit definition for SDIO_ICR register *******************/
5497 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001)
5498 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002)
5499 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004)
5500 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008)
5501 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010)
5502 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020)
5503 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040)
5504 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080)
5505 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100)
5506 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200)
5507 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400)
5508 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000)
5509 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000)
5511 /****************** Bit definition for SDIO_MASK register *******************/
5512 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001)
5513 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002)
5514 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004)
5515 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008)
5516 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010)
5517 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020)
5518 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040)
5519 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080)
5520 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100)
5521 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200)
5522 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400)
5523 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800)
5524 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000)
5525 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000)
5526 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000)
5527 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000)
5528 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000)
5529 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000)
5530 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000)
5531 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000)
5532 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000)
5533 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000)
5534 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000)
5535 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000)
5537 /***************** Bit definition for SDIO_FIFOCNT register *****************/
5538 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF)
5540 /****************** Bit definition for SDIO_FIFO register *******************/
5541 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF)
5543 /******************************************************************************/
5544 /* */
5545 /* USB Device FS */
5546 /* */
5547 /******************************************************************************/
5548 
5550 /******************* Bit definition for USB_EP0R register *******************/
5551 #define USB_EP0R_EA ((uint16_t)0x000F)
5553 #define USB_EP0R_STAT_TX ((uint16_t)0x0030)
5554 #define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010)
5555 #define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020)
5557 #define USB_EP0R_DTOG_TX ((uint16_t)0x0040)
5558 #define USB_EP0R_CTR_TX ((uint16_t)0x0080)
5559 #define USB_EP0R_EP_KIND ((uint16_t)0x0100)
5561 #define USB_EP0R_EP_TYPE ((uint16_t)0x0600)
5562 #define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200)
5563 #define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400)
5565 #define USB_EP0R_SETUP ((uint16_t)0x0800)
5567 #define USB_EP0R_STAT_RX ((uint16_t)0x3000)
5568 #define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000)
5569 #define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000)
5571 #define USB_EP0R_DTOG_RX ((uint16_t)0x4000)
5572 #define USB_EP0R_CTR_RX ((uint16_t)0x8000)
5574 /******************* Bit definition for USB_EP1R register *******************/
5575 #define USB_EP1R_EA ((uint16_t)0x000F)
5577 #define USB_EP1R_STAT_TX ((uint16_t)0x0030)
5578 #define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010)
5579 #define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020)
5581 #define USB_EP1R_DTOG_TX ((uint16_t)0x0040)
5582 #define USB_EP1R_CTR_TX ((uint16_t)0x0080)
5583 #define USB_EP1R_EP_KIND ((uint16_t)0x0100)
5585 #define USB_EP1R_EP_TYPE ((uint16_t)0x0600)
5586 #define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200)
5587 #define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400)
5589 #define USB_EP1R_SETUP ((uint16_t)0x0800)
5591 #define USB_EP1R_STAT_RX ((uint16_t)0x3000)
5592 #define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000)
5593 #define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000)
5595 #define USB_EP1R_DTOG_RX ((uint16_t)0x4000)
5596 #define USB_EP1R_CTR_RX ((uint16_t)0x8000)
5598 /******************* Bit definition for USB_EP2R register *******************/
5599 #define USB_EP2R_EA ((uint16_t)0x000F)
5601 #define USB_EP2R_STAT_TX ((uint16_t)0x0030)
5602 #define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010)
5603 #define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020)
5605 #define USB_EP2R_DTOG_TX ((uint16_t)0x0040)
5606 #define USB_EP2R_CTR_TX ((uint16_t)0x0080)
5607 #define USB_EP2R_EP_KIND ((uint16_t)0x0100)
5609 #define USB_EP2R_EP_TYPE ((uint16_t)0x0600)
5610 #define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200)
5611 #define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400)
5613 #define USB_EP2R_SETUP ((uint16_t)0x0800)
5615 #define USB_EP2R_STAT_RX ((uint16_t)0x3000)
5616 #define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000)
5617 #define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000)
5619 #define USB_EP2R_DTOG_RX ((uint16_t)0x4000)
5620 #define USB_EP2R_CTR_RX ((uint16_t)0x8000)
5622 /******************* Bit definition for USB_EP3R register *******************/
5623 #define USB_EP3R_EA ((uint16_t)0x000F)
5625 #define USB_EP3R_STAT_TX ((uint16_t)0x0030)
5626 #define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010)
5627 #define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020)
5629 #define USB_EP3R_DTOG_TX ((uint16_t)0x0040)
5630 #define USB_EP3R_CTR_TX ((uint16_t)0x0080)
5631 #define USB_EP3R_EP_KIND ((uint16_t)0x0100)
5633 #define USB_EP3R_EP_TYPE ((uint16_t)0x0600)
5634 #define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200)
5635 #define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400)
5637 #define USB_EP3R_SETUP ((uint16_t)0x0800)
5639 #define USB_EP3R_STAT_RX ((uint16_t)0x3000)
5640 #define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000)
5641 #define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000)
5643 #define USB_EP3R_DTOG_RX ((uint16_t)0x4000)
5644 #define USB_EP3R_CTR_RX ((uint16_t)0x8000)
5646 /******************* Bit definition for USB_EP4R register *******************/
5647 #define USB_EP4R_EA ((uint16_t)0x000F)
5649 #define USB_EP4R_STAT_TX ((uint16_t)0x0030)
5650 #define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010)
5651 #define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020)
5653 #define USB_EP4R_DTOG_TX ((uint16_t)0x0040)
5654 #define USB_EP4R_CTR_TX ((uint16_t)0x0080)
5655 #define USB_EP4R_EP_KIND ((uint16_t)0x0100)
5657 #define USB_EP4R_EP_TYPE ((uint16_t)0x0600)
5658 #define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200)
5659 #define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400)
5661 #define USB_EP4R_SETUP ((uint16_t)0x0800)
5663 #define USB_EP4R_STAT_RX ((uint16_t)0x3000)
5664 #define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000)
5665 #define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000)
5667 #define USB_EP4R_DTOG_RX ((uint16_t)0x4000)
5668 #define USB_EP4R_CTR_RX ((uint16_t)0x8000)
5670 /******************* Bit definition for USB_EP5R register *******************/
5671 #define USB_EP5R_EA ((uint16_t)0x000F)
5673 #define USB_EP5R_STAT_TX ((uint16_t)0x0030)
5674 #define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010)
5675 #define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020)
5677 #define USB_EP5R_DTOG_TX ((uint16_t)0x0040)
5678 #define USB_EP5R_CTR_TX ((uint16_t)0x0080)
5679 #define USB_EP5R_EP_KIND ((uint16_t)0x0100)
5681 #define USB_EP5R_EP_TYPE ((uint16_t)0x0600)
5682 #define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200)
5683 #define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400)
5685 #define USB_EP5R_SETUP ((uint16_t)0x0800)
5687 #define USB_EP5R_STAT_RX ((uint16_t)0x3000)
5688 #define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000)
5689 #define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000)
5691 #define USB_EP5R_DTOG_RX ((uint16_t)0x4000)
5692 #define USB_EP5R_CTR_RX ((uint16_t)0x8000)
5694 /******************* Bit definition for USB_EP6R register *******************/
5695 #define USB_EP6R_EA ((uint16_t)0x000F)
5697 #define USB_EP6R_STAT_TX ((uint16_t)0x0030)
5698 #define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010)
5699 #define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020)
5701 #define USB_EP6R_DTOG_TX ((uint16_t)0x0040)
5702 #define USB_EP6R_CTR_TX ((uint16_t)0x0080)
5703 #define USB_EP6R_EP_KIND ((uint16_t)0x0100)
5705 #define USB_EP6R_EP_TYPE ((uint16_t)0x0600)
5706 #define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200)
5707 #define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400)
5709 #define USB_EP6R_SETUP ((uint16_t)0x0800)
5711 #define USB_EP6R_STAT_RX ((uint16_t)0x3000)
5712 #define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000)
5713 #define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000)
5715 #define USB_EP6R_DTOG_RX ((uint16_t)0x4000)
5716 #define USB_EP6R_CTR_RX ((uint16_t)0x8000)
5718 /******************* Bit definition for USB_EP7R register *******************/
5719 #define USB_EP7R_EA ((uint16_t)0x000F)
5721 #define USB_EP7R_STAT_TX ((uint16_t)0x0030)
5722 #define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010)
5723 #define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020)
5725 #define USB_EP7R_DTOG_TX ((uint16_t)0x0040)
5726 #define USB_EP7R_CTR_TX ((uint16_t)0x0080)
5727 #define USB_EP7R_EP_KIND ((uint16_t)0x0100)
5729 #define USB_EP7R_EP_TYPE ((uint16_t)0x0600)
5730 #define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200)
5731 #define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400)
5733 #define USB_EP7R_SETUP ((uint16_t)0x0800)
5735 #define USB_EP7R_STAT_RX ((uint16_t)0x3000)
5736 #define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000)
5737 #define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000)
5739 #define USB_EP7R_DTOG_RX ((uint16_t)0x4000)
5740 #define USB_EP7R_CTR_RX ((uint16_t)0x8000)
5743 /******************* Bit definition for USB_CNTR register *******************/
5744 #define USB_CNTR_FRES ((uint16_t)0x0001)
5745 #define USB_CNTR_PDWN ((uint16_t)0x0002)
5746 #define USB_CNTR_LP_MODE ((uint16_t)0x0004)
5747 #define USB_CNTR_FSUSP ((uint16_t)0x0008)
5748 #define USB_CNTR_RESUME ((uint16_t)0x0010)
5749 #define USB_CNTR_ESOFM ((uint16_t)0x0100)
5750 #define USB_CNTR_SOFM ((uint16_t)0x0200)
5751 #define USB_CNTR_RESETM ((uint16_t)0x0400)
5752 #define USB_CNTR_SUSPM ((uint16_t)0x0800)
5753 #define USB_CNTR_WKUPM ((uint16_t)0x1000)
5754 #define USB_CNTR_ERRM ((uint16_t)0x2000)
5755 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000)
5756 #define USB_CNTR_CTRM ((uint16_t)0x8000)
5758 /******************* Bit definition for USB_ISTR register *******************/
5759 #define USB_ISTR_EP_ID ((uint16_t)0x000F)
5760 #define USB_ISTR_DIR ((uint16_t)0x0010)
5761 #define USB_ISTR_ESOF ((uint16_t)0x0100)
5762 #define USB_ISTR_SOF ((uint16_t)0x0200)
5763 #define USB_ISTR_RESET ((uint16_t)0x0400)
5764 #define USB_ISTR_SUSP ((uint16_t)0x0800)
5765 #define USB_ISTR_WKUP ((uint16_t)0x1000)
5766 #define USB_ISTR_ERR ((uint16_t)0x2000)
5767 #define USB_ISTR_PMAOVR ((uint16_t)0x4000)
5768 #define USB_ISTR_CTR ((uint16_t)0x8000)
5770 /******************* Bit definition for USB_FNR register ********************/
5771 #define USB_FNR_FN ((uint16_t)0x07FF)
5772 #define USB_FNR_LSOF ((uint16_t)0x1800)
5773 #define USB_FNR_LCK ((uint16_t)0x2000)
5774 #define USB_FNR_RXDM ((uint16_t)0x4000)
5775 #define USB_FNR_RXDP ((uint16_t)0x8000)
5777 /****************** Bit definition for USB_DADDR register *******************/
5778 #define USB_DADDR_ADD ((uint8_t)0x7F)
5779 #define USB_DADDR_ADD0 ((uint8_t)0x01)
5780 #define USB_DADDR_ADD1 ((uint8_t)0x02)
5781 #define USB_DADDR_ADD2 ((uint8_t)0x04)
5782 #define USB_DADDR_ADD3 ((uint8_t)0x08)
5783 #define USB_DADDR_ADD4 ((uint8_t)0x10)
5784 #define USB_DADDR_ADD5 ((uint8_t)0x20)
5785 #define USB_DADDR_ADD6 ((uint8_t)0x40)
5787 #define USB_DADDR_EF ((uint8_t)0x80)
5789 /****************** Bit definition for USB_BTABLE register ******************/
5790 #define USB_BTABLE_BTABLE ((uint16_t)0xFFF8)
5793 /***************** Bit definition for USB_ADDR0_TX register *****************/
5794 #define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE)
5796 /***************** Bit definition for USB_ADDR1_TX register *****************/
5797 #define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE)
5799 /***************** Bit definition for USB_ADDR2_TX register *****************/
5800 #define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE)
5802 /***************** Bit definition for USB_ADDR3_TX register *****************/
5803 #define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE)
5805 /***************** Bit definition for USB_ADDR4_TX register *****************/
5806 #define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE)
5808 /***************** Bit definition for USB_ADDR5_TX register *****************/
5809 #define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE)
5811 /***************** Bit definition for USB_ADDR6_TX register *****************/
5812 #define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE)
5814 /***************** Bit definition for USB_ADDR7_TX register *****************/
5815 #define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE)
5817 /*----------------------------------------------------------------------------*/
5818 
5819 /***************** Bit definition for USB_COUNT0_TX register ****************/
5820 #define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF)
5822 /***************** Bit definition for USB_COUNT1_TX register ****************/
5823 #define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF)
5825 /***************** Bit definition for USB_COUNT2_TX register ****************/
5826 #define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF)
5828 /***************** Bit definition for USB_COUNT3_TX register ****************/
5829 #define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF)
5831 /***************** Bit definition for USB_COUNT4_TX register ****************/
5832 #define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF)
5834 /***************** Bit definition for USB_COUNT5_TX register ****************/
5835 #define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF)
5837 /***************** Bit definition for USB_COUNT6_TX register ****************/
5838 #define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF)
5840 /***************** Bit definition for USB_COUNT7_TX register ****************/
5841 #define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF)
5843 /*----------------------------------------------------------------------------*/
5844 
5845 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
5846 #define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF)
5848 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
5849 #define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000)
5851 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
5852 #define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF)
5854 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
5855 #define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000)
5857 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
5858 #define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF)
5860 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
5861 #define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000)
5863 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
5864 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF)
5866 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
5867 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000)
5869 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
5870 #define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF)
5872 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
5873 #define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000)
5875 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
5876 #define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF)
5878 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
5879 #define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000)
5881 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
5882 #define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF)
5884 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
5885 #define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000)
5887 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
5888 #define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF)
5890 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
5891 #define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000)
5893 /*----------------------------------------------------------------------------*/
5894 
5895 /***************** Bit definition for USB_ADDR0_RX register *****************/
5896 #define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE)
5898 /***************** Bit definition for USB_ADDR1_RX register *****************/
5899 #define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE)
5901 /***************** Bit definition for USB_ADDR2_RX register *****************/
5902 #define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE)
5904 /***************** Bit definition for USB_ADDR3_RX register *****************/
5905 #define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE)
5907 /***************** Bit definition for USB_ADDR4_RX register *****************/
5908 #define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE)
5910 /***************** Bit definition for USB_ADDR5_RX register *****************/
5911 #define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE)
5913 /***************** Bit definition for USB_ADDR6_RX register *****************/
5914 #define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE)
5916 /***************** Bit definition for USB_ADDR7_RX register *****************/
5917 #define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE)
5919 /*----------------------------------------------------------------------------*/
5920 
5921 /***************** Bit definition for USB_COUNT0_RX register ****************/
5922 #define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF)
5924 #define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00)
5925 #define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
5926 #define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
5927 #define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
5928 #define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
5929 #define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
5931 #define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000)
5933 /***************** Bit definition for USB_COUNT1_RX register ****************/
5934 #define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF)
5936 #define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00)
5937 #define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
5938 #define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
5939 #define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
5940 #define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
5941 #define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
5943 #define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000)
5945 /***************** Bit definition for USB_COUNT2_RX register ****************/
5946 #define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF)
5948 #define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00)
5949 #define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
5950 #define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
5951 #define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
5952 #define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
5953 #define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
5955 #define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000)
5957 /***************** Bit definition for USB_COUNT3_RX register ****************/
5958 #define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF)
5960 #define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00)
5961 #define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
5962 #define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
5963 #define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
5964 #define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
5965 #define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
5967 #define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000)
5969 /***************** Bit definition for USB_COUNT4_RX register ****************/
5970 #define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF)
5972 #define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00)
5973 #define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
5974 #define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
5975 #define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
5976 #define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
5977 #define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
5979 #define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000)
5981 /***************** Bit definition for USB_COUNT5_RX register ****************/
5982 #define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF)
5984 #define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00)
5985 #define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
5986 #define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
5987 #define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
5988 #define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
5989 #define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
5991 #define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000)
5993 /***************** Bit definition for USB_COUNT6_RX register ****************/
5994 #define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF)
5996 #define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00)
5997 #define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
5998 #define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
5999 #define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
6000 #define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
6001 #define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
6003 #define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000)
6005 /***************** Bit definition for USB_COUNT7_RX register ****************/
6006 #define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF)
6008 #define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00)
6009 #define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
6010 #define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
6011 #define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
6012 #define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
6013 #define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
6015 #define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000)
6017 /*----------------------------------------------------------------------------*/
6018 
6019 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
6020 #define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF)
6022 #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
6023 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
6024 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
6025 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
6026 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
6027 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
6029 #define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
6031 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
6032 #define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000)
6034 #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
6035 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
6036 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
6037 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
6038 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
6039 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
6041 #define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
6043 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
6044 #define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF)
6046 #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
6047 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
6048 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
6049 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
6050 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
6051 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
6053 #define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
6055 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
6056 #define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000)
6058 #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
6059 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
6060 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
6061 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
6062 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
6063 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
6065 #define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
6067 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
6068 #define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF)
6070 #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
6071 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
6072 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
6073 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
6074 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
6075 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
6077 #define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
6079 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
6080 #define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000)
6082 #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
6083 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
6084 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
6085 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
6086 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
6087 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
6089 #define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
6091 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
6092 #define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF)
6094 #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
6095 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
6096 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
6097 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
6098 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
6099 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
6101 #define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
6103 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
6104 #define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000)
6106 #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
6107 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
6108 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
6109 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
6110 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
6111 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
6113 #define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
6115 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
6116 #define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF)
6118 #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
6119 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
6120 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
6121 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
6122 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
6123 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
6125 #define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
6127 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
6128 #define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000)
6130 #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
6131 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
6132 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
6133 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
6134 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
6135 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
6137 #define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
6139 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
6140 #define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF)
6142 #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
6143 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
6144 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
6145 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
6146 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
6147 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
6149 #define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
6151 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
6152 #define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000)
6154 #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
6155 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
6156 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
6157 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
6158 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
6159 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
6161 #define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
6163 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
6164 #define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF)
6166 #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
6167 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
6168 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
6169 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
6170 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
6171 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
6173 #define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
6175 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
6176 #define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000)
6178 #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
6179 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
6180 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
6181 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
6182 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
6183 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
6185 #define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
6187 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
6188 #define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF)
6190 #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
6191 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
6192 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
6193 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
6194 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
6195 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
6197 #define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
6199 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
6200 #define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000)
6202 #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
6203 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
6204 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
6205 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
6206 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
6207 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
6209 #define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
6211 /******************************************************************************/
6212 /* */
6213 /* Controller Area Network */
6214 /* */
6215 /******************************************************************************/
6216 
6218 /******************* Bit definition for CAN_MCR register ********************/
6219 #define CAN_MCR_INRQ ((uint16_t)0x0001)
6220 #define CAN_MCR_SLEEP ((uint16_t)0x0002)
6221 #define CAN_MCR_TXFP ((uint16_t)0x0004)
6222 #define CAN_MCR_RFLM ((uint16_t)0x0008)
6223 #define CAN_MCR_NART ((uint16_t)0x0010)
6224 #define CAN_MCR_AWUM ((uint16_t)0x0020)
6225 #define CAN_MCR_ABOM ((uint16_t)0x0040)
6226 #define CAN_MCR_TTCM ((uint16_t)0x0080)
6227 #define CAN_MCR_RESET ((uint16_t)0x8000)
6229 /******************* Bit definition for CAN_MSR register ********************/
6230 #define CAN_MSR_INAK ((uint16_t)0x0001)
6231 #define CAN_MSR_SLAK ((uint16_t)0x0002)
6232 #define CAN_MSR_ERRI ((uint16_t)0x0004)
6233 #define CAN_MSR_WKUI ((uint16_t)0x0008)
6234 #define CAN_MSR_SLAKI ((uint16_t)0x0010)
6235 #define CAN_MSR_TXM ((uint16_t)0x0100)
6236 #define CAN_MSR_RXM ((uint16_t)0x0200)
6237 #define CAN_MSR_SAMP ((uint16_t)0x0400)
6238 #define CAN_MSR_RX ((uint16_t)0x0800)
6240 /******************* Bit definition for CAN_TSR register ********************/
6241 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001)
6242 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002)
6243 #define CAN_TSR_ALST0 ((uint32_t)0x00000004)
6244 #define CAN_TSR_TERR0 ((uint32_t)0x00000008)
6245 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080)
6246 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100)
6247 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200)
6248 #define CAN_TSR_ALST1 ((uint32_t)0x00000400)
6249 #define CAN_TSR_TERR1 ((uint32_t)0x00000800)
6250 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000)
6251 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000)
6252 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000)
6253 #define CAN_TSR_ALST2 ((uint32_t)0x00040000)
6254 #define CAN_TSR_TERR2 ((uint32_t)0x00080000)
6255 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000)
6256 #define CAN_TSR_CODE ((uint32_t)0x03000000)
6258 #define CAN_TSR_TME ((uint32_t)0x1C000000)
6259 #define CAN_TSR_TME0 ((uint32_t)0x04000000)
6260 #define CAN_TSR_TME1 ((uint32_t)0x08000000)
6261 #define CAN_TSR_TME2 ((uint32_t)0x10000000)
6263 #define CAN_TSR_LOW ((uint32_t)0xE0000000)
6264 #define CAN_TSR_LOW0 ((uint32_t)0x20000000)
6265 #define CAN_TSR_LOW1 ((uint32_t)0x40000000)
6266 #define CAN_TSR_LOW2 ((uint32_t)0x80000000)
6268 /******************* Bit definition for CAN_RF0R register *******************/
6269 #define CAN_RF0R_FMP0 ((uint8_t)0x03)
6270 #define CAN_RF0R_FULL0 ((uint8_t)0x08)
6271 #define CAN_RF0R_FOVR0 ((uint8_t)0x10)
6272 #define CAN_RF0R_RFOM0 ((uint8_t)0x20)
6274 /******************* Bit definition for CAN_RF1R register *******************/
6275 #define CAN_RF1R_FMP1 ((uint8_t)0x03)
6276 #define CAN_RF1R_FULL1 ((uint8_t)0x08)
6277 #define CAN_RF1R_FOVR1 ((uint8_t)0x10)
6278 #define CAN_RF1R_RFOM1 ((uint8_t)0x20)
6280 /******************** Bit definition for CAN_IER register *******************/
6281 #define CAN_IER_TMEIE ((uint32_t)0x00000001)
6282 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002)
6283 #define CAN_IER_FFIE0 ((uint32_t)0x00000004)
6284 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008)
6285 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010)
6286 #define CAN_IER_FFIE1 ((uint32_t)0x00000020)
6287 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040)
6288 #define CAN_IER_EWGIE ((uint32_t)0x00000100)
6289 #define CAN_IER_EPVIE ((uint32_t)0x00000200)
6290 #define CAN_IER_BOFIE ((uint32_t)0x00000400)
6291 #define CAN_IER_LECIE ((uint32_t)0x00000800)
6292 #define CAN_IER_ERRIE ((uint32_t)0x00008000)
6293 #define CAN_IER_WKUIE ((uint32_t)0x00010000)
6294 #define CAN_IER_SLKIE ((uint32_t)0x00020000)
6296 /******************** Bit definition for CAN_ESR register *******************/
6297 #define CAN_ESR_EWGF ((uint32_t)0x00000001)
6298 #define CAN_ESR_EPVF ((uint32_t)0x00000002)
6299 #define CAN_ESR_BOFF ((uint32_t)0x00000004)
6301 #define CAN_ESR_LEC ((uint32_t)0x00000070)
6302 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010)
6303 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020)
6304 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040)
6306 #define CAN_ESR_TEC ((uint32_t)0x00FF0000)
6307 #define CAN_ESR_REC ((uint32_t)0xFF000000)
6309 /******************* Bit definition for CAN_BTR register ********************/
6310 #define CAN_BTR_BRP ((uint32_t)0x000003FF)
6311 #define CAN_BTR_TS1 ((uint32_t)0x000F0000)
6312 #define CAN_BTR_TS2 ((uint32_t)0x00700000)
6313 #define CAN_BTR_SJW ((uint32_t)0x03000000)
6314 #define CAN_BTR_LBKM ((uint32_t)0x40000000)
6315 #define CAN_BTR_SILM ((uint32_t)0x80000000)
6318 /****************** Bit definition for CAN_TI0R register ********************/
6319 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001)
6320 #define CAN_TI0R_RTR ((uint32_t)0x00000002)
6321 #define CAN_TI0R_IDE ((uint32_t)0x00000004)
6322 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8)
6323 #define CAN_TI0R_STID ((uint32_t)0xFFE00000)
6325 /****************** Bit definition for CAN_TDT0R register *******************/
6326 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F)
6327 #define CAN_TDT0R_TGT ((uint32_t)0x00000100)
6328 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000)
6330 /****************** Bit definition for CAN_TDL0R register *******************/
6331 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF)
6332 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00)
6333 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000)
6334 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000)
6336 /****************** Bit definition for CAN_TDH0R register *******************/
6337 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF)
6338 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00)
6339 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000)
6340 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000)
6342 /******************* Bit definition for CAN_TI1R register *******************/
6343 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001)
6344 #define CAN_TI1R_RTR ((uint32_t)0x00000002)
6345 #define CAN_TI1R_IDE ((uint32_t)0x00000004)
6346 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8)
6347 #define CAN_TI1R_STID ((uint32_t)0xFFE00000)
6349 /******************* Bit definition for CAN_TDT1R register ******************/
6350 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F)
6351 #define CAN_TDT1R_TGT ((uint32_t)0x00000100)
6352 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000)
6354 /******************* Bit definition for CAN_TDL1R register ******************/
6355 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF)
6356 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00)
6357 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000)
6358 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000)
6360 /******************* Bit definition for CAN_TDH1R register ******************/
6361 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF)
6362 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00)
6363 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000)
6364 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000)
6366 /******************* Bit definition for CAN_TI2R register *******************/
6367 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001)
6368 #define CAN_TI2R_RTR ((uint32_t)0x00000002)
6369 #define CAN_TI2R_IDE ((uint32_t)0x00000004)
6370 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8)
6371 #define CAN_TI2R_STID ((uint32_t)0xFFE00000)
6373 /******************* Bit definition for CAN_TDT2R register ******************/
6374 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F)
6375 #define CAN_TDT2R_TGT ((uint32_t)0x00000100)
6376 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000)
6378 /******************* Bit definition for CAN_TDL2R register ******************/
6379 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF)
6380 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00)
6381 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000)
6382 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000)
6384 /******************* Bit definition for CAN_TDH2R register ******************/
6385 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF)
6386 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00)
6387 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000)
6388 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000)
6390 /******************* Bit definition for CAN_RI0R register *******************/
6391 #define CAN_RI0R_RTR ((uint32_t)0x00000002)
6392 #define CAN_RI0R_IDE ((uint32_t)0x00000004)
6393 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8)
6394 #define CAN_RI0R_STID ((uint32_t)0xFFE00000)
6396 /******************* Bit definition for CAN_RDT0R register ******************/
6397 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F)
6398 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00)
6399 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000)
6401 /******************* Bit definition for CAN_RDL0R register ******************/
6402 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF)
6403 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00)
6404 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000)
6405 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000)
6407 /******************* Bit definition for CAN_RDH0R register ******************/
6408 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF)
6409 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00)
6410 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000)
6411 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000)
6413 /******************* Bit definition for CAN_RI1R register *******************/
6414 #define CAN_RI1R_RTR ((uint32_t)0x00000002)
6415 #define CAN_RI1R_IDE ((uint32_t)0x00000004)
6416 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8)
6417 #define CAN_RI1R_STID ((uint32_t)0xFFE00000)
6419 /******************* Bit definition for CAN_RDT1R register ******************/
6420 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F)
6421 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00)
6422 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000)
6424 /******************* Bit definition for CAN_RDL1R register ******************/
6425 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF)
6426 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00)
6427 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000)
6428 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000)
6430 /******************* Bit definition for CAN_RDH1R register ******************/
6431 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF)
6432 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00)
6433 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000)
6434 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000)
6437 /******************* Bit definition for CAN_FMR register ********************/
6438 #define CAN_FMR_FINIT ((uint8_t)0x01)
6440 /******************* Bit definition for CAN_FM1R register *******************/
6441 #define CAN_FM1R_FBM ((uint16_t)0x3FFF)
6442 #define CAN_FM1R_FBM0 ((uint16_t)0x0001)
6443 #define CAN_FM1R_FBM1 ((uint16_t)0x0002)
6444 #define CAN_FM1R_FBM2 ((uint16_t)0x0004)
6445 #define CAN_FM1R_FBM3 ((uint16_t)0x0008)
6446 #define CAN_FM1R_FBM4 ((uint16_t)0x0010)
6447 #define CAN_FM1R_FBM5 ((uint16_t)0x0020)
6448 #define CAN_FM1R_FBM6 ((uint16_t)0x0040)
6449 #define CAN_FM1R_FBM7 ((uint16_t)0x0080)
6450 #define CAN_FM1R_FBM8 ((uint16_t)0x0100)
6451 #define CAN_FM1R_FBM9 ((uint16_t)0x0200)
6452 #define CAN_FM1R_FBM10 ((uint16_t)0x0400)
6453 #define CAN_FM1R_FBM11 ((uint16_t)0x0800)
6454 #define CAN_FM1R_FBM12 ((uint16_t)0x1000)
6455 #define CAN_FM1R_FBM13 ((uint16_t)0x2000)
6457 /******************* Bit definition for CAN_FS1R register *******************/
6458 #define CAN_FS1R_FSC ((uint16_t)0x3FFF)
6459 #define CAN_FS1R_FSC0 ((uint16_t)0x0001)
6460 #define CAN_FS1R_FSC1 ((uint16_t)0x0002)
6461 #define CAN_FS1R_FSC2 ((uint16_t)0x0004)
6462 #define CAN_FS1R_FSC3 ((uint16_t)0x0008)
6463 #define CAN_FS1R_FSC4 ((uint16_t)0x0010)
6464 #define CAN_FS1R_FSC5 ((uint16_t)0x0020)
6465 #define CAN_FS1R_FSC6 ((uint16_t)0x0040)
6466 #define CAN_FS1R_FSC7 ((uint16_t)0x0080)
6467 #define CAN_FS1R_FSC8 ((uint16_t)0x0100)
6468 #define CAN_FS1R_FSC9 ((uint16_t)0x0200)
6469 #define CAN_FS1R_FSC10 ((uint16_t)0x0400)
6470 #define CAN_FS1R_FSC11 ((uint16_t)0x0800)
6471 #define CAN_FS1R_FSC12 ((uint16_t)0x1000)
6472 #define CAN_FS1R_FSC13 ((uint16_t)0x2000)
6474 /****************** Bit definition for CAN_FFA1R register *******************/
6475 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF)
6476 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001)
6477 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002)
6478 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004)
6479 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008)
6480 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010)
6481 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020)
6482 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040)
6483 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080)
6484 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100)
6485 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200)
6486 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400)
6487 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800)
6488 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000)
6489 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000)
6491 /******************* Bit definition for CAN_FA1R register *******************/
6492 #define CAN_FA1R_FACT ((uint16_t)0x3FFF)
6493 #define CAN_FA1R_FACT0 ((uint16_t)0x0001)
6494 #define CAN_FA1R_FACT1 ((uint16_t)0x0002)
6495 #define CAN_FA1R_FACT2 ((uint16_t)0x0004)
6496 #define CAN_FA1R_FACT3 ((uint16_t)0x0008)
6497 #define CAN_FA1R_FACT4 ((uint16_t)0x0010)
6498 #define CAN_FA1R_FACT5 ((uint16_t)0x0020)
6499 #define CAN_FA1R_FACT6 ((uint16_t)0x0040)
6500 #define CAN_FA1R_FACT7 ((uint16_t)0x0080)
6501 #define CAN_FA1R_FACT8 ((uint16_t)0x0100)
6502 #define CAN_FA1R_FACT9 ((uint16_t)0x0200)
6503 #define CAN_FA1R_FACT10 ((uint16_t)0x0400)
6504 #define CAN_FA1R_FACT11 ((uint16_t)0x0800)
6505 #define CAN_FA1R_FACT12 ((uint16_t)0x1000)
6506 #define CAN_FA1R_FACT13 ((uint16_t)0x2000)
6508 /******************* Bit definition for CAN_F0R1 register *******************/
6509 #define CAN_F0R1_FB0 ((uint32_t)0x00000001)
6510 #define CAN_F0R1_FB1 ((uint32_t)0x00000002)
6511 #define CAN_F0R1_FB2 ((uint32_t)0x00000004)
6512 #define CAN_F0R1_FB3 ((uint32_t)0x00000008)
6513 #define CAN_F0R1_FB4 ((uint32_t)0x00000010)
6514 #define CAN_F0R1_FB5 ((uint32_t)0x00000020)
6515 #define CAN_F0R1_FB6 ((uint32_t)0x00000040)
6516 #define CAN_F0R1_FB7 ((uint32_t)0x00000080)
6517 #define CAN_F0R1_FB8 ((uint32_t)0x00000100)
6518 #define CAN_F0R1_FB9 ((uint32_t)0x00000200)
6519 #define CAN_F0R1_FB10 ((uint32_t)0x00000400)
6520 #define CAN_F0R1_FB11 ((uint32_t)0x00000800)
6521 #define CAN_F0R1_FB12 ((uint32_t)0x00001000)
6522 #define CAN_F0R1_FB13 ((uint32_t)0x00002000)
6523 #define CAN_F0R1_FB14 ((uint32_t)0x00004000)
6524 #define CAN_F0R1_FB15 ((uint32_t)0x00008000)
6525 #define CAN_F0R1_FB16 ((uint32_t)0x00010000)
6526 #define CAN_F0R1_FB17 ((uint32_t)0x00020000)
6527 #define CAN_F0R1_FB18 ((uint32_t)0x00040000)
6528 #define CAN_F0R1_FB19 ((uint32_t)0x00080000)
6529 #define CAN_F0R1_FB20 ((uint32_t)0x00100000)
6530 #define CAN_F0R1_FB21 ((uint32_t)0x00200000)
6531 #define CAN_F0R1_FB22 ((uint32_t)0x00400000)
6532 #define CAN_F0R1_FB23 ((uint32_t)0x00800000)
6533 #define CAN_F0R1_FB24 ((uint32_t)0x01000000)
6534 #define CAN_F0R1_FB25 ((uint32_t)0x02000000)
6535 #define CAN_F0R1_FB26 ((uint32_t)0x04000000)
6536 #define CAN_F0R1_FB27 ((uint32_t)0x08000000)
6537 #define CAN_F0R1_FB28 ((uint32_t)0x10000000)
6538 #define CAN_F0R1_FB29 ((uint32_t)0x20000000)
6539 #define CAN_F0R1_FB30 ((uint32_t)0x40000000)
6540 #define CAN_F0R1_FB31 ((uint32_t)0x80000000)
6542 /******************* Bit definition for CAN_F1R1 register *******************/
6543 #define CAN_F1R1_FB0 ((uint32_t)0x00000001)
6544 #define CAN_F1R1_FB1 ((uint32_t)0x00000002)
6545 #define CAN_F1R1_FB2 ((uint32_t)0x00000004)
6546 #define CAN_F1R1_FB3 ((uint32_t)0x00000008)
6547 #define CAN_F1R1_FB4 ((uint32_t)0x00000010)
6548 #define CAN_F1R1_FB5 ((uint32_t)0x00000020)
6549 #define CAN_F1R1_FB6 ((uint32_t)0x00000040)
6550 #define CAN_F1R1_FB7 ((uint32_t)0x00000080)
6551 #define CAN_F1R1_FB8 ((uint32_t)0x00000100)
6552 #define CAN_F1R1_FB9 ((uint32_t)0x00000200)
6553 #define CAN_F1R1_FB10 ((uint32_t)0x00000400)
6554 #define CAN_F1R1_FB11 ((uint32_t)0x00000800)
6555 #define CAN_F1R1_FB12 ((uint32_t)0x00001000)
6556 #define CAN_F1R1_FB13 ((uint32_t)0x00002000)
6557 #define CAN_F1R1_FB14 ((uint32_t)0x00004000)
6558 #define CAN_F1R1_FB15 ((uint32_t)0x00008000)
6559 #define CAN_F1R1_FB16 ((uint32_t)0x00010000)
6560 #define CAN_F1R1_FB17 ((uint32_t)0x00020000)
6561 #define CAN_F1R1_FB18 ((uint32_t)0x00040000)
6562 #define CAN_F1R1_FB19 ((uint32_t)0x00080000)
6563 #define CAN_F1R1_FB20 ((uint32_t)0x00100000)
6564 #define CAN_F1R1_FB21 ((uint32_t)0x00200000)
6565 #define CAN_F1R1_FB22 ((uint32_t)0x00400000)
6566 #define CAN_F1R1_FB23 ((uint32_t)0x00800000)
6567 #define CAN_F1R1_FB24 ((uint32_t)0x01000000)
6568 #define CAN_F1R1_FB25 ((uint32_t)0x02000000)
6569 #define CAN_F1R1_FB26 ((uint32_t)0x04000000)
6570 #define CAN_F1R1_FB27 ((uint32_t)0x08000000)
6571 #define CAN_F1R1_FB28 ((uint32_t)0x10000000)
6572 #define CAN_F1R1_FB29 ((uint32_t)0x20000000)
6573 #define CAN_F1R1_FB30 ((uint32_t)0x40000000)
6574 #define CAN_F1R1_FB31 ((uint32_t)0x80000000)
6576 /******************* Bit definition for CAN_F2R1 register *******************/
6577 #define CAN_F2R1_FB0 ((uint32_t)0x00000001)
6578 #define CAN_F2R1_FB1 ((uint32_t)0x00000002)
6579 #define CAN_F2R1_FB2 ((uint32_t)0x00000004)
6580 #define CAN_F2R1_FB3 ((uint32_t)0x00000008)
6581 #define CAN_F2R1_FB4 ((uint32_t)0x00000010)
6582 #define CAN_F2R1_FB5 ((uint32_t)0x00000020)
6583 #define CAN_F2R1_FB6 ((uint32_t)0x00000040)
6584 #define CAN_F2R1_FB7 ((uint32_t)0x00000080)
6585 #define CAN_F2R1_FB8 ((uint32_t)0x00000100)
6586 #define CAN_F2R1_FB9 ((uint32_t)0x00000200)
6587 #define CAN_F2R1_FB10 ((uint32_t)0x00000400)
6588 #define CAN_F2R1_FB11 ((uint32_t)0x00000800)
6589 #define CAN_F2R1_FB12 ((uint32_t)0x00001000)
6590 #define CAN_F2R1_FB13 ((uint32_t)0x00002000)
6591 #define CAN_F2R1_FB14 ((uint32_t)0x00004000)
6592 #define CAN_F2R1_FB15 ((uint32_t)0x00008000)
6593 #define CAN_F2R1_FB16 ((uint32_t)0x00010000)
6594 #define CAN_F2R1_FB17 ((uint32_t)0x00020000)
6595 #define CAN_F2R1_FB18 ((uint32_t)0x00040000)
6596 #define CAN_F2R1_FB19 ((uint32_t)0x00080000)
6597 #define CAN_F2R1_FB20 ((uint32_t)0x00100000)
6598 #define CAN_F2R1_FB21 ((uint32_t)0x00200000)
6599 #define CAN_F2R1_FB22 ((uint32_t)0x00400000)
6600 #define CAN_F2R1_FB23 ((uint32_t)0x00800000)
6601 #define CAN_F2R1_FB24 ((uint32_t)0x01000000)
6602 #define CAN_F2R1_FB25 ((uint32_t)0x02000000)
6603 #define CAN_F2R1_FB26 ((uint32_t)0x04000000)
6604 #define CAN_F2R1_FB27 ((uint32_t)0x08000000)
6605 #define CAN_F2R1_FB28 ((uint32_t)0x10000000)
6606 #define CAN_F2R1_FB29 ((uint32_t)0x20000000)
6607 #define CAN_F2R1_FB30 ((uint32_t)0x40000000)
6608 #define CAN_F2R1_FB31 ((uint32_t)0x80000000)
6610 /******************* Bit definition for CAN_F3R1 register *******************/
6611 #define CAN_F3R1_FB0 ((uint32_t)0x00000001)
6612 #define CAN_F3R1_FB1 ((uint32_t)0x00000002)
6613 #define CAN_F3R1_FB2 ((uint32_t)0x00000004)
6614 #define CAN_F3R1_FB3 ((uint32_t)0x00000008)
6615 #define CAN_F3R1_FB4 ((uint32_t)0x00000010)
6616 #define CAN_F3R1_FB5 ((uint32_t)0x00000020)
6617 #define CAN_F3R1_FB6 ((uint32_t)0x00000040)
6618 #define CAN_F3R1_FB7 ((uint32_t)0x00000080)
6619 #define CAN_F3R1_FB8 ((uint32_t)0x00000100)
6620 #define CAN_F3R1_FB9 ((uint32_t)0x00000200)
6621 #define CAN_F3R1_FB10 ((uint32_t)0x00000400)
6622 #define CAN_F3R1_FB11 ((uint32_t)0x00000800)
6623 #define CAN_F3R1_FB12 ((uint32_t)0x00001000)
6624 #define CAN_F3R1_FB13 ((uint32_t)0x00002000)
6625 #define CAN_F3R1_FB14 ((uint32_t)0x00004000)
6626 #define CAN_F3R1_FB15 ((uint32_t)0x00008000)
6627 #define CAN_F3R1_FB16 ((uint32_t)0x00010000)
6628 #define CAN_F3R1_FB17 ((uint32_t)0x00020000)
6629 #define CAN_F3R1_FB18 ((uint32_t)0x00040000)
6630 #define CAN_F3R1_FB19 ((uint32_t)0x00080000)
6631 #define CAN_F3R1_FB20 ((uint32_t)0x00100000)
6632 #define CAN_F3R1_FB21 ((uint32_t)0x00200000)
6633 #define CAN_F3R1_FB22 ((uint32_t)0x00400000)
6634 #define CAN_F3R1_FB23 ((uint32_t)0x00800000)
6635 #define CAN_F3R1_FB24 ((uint32_t)0x01000000)
6636 #define CAN_F3R1_FB25 ((uint32_t)0x02000000)
6637 #define CAN_F3R1_FB26 ((uint32_t)0x04000000)
6638 #define CAN_F3R1_FB27 ((uint32_t)0x08000000)
6639 #define CAN_F3R1_FB28 ((uint32_t)0x10000000)
6640 #define CAN_F3R1_FB29 ((uint32_t)0x20000000)
6641 #define CAN_F3R1_FB30 ((uint32_t)0x40000000)
6642 #define CAN_F3R1_FB31 ((uint32_t)0x80000000)
6644 /******************* Bit definition for CAN_F4R1 register *******************/
6645 #define CAN_F4R1_FB0 ((uint32_t)0x00000001)
6646 #define CAN_F4R1_FB1 ((uint32_t)0x00000002)
6647 #define CAN_F4R1_FB2 ((uint32_t)0x00000004)
6648 #define CAN_F4R1_FB3 ((uint32_t)0x00000008)
6649 #define CAN_F4R1_FB4 ((uint32_t)0x00000010)
6650 #define CAN_F4R1_FB5 ((uint32_t)0x00000020)
6651 #define CAN_F4R1_FB6 ((uint32_t)0x00000040)
6652 #define CAN_F4R1_FB7 ((uint32_t)0x00000080)
6653 #define CAN_F4R1_FB8 ((uint32_t)0x00000100)
6654 #define CAN_F4R1_FB9 ((uint32_t)0x00000200)
6655 #define CAN_F4R1_FB10 ((uint32_t)0x00000400)
6656 #define CAN_F4R1_FB11 ((uint32_t)0x00000800)
6657 #define CAN_F4R1_FB12 ((uint32_t)0x00001000)
6658 #define CAN_F4R1_FB13 ((uint32_t)0x00002000)
6659 #define CAN_F4R1_FB14 ((uint32_t)0x00004000)
6660 #define CAN_F4R1_FB15 ((uint32_t)0x00008000)
6661 #define CAN_F4R1_FB16 ((uint32_t)0x00010000)
6662 #define CAN_F4R1_FB17 ((uint32_t)0x00020000)
6663 #define CAN_F4R1_FB18 ((uint32_t)0x00040000)
6664 #define CAN_F4R1_FB19 ((uint32_t)0x00080000)
6665 #define CAN_F4R1_FB20 ((uint32_t)0x00100000)
6666 #define CAN_F4R1_FB21 ((uint32_t)0x00200000)
6667 #define CAN_F4R1_FB22 ((uint32_t)0x00400000)
6668 #define CAN_F4R1_FB23 ((uint32_t)0x00800000)
6669 #define CAN_F4R1_FB24 ((uint32_t)0x01000000)
6670 #define CAN_F4R1_FB25 ((uint32_t)0x02000000)
6671 #define CAN_F4R1_FB26 ((uint32_t)0x04000000)
6672 #define CAN_F4R1_FB27 ((uint32_t)0x08000000)
6673 #define CAN_F4R1_FB28 ((uint32_t)0x10000000)
6674 #define CAN_F4R1_FB29 ((uint32_t)0x20000000)
6675 #define CAN_F4R1_FB30 ((uint32_t)0x40000000)
6676 #define CAN_F4R1_FB31 ((uint32_t)0x80000000)
6678 /******************* Bit definition for CAN_F5R1 register *******************/
6679 #define CAN_F5R1_FB0 ((uint32_t)0x00000001)
6680 #define CAN_F5R1_FB1 ((uint32_t)0x00000002)
6681 #define CAN_F5R1_FB2 ((uint32_t)0x00000004)
6682 #define CAN_F5R1_FB3 ((uint32_t)0x00000008)
6683 #define CAN_F5R1_FB4 ((uint32_t)0x00000010)
6684 #define CAN_F5R1_FB5 ((uint32_t)0x00000020)
6685 #define CAN_F5R1_FB6 ((uint32_t)0x00000040)
6686 #define CAN_F5R1_FB7 ((uint32_t)0x00000080)
6687 #define CAN_F5R1_FB8 ((uint32_t)0x00000100)
6688 #define CAN_F5R1_FB9 ((uint32_t)0x00000200)
6689 #define CAN_F5R1_FB10 ((uint32_t)0x00000400)
6690 #define CAN_F5R1_FB11 ((uint32_t)0x00000800)
6691 #define CAN_F5R1_FB12 ((uint32_t)0x00001000)
6692 #define CAN_F5R1_FB13 ((uint32_t)0x00002000)
6693 #define CAN_F5R1_FB14 ((uint32_t)0x00004000)
6694 #define CAN_F5R1_FB15 ((uint32_t)0x00008000)
6695 #define CAN_F5R1_FB16 ((uint32_t)0x00010000)
6696 #define CAN_F5R1_FB17 ((uint32_t)0x00020000)
6697 #define CAN_F5R1_FB18 ((uint32_t)0x00040000)
6698 #define CAN_F5R1_FB19 ((uint32_t)0x00080000)
6699 #define CAN_F5R1_FB20 ((uint32_t)0x00100000)
6700 #define CAN_F5R1_FB21 ((uint32_t)0x00200000)
6701 #define CAN_F5R1_FB22 ((uint32_t)0x00400000)
6702 #define CAN_F5R1_FB23 ((uint32_t)0x00800000)
6703 #define CAN_F5R1_FB24 ((uint32_t)0x01000000)
6704 #define CAN_F5R1_FB25 ((uint32_t)0x02000000)
6705 #define CAN_F5R1_FB26 ((uint32_t)0x04000000)
6706 #define CAN_F5R1_FB27 ((uint32_t)0x08000000)
6707 #define CAN_F5R1_FB28 ((uint32_t)0x10000000)
6708 #define CAN_F5R1_FB29 ((uint32_t)0x20000000)
6709 #define CAN_F5R1_FB30 ((uint32_t)0x40000000)
6710 #define CAN_F5R1_FB31 ((uint32_t)0x80000000)
6712 /******************* Bit definition for CAN_F6R1 register *******************/
6713 #define CAN_F6R1_FB0 ((uint32_t)0x00000001)
6714 #define CAN_F6R1_FB1 ((uint32_t)0x00000002)
6715 #define CAN_F6R1_FB2 ((uint32_t)0x00000004)
6716 #define CAN_F6R1_FB3 ((uint32_t)0x00000008)
6717 #define CAN_F6R1_FB4 ((uint32_t)0x00000010)
6718 #define CAN_F6R1_FB5 ((uint32_t)0x00000020)
6719 #define CAN_F6R1_FB6 ((uint32_t)0x00000040)
6720 #define CAN_F6R1_FB7 ((uint32_t)0x00000080)
6721 #define CAN_F6R1_FB8 ((uint32_t)0x00000100)
6722 #define CAN_F6R1_FB9 ((uint32_t)0x00000200)
6723 #define CAN_F6R1_FB10 ((uint32_t)0x00000400)
6724 #define CAN_F6R1_FB11 ((uint32_t)0x00000800)
6725 #define CAN_F6R1_FB12 ((uint32_t)0x00001000)
6726 #define CAN_F6R1_FB13 ((uint32_t)0x00002000)
6727 #define CAN_F6R1_FB14 ((uint32_t)0x00004000)
6728 #define CAN_F6R1_FB15 ((uint32_t)0x00008000)
6729 #define CAN_F6R1_FB16 ((uint32_t)0x00010000)
6730 #define CAN_F6R1_FB17 ((uint32_t)0x00020000)
6731 #define CAN_F6R1_FB18 ((uint32_t)0x00040000)
6732 #define CAN_F6R1_FB19 ((uint32_t)0x00080000)
6733 #define CAN_F6R1_FB20 ((uint32_t)0x00100000)
6734 #define CAN_F6R1_FB21 ((uint32_t)0x00200000)
6735 #define CAN_F6R1_FB22 ((uint32_t)0x00400000)
6736 #define CAN_F6R1_FB23 ((uint32_t)0x00800000)
6737 #define CAN_F6R1_FB24 ((uint32_t)0x01000000)
6738 #define CAN_F6R1_FB25 ((uint32_t)0x02000000)
6739 #define CAN_F6R1_FB26 ((uint32_t)0x04000000)
6740 #define CAN_F6R1_FB27 ((uint32_t)0x08000000)
6741 #define CAN_F6R1_FB28 ((uint32_t)0x10000000)
6742 #define CAN_F6R1_FB29 ((uint32_t)0x20000000)
6743 #define CAN_F6R1_FB30 ((uint32_t)0x40000000)
6744 #define CAN_F6R1_FB31 ((uint32_t)0x80000000)
6746 /******************* Bit definition for CAN_F7R1 register *******************/
6747 #define CAN_F7R1_FB0 ((uint32_t)0x00000001)
6748 #define CAN_F7R1_FB1 ((uint32_t)0x00000002)
6749 #define CAN_F7R1_FB2 ((uint32_t)0x00000004)
6750 #define CAN_F7R1_FB3 ((uint32_t)0x00000008)
6751 #define CAN_F7R1_FB4 ((uint32_t)0x00000010)
6752 #define CAN_F7R1_FB5 ((uint32_t)0x00000020)
6753 #define CAN_F7R1_FB6 ((uint32_t)0x00000040)
6754 #define CAN_F7R1_FB7 ((uint32_t)0x00000080)
6755 #define CAN_F7R1_FB8 ((uint32_t)0x00000100)
6756 #define CAN_F7R1_FB9 ((uint32_t)0x00000200)
6757 #define CAN_F7R1_FB10 ((uint32_t)0x00000400)
6758 #define CAN_F7R1_FB11 ((uint32_t)0x00000800)
6759 #define CAN_F7R1_FB12 ((uint32_t)0x00001000)
6760 #define CAN_F7R1_FB13 ((uint32_t)0x00002000)
6761 #define CAN_F7R1_FB14 ((uint32_t)0x00004000)
6762 #define CAN_F7R1_FB15 ((uint32_t)0x00008000)
6763 #define CAN_F7R1_FB16 ((uint32_t)0x00010000)
6764 #define CAN_F7R1_FB17 ((uint32_t)0x00020000)
6765 #define CAN_F7R1_FB18 ((uint32_t)0x00040000)
6766 #define CAN_F7R1_FB19 ((uint32_t)0x00080000)
6767 #define CAN_F7R1_FB20 ((uint32_t)0x00100000)
6768 #define CAN_F7R1_FB21 ((uint32_t)0x00200000)
6769 #define CAN_F7R1_FB22 ((uint32_t)0x00400000)
6770 #define CAN_F7R1_FB23 ((uint32_t)0x00800000)
6771 #define CAN_F7R1_FB24 ((uint32_t)0x01000000)
6772 #define CAN_F7R1_FB25 ((uint32_t)0x02000000)
6773 #define CAN_F7R1_FB26 ((uint32_t)0x04000000)
6774 #define CAN_F7R1_FB27 ((uint32_t)0x08000000)
6775 #define CAN_F7R1_FB28 ((uint32_t)0x10000000)
6776 #define CAN_F7R1_FB29 ((uint32_t)0x20000000)
6777 #define CAN_F7R1_FB30 ((uint32_t)0x40000000)
6778 #define CAN_F7R1_FB31 ((uint32_t)0x80000000)
6780 /******************* Bit definition for CAN_F8R1 register *******************/
6781 #define CAN_F8R1_FB0 ((uint32_t)0x00000001)
6782 #define CAN_F8R1_FB1 ((uint32_t)0x00000002)
6783 #define CAN_F8R1_FB2 ((uint32_t)0x00000004)
6784 #define CAN_F8R1_FB3 ((uint32_t)0x00000008)
6785 #define CAN_F8R1_FB4 ((uint32_t)0x00000010)
6786 #define CAN_F8R1_FB5 ((uint32_t)0x00000020)
6787 #define CAN_F8R1_FB6 ((uint32_t)0x00000040)
6788 #define CAN_F8R1_FB7 ((uint32_t)0x00000080)
6789 #define CAN_F8R1_FB8 ((uint32_t)0x00000100)
6790 #define CAN_F8R1_FB9 ((uint32_t)0x00000200)
6791 #define CAN_F8R1_FB10 ((uint32_t)0x00000400)
6792 #define CAN_F8R1_FB11 ((uint32_t)0x00000800)
6793 #define CAN_F8R1_FB12 ((uint32_t)0x00001000)
6794 #define CAN_F8R1_FB13 ((uint32_t)0x00002000)
6795 #define CAN_F8R1_FB14 ((uint32_t)0x00004000)
6796 #define CAN_F8R1_FB15 ((uint32_t)0x00008000)
6797 #define CAN_F8R1_FB16 ((uint32_t)0x00010000)
6798 #define CAN_F8R1_FB17 ((uint32_t)0x00020000)
6799 #define CAN_F8R1_FB18 ((uint32_t)0x00040000)
6800 #define CAN_F8R1_FB19 ((uint32_t)0x00080000)
6801 #define CAN_F8R1_FB20 ((uint32_t)0x00100000)
6802 #define CAN_F8R1_FB21 ((uint32_t)0x00200000)
6803 #define CAN_F8R1_FB22 ((uint32_t)0x00400000)
6804 #define CAN_F8R1_FB23 ((uint32_t)0x00800000)
6805 #define CAN_F8R1_FB24 ((uint32_t)0x01000000)
6806 #define CAN_F8R1_FB25 ((uint32_t)0x02000000)
6807 #define CAN_F8R1_FB26 ((uint32_t)0x04000000)
6808 #define CAN_F8R1_FB27 ((uint32_t)0x08000000)
6809 #define CAN_F8R1_FB28 ((uint32_t)0x10000000)
6810 #define CAN_F8R1_FB29 ((uint32_t)0x20000000)
6811 #define CAN_F8R1_FB30 ((uint32_t)0x40000000)
6812 #define CAN_F8R1_FB31 ((uint32_t)0x80000000)
6814 /******************* Bit definition for CAN_F9R1 register *******************/
6815 #define CAN_F9R1_FB0 ((uint32_t)0x00000001)
6816 #define CAN_F9R1_FB1 ((uint32_t)0x00000002)
6817 #define CAN_F9R1_FB2 ((uint32_t)0x00000004)
6818 #define CAN_F9R1_FB3 ((uint32_t)0x00000008)
6819 #define CAN_F9R1_FB4 ((uint32_t)0x00000010)
6820 #define CAN_F9R1_FB5 ((uint32_t)0x00000020)
6821 #define CAN_F9R1_FB6 ((uint32_t)0x00000040)
6822 #define CAN_F9R1_FB7 ((uint32_t)0x00000080)
6823 #define CAN_F9R1_FB8 ((uint32_t)0x00000100)
6824 #define CAN_F9R1_FB9 ((uint32_t)0x00000200)
6825 #define CAN_F9R1_FB10 ((uint32_t)0x00000400)
6826 #define CAN_F9R1_FB11 ((uint32_t)0x00000800)
6827 #define CAN_F9R1_FB12 ((uint32_t)0x00001000)
6828 #define CAN_F9R1_FB13 ((uint32_t)0x00002000)
6829 #define CAN_F9R1_FB14 ((uint32_t)0x00004000)
6830 #define CAN_F9R1_FB15 ((uint32_t)0x00008000)
6831 #define CAN_F9R1_FB16 ((uint32_t)0x00010000)
6832 #define CAN_F9R1_FB17 ((uint32_t)0x00020000)
6833 #define CAN_F9R1_FB18 ((uint32_t)0x00040000)
6834 #define CAN_F9R1_FB19 ((uint32_t)0x00080000)
6835 #define CAN_F9R1_FB20 ((uint32_t)0x00100000)
6836 #define CAN_F9R1_FB21 ((uint32_t)0x00200000)
6837 #define CAN_F9R1_FB22 ((uint32_t)0x00400000)
6838 #define CAN_F9R1_FB23 ((uint32_t)0x00800000)
6839 #define CAN_F9R1_FB24 ((uint32_t)0x01000000)
6840 #define CAN_F9R1_FB25 ((uint32_t)0x02000000)
6841 #define CAN_F9R1_FB26 ((uint32_t)0x04000000)
6842 #define CAN_F9R1_FB27 ((uint32_t)0x08000000)
6843 #define CAN_F9R1_FB28 ((uint32_t)0x10000000)
6844 #define CAN_F9R1_FB29 ((uint32_t)0x20000000)
6845 #define CAN_F9R1_FB30 ((uint32_t)0x40000000)
6846 #define CAN_F9R1_FB31 ((uint32_t)0x80000000)
6848 /******************* Bit definition for CAN_F10R1 register ******************/
6849 #define CAN_F10R1_FB0 ((uint32_t)0x00000001)
6850 #define CAN_F10R1_FB1 ((uint32_t)0x00000002)
6851 #define CAN_F10R1_FB2 ((uint32_t)0x00000004)
6852 #define CAN_F10R1_FB3 ((uint32_t)0x00000008)
6853 #define CAN_F10R1_FB4 ((uint32_t)0x00000010)
6854 #define CAN_F10R1_FB5 ((uint32_t)0x00000020)
6855 #define CAN_F10R1_FB6 ((uint32_t)0x00000040)
6856 #define CAN_F10R1_FB7 ((uint32_t)0x00000080)
6857 #define CAN_F10R1_FB8 ((uint32_t)0x00000100)
6858 #define CAN_F10R1_FB9 ((uint32_t)0x00000200)
6859 #define CAN_F10R1_FB10 ((uint32_t)0x00000400)
6860 #define CAN_F10R1_FB11 ((uint32_t)0x00000800)
6861 #define CAN_F10R1_FB12 ((uint32_t)0x00001000)
6862 #define CAN_F10R1_FB13 ((uint32_t)0x00002000)
6863 #define CAN_F10R1_FB14 ((uint32_t)0x00004000)
6864 #define CAN_F10R1_FB15 ((uint32_t)0x00008000)
6865 #define CAN_F10R1_FB16 ((uint32_t)0x00010000)
6866 #define CAN_F10R1_FB17 ((uint32_t)0x00020000)
6867 #define CAN_F10R1_FB18 ((uint32_t)0x00040000)
6868 #define CAN_F10R1_FB19 ((uint32_t)0x00080000)
6869 #define CAN_F10R1_FB20 ((uint32_t)0x00100000)
6870 #define CAN_F10R1_FB21 ((uint32_t)0x00200000)
6871 #define CAN_F10R1_FB22 ((uint32_t)0x00400000)
6872 #define CAN_F10R1_FB23 ((uint32_t)0x00800000)
6873 #define CAN_F10R1_FB24 ((uint32_t)0x01000000)
6874 #define CAN_F10R1_FB25 ((uint32_t)0x02000000)
6875 #define CAN_F10R1_FB26 ((uint32_t)0x04000000)
6876 #define CAN_F10R1_FB27 ((uint32_t)0x08000000)
6877 #define CAN_F10R1_FB28 ((uint32_t)0x10000000)
6878 #define CAN_F10R1_FB29 ((uint32_t)0x20000000)
6879 #define CAN_F10R1_FB30 ((uint32_t)0x40000000)
6880 #define CAN_F10R1_FB31 ((uint32_t)0x80000000)
6882 /******************* Bit definition for CAN_F11R1 register ******************/
6883 #define CAN_F11R1_FB0 ((uint32_t)0x00000001)
6884 #define CAN_F11R1_FB1 ((uint32_t)0x00000002)
6885 #define CAN_F11R1_FB2 ((uint32_t)0x00000004)
6886 #define CAN_F11R1_FB3 ((uint32_t)0x00000008)
6887 #define CAN_F11R1_FB4 ((uint32_t)0x00000010)
6888 #define CAN_F11R1_FB5 ((uint32_t)0x00000020)
6889 #define CAN_F11R1_FB6 ((uint32_t)0x00000040)
6890 #define CAN_F11R1_FB7 ((uint32_t)0x00000080)
6891 #define CAN_F11R1_FB8 ((uint32_t)0x00000100)
6892 #define CAN_F11R1_FB9 ((uint32_t)0x00000200)
6893 #define CAN_F11R1_FB10 ((uint32_t)0x00000400)
6894 #define CAN_F11R1_FB11 ((uint32_t)0x00000800)
6895 #define CAN_F11R1_FB12 ((uint32_t)0x00001000)
6896 #define CAN_F11R1_FB13 ((uint32_t)0x00002000)
6897 #define CAN_F11R1_FB14 ((uint32_t)0x00004000)
6898 #define CAN_F11R1_FB15 ((uint32_t)0x00008000)
6899 #define CAN_F11R1_FB16 ((uint32_t)0x00010000)
6900 #define CAN_F11R1_FB17 ((uint32_t)0x00020000)
6901 #define CAN_F11R1_FB18 ((uint32_t)0x00040000)
6902 #define CAN_F11R1_FB19 ((uint32_t)0x00080000)
6903 #define CAN_F11R1_FB20 ((uint32_t)0x00100000)
6904 #define CAN_F11R1_FB21 ((uint32_t)0x00200000)
6905 #define CAN_F11R1_FB22 ((uint32_t)0x00400000)
6906 #define CAN_F11R1_FB23 ((uint32_t)0x00800000)
6907 #define CAN_F11R1_FB24 ((uint32_t)0x01000000)
6908 #define CAN_F11R1_FB25 ((uint32_t)0x02000000)
6909 #define CAN_F11R1_FB26 ((uint32_t)0x04000000)
6910 #define CAN_F11R1_FB27 ((uint32_t)0x08000000)
6911 #define CAN_F11R1_FB28 ((uint32_t)0x10000000)
6912 #define CAN_F11R1_FB29 ((uint32_t)0x20000000)
6913 #define CAN_F11R1_FB30 ((uint32_t)0x40000000)
6914 #define CAN_F11R1_FB31 ((uint32_t)0x80000000)
6916 /******************* Bit definition for CAN_F12R1 register ******************/
6917 #define CAN_F12R1_FB0 ((uint32_t)0x00000001)
6918 #define CAN_F12R1_FB1 ((uint32_t)0x00000002)
6919 #define CAN_F12R1_FB2 ((uint32_t)0x00000004)
6920 #define CAN_F12R1_FB3 ((uint32_t)0x00000008)
6921 #define CAN_F12R1_FB4 ((uint32_t)0x00000010)
6922 #define CAN_F12R1_FB5 ((uint32_t)0x00000020)
6923 #define CAN_F12R1_FB6 ((uint32_t)0x00000040)
6924 #define CAN_F12R1_FB7 ((uint32_t)0x00000080)
6925 #define CAN_F12R1_FB8 ((uint32_t)0x00000100)
6926 #define CAN_F12R1_FB9 ((uint32_t)0x00000200)
6927 #define CAN_F12R1_FB10 ((uint32_t)0x00000400)
6928 #define CAN_F12R1_FB11 ((uint32_t)0x00000800)
6929 #define CAN_F12R1_FB12 ((uint32_t)0x00001000)
6930 #define CAN_F12R1_FB13 ((uint32_t)0x00002000)
6931 #define CAN_F12R1_FB14 ((uint32_t)0x00004000)
6932 #define CAN_F12R1_FB15 ((uint32_t)0x00008000)
6933 #define CAN_F12R1_FB16 ((uint32_t)0x00010000)
6934 #define CAN_F12R1_FB17 ((uint32_t)0x00020000)
6935 #define CAN_F12R1_FB18 ((uint32_t)0x00040000)
6936 #define CAN_F12R1_FB19 ((uint32_t)0x00080000)
6937 #define CAN_F12R1_FB20 ((uint32_t)0x00100000)
6938 #define CAN_F12R1_FB21 ((uint32_t)0x00200000)
6939 #define CAN_F12R1_FB22 ((uint32_t)0x00400000)
6940 #define CAN_F12R1_FB23 ((uint32_t)0x00800000)
6941 #define CAN_F12R1_FB24 ((uint32_t)0x01000000)
6942 #define CAN_F12R1_FB25 ((uint32_t)0x02000000)
6943 #define CAN_F12R1_FB26 ((uint32_t)0x04000000)
6944 #define CAN_F12R1_FB27 ((uint32_t)0x08000000)
6945 #define CAN_F12R1_FB28 ((uint32_t)0x10000000)
6946 #define CAN_F12R1_FB29 ((uint32_t)0x20000000)
6947 #define CAN_F12R1_FB30 ((uint32_t)0x40000000)
6948 #define CAN_F12R1_FB31 ((uint32_t)0x80000000)
6950 /******************* Bit definition for CAN_F13R1 register ******************/
6951 #define CAN_F13R1_FB0 ((uint32_t)0x00000001)
6952 #define CAN_F13R1_FB1 ((uint32_t)0x00000002)
6953 #define CAN_F13R1_FB2 ((uint32_t)0x00000004)
6954 #define CAN_F13R1_FB3 ((uint32_t)0x00000008)
6955 #define CAN_F13R1_FB4 ((uint32_t)0x00000010)
6956 #define CAN_F13R1_FB5 ((uint32_t)0x00000020)
6957 #define CAN_F13R1_FB6 ((uint32_t)0x00000040)
6958 #define CAN_F13R1_FB7 ((uint32_t)0x00000080)
6959 #define CAN_F13R1_FB8 ((uint32_t)0x00000100)
6960 #define CAN_F13R1_FB9 ((uint32_t)0x00000200)
6961 #define CAN_F13R1_FB10 ((uint32_t)0x00000400)
6962 #define CAN_F13R1_FB11 ((uint32_t)0x00000800)
6963 #define CAN_F13R1_FB12 ((uint32_t)0x00001000)
6964 #define CAN_F13R1_FB13 ((uint32_t)0x00002000)
6965 #define CAN_F13R1_FB14 ((uint32_t)0x00004000)
6966 #define CAN_F13R1_FB15 ((uint32_t)0x00008000)
6967 #define CAN_F13R1_FB16 ((uint32_t)0x00010000)
6968 #define CAN_F13R1_FB17 ((uint32_t)0x00020000)
6969 #define CAN_F13R1_FB18 ((uint32_t)0x00040000)
6970 #define CAN_F13R1_FB19 ((uint32_t)0x00080000)
6971 #define CAN_F13R1_FB20 ((uint32_t)0x00100000)
6972 #define CAN_F13R1_FB21 ((uint32_t)0x00200000)
6973 #define CAN_F13R1_FB22 ((uint32_t)0x00400000)
6974 #define CAN_F13R1_FB23 ((uint32_t)0x00800000)
6975 #define CAN_F13R1_FB24 ((uint32_t)0x01000000)
6976 #define CAN_F13R1_FB25 ((uint32_t)0x02000000)
6977 #define CAN_F13R1_FB26 ((uint32_t)0x04000000)
6978 #define CAN_F13R1_FB27 ((uint32_t)0x08000000)
6979 #define CAN_F13R1_FB28 ((uint32_t)0x10000000)
6980 #define CAN_F13R1_FB29 ((uint32_t)0x20000000)
6981 #define CAN_F13R1_FB30 ((uint32_t)0x40000000)
6982 #define CAN_F13R1_FB31 ((uint32_t)0x80000000)
6984 /******************* Bit definition for CAN_F0R2 register *******************/
6985 #define CAN_F0R2_FB0 ((uint32_t)0x00000001)
6986 #define CAN_F0R2_FB1 ((uint32_t)0x00000002)
6987 #define CAN_F0R2_FB2 ((uint32_t)0x00000004)
6988 #define CAN_F0R2_FB3 ((uint32_t)0x00000008)
6989 #define CAN_F0R2_FB4 ((uint32_t)0x00000010)
6990 #define CAN_F0R2_FB5 ((uint32_t)0x00000020)
6991 #define CAN_F0R2_FB6 ((uint32_t)0x00000040)
6992 #define CAN_F0R2_FB7 ((uint32_t)0x00000080)
6993 #define CAN_F0R2_FB8 ((uint32_t)0x00000100)
6994 #define CAN_F0R2_FB9 ((uint32_t)0x00000200)
6995 #define CAN_F0R2_FB10 ((uint32_t)0x00000400)
6996 #define CAN_F0R2_FB11 ((uint32_t)0x00000800)
6997 #define CAN_F0R2_FB12 ((uint32_t)0x00001000)
6998 #define CAN_F0R2_FB13 ((uint32_t)0x00002000)
6999 #define CAN_F0R2_FB14 ((uint32_t)0x00004000)
7000 #define CAN_F0R2_FB15 ((uint32_t)0x00008000)
7001 #define CAN_F0R2_FB16 ((uint32_t)0x00010000)
7002 #define CAN_F0R2_FB17 ((uint32_t)0x00020000)
7003 #define CAN_F0R2_FB18 ((uint32_t)0x00040000)
7004 #define CAN_F0R2_FB19 ((uint32_t)0x00080000)
7005 #define CAN_F0R2_FB20 ((uint32_t)0x00100000)
7006 #define CAN_F0R2_FB21 ((uint32_t)0x00200000)
7007 #define CAN_F0R2_FB22 ((uint32_t)0x00400000)
7008 #define CAN_F0R2_FB23 ((uint32_t)0x00800000)
7009 #define CAN_F0R2_FB24 ((uint32_t)0x01000000)
7010 #define CAN_F0R2_FB25 ((uint32_t)0x02000000)
7011 #define CAN_F0R2_FB26 ((uint32_t)0x04000000)
7012 #define CAN_F0R2_FB27 ((uint32_t)0x08000000)
7013 #define CAN_F0R2_FB28 ((uint32_t)0x10000000)
7014 #define CAN_F0R2_FB29 ((uint32_t)0x20000000)
7015 #define CAN_F0R2_FB30 ((uint32_t)0x40000000)
7016 #define CAN_F0R2_FB31 ((uint32_t)0x80000000)
7018 /******************* Bit definition for CAN_F1R2 register *******************/
7019 #define CAN_F1R2_FB0 ((uint32_t)0x00000001)
7020 #define CAN_F1R2_FB1 ((uint32_t)0x00000002)
7021 #define CAN_F1R2_FB2 ((uint32_t)0x00000004)
7022 #define CAN_F1R2_FB3 ((uint32_t)0x00000008)
7023 #define CAN_F1R2_FB4 ((uint32_t)0x00000010)
7024 #define CAN_F1R2_FB5 ((uint32_t)0x00000020)
7025 #define CAN_F1R2_FB6 ((uint32_t)0x00000040)
7026 #define CAN_F1R2_FB7 ((uint32_t)0x00000080)
7027 #define CAN_F1R2_FB8 ((uint32_t)0x00000100)
7028 #define CAN_F1R2_FB9 ((uint32_t)0x00000200)
7029 #define CAN_F1R2_FB10 ((uint32_t)0x00000400)
7030 #define CAN_F1R2_FB11 ((uint32_t)0x00000800)
7031 #define CAN_F1R2_FB12 ((uint32_t)0x00001000)
7032 #define CAN_F1R2_FB13 ((uint32_t)0x00002000)
7033 #define CAN_F1R2_FB14 ((uint32_t)0x00004000)
7034 #define CAN_F1R2_FB15 ((uint32_t)0x00008000)
7035 #define CAN_F1R2_FB16 ((uint32_t)0x00010000)
7036 #define CAN_F1R2_FB17 ((uint32_t)0x00020000)
7037 #define CAN_F1R2_FB18 ((uint32_t)0x00040000)
7038 #define CAN_F1R2_FB19 ((uint32_t)0x00080000)
7039 #define CAN_F1R2_FB20 ((uint32_t)0x00100000)
7040 #define CAN_F1R2_FB21 ((uint32_t)0x00200000)
7041 #define CAN_F1R2_FB22 ((uint32_t)0x00400000)
7042 #define CAN_F1R2_FB23 ((uint32_t)0x00800000)
7043 #define CAN_F1R2_FB24 ((uint32_t)0x01000000)
7044 #define CAN_F1R2_FB25 ((uint32_t)0x02000000)
7045 #define CAN_F1R2_FB26 ((uint32_t)0x04000000)
7046 #define CAN_F1R2_FB27 ((uint32_t)0x08000000)
7047 #define CAN_F1R2_FB28 ((uint32_t)0x10000000)
7048 #define CAN_F1R2_FB29 ((uint32_t)0x20000000)
7049 #define CAN_F1R2_FB30 ((uint32_t)0x40000000)
7050 #define CAN_F1R2_FB31 ((uint32_t)0x80000000)
7052 /******************* Bit definition for CAN_F2R2 register *******************/
7053 #define CAN_F2R2_FB0 ((uint32_t)0x00000001)
7054 #define CAN_F2R2_FB1 ((uint32_t)0x00000002)
7055 #define CAN_F2R2_FB2 ((uint32_t)0x00000004)
7056 #define CAN_F2R2_FB3 ((uint32_t)0x00000008)
7057 #define CAN_F2R2_FB4 ((uint32_t)0x00000010)
7058 #define CAN_F2R2_FB5 ((uint32_t)0x00000020)
7059 #define CAN_F2R2_FB6 ((uint32_t)0x00000040)
7060 #define CAN_F2R2_FB7 ((uint32_t)0x00000080)
7061 #define CAN_F2R2_FB8 ((uint32_t)0x00000100)
7062 #define CAN_F2R2_FB9 ((uint32_t)0x00000200)
7063 #define CAN_F2R2_FB10 ((uint32_t)0x00000400)
7064 #define CAN_F2R2_FB11 ((uint32_t)0x00000800)
7065 #define CAN_F2R2_FB12 ((uint32_t)0x00001000)
7066 #define CAN_F2R2_FB13 ((uint32_t)0x00002000)
7067 #define CAN_F2R2_FB14 ((uint32_t)0x00004000)
7068 #define CAN_F2R2_FB15 ((uint32_t)0x00008000)
7069 #define CAN_F2R2_FB16 ((uint32_t)0x00010000)
7070 #define CAN_F2R2_FB17 ((uint32_t)0x00020000)
7071 #define CAN_F2R2_FB18 ((uint32_t)0x00040000)
7072 #define CAN_F2R2_FB19 ((uint32_t)0x00080000)
7073 #define CAN_F2R2_FB20 ((uint32_t)0x00100000)
7074 #define CAN_F2R2_FB21 ((uint32_t)0x00200000)
7075 #define CAN_F2R2_FB22 ((uint32_t)0x00400000)
7076 #define CAN_F2R2_FB23 ((uint32_t)0x00800000)
7077 #define CAN_F2R2_FB24 ((uint32_t)0x01000000)
7078 #define CAN_F2R2_FB25 ((uint32_t)0x02000000)
7079 #define CAN_F2R2_FB26 ((uint32_t)0x04000000)
7080 #define CAN_F2R2_FB27 ((uint32_t)0x08000000)
7081 #define CAN_F2R2_FB28 ((uint32_t)0x10000000)
7082 #define CAN_F2R2_FB29 ((uint32_t)0x20000000)
7083 #define CAN_F2R2_FB30 ((uint32_t)0x40000000)
7084 #define CAN_F2R2_FB31 ((uint32_t)0x80000000)
7086 /******************* Bit definition for CAN_F3R2 register *******************/
7087 #define CAN_F3R2_FB0 ((uint32_t)0x00000001)
7088 #define CAN_F3R2_FB1 ((uint32_t)0x00000002)
7089 #define CAN_F3R2_FB2 ((uint32_t)0x00000004)
7090 #define CAN_F3R2_FB3 ((uint32_t)0x00000008)
7091 #define CAN_F3R2_FB4 ((uint32_t)0x00000010)
7092 #define CAN_F3R2_FB5 ((uint32_t)0x00000020)
7093 #define CAN_F3R2_FB6 ((uint32_t)0x00000040)
7094 #define CAN_F3R2_FB7 ((uint32_t)0x00000080)
7095 #define CAN_F3R2_FB8 ((uint32_t)0x00000100)
7096 #define CAN_F3R2_FB9 ((uint32_t)0x00000200)
7097 #define CAN_F3R2_FB10 ((uint32_t)0x00000400)
7098 #define CAN_F3R2_FB11 ((uint32_t)0x00000800)
7099 #define CAN_F3R2_FB12 ((uint32_t)0x00001000)
7100 #define CAN_F3R2_FB13 ((uint32_t)0x00002000)
7101 #define CAN_F3R2_FB14 ((uint32_t)0x00004000)
7102 #define CAN_F3R2_FB15 ((uint32_t)0x00008000)
7103 #define CAN_F3R2_FB16 ((uint32_t)0x00010000)
7104 #define CAN_F3R2_FB17 ((uint32_t)0x00020000)
7105 #define CAN_F3R2_FB18 ((uint32_t)0x00040000)
7106 #define CAN_F3R2_FB19 ((uint32_t)0x00080000)
7107 #define CAN_F3R2_FB20 ((uint32_t)0x00100000)
7108 #define CAN_F3R2_FB21 ((uint32_t)0x00200000)
7109 #define CAN_F3R2_FB22 ((uint32_t)0x00400000)
7110 #define CAN_F3R2_FB23 ((uint32_t)0x00800000)
7111 #define CAN_F3R2_FB24 ((uint32_t)0x01000000)
7112 #define CAN_F3R2_FB25 ((uint32_t)0x02000000)
7113 #define CAN_F3R2_FB26 ((uint32_t)0x04000000)
7114 #define CAN_F3R2_FB27 ((uint32_t)0x08000000)
7115 #define CAN_F3R2_FB28 ((uint32_t)0x10000000)
7116 #define CAN_F3R2_FB29 ((uint32_t)0x20000000)
7117 #define CAN_F3R2_FB30 ((uint32_t)0x40000000)
7118 #define CAN_F3R2_FB31 ((uint32_t)0x80000000)
7120 /******************* Bit definition for CAN_F4R2 register *******************/
7121 #define CAN_F4R2_FB0 ((uint32_t)0x00000001)
7122 #define CAN_F4R2_FB1 ((uint32_t)0x00000002)
7123 #define CAN_F4R2_FB2 ((uint32_t)0x00000004)
7124 #define CAN_F4R2_FB3 ((uint32_t)0x00000008)
7125 #define CAN_F4R2_FB4 ((uint32_t)0x00000010)
7126 #define CAN_F4R2_FB5 ((uint32_t)0x00000020)
7127 #define CAN_F4R2_FB6 ((uint32_t)0x00000040)
7128 #define CAN_F4R2_FB7 ((uint32_t)0x00000080)
7129 #define CAN_F4R2_FB8 ((uint32_t)0x00000100)
7130 #define CAN_F4R2_FB9 ((uint32_t)0x00000200)
7131 #define CAN_F4R2_FB10 ((uint32_t)0x00000400)
7132 #define CAN_F4R2_FB11 ((uint32_t)0x00000800)
7133 #define CAN_F4R2_FB12 ((uint32_t)0x00001000)
7134 #define CAN_F4R2_FB13 ((uint32_t)0x00002000)
7135 #define CAN_F4R2_FB14 ((uint32_t)0x00004000)
7136 #define CAN_F4R2_FB15 ((uint32_t)0x00008000)
7137 #define CAN_F4R2_FB16 ((uint32_t)0x00010000)
7138 #define CAN_F4R2_FB17 ((uint32_t)0x00020000)
7139 #define CAN_F4R2_FB18 ((uint32_t)0x00040000)
7140 #define CAN_F4R2_FB19 ((uint32_t)0x00080000)
7141 #define CAN_F4R2_FB20 ((uint32_t)0x00100000)
7142 #define CAN_F4R2_FB21 ((uint32_t)0x00200000)
7143 #define CAN_F4R2_FB22 ((uint32_t)0x00400000)
7144 #define CAN_F4R2_FB23 ((uint32_t)0x00800000)
7145 #define CAN_F4R2_FB24 ((uint32_t)0x01000000)
7146 #define CAN_F4R2_FB25 ((uint32_t)0x02000000)
7147 #define CAN_F4R2_FB26 ((uint32_t)0x04000000)
7148 #define CAN_F4R2_FB27 ((uint32_t)0x08000000)
7149 #define CAN_F4R2_FB28 ((uint32_t)0x10000000)
7150 #define CAN_F4R2_FB29 ((uint32_t)0x20000000)
7151 #define CAN_F4R2_FB30 ((uint32_t)0x40000000)
7152 #define CAN_F4R2_FB31 ((uint32_t)0x80000000)
7154 /******************* Bit definition for CAN_F5R2 register *******************/
7155 #define CAN_F5R2_FB0 ((uint32_t)0x00000001)
7156 #define CAN_F5R2_FB1 ((uint32_t)0x00000002)
7157 #define CAN_F5R2_FB2 ((uint32_t)0x00000004)
7158 #define CAN_F5R2_FB3 ((uint32_t)0x00000008)
7159 #define CAN_F5R2_FB4 ((uint32_t)0x00000010)
7160 #define CAN_F5R2_FB5 ((uint32_t)0x00000020)
7161 #define CAN_F5R2_FB6 ((uint32_t)0x00000040)
7162 #define CAN_F5R2_FB7 ((uint32_t)0x00000080)
7163 #define CAN_F5R2_FB8 ((uint32_t)0x00000100)
7164 #define CAN_F5R2_FB9 ((uint32_t)0x00000200)
7165 #define CAN_F5R2_FB10 ((uint32_t)0x00000400)
7166 #define CAN_F5R2_FB11 ((uint32_t)0x00000800)
7167 #define CAN_F5R2_FB12 ((uint32_t)0x00001000)
7168 #define CAN_F5R2_FB13 ((uint32_t)0x00002000)
7169 #define CAN_F5R2_FB14 ((uint32_t)0x00004000)
7170 #define CAN_F5R2_FB15 ((uint32_t)0x00008000)
7171 #define CAN_F5R2_FB16 ((uint32_t)0x00010000)
7172 #define CAN_F5R2_FB17 ((uint32_t)0x00020000)
7173 #define CAN_F5R2_FB18 ((uint32_t)0x00040000)
7174 #define CAN_F5R2_FB19 ((uint32_t)0x00080000)
7175 #define CAN_F5R2_FB20 ((uint32_t)0x00100000)
7176 #define CAN_F5R2_FB21 ((uint32_t)0x00200000)
7177 #define CAN_F5R2_FB22 ((uint32_t)0x00400000)
7178 #define CAN_F5R2_FB23 ((uint32_t)0x00800000)
7179 #define CAN_F5R2_FB24 ((uint32_t)0x01000000)
7180 #define CAN_F5R2_FB25 ((uint32_t)0x02000000)
7181 #define CAN_F5R2_FB26 ((uint32_t)0x04000000)
7182 #define CAN_F5R2_FB27 ((uint32_t)0x08000000)
7183 #define CAN_F5R2_FB28 ((uint32_t)0x10000000)
7184 #define CAN_F5R2_FB29 ((uint32_t)0x20000000)
7185 #define CAN_F5R2_FB30 ((uint32_t)0x40000000)
7186 #define CAN_F5R2_FB31 ((uint32_t)0x80000000)
7188 /******************* Bit definition for CAN_F6R2 register *******************/
7189 #define CAN_F6R2_FB0 ((uint32_t)0x00000001)
7190 #define CAN_F6R2_FB1 ((uint32_t)0x00000002)
7191 #define CAN_F6R2_FB2 ((uint32_t)0x00000004)
7192 #define CAN_F6R2_FB3 ((uint32_t)0x00000008)
7193 #define CAN_F6R2_FB4 ((uint32_t)0x00000010)
7194 #define CAN_F6R2_FB5 ((uint32_t)0x00000020)
7195 #define CAN_F6R2_FB6 ((uint32_t)0x00000040)
7196 #define CAN_F6R2_FB7 ((uint32_t)0x00000080)
7197 #define CAN_F6R2_FB8 ((uint32_t)0x00000100)
7198 #define CAN_F6R2_FB9 ((uint32_t)0x00000200)
7199 #define CAN_F6R2_FB10 ((uint32_t)0x00000400)
7200 #define CAN_F6R2_FB11 ((uint32_t)0x00000800)
7201 #define CAN_F6R2_FB12 ((uint32_t)0x00001000)
7202 #define CAN_F6R2_FB13 ((uint32_t)0x00002000)
7203 #define CAN_F6R2_FB14 ((uint32_t)0x00004000)
7204 #define CAN_F6R2_FB15 ((uint32_t)0x00008000)
7205 #define CAN_F6R2_FB16 ((uint32_t)0x00010000)
7206 #define CAN_F6R2_FB17 ((uint32_t)0x00020000)
7207 #define CAN_F6R2_FB18 ((uint32_t)0x00040000)
7208 #define CAN_F6R2_FB19 ((uint32_t)0x00080000)
7209 #define CAN_F6R2_FB20 ((uint32_t)0x00100000)
7210 #define CAN_F6R2_FB21 ((uint32_t)0x00200000)
7211 #define CAN_F6R2_FB22 ((uint32_t)0x00400000)
7212 #define CAN_F6R2_FB23 ((uint32_t)0x00800000)
7213 #define CAN_F6R2_FB24 ((uint32_t)0x01000000)
7214 #define CAN_F6R2_FB25 ((uint32_t)0x02000000)
7215 #define CAN_F6R2_FB26 ((uint32_t)0x04000000)
7216 #define CAN_F6R2_FB27 ((uint32_t)0x08000000)
7217 #define CAN_F6R2_FB28 ((uint32_t)0x10000000)
7218 #define CAN_F6R2_FB29 ((uint32_t)0x20000000)
7219 #define CAN_F6R2_FB30 ((uint32_t)0x40000000)
7220 #define CAN_F6R2_FB31 ((uint32_t)0x80000000)
7222 /******************* Bit definition for CAN_F7R2 register *******************/
7223 #define CAN_F7R2_FB0 ((uint32_t)0x00000001)
7224 #define CAN_F7R2_FB1 ((uint32_t)0x00000002)
7225 #define CAN_F7R2_FB2 ((uint32_t)0x00000004)
7226 #define CAN_F7R2_FB3 ((uint32_t)0x00000008)
7227 #define CAN_F7R2_FB4 ((uint32_t)0x00000010)
7228 #define CAN_F7R2_FB5 ((uint32_t)0x00000020)
7229 #define CAN_F7R2_FB6 ((uint32_t)0x00000040)
7230 #define CAN_F7R2_FB7 ((uint32_t)0x00000080)
7231 #define CAN_F7R2_FB8 ((uint32_t)0x00000100)
7232 #define CAN_F7R2_FB9 ((uint32_t)0x00000200)
7233 #define CAN_F7R2_FB10 ((uint32_t)0x00000400)
7234 #define CAN_F7R2_FB11 ((uint32_t)0x00000800)
7235 #define CAN_F7R2_FB12 ((uint32_t)0x00001000)
7236 #define CAN_F7R2_FB13 ((uint32_t)0x00002000)
7237 #define CAN_F7R2_FB14 ((uint32_t)0x00004000)
7238 #define CAN_F7R2_FB15 ((uint32_t)0x00008000)
7239 #define CAN_F7R2_FB16 ((uint32_t)0x00010000)
7240 #define CAN_F7R2_FB17 ((uint32_t)0x00020000)
7241 #define CAN_F7R2_FB18 ((uint32_t)0x00040000)
7242 #define CAN_F7R2_FB19 ((uint32_t)0x00080000)
7243 #define CAN_F7R2_FB20 ((uint32_t)0x00100000)
7244 #define CAN_F7R2_FB21 ((uint32_t)0x00200000)
7245 #define CAN_F7R2_FB22 ((uint32_t)0x00400000)
7246 #define CAN_F7R2_FB23 ((uint32_t)0x00800000)
7247 #define CAN_F7R2_FB24 ((uint32_t)0x01000000)
7248 #define CAN_F7R2_FB25 ((uint32_t)0x02000000)
7249 #define CAN_F7R2_FB26 ((uint32_t)0x04000000)
7250 #define CAN_F7R2_FB27 ((uint32_t)0x08000000)
7251 #define CAN_F7R2_FB28 ((uint32_t)0x10000000)
7252 #define CAN_F7R2_FB29 ((uint32_t)0x20000000)
7253 #define CAN_F7R2_FB30 ((uint32_t)0x40000000)
7254 #define CAN_F7R2_FB31 ((uint32_t)0x80000000)
7256 /******************* Bit definition for CAN_F8R2 register *******************/
7257 #define CAN_F8R2_FB0 ((uint32_t)0x00000001)
7258 #define CAN_F8R2_FB1 ((uint32_t)0x00000002)
7259 #define CAN_F8R2_FB2 ((uint32_t)0x00000004)
7260 #define CAN_F8R2_FB3 ((uint32_t)0x00000008)
7261 #define CAN_F8R2_FB4 ((uint32_t)0x00000010)
7262 #define CAN_F8R2_FB5 ((uint32_t)0x00000020)
7263 #define CAN_F8R2_FB6 ((uint32_t)0x00000040)
7264 #define CAN_F8R2_FB7 ((uint32_t)0x00000080)
7265 #define CAN_F8R2_FB8 ((uint32_t)0x00000100)
7266 #define CAN_F8R2_FB9 ((uint32_t)0x00000200)
7267 #define CAN_F8R2_FB10 ((uint32_t)0x00000400)
7268 #define CAN_F8R2_FB11 ((uint32_t)0x00000800)
7269 #define CAN_F8R2_FB12 ((uint32_t)0x00001000)
7270 #define CAN_F8R2_FB13 ((uint32_t)0x00002000)
7271 #define CAN_F8R2_FB14 ((uint32_t)0x00004000)
7272 #define CAN_F8R2_FB15 ((uint32_t)0x00008000)
7273 #define CAN_F8R2_FB16 ((uint32_t)0x00010000)
7274 #define CAN_F8R2_FB17 ((uint32_t)0x00020000)
7275 #define CAN_F8R2_FB18 ((uint32_t)0x00040000)
7276 #define CAN_F8R2_FB19 ((uint32_t)0x00080000)
7277 #define CAN_F8R2_FB20 ((uint32_t)0x00100000)
7278 #define CAN_F8R2_FB21 ((uint32_t)0x00200000)
7279 #define CAN_F8R2_FB22 ((uint32_t)0x00400000)
7280 #define CAN_F8R2_FB23 ((uint32_t)0x00800000)
7281 #define CAN_F8R2_FB24 ((uint32_t)0x01000000)
7282 #define CAN_F8R2_FB25 ((uint32_t)0x02000000)
7283 #define CAN_F8R2_FB26 ((uint32_t)0x04000000)
7284 #define CAN_F8R2_FB27 ((uint32_t)0x08000000)
7285 #define CAN_F8R2_FB28 ((uint32_t)0x10000000)
7286 #define CAN_F8R2_FB29 ((uint32_t)0x20000000)
7287 #define CAN_F8R2_FB30 ((uint32_t)0x40000000)
7288 #define CAN_F8R2_FB31 ((uint32_t)0x80000000)
7290 /******************* Bit definition for CAN_F9R2 register *******************/
7291 #define CAN_F9R2_FB0 ((uint32_t)0x00000001)
7292 #define CAN_F9R2_FB1 ((uint32_t)0x00000002)
7293 #define CAN_F9R2_FB2 ((uint32_t)0x00000004)
7294 #define CAN_F9R2_FB3 ((uint32_t)0x00000008)
7295 #define CAN_F9R2_FB4 ((uint32_t)0x00000010)
7296 #define CAN_F9R2_FB5 ((uint32_t)0x00000020)
7297 #define CAN_F9R2_FB6 ((uint32_t)0x00000040)
7298 #define CAN_F9R2_FB7 ((uint32_t)0x00000080)
7299 #define CAN_F9R2_FB8 ((uint32_t)0x00000100)
7300 #define CAN_F9R2_FB9 ((uint32_t)0x00000200)
7301 #define CAN_F9R2_FB10 ((uint32_t)0x00000400)
7302 #define CAN_F9R2_FB11 ((uint32_t)0x00000800)
7303 #define CAN_F9R2_FB12 ((uint32_t)0x00001000)
7304 #define CAN_F9R2_FB13 ((uint32_t)0x00002000)
7305 #define CAN_F9R2_FB14 ((uint32_t)0x00004000)
7306 #define CAN_F9R2_FB15 ((uint32_t)0x00008000)
7307 #define CAN_F9R2_FB16 ((uint32_t)0x00010000)
7308 #define CAN_F9R2_FB17 ((uint32_t)0x00020000)
7309 #define CAN_F9R2_FB18 ((uint32_t)0x00040000)
7310 #define CAN_F9R2_FB19 ((uint32_t)0x00080000)
7311 #define CAN_F9R2_FB20 ((uint32_t)0x00100000)
7312 #define CAN_F9R2_FB21 ((uint32_t)0x00200000)
7313 #define CAN_F9R2_FB22 ((uint32_t)0x00400000)
7314 #define CAN_F9R2_FB23 ((uint32_t)0x00800000)
7315 #define CAN_F9R2_FB24 ((uint32_t)0x01000000)
7316 #define CAN_F9R2_FB25 ((uint32_t)0x02000000)
7317 #define CAN_F9R2_FB26 ((uint32_t)0x04000000)
7318 #define CAN_F9R2_FB27 ((uint32_t)0x08000000)
7319 #define CAN_F9R2_FB28 ((uint32_t)0x10000000)
7320 #define CAN_F9R2_FB29 ((uint32_t)0x20000000)
7321 #define CAN_F9R2_FB30 ((uint32_t)0x40000000)
7322 #define CAN_F9R2_FB31 ((uint32_t)0x80000000)
7324 /******************* Bit definition for CAN_F10R2 register ******************/
7325 #define CAN_F10R2_FB0 ((uint32_t)0x00000001)
7326 #define CAN_F10R2_FB1 ((uint32_t)0x00000002)
7327 #define CAN_F10R2_FB2 ((uint32_t)0x00000004)
7328 #define CAN_F10R2_FB3 ((uint32_t)0x00000008)
7329 #define CAN_F10R2_FB4 ((uint32_t)0x00000010)
7330 #define CAN_F10R2_FB5 ((uint32_t)0x00000020)
7331 #define CAN_F10R2_FB6 ((uint32_t)0x00000040)
7332 #define CAN_F10R2_FB7 ((uint32_t)0x00000080)
7333 #define CAN_F10R2_FB8 ((uint32_t)0x00000100)
7334 #define CAN_F10R2_FB9 ((uint32_t)0x00000200)
7335 #define CAN_F10R2_FB10 ((uint32_t)0x00000400)
7336 #define CAN_F10R2_FB11 ((uint32_t)0x00000800)
7337 #define CAN_F10R2_FB12 ((uint32_t)0x00001000)
7338 #define CAN_F10R2_FB13 ((uint32_t)0x00002000)
7339 #define CAN_F10R2_FB14 ((uint32_t)0x00004000)
7340 #define CAN_F10R2_FB15 ((uint32_t)0x00008000)
7341 #define CAN_F10R2_FB16 ((uint32_t)0x00010000)
7342 #define CAN_F10R2_FB17 ((uint32_t)0x00020000)
7343 #define CAN_F10R2_FB18 ((uint32_t)0x00040000)
7344 #define CAN_F10R2_FB19 ((uint32_t)0x00080000)
7345 #define CAN_F10R2_FB20 ((uint32_t)0x00100000)
7346 #define CAN_F10R2_FB21 ((uint32_t)0x00200000)
7347 #define CAN_F10R2_FB22 ((uint32_t)0x00400000)
7348 #define CAN_F10R2_FB23 ((uint32_t)0x00800000)
7349 #define CAN_F10R2_FB24 ((uint32_t)0x01000000)
7350 #define CAN_F10R2_FB25 ((uint32_t)0x02000000)
7351 #define CAN_F10R2_FB26 ((uint32_t)0x04000000)
7352 #define CAN_F10R2_FB27 ((uint32_t)0x08000000)
7353 #define CAN_F10R2_FB28 ((uint32_t)0x10000000)
7354 #define CAN_F10R2_FB29 ((uint32_t)0x20000000)
7355 #define CAN_F10R2_FB30 ((uint32_t)0x40000000)
7356 #define CAN_F10R2_FB31 ((uint32_t)0x80000000)
7358 /******************* Bit definition for CAN_F11R2 register ******************/
7359 #define CAN_F11R2_FB0 ((uint32_t)0x00000001)
7360 #define CAN_F11R2_FB1 ((uint32_t)0x00000002)
7361 #define CAN_F11R2_FB2 ((uint32_t)0x00000004)
7362 #define CAN_F11R2_FB3 ((uint32_t)0x00000008)
7363 #define CAN_F11R2_FB4 ((uint32_t)0x00000010)
7364 #define CAN_F11R2_FB5 ((uint32_t)0x00000020)
7365 #define CAN_F11R2_FB6 ((uint32_t)0x00000040)
7366 #define CAN_F11R2_FB7 ((uint32_t)0x00000080)
7367 #define CAN_F11R2_FB8 ((uint32_t)0x00000100)
7368 #define CAN_F11R2_FB9 ((uint32_t)0x00000200)
7369 #define CAN_F11R2_FB10 ((uint32_t)0x00000400)
7370 #define CAN_F11R2_FB11 ((uint32_t)0x00000800)
7371 #define CAN_F11R2_FB12 ((uint32_t)0x00001000)
7372 #define CAN_F11R2_FB13 ((uint32_t)0x00002000)
7373 #define CAN_F11R2_FB14 ((uint32_t)0x00004000)
7374 #define CAN_F11R2_FB15 ((uint32_t)0x00008000)
7375 #define CAN_F11R2_FB16 ((uint32_t)0x00010000)
7376 #define CAN_F11R2_FB17 ((uint32_t)0x00020000)
7377 #define CAN_F11R2_FB18 ((uint32_t)0x00040000)
7378 #define CAN_F11R2_FB19 ((uint32_t)0x00080000)
7379 #define CAN_F11R2_FB20 ((uint32_t)0x00100000)
7380 #define CAN_F11R2_FB21 ((uint32_t)0x00200000)
7381 #define CAN_F11R2_FB22 ((uint32_t)0x00400000)
7382 #define CAN_F11R2_FB23 ((uint32_t)0x00800000)
7383 #define CAN_F11R2_FB24 ((uint32_t)0x01000000)
7384 #define CAN_F11R2_FB25 ((uint32_t)0x02000000)
7385 #define CAN_F11R2_FB26 ((uint32_t)0x04000000)
7386 #define CAN_F11R2_FB27 ((uint32_t)0x08000000)
7387 #define CAN_F11R2_FB28 ((uint32_t)0x10000000)
7388 #define CAN_F11R2_FB29 ((uint32_t)0x20000000)
7389 #define CAN_F11R2_FB30 ((uint32_t)0x40000000)
7390 #define CAN_F11R2_FB31 ((uint32_t)0x80000000)
7392 /******************* Bit definition for CAN_F12R2 register ******************/
7393 #define CAN_F12R2_FB0 ((uint32_t)0x00000001)
7394 #define CAN_F12R2_FB1 ((uint32_t)0x00000002)
7395 #define CAN_F12R2_FB2 ((uint32_t)0x00000004)
7396 #define CAN_F12R2_FB3 ((uint32_t)0x00000008)
7397 #define CAN_F12R2_FB4 ((uint32_t)0x00000010)
7398 #define CAN_F12R2_FB5 ((uint32_t)0x00000020)
7399 #define CAN_F12R2_FB6 ((uint32_t)0x00000040)
7400 #define CAN_F12R2_FB7 ((uint32_t)0x00000080)
7401 #define CAN_F12R2_FB8 ((uint32_t)0x00000100)
7402 #define CAN_F12R2_FB9 ((uint32_t)0x00000200)
7403 #define CAN_F12R2_FB10 ((uint32_t)0x00000400)
7404 #define CAN_F12R2_FB11 ((uint32_t)0x00000800)
7405 #define CAN_F12R2_FB12 ((uint32_t)0x00001000)
7406 #define CAN_F12R2_FB13 ((uint32_t)0x00002000)
7407 #define CAN_F12R2_FB14 ((uint32_t)0x00004000)
7408 #define CAN_F12R2_FB15 ((uint32_t)0x00008000)
7409 #define CAN_F12R2_FB16 ((uint32_t)0x00010000)
7410 #define CAN_F12R2_FB17 ((uint32_t)0x00020000)
7411 #define CAN_F12R2_FB18 ((uint32_t)0x00040000)
7412 #define CAN_F12R2_FB19 ((uint32_t)0x00080000)
7413 #define CAN_F12R2_FB20 ((uint32_t)0x00100000)
7414 #define CAN_F12R2_FB21 ((uint32_t)0x00200000)
7415 #define CAN_F12R2_FB22 ((uint32_t)0x00400000)
7416 #define CAN_F12R2_FB23 ((uint32_t)0x00800000)
7417 #define CAN_F12R2_FB24 ((uint32_t)0x01000000)
7418 #define CAN_F12R2_FB25 ((uint32_t)0x02000000)
7419 #define CAN_F12R2_FB26 ((uint32_t)0x04000000)
7420 #define CAN_F12R2_FB27 ((uint32_t)0x08000000)
7421 #define CAN_F12R2_FB28 ((uint32_t)0x10000000)
7422 #define CAN_F12R2_FB29 ((uint32_t)0x20000000)
7423 #define CAN_F12R2_FB30 ((uint32_t)0x40000000)
7424 #define CAN_F12R2_FB31 ((uint32_t)0x80000000)
7426 /******************* Bit definition for CAN_F13R2 register ******************/
7427 #define CAN_F13R2_FB0 ((uint32_t)0x00000001)
7428 #define CAN_F13R2_FB1 ((uint32_t)0x00000002)
7429 #define CAN_F13R2_FB2 ((uint32_t)0x00000004)
7430 #define CAN_F13R2_FB3 ((uint32_t)0x00000008)
7431 #define CAN_F13R2_FB4 ((uint32_t)0x00000010)
7432 #define CAN_F13R2_FB5 ((uint32_t)0x00000020)
7433 #define CAN_F13R2_FB6 ((uint32_t)0x00000040)
7434 #define CAN_F13R2_FB7 ((uint32_t)0x00000080)
7435 #define CAN_F13R2_FB8 ((uint32_t)0x00000100)
7436 #define CAN_F13R2_FB9 ((uint32_t)0x00000200)
7437 #define CAN_F13R2_FB10 ((uint32_t)0x00000400)
7438 #define CAN_F13R2_FB11 ((uint32_t)0x00000800)
7439 #define CAN_F13R2_FB12 ((uint32_t)0x00001000)
7440 #define CAN_F13R2_FB13 ((uint32_t)0x00002000)
7441 #define CAN_F13R2_FB14 ((uint32_t)0x00004000)
7442 #define CAN_F13R2_FB15 ((uint32_t)0x00008000)
7443 #define CAN_F13R2_FB16 ((uint32_t)0x00010000)
7444 #define CAN_F13R2_FB17 ((uint32_t)0x00020000)
7445 #define CAN_F13R2_FB18 ((uint32_t)0x00040000)
7446 #define CAN_F13R2_FB19 ((uint32_t)0x00080000)
7447 #define CAN_F13R2_FB20 ((uint32_t)0x00100000)
7448 #define CAN_F13R2_FB21 ((uint32_t)0x00200000)
7449 #define CAN_F13R2_FB22 ((uint32_t)0x00400000)
7450 #define CAN_F13R2_FB23 ((uint32_t)0x00800000)
7451 #define CAN_F13R2_FB24 ((uint32_t)0x01000000)
7452 #define CAN_F13R2_FB25 ((uint32_t)0x02000000)
7453 #define CAN_F13R2_FB26 ((uint32_t)0x04000000)
7454 #define CAN_F13R2_FB27 ((uint32_t)0x08000000)
7455 #define CAN_F13R2_FB28 ((uint32_t)0x10000000)
7456 #define CAN_F13R2_FB29 ((uint32_t)0x20000000)
7457 #define CAN_F13R2_FB30 ((uint32_t)0x40000000)
7458 #define CAN_F13R2_FB31 ((uint32_t)0x80000000)
7460 /******************************************************************************/
7461 /* */
7462 /* Serial Peripheral Interface */
7463 /* */
7464 /******************************************************************************/
7465 
7466 /******************* Bit definition for SPI_CR1 register ********************/
7467 #define SPI_CR1_CPHA ((uint16_t)0x0001)
7468 #define SPI_CR1_CPOL ((uint16_t)0x0002)
7469 #define SPI_CR1_MSTR ((uint16_t)0x0004)
7471 #define SPI_CR1_BR ((uint16_t)0x0038)
7472 #define SPI_CR1_BR_0 ((uint16_t)0x0008)
7473 #define SPI_CR1_BR_1 ((uint16_t)0x0010)
7474 #define SPI_CR1_BR_2 ((uint16_t)0x0020)
7476 #define SPI_CR1_SPE ((uint16_t)0x0040)
7477 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080)
7478 #define SPI_CR1_SSI ((uint16_t)0x0100)
7479 #define SPI_CR1_SSM ((uint16_t)0x0200)
7480 #define SPI_CR1_RXONLY ((uint16_t)0x0400)
7481 #define SPI_CR1_DFF ((uint16_t)0x0800)
7482 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000)
7483 #define SPI_CR1_CRCEN ((uint16_t)0x2000)
7484 #define SPI_CR1_BIDIOE ((uint16_t)0x4000)
7485 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000)
7487 /******************* Bit definition for SPI_CR2 register ********************/
7488 #define SPI_CR2_RXDMAEN ((uint8_t)0x01)
7489 #define SPI_CR2_TXDMAEN ((uint8_t)0x02)
7490 #define SPI_CR2_SSOE ((uint8_t)0x04)
7491 #define SPI_CR2_ERRIE ((uint8_t)0x20)
7492 #define SPI_CR2_RXNEIE ((uint8_t)0x40)
7493 #define SPI_CR2_TXEIE ((uint8_t)0x80)
7495 /******************** Bit definition for SPI_SR register ********************/
7496 #define SPI_SR_RXNE ((uint8_t)0x01)
7497 #define SPI_SR_TXE ((uint8_t)0x02)
7498 #define SPI_SR_CHSIDE ((uint8_t)0x04)
7499 #define SPI_SR_UDR ((uint8_t)0x08)
7500 #define SPI_SR_CRCERR ((uint8_t)0x10)
7501 #define SPI_SR_MODF ((uint8_t)0x20)
7502 #define SPI_SR_OVR ((uint8_t)0x40)
7503 #define SPI_SR_BSY ((uint8_t)0x80)
7505 /******************** Bit definition for SPI_DR register ********************/
7506 #define SPI_DR_DR ((uint16_t)0xFFFF)
7508 /******************* Bit definition for SPI_CRCPR register ******************/
7509 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF)
7511 /****************** Bit definition for SPI_RXCRCR register ******************/
7512 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF)
7514 /****************** Bit definition for SPI_TXCRCR register ******************/
7515 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF)
7517 /****************** Bit definition for SPI_I2SCFGR register *****************/
7518 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001)
7520 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006)
7521 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002)
7522 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004)
7524 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008)
7526 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030)
7527 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010)
7528 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020)
7530 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080)
7532 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300)
7533 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100)
7534 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200)
7536 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400)
7537 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800)
7539 /****************** Bit definition for SPI_I2SPR register *******************/
7540 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF)
7541 #define SPI_I2SPR_ODD ((uint16_t)0x0100)
7542 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200)
7544 /******************************************************************************/
7545 /* */
7546 /* Inter-integrated Circuit Interface */
7547 /* */
7548 /******************************************************************************/
7549 
7550 /******************* Bit definition for I2C_CR1 register ********************/
7551 #define I2C_CR1_PE ((uint16_t)0x0001)
7552 #define I2C_CR1_SMBUS ((uint16_t)0x0002)
7553 #define I2C_CR1_SMBTYPE ((uint16_t)0x0008)
7554 #define I2C_CR1_ENARP ((uint16_t)0x0010)
7555 #define I2C_CR1_ENPEC ((uint16_t)0x0020)
7556 #define I2C_CR1_ENGC ((uint16_t)0x0040)
7557 #define I2C_CR1_NOSTRETCH ((uint16_t)0x0080)
7558 #define I2C_CR1_START ((uint16_t)0x0100)
7559 #define I2C_CR1_STOP ((uint16_t)0x0200)
7560 #define I2C_CR1_ACK ((uint16_t)0x0400)
7561 #define I2C_CR1_POS ((uint16_t)0x0800)
7562 #define I2C_CR1_PEC ((uint16_t)0x1000)
7563 #define I2C_CR1_ALERT ((uint16_t)0x2000)
7564 #define I2C_CR1_SWRST ((uint16_t)0x8000)
7566 /******************* Bit definition for I2C_CR2 register ********************/
7567 #define I2C_CR2_FREQ ((uint16_t)0x003F)
7568 #define I2C_CR2_FREQ_0 ((uint16_t)0x0001)
7569 #define I2C_CR2_FREQ_1 ((uint16_t)0x0002)
7570 #define I2C_CR2_FREQ_2 ((uint16_t)0x0004)
7571 #define I2C_CR2_FREQ_3 ((uint16_t)0x0008)
7572 #define I2C_CR2_FREQ_4 ((uint16_t)0x0010)
7573 #define I2C_CR2_FREQ_5 ((uint16_t)0x0020)
7575 #define I2C_CR2_ITERREN ((uint16_t)0x0100)
7576 #define I2C_CR2_ITEVTEN ((uint16_t)0x0200)
7577 #define I2C_CR2_ITBUFEN ((uint16_t)0x0400)
7578 #define I2C_CR2_DMAEN ((uint16_t)0x0800)
7579 #define I2C_CR2_LAST ((uint16_t)0x1000)
7581 /******************* Bit definition for I2C_OAR1 register *******************/
7582 #define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE)
7583 #define I2C_OAR1_ADD8_9 ((uint16_t)0x0300)
7585 #define I2C_OAR1_ADD0 ((uint16_t)0x0001)
7586 #define I2C_OAR1_ADD1 ((uint16_t)0x0002)
7587 #define I2C_OAR1_ADD2 ((uint16_t)0x0004)
7588 #define I2C_OAR1_ADD3 ((uint16_t)0x0008)
7589 #define I2C_OAR1_ADD4 ((uint16_t)0x0010)
7590 #define I2C_OAR1_ADD5 ((uint16_t)0x0020)
7591 #define I2C_OAR1_ADD6 ((uint16_t)0x0040)
7592 #define I2C_OAR1_ADD7 ((uint16_t)0x0080)
7593 #define I2C_OAR1_ADD8 ((uint16_t)0x0100)
7594 #define I2C_OAR1_ADD9 ((uint16_t)0x0200)
7596 #define I2C_OAR1_ADDMODE ((uint16_t)0x8000)
7598 /******************* Bit definition for I2C_OAR2 register *******************/
7599 #define I2C_OAR2_ENDUAL ((uint8_t)0x01)
7600 #define I2C_OAR2_ADD2 ((uint8_t)0xFE)
7602 /******************** Bit definition for I2C_DR register ********************/
7603 #define I2C_DR_DR ((uint8_t)0xFF)
7605 /******************* Bit definition for I2C_SR1 register ********************/
7606 #define I2C_SR1_SB ((uint16_t)0x0001)
7607 #define I2C_SR1_ADDR ((uint16_t)0x0002)
7608 #define I2C_SR1_BTF ((uint16_t)0x0004)
7609 #define I2C_SR1_ADD10 ((uint16_t)0x0008)
7610 #define I2C_SR1_STOPF ((uint16_t)0x0010)
7611 #define I2C_SR1_RXNE ((uint16_t)0x0040)
7612 #define I2C_SR1_TXE ((uint16_t)0x0080)
7613 #define I2C_SR1_BERR ((uint16_t)0x0100)
7614 #define I2C_SR1_ARLO ((uint16_t)0x0200)
7615 #define I2C_SR1_AF ((uint16_t)0x0400)
7616 #define I2C_SR1_OVR ((uint16_t)0x0800)
7617 #define I2C_SR1_PECERR ((uint16_t)0x1000)
7618 #define I2C_SR1_TIMEOUT ((uint16_t)0x4000)
7619 #define I2C_SR1_SMBALERT ((uint16_t)0x8000)
7621 /******************* Bit definition for I2C_SR2 register ********************/
7622 #define I2C_SR2_MSL ((uint16_t)0x0001)
7623 #define I2C_SR2_BUSY ((uint16_t)0x0002)
7624 #define I2C_SR2_TRA ((uint16_t)0x0004)
7625 #define I2C_SR2_GENCALL ((uint16_t)0x0010)
7626 #define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020)
7627 #define I2C_SR2_SMBHOST ((uint16_t)0x0040)
7628 #define I2C_SR2_DUALF ((uint16_t)0x0080)
7629 #define I2C_SR2_PEC ((uint16_t)0xFF00)
7631 /******************* Bit definition for I2C_CCR register ********************/
7632 #define I2C_CCR_CCR ((uint16_t)0x0FFF)
7633 #define I2C_CCR_DUTY ((uint16_t)0x4000)
7634 #define I2C_CCR_FS ((uint16_t)0x8000)
7636 /****************** Bit definition for I2C_TRISE register *******************/
7637 #define I2C_TRISE_TRISE ((uint8_t)0x3F)
7639 /******************************************************************************/
7640 /* */
7641 /* Universal Synchronous Asynchronous Receiver Transmitter */
7642 /* */
7643 /******************************************************************************/
7644 
7645 /******************* Bit definition for USART_SR register *******************/
7646 #define USART_SR_PE ((uint16_t)0x0001)
7647 #define USART_SR_FE ((uint16_t)0x0002)
7648 #define USART_SR_NE ((uint16_t)0x0004)
7649 #define USART_SR_ORE ((uint16_t)0x0008)
7650 #define USART_SR_IDLE ((uint16_t)0x0010)
7651 #define USART_SR_RXNE ((uint16_t)0x0020)
7652 #define USART_SR_TC ((uint16_t)0x0040)
7653 #define USART_SR_TXE ((uint16_t)0x0080)
7654 #define USART_SR_LBD ((uint16_t)0x0100)
7655 #define USART_SR_CTS ((uint16_t)0x0200)
7657 /******************* Bit definition for USART_DR register *******************/
7658 #define USART_DR_DR ((uint16_t)0x01FF)
7660 /****************** Bit definition for USART_BRR register *******************/
7661 #define USART_BRR_DIV_Fraction ((uint16_t)0x000F)
7662 #define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0)
7664 /****************** Bit definition for USART_CR1 register *******************/
7665 #define USART_CR1_SBK ((uint16_t)0x0001)
7666 #define USART_CR1_RWU ((uint16_t)0x0002)
7667 #define USART_CR1_RE ((uint16_t)0x0004)
7668 #define USART_CR1_TE ((uint16_t)0x0008)
7669 #define USART_CR1_IDLEIE ((uint16_t)0x0010)
7670 #define USART_CR1_RXNEIE ((uint16_t)0x0020)
7671 #define USART_CR1_TCIE ((uint16_t)0x0040)
7672 #define USART_CR1_TXEIE ((uint16_t)0x0080)
7673 #define USART_CR1_PEIE ((uint16_t)0x0100)
7674 #define USART_CR1_PS ((uint16_t)0x0200)
7675 #define USART_CR1_PCE ((uint16_t)0x0400)
7676 #define USART_CR1_WAKE ((uint16_t)0x0800)
7677 #define USART_CR1_M ((uint16_t)0x1000)
7678 #define USART_CR1_UE ((uint16_t)0x2000)
7679 #define USART_CR1_OVER8 ((uint16_t)0x8000)
7681 /****************** Bit definition for USART_CR2 register *******************/
7682 #define USART_CR2_ADD ((uint16_t)0x000F)
7683 #define USART_CR2_LBDL ((uint16_t)0x0020)
7684 #define USART_CR2_LBDIE ((uint16_t)0x0040)
7685 #define USART_CR2_LBCL ((uint16_t)0x0100)
7686 #define USART_CR2_CPHA ((uint16_t)0x0200)
7687 #define USART_CR2_CPOL ((uint16_t)0x0400)
7688 #define USART_CR2_CLKEN ((uint16_t)0x0800)
7690 #define USART_CR2_STOP ((uint16_t)0x3000)
7691 #define USART_CR2_STOP_0 ((uint16_t)0x1000)
7692 #define USART_CR2_STOP_1 ((uint16_t)0x2000)
7694 #define USART_CR2_LINEN ((uint16_t)0x4000)
7696 /****************** Bit definition for USART_CR3 register *******************/
7697 #define USART_CR3_EIE ((uint16_t)0x0001)
7698 #define USART_CR3_IREN ((uint16_t)0x0002)
7699 #define USART_CR3_IRLP ((uint16_t)0x0004)
7700 #define USART_CR3_HDSEL ((uint16_t)0x0008)
7701 #define USART_CR3_NACK ((uint16_t)0x0010)
7702 #define USART_CR3_SCEN ((uint16_t)0x0020)
7703 #define USART_CR3_DMAR ((uint16_t)0x0040)
7704 #define USART_CR3_DMAT ((uint16_t)0x0080)
7705 #define USART_CR3_RTSE ((uint16_t)0x0100)
7706 #define USART_CR3_CTSE ((uint16_t)0x0200)
7707 #define USART_CR3_CTSIE ((uint16_t)0x0400)
7708 #define USART_CR3_ONEBIT ((uint16_t)0x0800)
7710 /****************** Bit definition for USART_GTPR register ******************/
7711 #define USART_GTPR_PSC ((uint16_t)0x00FF)
7712 #define USART_GTPR_PSC_0 ((uint16_t)0x0001)
7713 #define USART_GTPR_PSC_1 ((uint16_t)0x0002)
7714 #define USART_GTPR_PSC_2 ((uint16_t)0x0004)
7715 #define USART_GTPR_PSC_3 ((uint16_t)0x0008)
7716 #define USART_GTPR_PSC_4 ((uint16_t)0x0010)
7717 #define USART_GTPR_PSC_5 ((uint16_t)0x0020)
7718 #define USART_GTPR_PSC_6 ((uint16_t)0x0040)
7719 #define USART_GTPR_PSC_7 ((uint16_t)0x0080)
7721 #define USART_GTPR_GT ((uint16_t)0xFF00)
7723 /******************************************************************************/
7724 /* */
7725 /* Debug MCU */
7726 /* */
7727 /******************************************************************************/
7728 
7729 /**************** Bit definition for DBGMCU_IDCODE register *****************/
7730 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
7732 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
7733 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000)
7734 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000)
7735 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000)
7736 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000)
7737 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000)
7738 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000)
7739 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000)
7740 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000)
7741 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000)
7742 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000)
7743 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000)
7744 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000)
7745 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000)
7746 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000)
7747 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000)
7748 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000)
7750 /****************** Bit definition for DBGMCU_CR register *******************/
7751 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
7752 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
7753 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
7754 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
7756 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
7757 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)
7758 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)
7760 #define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100)
7761 #define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200)
7762 #define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400)
7763 #define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800)
7764 #define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000)
7765 #define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000)
7766 #define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000)
7767 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
7768 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
7769 #define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000)
7770 #define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000)
7771 #define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000)
7772 #define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000)
7773 #define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000)
7774 #define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000)
7775 #define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000)
7776 #define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000)
7777 #define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000)
7778 #define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000)
7779 #define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000)
7780 #define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000)
7781 #define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000)
7782 #define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000)
7784 /******************************************************************************/
7785 /* */
7786 /* FLASH and Option Bytes Registers */
7787 /* */
7788 /******************************************************************************/
7789 
7790 /******************* Bit definition for FLASH_ACR register ******************/
7791 #define FLASH_ACR_LATENCY ((uint8_t)0x03)
7792 #define FLASH_ACR_LATENCY_0 ((uint8_t)0x00)
7793 #define FLASH_ACR_LATENCY_1 ((uint8_t)0x01)
7794 #define FLASH_ACR_LATENCY_2 ((uint8_t)0x02)
7796 #define FLASH_ACR_HLFCYA ((uint8_t)0x08)
7797 #define FLASH_ACR_PRFTBE ((uint8_t)0x10)
7798 #define FLASH_ACR_PRFTBS ((uint8_t)0x20)
7800 /****************** Bit definition for FLASH_KEYR register ******************/
7801 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF)
7803 /***************** Bit definition for FLASH_OPTKEYR register ****************/
7804 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF)
7806 /****************** Bit definition for FLASH_SR register *******************/
7807 #define FLASH_SR_BSY ((uint8_t)0x01)
7808 #define FLASH_SR_PGERR ((uint8_t)0x04)
7809 #define FLASH_SR_WRPRTERR ((uint8_t)0x10)
7810 #define FLASH_SR_EOP ((uint8_t)0x20)
7812 /******************* Bit definition for FLASH_CR register *******************/
7813 #define FLASH_CR_PG ((uint16_t)0x0001)
7814 #define FLASH_CR_PER ((uint16_t)0x0002)
7815 #define FLASH_CR_MER ((uint16_t)0x0004)
7816 #define FLASH_CR_OPTPG ((uint16_t)0x0010)
7817 #define FLASH_CR_OPTER ((uint16_t)0x0020)
7818 #define FLASH_CR_STRT ((uint16_t)0x0040)
7819 #define FLASH_CR_LOCK ((uint16_t)0x0080)
7820 #define FLASH_CR_OPTWRE ((uint16_t)0x0200)
7821 #define FLASH_CR_ERRIE ((uint16_t)0x0400)
7822 #define FLASH_CR_EOPIE ((uint16_t)0x1000)
7824 /******************* Bit definition for FLASH_AR register *******************/
7825 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF)
7827 /****************** Bit definition for FLASH_OBR register *******************/
7828 #define FLASH_OBR_OPTERR ((uint16_t)0x0001)
7829 #define FLASH_OBR_RDPRT ((uint16_t)0x0002)
7831 #define FLASH_OBR_USER ((uint16_t)0x03FC)
7832 #define FLASH_OBR_WDG_SW ((uint16_t)0x0004)
7833 #define FLASH_OBR_nRST_STOP ((uint16_t)0x0008)
7834 #define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010)
7835 #define FLASH_OBR_BFB2 ((uint16_t)0x0020)
7837 /****************** Bit definition for FLASH_WRPR register ******************/
7838 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF)
7840 /*----------------------------------------------------------------------------*/
7841 
7842 /****************** Bit definition for FLASH_RDP register *******************/
7843 #define FLASH_RDP_RDP ((uint32_t)0x000000FF)
7844 #define FLASH_RDP_nRDP ((uint32_t)0x0000FF00)
7846 /****************** Bit definition for FLASH_USER register ******************/
7847 #define FLASH_USER_USER ((uint32_t)0x00FF0000)
7848 #define FLASH_USER_nUSER ((uint32_t)0xFF000000)
7850 /****************** Bit definition for FLASH_Data0 register *****************/
7851 #define FLASH_Data0_Data0 ((uint32_t)0x000000FF)
7852 #define FLASH_Data0_nData0 ((uint32_t)0x0000FF00)
7854 /****************** Bit definition for FLASH_Data1 register *****************/
7855 #define FLASH_Data1_Data1 ((uint32_t)0x00FF0000)
7856 #define FLASH_Data1_nData1 ((uint32_t)0xFF000000)
7858 /****************** Bit definition for FLASH_WRP0 register ******************/
7859 #define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF)
7860 #define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00)
7862 /****************** Bit definition for FLASH_WRP1 register ******************/
7863 #define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000)
7864 #define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000)
7866 /****************** Bit definition for FLASH_WRP2 register ******************/
7867 #define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF)
7868 #define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00)
7870 /****************** Bit definition for FLASH_WRP3 register ******************/
7871 #define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000)
7872 #define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000)
7874 #ifdef STM32F10X_CL
7875 /******************************************************************************/
7876 /* Ethernet MAC Registers bits definitions */
7877 /******************************************************************************/
7878 /* Bit definition for Ethernet MAC Control Register register */
7879 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
7880 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
7881 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
7882  #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
7883  #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
7884  #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
7885  #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
7886  #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
7887  #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
7888  #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
7889  #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
7890 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
7891 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
7892 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
7893 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
7894 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
7895 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
7896 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
7897 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
7898 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
7899  a transmission attempt during retries after a collision: 0 =< r <2^k */
7900  #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
7901  #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
7902  #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
7903  #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
7904 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
7905 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
7906 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
7907 
7908 /* Bit definition for Ethernet MAC Frame Filter Register */
7909 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
7910 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
7911 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
7912 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
7913 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
7914  #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
7915  #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
7916  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
7917 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
7918 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
7919 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
7920 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
7921 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
7922 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
7923 
7924 /* Bit definition for Ethernet MAC Hash Table High Register */
7925 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
7926 
7927 /* Bit definition for Ethernet MAC Hash Table Low Register */
7928 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
7929 
7930 /* Bit definition for Ethernet MAC MII Address Register */
7931 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
7932 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
7933 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
7934  #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
7935  #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
7936  #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
7937 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
7938 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
7939 
7940 /* Bit definition for Ethernet MAC MII Data Register */
7941 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
7942 
7943 /* Bit definition for Ethernet MAC Flow Control Register */
7944 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
7945 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
7946 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
7947  #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
7948  #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
7949  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
7950  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
7951 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
7952 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
7953 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
7954 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
7955 
7956 /* Bit definition for Ethernet MAC VLAN Tag Register */
7957 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
7958 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
7959 
7960 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
7961 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
7962 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
7963  Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
7964 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
7965  Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
7966  Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
7967  Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
7968  Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
7969  RSVD - Filter1 Command - RSVD - Filter0 Command
7970  Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
7971  Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
7972  Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
7973 
7974 /* Bit definition for Ethernet MAC PMT Control and Status Register */
7975 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
7976 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
7977 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
7978 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
7979 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
7980 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
7981 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
7982 
7983 /* Bit definition for Ethernet MAC Status Register */
7984 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
7985 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
7986 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
7987 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
7988 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
7989 
7990 /* Bit definition for Ethernet MAC Interrupt Mask Register */
7991 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
7992 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
7993 
7994 /* Bit definition for Ethernet MAC Address0 High Register */
7995 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
7996 
7997 /* Bit definition for Ethernet MAC Address0 Low Register */
7998 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
7999 
8000 /* Bit definition for Ethernet MAC Address1 High Register */
8001 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
8002 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
8003 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
8004  #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
8005  #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
8006  #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
8007  #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
8008  #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
8009  #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
8010 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
8011 
8012 /* Bit definition for Ethernet MAC Address1 Low Register */
8013 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
8014 
8015 /* Bit definition for Ethernet MAC Address2 High Register */
8016 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
8017 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
8018 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
8019  #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
8020  #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
8021  #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
8022  #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
8023  #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
8024  #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
8025 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
8026 
8027 /* Bit definition for Ethernet MAC Address2 Low Register */
8028 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
8029 
8030 /* Bit definition for Ethernet MAC Address3 High Register */
8031 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
8032 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
8033 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
8034  #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
8035  #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
8036  #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
8037  #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
8038  #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
8039  #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
8040 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
8041 
8042 /* Bit definition for Ethernet MAC Address3 Low Register */
8043 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
8044 
8045 /******************************************************************************/
8046 /* Ethernet MMC Registers bits definition */
8047 /******************************************************************************/
8048 
8049 /* Bit definition for Ethernet MMC Contol Register */
8050 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
8051 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
8052 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
8053 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
8054 
8055 /* Bit definition for Ethernet MMC Receive Interrupt Register */
8056 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
8057 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
8058 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
8059 
8060 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
8061 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
8062 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
8063 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
8064 
8065 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
8066 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
8067 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
8068 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
8069 
8070 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
8071 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
8072 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
8073 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
8074 
8075 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
8076 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
8077 
8078 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
8079 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
8080 
8081 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
8082 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
8083 
8084 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
8085 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
8086 
8087 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
8088 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
8089 
8090 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
8091 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
8092 
8093 /******************************************************************************/
8094 /* Ethernet PTP Registers bits definition */
8095 /******************************************************************************/
8096 
8097 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
8098 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
8099 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
8100 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
8101 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
8102 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
8103 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
8104 
8105 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
8106 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
8107 
8108 /* Bit definition for Ethernet PTP Time Stamp High Register */
8109 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
8110 
8111 /* Bit definition for Ethernet PTP Time Stamp Low Register */
8112 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
8113 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
8114 
8115 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
8116 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
8117 
8118 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
8119 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
8120 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
8121 
8122 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
8123 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
8124 
8125 /* Bit definition for Ethernet PTP Target Time High Register */
8126 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
8127 
8128 /* Bit definition for Ethernet PTP Target Time Low Register */
8129 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
8130 
8131 /******************************************************************************/
8132 /* Ethernet DMA Registers bits definition */
8133 /******************************************************************************/
8134 
8135 /* Bit definition for Ethernet DMA Bus Mode Register */
8136 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
8137 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
8138 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
8139 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
8140  #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
8141  #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
8142  #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8143  #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8144  #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8145  #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8146  #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8147  #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8148  #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8149  #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8150  #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
8151  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
8152 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
8153 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
8154  #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
8155  #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
8156  #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
8157  #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
8158 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
8159  #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
8160  #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
8161  #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
8162  #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
8163  #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
8164  #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
8165  #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
8166  #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
8167  #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
8168  #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
8169  #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
8170  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
8171 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
8172 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
8173 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
8174 
8175 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
8176 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
8177 
8178 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
8179 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
8180 
8181 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
8182 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
8183 
8184 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
8185 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
8186 
8187 /* Bit definition for Ethernet DMA Status Register */
8188 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
8189 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
8190 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
8191 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
8192  /* combination with EBS[2:0] for GetFlagStatus function */
8193  #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
8194  #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
8195  #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
8196 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
8197  #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
8198  #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
8199  #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
8200  #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
8201  #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
8202  #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
8203 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
8204  #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
8205  #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
8206  #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
8207  #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
8208  #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
8209  #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
8210 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
8211 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
8212 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
8213 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
8214 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
8215 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
8216 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
8217 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
8218 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
8219 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
8220 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
8221 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
8222 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
8223 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
8224 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
8225 
8226 /* Bit definition for Ethernet DMA Operation Mode Register */
8227 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
8228 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
8229 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
8230 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
8231 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
8232 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
8233  #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
8234  #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
8235  #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
8236  #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
8237  #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
8238  #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
8239  #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
8240  #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
8241 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
8242 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
8243 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
8244 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
8245  #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
8246  #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
8247  #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
8248  #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
8249 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
8250 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
8251 
8252 /* Bit definition for Ethernet DMA Interrupt Enable Register */
8253 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
8254 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
8255 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
8256 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
8257 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
8258 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
8259 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
8260 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
8261 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
8262 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
8263 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
8264 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
8265 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
8266 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
8267 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
8268 
8269 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
8270 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
8271 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
8272 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
8273 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
8274 
8275 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
8276 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
8277 
8278 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
8279 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
8280 
8281 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
8282 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
8283 
8284 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
8285 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
8286 #endif /* STM32F10X_CL */
8287 
8296 #ifdef USE_STDPERIPH_DRIVER
8297  #include "stm32f10x_conf.h"
8298 #endif
8299 
8304 #define SET_BIT(REG, BIT) ((REG) |= (BIT))
8305 
8306 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
8307 
8308 #define READ_BIT(REG, BIT) ((REG) & (BIT))
8309 
8310 #define CLEAR_REG(REG) ((REG) = (0x0))
8311 
8312 #define WRITE_REG(REG, VAL) ((REG) = (VAL))
8313 
8314 #define READ_REG(REG) ((REG))
8315 
8316 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
8317 
8322 #ifdef __cplusplus
8323 }
8324 #endif
8325 
8326 #endif /* __STM32F10x_H */
8327 
8336 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
BKP_TypeDef::DR23
__IO uint16_t DR23
Definition: stm32f10x.h:623
RTC_TypeDef::RESERVED9
uint16_t RESERVED9
Definition: stm32f10x.h:1125
BKP_TypeDef::RESERVED33
uint16_t RESERVED33
Definition: stm32f10x.h:638
FlagStatus
FlagStatus
Definition: stm32f10x.h:519
SVCall_IRQn
Definition: stm32f10x.h:174
CRC_TypeDef
CRC calculation unit.
Definition: stm32f4xx.h:841
BKP_TypeDef::RESERVED16
uint16_t RESERVED16
Definition: stm32f10x.h:604
NonMaskableInt_IRQn
Definition: stm32f10x.h:170
BKP_TypeDef::RESERVED19
uint16_t RESERVED19
Definition: stm32f10x.h:610
SysTick_IRQn
Definition: stm32f10x.h:177
PVD_IRQn
Definition: stm32f10x.h:181
RTC_TypeDef::RESERVED7
uint16_t RESERVED7
Definition: stm32f10x.h:1121
vsc8
__I int8_t vsc8
Definition: stm32f10x.h:501
BKP_TypeDef::RESERVED20
uint16_t RESERVED20
Definition: stm32f10x.h:612
TIM_TypeDef::RESERVED18
uint16_t RESERVED18
Definition: stm32f10x.h:1225
BKP_TypeDef::DR34
__IO uint16_t DR34
Definition: stm32f10x.h:645
BKP_TypeDef::DR41
__IO uint16_t DR41
Definition: stm32f10x.h:659
BKP_TypeDef::DR32
__IO uint16_t DR32
Definition: stm32f10x.h:641
RTC_TypeDef::ALRH
__IO uint16_t ALRH
Definition: stm32f10x.h:1122
TIM_TypeDef::RESERVED15
uint16_t RESERVED15
Definition: stm32f10x.h:1219
BKP_TypeDef::RESERVED38
uint16_t RESERVED38
Definition: stm32f10x.h:648
BKP_TypeDef::RESERVED26
uint16_t RESERVED26
Definition: stm32f10x.h:624
FunctionalState
FunctionalState
Definition: stm32f10x.h:521
BKP_TypeDef::DR39
__IO uint16_t DR39
Definition: stm32f10x.h:655
BKP_TypeDef::DR3
__IO uint16_t DR3
Definition: stm32f10x.h:577
BKP_TypeDef::RESERVED28
uint16_t RESERVED28
Definition: stm32f10x.h:628
BKP_TypeDef
Backup Registers.
Definition: stm32f10x.h:570
SUCCESS
Definition: stm32f10x.h:524
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f4xx.h:1710
system_stm32f10x.h
CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
EXTI2_IRQn
Definition: stm32f10x.h:188
BKP_TypeDef::DR42
__IO uint16_t DR42
Definition: stm32f10x.h:661
uc8
const uint8_t uc8
Definition: stm32f10x.h:509
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f4xx.h:725
BKP_TypeDef::RESERVED34
uint16_t RESERVED34
Definition: stm32f10x.h:640
BKP_TypeDef::DR21
__IO uint16_t DR21
Definition: stm32f10x.h:619
RTC_TypeDef::CRH
__IO uint16_t CRH
Definition: stm32f10x.h:1106
BKP_TypeDef::DR35
__IO uint16_t DR35
Definition: stm32f10x.h:647
RTC_TypeDef::CNTL
__IO uint16_t CNTL
Definition: stm32f10x.h:1120
BKP_TypeDef::RESERVED9
uint16_t RESERVED9
Definition: stm32f10x.h:590
RTC_TypeDef::CRL
__IO uint16_t CRL
Definition: stm32f10x.h:1108
GPIO_TypeDef::CRL
__IO uint32_t CRL
Definition: stm32f10x.h:1003
FLASH_TypeDef
FLASH Registers.
Definition: stm32f4xx.h:1131
RESET
Definition: stm32f10x.h:519
IRQn_Type
enum IRQn IRQn_Type
STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_sect...
BKP_TypeDef::DR13
__IO uint16_t DR13
Definition: stm32f10x.h:603
BKP_TypeDef::RESERVED10
uint16_t RESERVED10
Definition: stm32f10x.h:592
vs16
__IO int16_t vs16
Definition: stm32f10x.h:496
BKP_TypeDef::DR25
__IO uint16_t DR25
Definition: stm32f10x.h:627
BKP_TypeDef::RESERVED39
uint16_t RESERVED39
Definition: stm32f10x.h:650
FLASH_TypeDef::WRPR
__IO uint32_t WRPR
Definition: stm32f10x.h:911
FLASH_TypeDef::OBR
__IO uint32_t OBR
Definition: stm32f10x.h:910
BKP_TypeDef::RESERVED30
uint16_t RESERVED30
Definition: stm32f10x.h:632
vu32
__IO uint32_t vu32
Definition: stm32f10x.h:511
DMA1_Channel4_IRQn
Definition: stm32f10x.h:194
uc32
const uint32_t uc32
Definition: stm32f10x.h:507
TIM_TypeDef::CNT
__IO uint16_t CNT
Definition: stm32f10x.h:1206
BKP_TypeDef::DR9
__IO uint16_t DR9
Definition: stm32f10x.h:589
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f4xx.h:774
BKP_TypeDef::DR40
__IO uint16_t DR40
Definition: stm32f10x.h:657
OB_TypeDef::WRP0
__IO uint16_t WRP0
Definition: stm32f10x.h:932
AFIO_TypeDef
Alternate Function I/O.
Definition: stm32f10x.h:1016
FSMC_Bank4_TypeDef
Flexible Static Memory Controller Bank4.
Definition: stm32f10x.h:988
BKP_TypeDef::DR22
__IO uint16_t DR22
Definition: stm32f10x.h:621
GPIO_TypeDef::CRH
__IO uint32_t CRH
Definition: stm32f10x.h:1004
BKP_TypeDef::RESERVED29
uint16_t RESERVED29
Definition: stm32f10x.h:630
EXTI3_IRQn
Definition: stm32f10x.h:189
MemoryManagement_IRQn
Definition: stm32f10x.h:171
BKP_TypeDef::RESERVED25
uint16_t RESERVED25
Definition: stm32f10x.h:622
BKP_TypeDef::RESERVED14
uint16_t RESERVED14
Definition: stm32f10x.h:600
CEC_TypeDef::PRES
__IO uint32_t PRES
Definition: stm32f10x.h:740
RTC_TypeDef
Real-Time Clock.
Definition: stm32f4xx.h:1482
TIM_TypeDef::CCR2
__IO uint16_t CCR2
Definition: stm32f10x.h:1216
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f4xx.h:854
BKP_TypeDef::DR15
__IO uint16_t DR15
Definition: stm32f10x.h:607
BKP_TypeDef::RESERVED23
uint16_t RESERVED23
Definition: stm32f10x.h:618
AFIO_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f10x.h:1021
RTC_TypeDef::RESERVED2
uint16_t RESERVED2
Definition: stm32f10x.h:1111
BKP_TypeDef::RESERVED22
uint16_t RESERVED22
Definition: stm32f10x.h:616
BKP_TypeDef::DR26
__IO uint16_t DR26
Definition: stm32f10x.h:629
BKP_TypeDef::RESERVED37
uint16_t RESERVED37
Definition: stm32f10x.h:646
OB_TypeDef::WRP1
__IO uint16_t WRP1
Definition: stm32f10x.h:933
BKP_TypeDef::RESERVED45
uint16_t RESERVED45
Definition: stm32f10x.h:662
CEC_TypeDef::ESR
__IO uint32_t ESR
Definition: stm32f10x.h:741
SDIO_TypeDef
SD host Interface.
Definition: stm32f4xx.h:1552
s16
int16_t s16
Definition: stm32f10x.h:488
BKP_TypeDef::RTCCR
__IO uint16_t RTCCR
Definition: stm32f10x.h:593
CEC_TypeDef::OAR
__IO uint32_t OAR
Definition: stm32f10x.h:739
RTC_TypeDef::RESERVED3
uint16_t RESERVED3
Definition: stm32f10x.h:1113
BKP_TypeDef::RESERVED11
uint16_t RESERVED11
Definition: stm32f10x.h:594
__I
#define __I
Definition: core_cm0.h:195
AFIO_TypeDef::EVCR
__IO uint32_t EVCR
Definition: stm32f10x.h:1018
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f4xx.h:1580
BKP_TypeDef::RESERVED2
uint16_t RESERVED2
Definition: stm32f10x.h:576
FLASH_TypeDef::RESERVED
__IO uint32_t RESERVED
Definition: stm32f10x.h:909
OB_TypeDef::Data0
__IO uint16_t Data0
Definition: stm32f10x.h:930
TIM_TypeDef::CCR4
__IO uint16_t CCR4
Definition: stm32f10x.h:1220
BKP_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32f10x.h:574
BKP_TypeDef::DR8
__IO uint16_t DR8
Definition: stm32f10x.h:587
BKP_TypeDef::DR31
__IO uint16_t DR31
Definition: stm32f10x.h:639
FSMC_Bank1_TypeDef
Flexible Static Memory Controller.
Definition: stm32f10x.h:942
TIM_TypeDef::RESERVED19
uint16_t RESERVED19
Definition: stm32f10x.h:1227
EXTI4_IRQn
Definition: stm32f10x.h:190
vuc8
__I uint8_t vuc8
Definition: stm32f10x.h:517
BKP_TypeDef::RESERVED15
uint16_t RESERVED15
Definition: stm32f10x.h:602
BKP_TypeDef::DR29
__IO uint16_t DR29
Definition: stm32f10x.h:635
FSMC_Bank4_TypeDef::PIO4
__IO uint32_t PIO4
Definition: stm32f10x.h:994
DMA_Channel_TypeDef::CMAR
__IO uint32_t CMAR
Definition: stm32f10x.h:803
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f4xx.h:1117
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f4xx.h:876
FSMC_Bank2_TypeDef
Flexible Static Memory Controller Bank2.
Definition: stm32f10x.h:960
BKP_TypeDef::DR5
__IO uint16_t DR5
Definition: stm32f10x.h:581
WWDG_IRQn
Definition: stm32f10x.h:180
SET
Definition: stm32f10x.h:519
FSMC_Bank2_TypeDef::PMEM2
__IO uint32_t PMEM2
Definition: stm32f10x.h:964
BKP_TypeDef::DR20
__IO uint16_t DR20
Definition: stm32f10x.h:617
FSMC_Bank3_TypeDef
Flexible Static Memory Controller Bank3.
Definition: stm32f10x.h:974
BKP_TypeDef::DR38
__IO uint16_t DR38
Definition: stm32f10x.h:653
RTC_TypeDef::ALRL
__IO uint16_t ALRL
Definition: stm32f10x.h:1124
ITStatus
enum FlagStatus ITStatus
FSMC_Bank2_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f10x.h:966
TIM_TypeDef::RESERVED17
uint16_t RESERVED17
Definition: stm32f10x.h:1223
FLASH_IRQn
Definition: stm32f10x.h:184
BKP_TypeDef::DR7
__IO uint16_t DR7
Definition: stm32f10x.h:585
CEC_TypeDef
Consumer Electronics Control (CEC)
Definition: stm32f10x.h:736
BKP_TypeDef::RESERVED18
uint16_t RESERVED18
Definition: stm32f10x.h:608
BKP_TypeDef::DR24
__IO uint16_t DR24
Definition: stm32f10x.h:625
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f4xx.h:1281
BKP_TypeDef::RESERVED36
uint16_t RESERVED36
Definition: stm32f10x.h:644
TIM_TypeDef::CCR1
__IO uint16_t CCR1
Definition: stm32f10x.h:1214
__IO
#define __IO
Definition: core_cm0.h:198
vsc32
__I int32_t vsc32
Definition: stm32f10x.h:499
FSMC_Bank4_TypeDef::PATT4
__IO uint32_t PATT4
Definition: stm32f10x.h:993
vuc16
__I uint16_t vuc16
Definition: stm32f10x.h:516
vu8
__IO uint8_t vu8
Definition: stm32f10x.h:513
BKP_TypeDef::DR19
__IO uint16_t DR19
Definition: stm32f10x.h:615
stm32f10x_conf.h
AFIO_TypeDef::MAPR2
__IO uint32_t MAPR2
Definition: stm32f10x.h:1022
BKP_TypeDef::DR28
__IO uint16_t DR28
Definition: stm32f10x.h:633
ETH_TypeDef
Ethernet MAC.
Definition: stm32f4xx.h:1043
sc16
const int16_t sc16
Definition: stm32f10x.h:492
EXTI0_IRQn
Definition: stm32f10x.h:186
BKP_TypeDef::RESERVED27
uint16_t RESERVED27
Definition: stm32f10x.h:626
FSMC_Bank4_TypeDef::SR4
__IO uint32_t SR4
Definition: stm32f10x.h:991
BKP_TypeDef::DR14
__IO uint16_t DR14
Definition: stm32f10x.h:605
FSMC_Bank4_TypeDef::PMEM4
__IO uint32_t PMEM4
Definition: stm32f10x.h:992
OB_TypeDef::Data1
__IO uint16_t Data1
Definition: stm32f10x.h:931
DMA1_Channel7_IRQn
Definition: stm32f10x.h:197
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f4xx.h:1369
RCC_TypeDef::AHBENR
__IO uint32_t AHBENR
Definition: stm32f10x.h:1083
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f4xx.h:1732
sc8
const int8_t sc8
Definition: stm32f10x.h:493
FSMC_Bank3_TypeDef::PATT3
__IO uint32_t PATT3
Definition: stm32f10x.h:979
BKP_TypeDef::RESERVED3
uint16_t RESERVED3
Definition: stm32f10x.h:578
CEC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32f10x.h:738
RTC_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32f10x.h:1109
RTC_TypeDef::RESERVED8
uint16_t RESERVED8
Definition: stm32f10x.h:1123
BKP_TypeDef::RESERVED44
uint16_t RESERVED44
Definition: stm32f10x.h:660
BKP_TypeDef::DR10
__IO uint16_t DR10
Definition: stm32f10x.h:591
BKP_TypeDef::RESERVED40
uint16_t RESERVED40
Definition: stm32f10x.h:652
DebugMonitor_IRQn
Definition: stm32f10x.h:175
BKP_TypeDef::DR16
__IO uint16_t DR16
Definition: stm32f10x.h:609
uc16
const uint16_t uc16
Definition: stm32f10x.h:508
FLASH_TypeDef::AR
__IO uint32_t AR
Definition: stm32f10x.h:908
TIM_TypeDef::CCR3
__IO uint16_t CCR3
Definition: stm32f10x.h:1218
ErrorStatus
ErrorStatus
Definition: stm32f10x.h:524
s32
int32_t s32
Definition: stm32f10x.h:487
BKP_TypeDef::RESERVED12
uint16_t RESERVED12
Definition: stm32f10x.h:596
DMA1_Channel5_IRQn
Definition: stm32f10x.h:195
ENABLE
Definition: stm32f10x.h:521
BKP_TypeDef::CR
__IO uint16_t CR
Definition: stm32f10x.h:595
RTC_TypeDef::CNTH
__IO uint16_t CNTH
Definition: stm32f10x.h:1118
BKP_TypeDef::DR12
__IO uint16_t DR12
Definition: stm32f10x.h:601
BusFault_IRQn
Definition: stm32f10x.h:172
BKP_TypeDef::RESERVED32
uint16_t RESERVED32
Definition: stm32f10x.h:636
DMA1_Channel2_IRQn
Definition: stm32f10x.h:192
PendSV_IRQn
Definition: stm32f10x.h:176
TIM_TypeDef
TIM.
Definition: stm32f4xx.h:1666
RTC_TypeDef::DIVH
__IO uint16_t DIVH
Definition: stm32f10x.h:1114
BKP_TypeDef::DR4
__IO uint16_t DR4
Definition: stm32f10x.h:579
DMA_TypeDef
Definition: stm32f4xx.h:917
BKP_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f10x.h:572
OB_TypeDef::RDP
__IO uint16_t RDP
Definition: stm32f10x.h:928
DISABLE
Definition: stm32f10x.h:521
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f4xx.h:786
BKP_TypeDef::DR17
__IO uint16_t DR17
Definition: stm32f10x.h:611
vs32
__IO int32_t vs32
Definition: stm32f10x.h:495
PWR_TypeDef
Power Control.
Definition: stm32f4xx.h:1429
FSMC_Bank3_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f10x.h:980
OB_TypeDef::WRP2
__IO uint16_t WRP2
Definition: stm32f10x.h:934
FSMC_Bank3_TypeDef::SR3
__IO uint32_t SR3
Definition: stm32f10x.h:977
u16
uint16_t u16
Definition: stm32f10x.h:504
FSMC_Bank2_TypeDef::SR2
__IO uint32_t SR2
Definition: stm32f10x.h:963
BKP_TypeDef::RESERVED7
uint16_t RESERVED7
Definition: stm32f10x.h:586
UsageFault_IRQn
Definition: stm32f10x.h:173
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f4xx.h:1439
FSMC_Bank2_TypeDef::PCR2
__IO uint32_t PCR2
Definition: stm32f10x.h:962
AFIO_TypeDef::MAPR
__IO uint32_t MAPR
Definition: stm32f10x.h:1019
RTC_TypeDef::RESERVED6
uint16_t RESERVED6
Definition: stm32f10x.h:1119
FSMC_Bank2_TypeDef::PATT2
__IO uint32_t PATT2
Definition: stm32f10x.h:965
DMA_Channel_TypeDef
DMA Controller.
Definition: stm32f10x.h:798
RTC_TypeDef::RESERVED5
uint16_t RESERVED5
Definition: stm32f10x.h:1117
OB_TypeDef::USER
__IO uint16_t USER
Definition: stm32f10x.h:929
BKP_TypeDef::RESERVED17
uint16_t RESERVED17
Definition: stm32f10x.h:606
ERROR
Definition: stm32f10x.h:524
BKP_TypeDef::DR30
__IO uint16_t DR30
Definition: stm32f10x.h:637
CAN_TypeDef
Controller Area Network.
Definition: stm32f4xx.h:796
BKP_TypeDef::DR2
__IO uint16_t DR2
Definition: stm32f10x.h:575
TIM_TypeDef::ARR
__IO uint16_t ARR
Definition: stm32f10x.h:1210
DMA_Channel_TypeDef::CPAR
__IO uint32_t CPAR
Definition: stm32f10x.h:802
BKP_TypeDef::RESERVED43
uint16_t RESERVED43
Definition: stm32f10x.h:658
TIM_TypeDef::RESERVED16
uint16_t RESERVED16
Definition: stm32f10x.h:1221
RCC_IRQn
Definition: stm32f10x.h:185
RTC_TypeDef::PRLL
__IO uint16_t PRLL
Definition: stm32f10x.h:1112
CEC_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f10x.h:742
s8
int8_t s8
Definition: stm32f10x.h:489
FSMC_Bank3_TypeDef::PMEM3
__IO uint32_t PMEM3
Definition: stm32f10x.h:978
DMA_Channel_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32f10x.h:800
RTC_TypeDef::PRLH
__IO uint16_t PRLH
Definition: stm32f10x.h:1110
RTC_IRQn
Definition: stm32f10x.h:183
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f4xx.h:1320
BKP_TypeDef::RESERVED5
uint16_t RESERVED5
Definition: stm32f10x.h:582
EXTI1_IRQn
Definition: stm32f10x.h:187
u32
uint32_t u32
Definition: stm32f10x.h:503
BKP_TypeDef::DR37
__IO uint16_t DR37
Definition: stm32f10x.h:651
DMA_Channel_TypeDef::CNDTR
__IO uint32_t CNDTR
Definition: stm32f10x.h:801
BKP_TypeDef::DR6
__IO uint16_t DR6
Definition: stm32f10x.h:583
BKP_TypeDef::RESERVED31
uint16_t RESERVED31
Definition: stm32f10x.h:634
vuc32
__I uint32_t vuc32
Definition: stm32f10x.h:515
GPIO_TypeDef::BSRR
__IO uint32_t BSRR
Definition: stm32f10x.h:1007
RTC_TypeDef::RESERVED4
uint16_t RESERVED4
Definition: stm32f10x.h:1115
FSMC_Bank4_TypeDef::PCR4
__IO uint32_t PCR4
Definition: stm32f10x.h:990
DMA1_Channel3_IRQn
Definition: stm32f10x.h:193
BKP_TypeDef::DR1
__IO uint16_t DR1
Definition: stm32f10x.h:573
RTC_TypeDef::DIVL
__IO uint16_t DIVL
Definition: stm32f10x.h:1116
BKP_TypeDef::DR18
__IO uint16_t DR18
Definition: stm32f10x.h:613
GPIO_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32f10x.h:1008
vsc16
__I int16_t vsc16
Definition: stm32f10x.h:500
DMA_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f10x.h:808
BKP_TypeDef::RESERVED21
uint16_t RESERVED21
Definition: stm32f10x.h:614
BKP_TypeDef::RESERVED24
uint16_t RESERVED24
Definition: stm32f10x.h:620
BKP_TypeDef::RESERVED4
uint16_t RESERVED4
Definition: stm32f10x.h:580
RTC_TypeDef::RESERVED0
uint16_t RESERVED0
Definition: stm32f10x.h:1107
BKP_TypeDef::RESERVED35
uint16_t RESERVED35
Definition: stm32f10x.h:642
DMA1_Channel6_IRQn
Definition: stm32f10x.h:196
BKP_TypeDef::DR36
__IO uint16_t DR36
Definition: stm32f10x.h:649
vu16
__IO uint16_t vu16
Definition: stm32f10x.h:512
FSMC_Bank1E_TypeDef
Flexible Static Memory Controller Bank1E.
Definition: stm32f10x.h:951
OB_TypeDef::WRP3
__IO uint16_t WRP3
Definition: stm32f10x.h:935
BKP_TypeDef::RESERVED41
uint16_t RESERVED41
Definition: stm32f10x.h:654
DMA1_Channel1_IRQn
Definition: stm32f10x.h:191
BKP_TypeDef::CSR
__IO uint16_t CSR
Definition: stm32f10x.h:597
u8
uint8_t u8
Definition: stm32f10x.h:505
FSMC_Bank2_TypeDef::ECCR2
__IO uint32_t ECCR2
Definition: stm32f10x.h:967
BKP_TypeDef::RESERVED42
uint16_t RESERVED42
Definition: stm32f10x.h:656
OB_TypeDef
Option Bytes Registers.
Definition: stm32f10x.h:926
BKP_TypeDef::DR27
__IO uint16_t DR27
Definition: stm32f10x.h:631
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f4xx.h:762
BKP_TypeDef::RESERVED8
uint16_t RESERVED8
Definition: stm32f10x.h:588
DMA_TypeDef::IFCR
__IO uint32_t IFCR
Definition: stm32f10x.h:809
sc32
const int32_t sc32
Definition: stm32f10x.h:491
vs8
__IO int8_t vs8
Definition: stm32f10x.h:497
BKP_TypeDef::DR11
__IO uint16_t DR11
Definition: stm32f10x.h:599
CEC_TypeDef::RXD
__IO uint32_t RXD
Definition: stm32f10x.h:744
FSMC_Bank3_TypeDef::ECCR3
__IO uint32_t ECCR3
Definition: stm32f10x.h:981
CEC_TypeDef::TXD
__IO uint32_t TXD
Definition: stm32f10x.h:743
FSMC_Bank3_TypeDef::PCR3
__IO uint32_t PCR3
Definition: stm32f10x.h:976
BKP_TypeDef::RESERVED6
uint16_t RESERVED6
Definition: stm32f10x.h:584
BKP_TypeDef::DR33
__IO uint16_t DR33
Definition: stm32f10x.h:643
TAMPER_IRQn
Definition: stm32f10x.h:182

rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Wed Jul 3 2019 19:59:25