usart.c
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1 
34 /*
35  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
36  */
37 
38 #include "usart.h"
39 
41 
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45 
46 
66 /* The write protect key value. */
67 #ifndef US_WPMR_WPKEY_PASSWD
68 #define US_WPMR_WPKEY_PASSWD US_WPMR_WPKEY(0x555341U)
69 #endif
70 
71 #ifndef US_WPMR_WPKEY_PASSWD
72 # define US_WPMR_WPKEY_PASSWD US_WPMR_WPKEY(US_WPKEY_VALUE)
73 #endif
74 
75 /* The CD value scope programmed in MR register. */
76 #define MIN_CD_VALUE 0x01
77 #define MIN_CD_VALUE_SPI 0x04
78 #define MAX_CD_VALUE US_BRGR_CD_Msk
79 
80 /* The receiver sampling divide of baudrate clock. */
81 #define HIGH_FRQ_SAMPLE_DIV 16
82 #define LOW_FRQ_SAMPLE_DIV 8
83 
84 /* Max transmitter timeguard. */
85 #define MAX_TRAN_GUARD_TIME US_TTGR_TG_Msk
86 
87 /* The non-existent parity error number. */
88 #define USART_PARITY_ERROR 5
89 
90 /* ISO7816 protocol type. */
91 #define ISO7816_T_0 0
92 #define ISO7816_T_1 1
93 
111 uint32_t usart_set_async_baudrate(Usart *p_usart,
112  uint32_t baudrate, uint32_t ul_mck)
113 {
114  uint32_t over;
115  uint32_t cd_fp;
116  uint32_t cd;
117  uint32_t fp;
118 
119  /* Calculate the receiver sampling divide of baudrate clock. */
120  if (ul_mck >= HIGH_FRQ_SAMPLE_DIV * baudrate) {
121  over = HIGH_FRQ_SAMPLE_DIV;
122  } else {
123  over = LOW_FRQ_SAMPLE_DIV;
124  }
125 
126  /* Calculate clock divider according to the fraction calculated formula. */
127  cd_fp = (8 * ul_mck + (over * baudrate) / 2) / (over * baudrate);
128  cd = cd_fp >> 3;
129  fp = cd_fp & 0x07;
130  if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) {
131  return 1;
132  }
133 
134  /* Configure the OVER bit in MR register. */
135  if (over == 8) {
136  p_usart->US_MR |= US_MR_OVER;
137  }
138 
139  /* Configure the baudrate generate register. */
140  p_usart->US_BRGR = (cd << US_BRGR_CD_Pos) | (fp << US_BRGR_FP_Pos);
141 
142  return 0;
143 }
144 
159 static uint32_t usart_set_sync_master_baudrate(Usart *p_usart,
160  uint32_t baudrate, uint32_t ul_mck)
161 {
162  uint32_t cd;
163 
164  /* Calculate clock divider according to the formula in synchronous mode. */
165  cd = (ul_mck + baudrate / 2) / baudrate;
166 
167  if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) {
168  return 1;
169  }
170 
171  /* Configure the baudrate generate register. */
172  p_usart->US_BRGR = cd << US_BRGR_CD_Pos;
173 
174  p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) |
176  return 0;
177 }
178 
186 {
187  p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) |
189 }
190 
206 static uint32_t usart_set_spi_master_baudrate(Usart *p_usart,
207  uint32_t baudrate, uint32_t ul_mck)
208 {
209  uint32_t cd;
210 
211  /* Calculate the clock divider according to the formula in SPI mode. */
212  cd = (ul_mck + baudrate / 2) / baudrate;
213 
214  if (cd < MIN_CD_VALUE_SPI || cd > MAX_CD_VALUE) {
215  return 1;
216  }
217 
218  p_usart->US_BRGR = cd << US_BRGR_CD_Pos;
219 
220  return 0;
221 }
222 
229 static void usart_set_spi_slave_baudrate(Usart *p_usart)
230 {
231  p_usart->US_MR &= ~US_MR_USCLKS_Msk;
232  p_usart->US_MR |= US_MR_USCLKS_SCK;
233 }
234 
240 void usart_reset(Usart *p_usart)
241 {
242  /* Disable the Write Protect. */
244 
245  /* Reset registers that could cause unpredictable behavior after reset. */
246  p_usart->US_MR = 0;
247  p_usart->US_RTOR = 0;
248  p_usart->US_TTGR = 0;
249 
250  /* Disable TX and RX. */
251  usart_reset_tx(p_usart);
252  usart_reset_rx(p_usart);
253  /* Reset status bits. */
254  usart_reset_status(p_usart);
255  /* Turn off RTS and DTR if exist. */
256  usart_drive_RTS_pin_high(p_usart);
257 #if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E)
258  usart_drive_DTR_pin_high(p_usart);
259 #endif
260 }
261 
274 uint32_t usart_init_rs232(Usart *p_usart,
275  const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
276 {
277  static uint32_t ul_reg_val;
278 
279  /* Reset the USART and shut down TX and RX. */
280  usart_reset(p_usart);
281 
282  ul_reg_val = 0;
283  /* Check whether the input values are legal. */
284  if (!p_usart_opt || usart_set_async_baudrate(p_usart,
285  p_usart_opt->baudrate, ul_mck)) {
286  return 1;
287  }
288 
289  /* Configure the USART option. */
290  ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type |
291  p_usart_opt->channel_mode | p_usart_opt->stop_bits;
292 
293  /* Configure the USART mode as normal mode. */
294  ul_reg_val |= US_MR_USART_MODE_NORMAL;
295 
296  p_usart->US_MR |= ul_reg_val;
297 
298  return 0;
299 }
300 
314  const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
315 {
316  /* Initialize the USART as standard RS232. */
317  if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {
318  return 1;
319  }
320 
321  /* Set hardware handshaking mode. */
322  p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
324 
325  return 0;
326 }
327 
328 #if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E)
329 
342 uint32_t usart_init_modem(Usart *p_usart,
343  const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
344 {
345  /*
346  * SAM3S, SAM4S and SAM4E series support MODEM mode only on USART1,
347  * SAM3U and SAM4L series support MODEM mode only on USART0.
348  */
349 #if (SAM3S || SAM4S || SAM4E)
350 #ifdef USART1
351  if (p_usart != USART1) {
352  return 1;
353  }
354 #endif
355 #elif (SAM3U || SAM4L)
356  if (p_usart != USART0) {
357  return 1;
358  }
359 #endif
360 
361  /* Initialize the USART as standard RS232. */
362  if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {
363  return 1;
364  }
365 
366  /* Set MODEM mode. */
367  p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
369 
370  return 0;
371 }
372 #endif
373 
386 uint32_t usart_init_sync_master(Usart *p_usart,
387  const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
388 {
389  static uint32_t ul_reg_val;
390 
391  /* Reset the USART and shut down TX and RX. */
392  usart_reset(p_usart);
393 
394  ul_reg_val = 0;
395  /* Check whether the input values are legal. */
396  if (!p_usart_opt || usart_set_sync_master_baudrate(p_usart,
397  p_usart_opt->baudrate, ul_mck)) {
398  return 1;
399  }
400 
401  /* Configure the USART option. */
402  ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type |
403  p_usart_opt->channel_mode | p_usart_opt->stop_bits;
404 
405  /* Set normal mode and output clock as synchronous master. */
406  ul_reg_val |= US_MR_USART_MODE_NORMAL | US_MR_CLKO;
407  p_usart->US_MR |= ul_reg_val;
408 
409  return 0;
410 }
411 
423 uint32_t usart_init_sync_slave(Usart *p_usart,
424  const sam_usart_opt_t *p_usart_opt)
425 {
426  static uint32_t ul_reg_val;
427 
428  /* Reset the USART and shut down TX and RX. */
429  usart_reset(p_usart);
430 
431  ul_reg_val = 0;
433 
434  /* Check whether the input values are legal. */
435  if (!p_usart_opt) {
436  return 1;
437  }
438 
439  /* Configure the USART option. */
440  ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type |
441  p_usart_opt->channel_mode | p_usart_opt->stop_bits;
442 
443  /* Set normal mode. */
444  ul_reg_val |= US_MR_USART_MODE_NORMAL;
445  p_usart->US_MR |= ul_reg_val;
446 
447  return 0;
448 }
449 
462 uint32_t usart_init_rs485(Usart *p_usart,
463  const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
464 {
465  /* Initialize the USART as standard RS232. */
466  if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {
467  return 1;
468  }
469 
470  /* Set RS485 mode. */
471  p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
473 
474  return 0;
475 }
476 
477 #if (!SAMG55 && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70)
478 
490 uint32_t usart_init_irda(Usart *p_usart,
491  const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
492 {
493  /* Initialize the USART as standard RS232. */
494  if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {
495  return 1;
496  }
497 
498  /* Set IrDA filter. */
499  p_usart->US_IF = p_usart_opt->irda_filter;
500 
501  /* Set IrDA mode. */
502  p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
504 
505  return 0;
506 }
507 #endif
508 
509 #if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70)
510 
524 static uint32_t usart_set_iso7816_clock(Usart *p_usart,
525  uint32_t clock, uint32_t ul_mck)
526 {
527  uint32_t cd;
528 
529  /* Calculate clock divider according to the formula in ISO7816 mode. */
530  cd = (ul_mck + clock / 2) / clock;
531 
532  if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) {
533  return 1;
534  }
535 
536  p_usart->US_MR = (p_usart->US_MR & ~(US_MR_USCLKS_Msk | US_MR_SYNC |
538 
539  /* Configure the baudrate generate register. */
540  p_usart->US_BRGR = cd << US_BRGR_CD_Pos;
541 
542  return 0;
543 }
544 
557 uint32_t usart_init_iso7816(Usart *p_usart,
558  const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck)
559 {
560  static uint32_t ul_reg_val;
561 
562  /* Reset the USART and shut down TX and RX. */
563  usart_reset(p_usart);
564 
565  ul_reg_val = 0;
566 
567  /* Check whether the input values are legal. */
568  if (!p_usart_opt || ((p_usart_opt->parity_type != US_MR_PAR_EVEN) &&
569  (p_usart_opt->parity_type != US_MR_PAR_ODD))) {
570  return 1;
571  }
572 
573  if (p_usart_opt->protocol_type == ISO7816_T_0) {
575  (p_usart_opt->max_iterations << US_MR_MAX_ITERATION_Pos);
576 
577  if (p_usart_opt->bit_order) {
578  ul_reg_val |= US_MR_MSBF;
579  }
580  } else if (p_usart_opt->protocol_type == ISO7816_T_1) {
581  /*
582  * Only LSBF is used in the T=1 protocol, and max_iterations field
583  * is only used in T=0 mode.
584  */
585  if (p_usart_opt->bit_order || p_usart_opt->max_iterations) {
586  return 1;
587  }
588 
589  /* Set USART mode to ISO7816, T=1, and always uses 1 stop bit. */
591  } else {
592  return 1;
593  }
594 
595  /* Set up the baudrate. */
596  if (usart_set_iso7816_clock(p_usart, p_usart_opt->iso7816_hz, ul_mck)) {
597  return 1;
598  }
599 
600  /* Set FIDI register: bit rate = iso7816_hz / fidi_ratio. */
601  p_usart->US_FIDI = p_usart_opt->fidi_ratio;
602 
603  /* Set ISO7816 parity type in the MODE register. */
604  ul_reg_val |= p_usart_opt->parity_type;
605 
606  if (p_usart_opt->inhibit_nack) {
607  ul_reg_val |= US_MR_INACK;
608  }
609  if (p_usart_opt->dis_suc_nack) {
610  ul_reg_val |= US_MR_DSNACK;
611  }
612 
613  p_usart->US_MR |= ul_reg_val;
614 
615  return 0;
616 }
617 
624 {
625  p_usart->US_CR = US_CR_RSTIT;
626 }
627 
633 void usart_reset_nack(Usart *p_usart)
634 {
635  p_usart->US_CR = US_CR_RSTNACK;
636 }
637 
646 uint32_t usart_is_rx_buf_full(Usart *p_usart)
647 {
648  return (p_usart->US_CSR & US_CSR_RXBUFF) > 0;
649 }
650 
651 #if (!SAM4L)
652 
660 uint32_t usart_is_rx_buf_end(Usart *p_usart)
661 {
662  return (p_usart->US_CSR & US_CSR_ENDRX) > 0;
663 }
664 
673 uint32_t usart_is_tx_buf_end(Usart *p_usart)
674 {
675  return (p_usart->US_CSR & US_CSR_ENDTX) > 0;
676 }
677 
686 uint32_t usart_is_tx_buf_empty(Usart *p_usart)
687 {
688  return (p_usart->US_CSR & US_CSR_TXBUFE) > 0;
689 }
690 #endif
691 
699 uint8_t usart_get_error_number(Usart *p_usart)
700 {
701  return (p_usart->US_NER & US_NER_NB_ERRORS_Msk);
702 }
703 
704 #endif
705 
718 uint32_t usart_init_spi_master(Usart *p_usart,
719  const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck)
720 {
721  static uint32_t ul_reg_val;
722 
723  /* Reset the USART and shut down TX and RX. */
724  usart_reset(p_usart);
725 
726  ul_reg_val = 0;
727  /* Check whether the input values are legal. */
728  if (!p_usart_opt || (p_usart_opt->spi_mode > SPI_MODE_3) ||
729  usart_set_spi_master_baudrate(p_usart, p_usart_opt->baudrate,
730  ul_mck)) {
731  return 1;
732  }
733 
734  /* Configure the character length bit in MR register. */
735  ul_reg_val |= p_usart_opt->char_length;
736 
737  /* Set SPI master mode and channel mode. */
738  ul_reg_val |= US_MR_USART_MODE_SPI_MASTER | US_MR_CLKO |
739  p_usart_opt->channel_mode;
740 
741  switch (p_usart_opt->spi_mode) {
742  case SPI_MODE_0:
743  ul_reg_val |= US_MR_CPHA;
744  ul_reg_val &= ~US_MR_CPOL;
745  break;
746 
747  case SPI_MODE_1:
748  ul_reg_val &= ~US_MR_CPHA;
749  ul_reg_val &= ~US_MR_CPOL;
750  break;
751 
752  case SPI_MODE_2:
753  ul_reg_val |= US_MR_CPHA;
754  ul_reg_val |= US_MR_CPOL;
755  break;
756 
757  case SPI_MODE_3:
758  ul_reg_val &= ~US_MR_CPHA;
759  ul_reg_val |= US_MR_CPOL;
760  break;
761 
762  default:
763  break;
764  }
765 
766  p_usart->US_MR |= ul_reg_val;
767 
768  return 0;
769 }
770 
782 uint32_t usart_init_spi_slave(Usart *p_usart,
783  const usart_spi_opt_t *p_usart_opt)
784 {
785  static uint32_t ul_reg_val;
786 
787  /* Reset the USART and shut down TX and RX. */
788  usart_reset(p_usart);
789 
790  ul_reg_val = 0;
792 
793  /* Check whether the input values are legal. */
794  if (!p_usart_opt || p_usart_opt->spi_mode > SPI_MODE_3) {
795  return 1;
796  }
797 
798  /* Configure the character length bit in MR register. */
799  ul_reg_val |= p_usart_opt->char_length;
800 
801  /* Set SPI slave mode and channel mode. */
802  ul_reg_val |= US_MR_USART_MODE_SPI_SLAVE | p_usart_opt->channel_mode;
803 
804  switch (p_usart_opt->spi_mode) {
805  case SPI_MODE_0:
806  ul_reg_val |= US_MR_CPHA;
807  ul_reg_val &= ~US_MR_CPOL;
808  break;
809 
810  case SPI_MODE_1:
811  ul_reg_val &= ~US_MR_CPHA;
812  ul_reg_val &= ~US_MR_CPOL;
813  break;
814 
815  case SPI_MODE_2:
816  ul_reg_val |= US_MR_CPHA;
817  ul_reg_val |= US_MR_CPOL;
818  break;
819 
820  case SPI_MODE_3:
821  ul_reg_val |= US_MR_CPOL;
822  ul_reg_val &= ~US_MR_CPHA;
823  break;
824 
825  default:
826  break;
827  }
828 
829  p_usart->US_MR |= ul_reg_val;
830 
831  return 0;
832 }
833 
834 #if (SAM3XA || SAM4L || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
835 
848 uint32_t usart_init_lin_master(Usart *p_usart,uint32_t ul_baudrate,
849  uint32_t ul_mck)
850 {
851  /* Reset the USART and shut down TX and RX. */
852  usart_reset(p_usart);
853 
854  /* Set up the baudrate. */
855  if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) {
856  return 1;
857  }
858 
859  /* Set LIN master mode. */
860  p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
862 
863  usart_enable_rx(p_usart);
864  usart_enable_tx(p_usart);
865 
866  return 0;
867 }
868 
881 uint32_t usart_init_lin_slave(Usart *p_usart, uint32_t ul_baudrate,
882  uint32_t ul_mck)
883 {
884  /* Reset the USART and shut down TX and RX. */
885  usart_reset(p_usart);
886 
887  usart_enable_rx(p_usart);
888  usart_enable_tx(p_usart);
889 
890  /* Set LIN slave mode. */
891  p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
893 
894  /* Set up the baudrate. */
895  if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) {
896  return 1;
897  }
898 
899  return 0;
900 }
901 
907 void usart_lin_abort_tx(Usart *p_usart)
908 {
909  p_usart->US_CR = US_CR_LINABT;
910 }
911 
917 void usart_lin_send_wakeup_signal(Usart *p_usart)
918 {
919  p_usart->US_CR = US_CR_LINWKUP;
920 }
921 
929 void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action)
930 {
931  p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_NACT_Msk) |
932  (uc_action << US_LINMR_NACT_Pos);
933 }
934 
940 void usart_lin_disable_parity(Usart *p_usart)
941 {
942  p_usart->US_LINMR |= US_LINMR_PARDIS;
943 }
944 
950 void usart_lin_enable_parity(Usart *p_usart)
951 {
952  p_usart->US_LINMR &= ~US_LINMR_PARDIS;
953 }
954 
960 void usart_lin_disable_checksum(Usart *p_usart)
961 {
962  p_usart->US_LINMR |= US_LINMR_CHKDIS;
963 }
964 
970 void usart_lin_enable_checksum(Usart *p_usart)
971 {
972  p_usart->US_LINMR &= ~US_LINMR_CHKDIS;
973 }
974 
982 void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type)
983 {
984  p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_CHKTYP) |
985  (uc_type << 4);
986 }
987 
996 void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode)
997 {
998  p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLM) |
999  (uc_mode << 5);
1000 }
1001 
1007 void usart_lin_disable_frame_slot(Usart *p_usart)
1008 {
1009  p_usart->US_LINMR |= US_LINMR_FSDIS;
1010 }
1011 
1017 void usart_lin_enable_frame_slot(Usart *p_usart)
1018 {
1019  p_usart->US_LINMR &= ~US_LINMR_FSDIS;
1020 }
1021 
1029 void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type)
1030 {
1031  p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_WKUPTYP) |
1032  (uc_type << 7);
1033 }
1034 
1042 void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len)
1043 {
1044  p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLC_Msk) |
1045  ((uc_len - 1) << US_LINMR_DLC_Pos);
1046 }
1047 
1053 void usart_lin_disable_pdc_mode(Usart *p_usart)
1054 {
1055  p_usart->US_LINMR &= ~US_LINMR_PDCM;
1056 }
1057 
1063 void usart_lin_enable_pdc_mode(Usart *p_usart)
1064 {
1065  p_usart->US_LINMR |= US_LINMR_PDCM;
1066 }
1067 
1074 void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id)
1075 {
1076  p_usart->US_LINIR = (p_usart->US_LINIR & ~US_LINIR_IDCHR_Msk) |
1077  US_LINIR_IDCHR(uc_id);
1078 }
1079 
1088 uint8_t usart_lin_read_identifier(Usart *p_usart)
1089 {
1090  return (p_usart->US_LINIR & US_LINIR_IDCHR_Msk);
1091 }
1092 
1100 uint8_t usart_lin_get_data_length(Usart *usart)
1101 {
1102  if (usart->US_LINMR & US_LINMR_DLM) {
1103  uint8_t data_length = 1 << ((usart->US_LINIR >>
1104  (US_LINIR_IDCHR_Pos + 4)) & 0x03);
1105  return data_length;
1106  } else {
1107  return ((usart->US_LINMR & US_LINMR_DLC_Msk) >> US_LINMR_DLC_Pos) + 1;
1108  }
1109 }
1110 
1111 #endif
1112 
1113 #if (SAMV71 || SAMV70 || SAME70 || SAMS70)
1114 
1123 uint8_t usart_lin_identifier_send_complete(Usart *usart)
1124 {
1125  return (usart->US_CSR & US_CSR_LINID) > 0;
1126 }
1127 
1137 uint8_t usart_lin_identifier_reception_complete(Usart *usart)
1138 {
1139  return (usart->US_CSR & US_CSR_LINID) > 0;
1140 }
1141 
1151 uint8_t usart_lin_tx_complete(Usart *usart)
1152 {
1153  return (usart->US_CSR & US_CSR_LINTC) > 0;
1154 }
1155 
1168 uint32_t usart_init_lon(Usart *p_usart,uint32_t ul_baudrate,
1169  uint32_t ul_mck)
1170 {
1171  /* Reset the USART and shut down TX and RX. */
1172  usart_reset(p_usart);
1173 
1174  /* Set up the baudrate. */
1175  if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) {
1176  return 1;
1177  }
1178 
1179  /* Set LIN master mode. */
1180  p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
1182 
1183  usart_enable_rx(p_usart);
1184  usart_enable_tx(p_usart);
1185 
1186  return 0;
1187 }
1188 
1196 void usart_lon_set_comm_type(Usart *p_usart, uint8_t uc_type)
1197 {
1198  p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_COMMT) |
1199  (uc_type << 0);
1200 }
1201 
1207 void usart_lon_disable_coll_detection(Usart *p_usart)
1208 {
1209  p_usart->US_LONMR |= US_LONMR_COLDET;
1210 }
1211 
1217 void usart_lon_enable_coll_detection(Usart *p_usart)
1218 {
1219  p_usart->US_LONMR &= ~US_LONMR_COLDET;
1220 }
1221 
1229 void usart_lon_set_tcol(Usart *p_usart, uint8_t uc_type)
1230 {
1231  p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_TCOL) |
1232  (uc_type << 2);
1233 }
1234 
1242 void usart_lon_set_cdtail(Usart *p_usart, uint8_t uc_type)
1243 {
1244  p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_CDTAIL) |
1245  (uc_type << 3);
1246 }
1247 
1255 void usart_lon_set_dmam(Usart *p_usart, uint8_t uc_type)
1256 {
1257  p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_DMAM) |
1258  (uc_type << 4);
1259 }
1260 
1267 void usart_lon_set_beta1_tx_len(Usart *p_usart, uint32_t ul_len)
1268 {
1269  p_usart->US_LONB1TX = US_LONB1TX_BETA1TX(ul_len);
1270 }
1271 
1278 void usart_lon_set_beta1_rx_len(Usart *p_usart, uint32_t ul_len)
1279 {
1280  p_usart->US_LONB1RX = US_LONB1RX_BETA1RX(ul_len);
1281 }
1282 
1290 void usart_lon_set_priority(Usart *p_usart, uint8_t uc_psnb, uint8_t uc_nps)
1291 {
1292  p_usart->US_LONPRIO = US_LONPRIO_PSNB(uc_psnb) | US_LONPRIO_NPS(uc_nps);
1293 }
1294 
1301 void usart_lon_set_tx_idt(Usart *p_usart, uint32_t ul_time)
1302 {
1303  p_usart->US_IDTTX = US_IDTTX_IDTTX(ul_time);
1304 }
1305 
1312 void usart_lon_set_rx_idt(Usart *p_usart, uint32_t ul_time)
1313 {
1314  p_usart->US_IDTRX = US_IDTRX_IDTRX(ul_time);
1315 }
1316 
1323 void usart_lon_set_pre_len(Usart *p_usart, uint32_t ul_len)
1324 {
1325  p_usart->US_LONPR = US_LONPR_LONPL(ul_len);
1326 }
1327 
1334 void usart_lon_set_data_len(Usart *p_usart, uint8_t uc_len)
1335 {
1336  p_usart->US_LONDL = US_LONDL_LONDL(uc_len);
1337 }
1338 
1347 void usart_lon_set_l2hdr(Usart *p_usart, uint8_t uc_bli, uint8_t uc_altp, uint8_t uc_pb)
1348 {
1349  p_usart->US_LONL2HDR = US_LONL2HDR_BLI(uc_bli) | (uc_altp << 6) | (uc_pb << 7);
1350 }
1351 
1360 uint32_t usart_lon_is_tx_end(Usart *p_usart)
1361 {
1362  return (p_usart->US_CSR & US_CSR_LTXD) > 0;
1363 }
1364 
1373 uint32_t usart_lon_is_rx_end(Usart *p_usart)
1374 {
1375  return (p_usart->US_CSR & US_CSR_LRXD) > 0;
1376 }
1377 #endif
1378 
1384 void usart_enable_tx(Usart *p_usart)
1385 {
1386  p_usart->US_CR = US_CR_TXEN;
1387 }
1388 
1394 void usart_disable_tx(Usart *p_usart)
1395 {
1396  p_usart->US_CR = US_CR_TXDIS;
1397 }
1398 
1404 void usart_reset_tx(Usart *p_usart)
1405 {
1406  /* Reset transmitter */
1407  p_usart->US_CR = US_CR_RSTTX | US_CR_TXDIS;
1408 }
1409 
1416 void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard)
1417 {
1418  p_usart->US_TTGR = timeguard;
1419 }
1420 
1426 void usart_enable_rx(Usart *p_usart)
1427 {
1428  p_usart->US_CR = US_CR_RXEN;
1429 }
1430 
1436 void usart_disable_rx(Usart *p_usart)
1437 {
1438  p_usart->US_CR = US_CR_RXDIS;
1439 }
1440 
1446 void usart_reset_rx(Usart *p_usart)
1447 {
1448  /* Reset Receiver */
1449  p_usart->US_CR = US_CR_RSTRX | US_CR_RXDIS;
1450 }
1451 
1458 void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout)
1459 {
1460  p_usart->US_RTOR = timeout;
1461 }
1462 
1469 void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources)
1470 {
1471  p_usart->US_IER = ul_sources;
1472 }
1473 
1480 void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources)
1481 {
1482  p_usart->US_IDR = ul_sources;
1483 }
1484 
1493 {
1494  return p_usart->US_IMR;
1495 }
1496 
1504 uint32_t usart_get_status(Usart *p_usart)
1505 {
1506  return p_usart->US_CSR;
1507 }
1508 
1515 {
1516  p_usart->US_CR = US_CR_RSTSTA;
1517 }
1518 
1525 {
1526  p_usart->US_CR = US_CR_STTBRK;
1527 }
1528 
1535 {
1536  p_usart->US_CR = US_CR_STPBRK;
1537 }
1538 
1546 {
1547  p_usart->US_CR = US_CR_STTTO;
1548 }
1549 
1560 uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr)
1561 {
1562  if ((p_usart->US_MR & US_MR_PAR_MULTIDROP) != US_MR_PAR_MULTIDROP) {
1563  return 1;
1564  }
1565 
1566  p_usart->US_CR = US_CR_SENDA;
1567 
1568  if (usart_write(p_usart, ul_addr)) {
1569  return 1;
1570  } else {
1571  return 0;
1572  }
1573 }
1574 
1581 {
1582  p_usart->US_CR = US_CR_RETTO;
1583 }
1584 
1585 #if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E)
1586 
1592 void usart_drive_DTR_pin_low(Usart *p_usart)
1593 {
1594  p_usart->US_CR = US_CR_DTREN;
1595 }
1596 
1602 void usart_drive_DTR_pin_high(Usart *p_usart)
1603 {
1604  p_usart->US_CR = US_CR_DTRDIS;
1605 }
1606 
1607 #endif
1608 
1615 {
1616  p_usart->US_CR = US_CR_RTSEN;
1617 }
1618 
1625 {
1626  p_usart->US_CR = US_CR_RTSDIS;
1627 }
1628 
1635 {
1636  p_usart->US_CR = US_CR_FCS;
1637 }
1638 
1645 {
1646  p_usart->US_CR = US_CR_RCS;
1647 }
1648 
1659 uint32_t usart_is_tx_ready(Usart *p_usart)
1660 {
1661  return (p_usart->US_CSR & US_CSR_TXRDY) > 0;
1662 }
1663 
1674 uint32_t usart_is_tx_empty(Usart *p_usart)
1675 {
1676  return (p_usart->US_CSR & US_CSR_TXEMPTY) > 0;
1677 }
1678 
1688 uint32_t usart_is_rx_ready(Usart *p_usart)
1689 {
1690  return (p_usart->US_CSR & US_CSR_RXRDY) > 0;
1691 }
1692 
1704 uint32_t usart_write(Usart *p_usart, uint32_t c)
1705 {
1706  if (!(p_usart->US_CSR & US_CSR_TXRDY)) {
1707  return 1;
1708  }
1709 
1710  p_usart->US_THR = US_THR_TXCHR(c);
1711  return 0;
1712 }
1713 
1725 uint32_t usart_putchar(Usart *p_usart, uint32_t c)
1726 {
1727  while (!(p_usart->US_CSR & US_CSR_TXRDY)) {
1728  }
1729 
1730  p_usart->US_THR = US_THR_TXCHR(c);
1731 
1732  return 0;
1733 }
1734 
1741 void usart_write_line(Usart *p_usart, const char *string)
1742 {
1743  while (*string != '\0') {
1744  usart_putchar(p_usart, *string++);
1745  }
1746 }
1747 
1759 uint32_t usart_read(Usart *p_usart, uint32_t *c)
1760 {
1761  if (!(p_usart->US_CSR & US_CSR_RXRDY)) {
1762  return 1;
1763  }
1764 
1765  /* Read character */
1766  *c = p_usart->US_RHR & US_RHR_RXCHR_Msk;
1767 
1768  return 0;
1769 }
1770 
1781 uint32_t usart_getchar(Usart *p_usart, uint32_t *c)
1782 {
1783  /* Wait until it's not empty or timeout has reached. */
1784  while (!(p_usart->US_CSR & US_CSR_RXRDY)) {
1785  }
1786 
1787  /* Read character */
1788  *c = p_usart->US_RHR & US_RHR_RXCHR_Msk;
1789 
1790  return 0;
1791 }
1792 
1793 #if (SAM3XA || SAM3U)
1794 
1801 uint32_t *usart_get_tx_access(Usart *p_usart)
1802 {
1803  return (uint32_t *)&(p_usart->US_THR);
1804 }
1805 
1813 uint32_t *usart_get_rx_access(Usart *p_usart)
1814 {
1815  return (uint32_t *)&(p_usart->US_RHR);
1816 }
1817 #endif
1818 
1819 #if (!SAM4L && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70)
1820 
1828 {
1829  Pdc *p_pdc_base;
1830 
1831  p_pdc_base = (Pdc *)NULL;
1832 
1833 #ifdef PDC_USART
1834  if (p_usart == USART) {
1835  p_pdc_base = PDC_USART;
1836  return p_pdc_base;
1837  }
1838 #endif
1839 #ifdef PDC_USART0
1840  if (p_usart == USART0) {
1841  p_pdc_base = PDC_USART0;
1842  return p_pdc_base;
1843  }
1844 #endif
1845 #ifdef PDC_USART1
1846  else if (p_usart == USART1) {
1847  p_pdc_base = PDC_USART1;
1848  return p_pdc_base;
1849  }
1850 #endif
1851 #ifdef PDC_USART2
1852  else if (p_usart == USART2) {
1853  p_pdc_base = PDC_USART2;
1854  return p_pdc_base;
1855  }
1856 #endif
1857 #ifdef PDC_USART3
1858  else if (p_usart == USART3) {
1859  p_pdc_base = PDC_USART3;
1860  return p_pdc_base;
1861  }
1862 #endif
1863 #ifdef PDC_USART4
1864  else if (p_usart == USART4) {
1865  p_pdc_base = PDC_USART4;
1866  return p_pdc_base;
1867  }
1868 #endif
1869 #ifdef PDC_USART5
1870  else if (p_usart == USART5) {
1871  p_pdc_base = PDC_USART5;
1872  return p_pdc_base;
1873  }
1874 #endif
1875 #ifdef PDC_USART6
1876  else if (p_usart == USART6) {
1877  p_pdc_base = PDC_USART6;
1878  return p_pdc_base;
1879  }
1880 #endif
1881 #ifdef PDC_USART7
1882  else if (p_usart == USART7) {
1883  p_pdc_base = PDC_USART7;
1884  return p_pdc_base;
1885  }
1886 #endif
1887 
1888  return p_pdc_base;
1889 }
1890 #endif
1891 
1898 {
1900 }
1901 
1908 {
1909  p_usart->US_WPMR = US_WPMR_WPKEY_PASSWD;
1910 }
1911 
1921 {
1922  uint32_t reg_value;
1923 
1924  reg_value = p_usart->US_WPSR;
1925  if (reg_value & US_WPSR_WPVS) {
1926  return (reg_value & US_WPSR_WPVSRC_Msk) >> US_WPSR_WPVSRC_Pos;
1927  } else {
1928  return 0;
1929  }
1930 }
1931 
1932 #if (SAM3S || SAM4S || SAM3U || SAM3XA || SAM4L || SAM4E || SAM4C || SAM4CP || SAM4CM)
1933 
1941 void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len)
1942 {
1943  p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PL_Msk) |
1944  US_MAN_TX_PL(uc_len);
1945 }
1946 
1957 void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern)
1958 {
1959  p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PP_Msk) |
1960  (uc_pattern << US_MAN_TX_PP_Pos);
1961 }
1962 
1971 void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity)
1972 {
1973  p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_MPOL) |
1974  (uc_polarity << 12);
1975 }
1976 
1984 void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len)
1985 {
1986  p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PL_Msk) |
1987  US_MAN_RX_PL(uc_len);
1988 }
1989 
2000 void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern)
2001 {
2002  p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PP_Msk) |
2003  (uc_pattern << US_MAN_RX_PP_Pos);
2004 }
2005 
2014 void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity)
2015 {
2016  p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_MPOL) |
2017  (uc_polarity << 28);
2018 }
2019 
2027 void usart_man_enable_drift_compensation(Usart *p_usart)
2028 {
2029  p_usart->US_MAN |= US_MAN_DRIFT;
2030 }
2031 
2037 void usart_man_disable_drift_compensation(Usart *p_usart)
2038 {
2039  p_usart->US_MAN &= ~US_MAN_DRIFT;
2040 }
2041 
2042 #endif
2043 
2044 #if SAM4L
2045 
2046 uint32_t usart_get_version(Usart *p_usart)
2047 {
2048  return p_usart->US_VERSION;
2049 }
2050 
2051 #endif
2052 
2053 #if SAMG55
2054 
2063 void usart_set_sleepwalking(Usart *p_uart, uint8_t ul_low_value,
2064  bool cmpmode, bool cmppar, uint8_t ul_high_value)
2065 {
2066  Assert(ul_low_value <= ul_high_value);
2067 
2068  uint32_t temp = 0;
2069 
2070  if (cmpmode) {
2071  temp |= US_CMPR_CMPMODE_START_CONDITION;
2072  }
2073 
2074  if (cmppar) {
2075  temp |= US_CMPR_CMPPAR;
2076  }
2077 
2078  temp |= US_CMPR_VAL1(ul_low_value);
2079 
2080  temp |= US_CMPR_VAL2(ul_high_value);
2081 
2082  p_uart->US_CMPR= temp;
2083 }
2084 #endif
2085 
2087 
2089 
2090 #ifdef __cplusplus
2091 }
2092 #endif
2093 
2094 
#define US_MR_USART_MODE_Msk
(US_MR) USART Mode of Operation
#define US_CR_RETTO
(US_CR) Start Time-out Immediately
#define US_LONB1TX_BETA1TX(value)
__IO uint32_t US_IDTRX
(Usart Offset: 0x0084) LON IDT Rx Register
void usart_enable_rx(Usart *p_usart)
Enable USART receiver.
Definition: usart.c:1426
__IO uint32_t US_BRGR
(Usart Offset: 0x0020) Baud Rate Generator Register
static uint32_t usart_set_iso7816_clock(Usart *p_usart, uint32_t clock, uint32_t ul_mck)
Calculate a clock divider (CD) for the USART ISO7816 mode to generate an ISO7816 clock as close as po...
Definition: usart.c:524
#define US_MR_CLKO
(US_MR) Clock Output Select
void usart_start_rx_timeout(Usart *p_usart)
Start waiting for a character before clocking the timeout count. Reset the status bit TIMEOUT in US_C...
Definition: usart.c:1545
__IO uint32_t US_LINMR
(Usart Offset: 0x0054) LIN Mode Register
void usart_drive_RTS_pin_low(Usart *p_usart)
Drive the pin RTS to 0.
Definition: usart.c:1614
#define US_LONL2HDR_BLI(value)
uint8_t usart_get_error_number(Usart *p_usart)
Get the total number of errors that occur during an ISO7816 transfer.
Definition: usart.c:699
#define US_LINMR_CHKDIS
(US_LINMR) Checksum Disable
uint32_t usart_init_rs485(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
Configure USART to work in RS485 mode.
Definition: usart.c:462
#define US_MR_USART_MODE_LIN_MASTER
(US_MR) LIN Master mode
#define US_MR_USCLKS_Msk
(US_MR) Clock Selection
#define US_CR_LINWKUP
(US_CR) Send LIN Wakeup Signal
#define US_MAN_RX_MPOL
(US_MAN) Receiver Manchester Polarity
void usart_restart_rx_timeout(Usart *p_usart)
Restart the receive timeout.
Definition: usart.c:1580
#define US_CR_STTTO
(US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received
__IO uint32_t US_LINIR
(Usart Offset: 0x0058) LIN Identifier Register
#define US_MAN_TX_MPOL
(US_MAN) Transmitter Manchester Polarity
#define US_LINMR_FSDIS
(US_LINMR) Frame Slot Mode Disable
#define US_MR_PAR_MULTIDROP
(US_MR) Multidrop mode
#define US_MR_USART_MODE_RS485
(US_MR) RS485
#define US_MR_PAR_EVEN
(US_MR) Even parity
#define US_MR_NBSTOP_1_BIT
(US_MR) 1 stop bit
#define US_LONMR_COLDET
(US_LONMR) LON Collision Detection Feature
void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard)
Configure the transmit timeguard register.
Definition: usart.c:1416
#define US_CR_RSTRX
(US_CR) Reset Receiver
void usart_write_line(Usart *p_usart, const char *string)
Write one-line string through USART.
Definition: usart.c:1741
static void usart_set_spi_slave_baudrate(Usart *p_usart)
Select the SCK pin as the source of baudrate for the USART SPI slave mode.
Definition: usart.c:229
uint32_t usart_is_rx_buf_full(Usart *p_usart)
Check if both receive buffers are full.
Definition: usart.c:646
#define US_MAN_RX_PL_Msk
(US_MAN) Receiver Preamble Length
uint32_t usart_get_interrupt_mask(Usart *p_usart)
Read USART interrupt mask.
Definition: usart.c:1492
#define US_CR_STPBRK
(US_CR) Stop Break
#define LOW_FRQ_SAMPLE_DIV
Definition: usart.c:82
void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources)
Disable USART interrupts.
Definition: usart.c:1480
uint32_t usart_init_spi_slave(Usart *p_usart, const usart_spi_opt_t *p_usart_opt)
Configure USART to work in SPI mode and act as a slave.
Definition: usart.c:782
__I uint32_t US_VERSION
(Usart Offset: 0x00FC) Version Register
Usart hardware registers.
void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources)
Enable USART interrupts.
Definition: usart.c:1469
void usart_drive_RTS_pin_high(Usart *p_usart)
Drive the pin RTS to 1.
Definition: usart.c:1624
#define US_CSR_LTXD
(US_CSR) LON Transmission End Flag (cleared by writing a one to bit US_CR.RSTSTA) ...
#define US_LONPRIO_PSNB(value)
#define US_MR_USART_MODE_HW_HANDSHAKING
(US_MR) Hardware Handshaking
#define US_WPSR_WPVSRC_Msk
(US_WPSR) Write Protection Violation Source
void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout)
Configure the receive timeout register.
Definition: usart.c:1458
static uint32_t usart_set_spi_master_baudrate(Usart *p_usart, uint32_t baudrate, uint32_t ul_mck)
Calculate a clock divider (CD) for the USART SPI master mode to generate a baud rate as close as poss...
Definition: usart.c:206
#define US_LONMR_DMAM
(US_LONMR) LON DMA Mode
#define US_WPSR_WPVS
(US_WPSR) Write Protection Violation Status
Pdc * usart_get_pdc_base(Usart *p_usart)
Get USART PDC base address.
Definition: usart.c:1827
uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr)
In Multidrop mode only, the next character written to the US_THR is sent with the address bit set...
Definition: usart.c:1560
static void usart_set_sync_slave_baudrate(Usart *p_usart)
Select the SCK pin as the source of baud rate for the USART synchronous slave modes.
Definition: usart.c:185
#define NULL
Definition: nm_bsp.h:52
#define US_MR_USART_MODE_LON
(US_MR) LON
void usart_disable_writeprotect(Usart *p_usart)
Disable write protect of USART registers.
Definition: usart.c:1907
#define US_MR_DSNACK
(US_MR) Disable Successive NACK
Universal Synchronous Asynchronous Receiver Transmitter (USART) driver for SAM.
#define US_LONB1RX_BETA1RX(value)
uint32_t usart_is_rx_buf_end(Usart *p_usart)
Check if one receive buffer is filled.
Definition: usart.c:660
#define US_LINMR_DLM
(US_LINMR) Data Length Mode
#define US_MR_USCLKS_MCK
(US_MR) Peripheral clock is selected
#define US_CSR_TXEMPTY
(US_CSR) Transmitter Empty (cleared by writing US_THR)
#define US_MR_CPHA
(US_MR) SPI Clock Phase
#define SPI_MODE_1
SPI mode 1.
#define US_CR_DTRDIS
(US_CR) Data Terminal Ready Disable
#define USART0
(USART0) Base Address
Definition: same70j19.h:505
#define US_MAN_TX_PL_Msk
(US_MAN) Transmitter Preamble Length
#define US_CR_LINABT
(US_CR) Abort LIN Transmission
void usart_reset_iterations(Usart *p_usart)
Reset the ITERATION in US_CSR when the ISO7816 mode is enabled.
Definition: usart.c:623
#define USART1
(USART1) Base Address
Definition: same70j19.h:506
uint32_t usart_get_status(Usart *p_usart)
Get current status.
Definition: usart.c:1504
#define US_MR_OVER
(US_MR) Oversampling Mode
#define US_MR_USART_MODE_IRDA
(US_MR) IrDA
__IO uint32_t US_RTOR
(Usart Offset: 0x0024) Receiver Time-out Register
__IO uint32_t US_TTGR
(Usart Offset: 0x0028) Transmitter Timeguard Register
uint32_t usart_is_tx_buf_end(Usart *p_usart)
Check if one transmit buffer is empty.
Definition: usart.c:673
#define US_LINMR_DLC_Msk
(US_LINMR) Data Length Control
void usart_spi_release_chip_select(Usart *p_usart)
Drive the slave select line NSS (RTS pin) to 1 in SPI master mode.
Definition: usart.c:1644
uint32_t usart_is_tx_ready(Usart *p_usart)
Check if Transmit is Ready. Check if data have been loaded in USART_THR and are waiting to be loaded ...
Definition: usart.c:1659
__IO uint32_t US_LONPR
(Usart Offset: 0x0064) LON Preamble Register
#define US_MR_USART_MODE_SPI_SLAVE
(US_MR) SPI Slave mode
#define US_LINMR_CHKTYP
(US_LINMR) Checksum Type
#define US_MR_NBSTOP_2_BIT
(US_MR) 2 stop bits
void usart_reset_rx(Usart *p_usart)
Immediately stop and disable USART receiver.
Definition: usart.c:1446
uint32_t usart_read(Usart *p_usart, uint32_t *c)
Read from USART Receive Holding Register.
Definition: usart.c:1759
#define US_LONMR_CDTAIL
(US_LONMR) LON Collision Detection on Frame Tail
#define US_CR_FCS
(US_CR) Force SPI Chip Select
#define US_LONMR_COMMT
(US_LONMR) LON comm_type Parameter Value
#define US_CR_RCS
(US_CR) Release SPI Chip Select
#define US_LINMR_WKUPTYP
(US_LINMR) Wakeup Signal Type
#define US_WPMR_WPKEY_PASSWD
Definition: usart.c:68
#define US_LONMR_TCOL
(US_LONMR) Terminate Frame upon Collision Notification
#define US_MR_CPOL
(US_MR) SPI Clock Polarity
__IO uint32_t US_LONB1TX
(Usart Offset: 0x0074) LON Beta1 Tx Register
uint32_t usart_is_rx_ready(Usart *p_usart)
Check if the received data are ready. Check if Data have been received and loaded into USART_RHR...
Definition: usart.c:1688
#define ISO7816_T_0
Definition: usart.c:91
uint32_t usart_init_rs232(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
Configure USART to work in RS232 mode.
Definition: usart.c:274
#define US_LINMR_PDCM
(US_LINMR) DMAC Mode
#define US_MR_USART_MODE_IS07816_T_0
(US_MR) IS07816 Protocol: T = 0
uint32_t usart_set_async_baudrate(Usart *p_usart, uint32_t baudrate, uint32_t ul_mck)
Calculate a clock divider(CD) and a fractional part (FP) for the USART asynchronous modes to generate...
Definition: usart.c:111
void usart_enable_writeprotect(Usart *p_usart)
Enable write protect of USART registers.
Definition: usart.c:1897
#define US_CR_DTREN
(US_CR) Data Terminal Ready Enable
#define US_MAN_DRIFT
(US_MAN) Drift Compensation
void usart_reset_status(Usart *p_usart)
Reset status bits (PARE, OVER, MANERR, UNRE and PXBRK in US_CSR).
Definition: usart.c:1514
#define US_MR_USART_MODE_MODEM
(US_MR) Modem
#define US_CSR_LINID
(US_CSR) LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR...
#define US_CR_SENDA
(US_CR) Send Address
uint32_t usart_init_spi_master(Usart *p_usart, const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck)
Configure USART to work in SPI mode and act as a master.
Definition: usart.c:718
void usart_reset(Usart *p_usart)
Reset the USART and disable TX and RX.
Definition: usart.c:240
uint32_t usart_init_sync_master(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
Configure USART to work in SYNC mode and act as a master.
Definition: usart.c:386
__IO uint32_t US_MAN
(Usart Offset: 0x0050) Manchester Configuration Register
__IO uint32_t US_LONL2HDR
(Usart Offset: 0x006C) LON L2HDR Register
uint32_t usart_init_iso7816(Usart *p_usart, const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck)
Configure USART to work in ISO7816 mode.
Definition: usart.c:557
#define US_MR_PAR_ODD
(US_MR) Odd parity
#define US_MR_MSBF
(US_MR) Bit Order
#define US_CR_RSTTX
(US_CR) Reset Transmitter
__I uint32_t US_CSR
(Usart Offset: 0x0014) Channel Status Register
uint32_t usart_init_sync_slave(Usart *p_usart, const sam_usart_opt_t *p_usart_opt)
Configure USART to work in SYNC mode and act as a slave.
Definition: usart.c:423
#define US_CSR_LRXD
(US_CSR) LON Reception End Flag (cleared by writing a one to bit US_CR.RSTSTA)
uint32_t usart_init_hw_handshaking(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
Configure USART to work in hardware handshaking mode.
Definition: usart.c:313
#define US_CSR_RXRDY
(US_CSR) Receiver Ready (cleared by reading US_RHR)
#define US_CR_RTSDIS
(US_CR) Request to Send Pin Control
void usart_reset_nack(Usart *p_usart)
Reset NACK in US_CSR.
Definition: usart.c:633
#define US_MAN_TX_PP_Msk
(US_MAN) Transmitter Preamble Pattern
uint32_t usart_getchar(Usart *p_usart, uint32_t *c)
Read from USART Receive Holding Register. Before reading user should check if rx is ready...
Definition: usart.c:1781
__I uint32_t US_IMR
(Usart Offset: 0x0010) Interrupt Mask Register
#define US_RHR_RXCHR_Msk
(US_RHR) Received Character
void usart_disable_rx(Usart *p_usart)
Disable USART receiver.
Definition: usart.c:1436
__O uint32_t US_CR
(Usart Offset: 0x0000) Control Register
#define US_LINIR_IDCHR_Msk
(US_LINIR) Identifier Character
__O uint32_t US_IDR
(Usart Offset: 0x000C) Interrupt Disable Register
#define US_MR_USART_MODE_IS07816_T_1
(US_MR) IS07816 Protocol: T = 1
#define US_CR_TXEN
(US_CR) Transmitter Enable
#define MAX_CD_VALUE
Definition: usart.c:78
void usart_stop_tx_break(Usart *p_usart)
Stop transmission of a break.
Definition: usart.c:1534
#define US_LINMR_NACT_Msk
(US_LINMR) LIN Node Action
__O uint32_t US_IER
(Usart Offset: 0x0008) Interrupt Enable Register
#define US_MR_USART_MODE_NORMAL
(US_MR) Normal mode
#define US_MR_SYNC
(US_MR) Synchronous Mode Select
#define SPI_MODE_3
SPI mode 3.
#define US_MR_USART_MODE_SPI_MASTER
(US_MR) SPI master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2)
__IO uint32_t US_IF
(Usart Offset: 0x004C) IrDA Filter Register
uint32_t usart_putchar(Usart *p_usart, uint32_t c)
Write to USART Transmit Holding Register.
Definition: usart.c:1725
#define US_CSR_TXRDY
(US_CSR) Transmitter Ready (cleared by writing US_THR)
__I uint32_t US_RHR
(Usart Offset: 0x0018) Receive Holding Register
#define US_CSR_LINTC
(US_CSR) LIN Transfer Completed (cleared by writing a one to bit US_CR.RSTSTA)
#define US_CR_RTSEN
(US_CR) Request to Send Pin Control
__I uint32_t US_WPSR
(Usart Offset: 0x00E8) Write Protection Status Register
#define HIGH_FRQ_SAMPLE_DIV
Definition: usart.c:81
#define US_WPMR_WPEN
(US_WPMR) Write Protection Enable
#define US_MR_INACK
(US_MR) Inhibit Non Acknowledge
#define SPI_MODE_0
SPI mode 0.
void usart_disable_tx(Usart *p_usart)
Disable USART transmitter.
Definition: usart.c:1394
#define US_MR_USCLKS_SCK
(US_MR) Serial clock (SCK) is selected
#define SPI_MODE_2
SPI mode 2.
#define US_CR_STTBRK
(US_CR) Start Break
void usart_start_tx_break(Usart *p_usart)
Start transmission of a break.
Definition: usart.c:1524
__IO uint32_t US_MR
(Usart Offset: 0x0004) Mode Register
__IO uint32_t US_LONMR
(Usart Offset: 0x0060) LON Mode Register
uint32_t usart_init_irda(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
Configure USART to work in IrDA mode.
Definition: usart.c:490
static uint32_t usart_set_sync_master_baudrate(Usart *p_usart, uint32_t baudrate, uint32_t ul_mck)
Calculate a clock divider for the USART synchronous master modes to generate a baudrate as close as p...
Definition: usart.c:159
#define US_CR_RSTNACK
(US_CR) Reset Non Acknowledge
#define US_NER_NB_ERRORS_Msk
(US_NER) Number of Errors
__IO uint32_t US_LONPRIO
(Usart Offset: 0x007C) LON Priority Register
#define US_CR_RXEN
(US_CR) Receiver Enable
__IO uint32_t US_LONDL
(Usart Offset: 0x0068) LON Data Length Register
__O uint32_t US_THR
(Usart Offset: 0x001C) Transmit Holding Register
void usart_spi_force_chip_select(Usart *p_usart)
Drive the slave select line NSS (RTS pin) to 0 in SPI master mode.
Definition: usart.c:1634
#define US_CR_TXDIS
(US_CR) Transmitter Disable
void usart_enable_tx(Usart *p_usart)
Enable USART transmitter.
Definition: usart.c:1384
#define ISO7816_T_1
Definition: usart.c:92
#define US_MR_USART_MODE_LIN_SLAVE
(US_MR) LIN Slave mode
__IO uint32_t US_IDTTX
(Usart Offset: 0x0080) LON IDT Tx Register
__IO uint32_t US_WPMR
(Usart Offset: 0x00E4) Write Protection Mode Register
#define US_MAN_RX_PP_Msk
(US_MAN) Receiver Preamble Pattern detected
#define USART2
(USART2) Base Address
Definition: same70n19.h:548
#define US_LINMR_PARDIS
(US_LINMR) Parity Disable
uint32_t usart_write(Usart *p_usart, uint32_t c)
Write to USART Transmit Holding Register.
Definition: usart.c:1704
uint32_t usart_is_tx_empty(Usart *p_usart)
Check if Transmit Holding Register is empty. Check if the last data written in USART_THR have been lo...
Definition: usart.c:1674
#define Assert(expr)
This macro is used to test fatal errors.
Definition: compiler.h:196
__IO uint32_t US_LONB1RX
(Usart Offset: 0x0078) LON Beta1 Rx Register
uint32_t usart_get_writeprotect_status(Usart *p_usart)
Get write protect status.
Definition: usart.c:1920
#define US_CR_RSTIT
(US_CR) Reset Iterations
#define US_CR_RXDIS
(US_CR) Receiver Disable
#define US_CR_RSTSTA
(US_CR) Reset Status Bits
__IO uint32_t US_FIDI
(Usart Offset: 0x0040) FI DI Ratio Register
void usart_reset_tx(Usart *p_usart)
Immediately stop and disable USART transmitter.
Definition: usart.c:1404
__I uint32_t US_NER
(Usart Offset: 0x0044) Number of Errors Register
uint32_t usart_is_tx_buf_empty(Usart *p_usart)
Check if both transmit buffers are empty.
Definition: usart.c:686


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:05