Classes | Macros
Universal Synchronous Asynchronous Receiver Transmitter

Classes

struct  Usart
 Usart hardware registers. More...
 

Macros

#define US_BRGR_CD(value)   ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
 
#define US_BRGR_CD_Msk   (0xffffu << US_BRGR_CD_Pos)
 (US_BRGR) Clock Divider More...
 
#define US_BRGR_CD_Pos   0
 
#define US_BRGR_FP(value)   ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
 
#define US_BRGR_FP_Msk   (0x7u << US_BRGR_FP_Pos)
 (US_BRGR) Fractional Part More...
 
#define US_BRGR_FP_Pos   16
 
#define US_CR_DTRDIS   (0x1u << 17)
 (US_CR) Data Terminal Ready Disable More...
 
#define US_CR_DTREN   (0x1u << 16)
 (US_CR) Data Terminal Ready Enable More...
 
#define US_CR_FCS   (0x1u << 18)
 (US_CR) Force SPI Chip Select More...
 
#define US_CR_LINABT   (0x1u << 20)
 (US_CR) Abort LIN Transmission More...
 
#define US_CR_LINWKUP   (0x1u << 21)
 (US_CR) Send LIN Wakeup Signal More...
 
#define US_CR_RCS   (0x1u << 19)
 (US_CR) Release SPI Chip Select More...
 
#define US_CR_RETTO   (0x1u << 15)
 (US_CR) Start Time-out Immediately More...
 
#define US_CR_RSTIT   (0x1u << 13)
 (US_CR) Reset Iterations More...
 
#define US_CR_RSTNACK   (0x1u << 14)
 (US_CR) Reset Non Acknowledge More...
 
#define US_CR_RSTRX   (0x1u << 2)
 (US_CR) Reset Receiver More...
 
#define US_CR_RSTSTA   (0x1u << 8)
 (US_CR) Reset Status Bits More...
 
#define US_CR_RSTTX   (0x1u << 3)
 (US_CR) Reset Transmitter More...
 
#define US_CR_RTSDIS   (0x1u << 19)
 (US_CR) Request to Send Pin Control More...
 
#define US_CR_RTSEN   (0x1u << 18)
 (US_CR) Request to Send Pin Control More...
 
#define US_CR_RXDIS   (0x1u << 5)
 (US_CR) Receiver Disable More...
 
#define US_CR_RXEN   (0x1u << 4)
 (US_CR) Receiver Enable More...
 
#define US_CR_SENDA   (0x1u << 12)
 (US_CR) Send Address More...
 
#define US_CR_STPBRK   (0x1u << 10)
 (US_CR) Stop Break More...
 
#define US_CR_STTBRK   (0x1u << 9)
 (US_CR) Start Break More...
 
#define US_CR_STTTO   (0x1u << 11)
 (US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received More...
 
#define US_CR_TXDIS   (0x1u << 7)
 (US_CR) Transmitter Disable More...
 
#define US_CR_TXEN   (0x1u << 6)
 (US_CR) Transmitter Enable More...
 
#define US_CSR_CTS   (0x1u << 23)
 (US_CSR) Image of CTS Input More...
 
#define US_CSR_CTSIC   (0x1u << 19)
 (US_CSR) Clear to Send Input Change Flag (cleared on read) More...
 
#define US_CSR_DCD   (0x1u << 22)
 (US_CSR) Image of DCD Input More...
 
#define US_CSR_DCDIC   (0x1u << 18)
 (US_CSR) Data Carrier Detect Input Change Flag (cleared on read) More...
 
#define US_CSR_DSR   (0x1u << 21)
 (US_CSR) Image of DSR Input More...
 
#define US_CSR_DSRIC   (0x1u << 17)
 (US_CSR) Data Set Ready Input Change Flag (cleared on read) More...
 
#define US_CSR_FRAME   (0x1u << 6)
 (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_ITER   (0x1u << 10)
 (US_CSR) Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) More...
 
#define US_CSR_LBLOVFE   (0x1u << 28)
 (US_CSR) LON Backlog Overflow Error (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_LCOL   (0x1u << 25)
 (US_CSR) LON Collision Detected Flag (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_LCRCE   (0x1u << 7)
 (US_CSR) LON CRC Error (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_LFET   (0x1u << 26)
 (US_CSR) LON Frame Early Termination (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_LINBE   (0x1u << 25)
 (US_CSR) LIN Bit Error (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_LINBK   (0x1u << 13)
 (US_CSR) LIN Break Sent or LIN Break Received (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_LINBLS   (0x1u << 23)
 (US_CSR) LIN Bus Line Status More...
 
#define US_CSR_LINCE   (0x1u << 28)
 (US_CSR) LIN Checksum Error (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_LINHTE   (0x1u << 31)
 (US_CSR) LIN Header Timeout Error (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_LINID   (0x1u << 14)
 (US_CSR) LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_LINIPE   (0x1u << 27)
 (US_CSR) LIN Identifier Parity Error (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_LINISFE   (0x1u << 26)
 (US_CSR) LIN Inconsistent Synch Field Error (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_LINSNRE   (0x1u << 29)
 (US_CSR) LIN Slave Not Responding Error (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_LINSTE   (0x1u << 30)
 (US_CSR) LIN Synch Tolerance Error (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_LINTC   (0x1u << 15)
 (US_CSR) LIN Transfer Completed (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_LRXD   (0x1u << 27)
 (US_CSR) LON Reception End Flag (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_LSFE   (0x1u << 6)
 (US_CSR) LON Short Frame Error (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_LTXD   (0x1u << 24)
 (US_CSR) LON Transmission End Flag (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_MANERR   (0x1u << 24)
 (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) More...
 
#define US_CSR_NACK   (0x1u << 13)
 (US_CSR) Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) More...
 
#define US_CSR_NSS   (0x1u << 23)
 (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) More...
 
#define US_CSR_NSSE   (0x1u << 19)
 (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) More...
 
#define US_CSR_OVRE   (0x1u << 5)
 (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_PARE   (0x1u << 7)
 (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_RI   (0x1u << 20)
 (US_CSR) Image of RI Input More...
 
#define US_CSR_RIIC   (0x1u << 16)
 (US_CSR) Ring Indicator Input Change Flag (cleared on read) More...
 
#define US_CSR_RXBRK   (0x1u << 2)
 (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_CSR_RXRDY   (0x1u << 0)
 (US_CSR) Receiver Ready (cleared by reading US_RHR) More...
 
#define US_CSR_TIMEOUT   (0x1u << 8)
 (US_CSR) Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) More...
 
#define US_CSR_TXEMPTY   (0x1u << 9)
 (US_CSR) Transmitter Empty (cleared by writing US_THR) More...
 
#define US_CSR_TXRDY   (0x1u << 1)
 (US_CSR) Transmitter Ready (cleared by writing US_THR) More...
 
#define US_CSR_UNRE   (0x1u << 10)
 (US_CSR) Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) More...
 
#define US_FIDI_BETA2(value)   ((US_FIDI_BETA2_Msk & ((value) << US_FIDI_BETA2_Pos)))
 
#define US_FIDI_BETA2_Msk   (0xffffffu << US_FIDI_BETA2_Pos)
 (US_FIDI) LON BETA2 Length More...
 
#define US_FIDI_BETA2_Pos   0
 
#define US_FIDI_FI_DI_RATIO(value)   ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
 
#define US_FIDI_FI_DI_RATIO_Msk   (0xffffu << US_FIDI_FI_DI_RATIO_Pos)
 (US_FIDI) FI Over DI Ratio Value More...
 
#define US_FIDI_FI_DI_RATIO_Pos   0
 
#define US_ICDIFF_ICDIFF(value)   ((US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos)))
 
#define US_ICDIFF_ICDIFF_Msk   (0xfu << US_ICDIFF_ICDIFF_Pos)
 (US_ICDIFF) IC Differentiator Number More...
 
#define US_ICDIFF_ICDIFF_Pos   0
 
#define US_IDR_CTSIC   (0x1u << 19)
 (US_IDR) Clear to Send Input Change Interrupt Disable More...
 
#define US_IDR_DCDIC   (0x1u << 18)
 (US_IDR) Data Carrier Detect Input Change Interrupt Disable More...
 
#define US_IDR_DSRIC   (0x1u << 17)
 (US_IDR) Data Set Ready Input Change Disable More...
 
#define US_IDR_FRAME   (0x1u << 6)
 (US_IDR) Framing Error Interrupt Disable More...
 
#define US_IDR_ITER   (0x1u << 10)
 (US_IDR) Max Number of Repetitions Reached Interrupt Disable More...
 
#define US_IDR_LBLOVFE   (0x1u << 28)
 (US_IDR) LON Backlog Overflow Error Interrupt Disable More...
 
#define US_IDR_LCOL   (0x1u << 25)
 (US_IDR) LON Collision Interrupt Disable More...
 
#define US_IDR_LCRCE   (0x1u << 7)
 (US_IDR) LON CRC Error Interrupt Disable More...
 
#define US_IDR_LFET   (0x1u << 26)
 (US_IDR) LON Frame Early Termination Interrupt Disable More...
 
#define US_IDR_LINBE   (0x1u << 25)
 (US_IDR) LIN Bus Error Interrupt Disable More...
 
#define US_IDR_LINBK   (0x1u << 13)
 (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable More...
 
#define US_IDR_LINCE   (0x1u << 28)
 (US_IDR) LIN Checksum Error Interrupt Disable More...
 
#define US_IDR_LINHTE   (0x1u << 31)
 (US_IDR) LIN Header Timeout Error Interrupt Disable More...
 
#define US_IDR_LINID   (0x1u << 14)
 (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable More...
 
#define US_IDR_LINIPE   (0x1u << 27)
 (US_IDR) LIN Identifier Parity Interrupt Disable More...
 
#define US_IDR_LINISFE   (0x1u << 26)
 (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable More...
 
#define US_IDR_LINSNRE   (0x1u << 29)
 (US_IDR) LIN Slave Not Responding Error Interrupt Disable More...
 
#define US_IDR_LINSTE   (0x1u << 30)
 (US_IDR) LIN Synch Tolerance Error Interrupt Disable More...
 
#define US_IDR_LINTC   (0x1u << 15)
 (US_IDR) LIN Transfer Completed Interrupt Disable More...
 
#define US_IDR_LRXD   (0x1u << 27)
 (US_IDR) LON Reception Done Interrupt Disable More...
 
#define US_IDR_LSFE   (0x1u << 6)
 (US_IDR) LON Short Frame Error Interrupt Disable More...
 
#define US_IDR_LTXD   (0x1u << 24)
 (US_IDR) LON Transmission Done Interrupt Disable More...
 
#define US_IDR_MANE   (0x1u << 24)
 (US_IDR) Manchester Error Interrupt Disable More...
 
#define US_IDR_NACK   (0x1u << 13)
 (US_IDR) Non Acknowledge Interrupt Disable More...
 
#define US_IDR_NSSE   (0x1u << 19)
 (US_IDR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable More...
 
#define US_IDR_OVRE   (0x1u << 5)
 (US_IDR) Overrun Error Interrupt Enable More...
 
#define US_IDR_PARE   (0x1u << 7)
 (US_IDR) Parity Error Interrupt Disable More...
 
#define US_IDR_RIIC   (0x1u << 16)
 (US_IDR) Ring Indicator Input Change Disable More...
 
#define US_IDR_RXBRK   (0x1u << 2)
 (US_IDR) Receiver Break Interrupt Disable More...
 
#define US_IDR_RXRDY   (0x1u << 0)
 (US_IDR) RXRDY Interrupt Disable More...
 
#define US_IDR_TIMEOUT   (0x1u << 8)
 (US_IDR) Time-out Interrupt Disable More...
 
#define US_IDR_TXEMPTY   (0x1u << 9)
 (US_IDR) TXEMPTY Interrupt Disable More...
 
#define US_IDR_TXRDY   (0x1u << 1)
 (US_IDR) TXRDY Interrupt Disable More...
 
#define US_IDR_UNRE   (0x1u << 10)
 (US_IDR) SPI Underrun Error Interrupt Disable More...
 
#define US_IDTRX_IDTRX(value)   ((US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos)))
 
#define US_IDTRX_IDTRX_Msk   (0xffffffu << US_IDTRX_IDTRX_Pos)
 (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) More...
 
#define US_IDTRX_IDTRX_Pos   0
 
#define US_IDTTX_IDTTX(value)   ((US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos)))
 
#define US_IDTTX_IDTTX_Msk   (0xffffffu << US_IDTTX_IDTTX_Pos)
 (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) More...
 
#define US_IDTTX_IDTTX_Pos   0
 
#define US_IER_CTSIC   (0x1u << 19)
 (US_IER) Clear to Send Input Change Interrupt Enable More...
 
#define US_IER_DCDIC   (0x1u << 18)
 (US_IER) Data Carrier Detect Input Change Interrupt Enable More...
 
#define US_IER_DSRIC   (0x1u << 17)
 (US_IER) Data Set Ready Input Change Enable More...
 
#define US_IER_FRAME   (0x1u << 6)
 (US_IER) Framing Error Interrupt Enable More...
 
#define US_IER_ITER   (0x1u << 10)
 (US_IER) Max number of Repetitions Reached Interrupt Enable More...
 
#define US_IER_LBLOVFE   (0x1u << 28)
 (US_IER) LON Backlog Overflow Error Interrupt Enable More...
 
#define US_IER_LCOL   (0x1u << 25)
 (US_IER) LON Collision Interrupt Enable More...
 
#define US_IER_LCRCE   (0x1u << 7)
 (US_IER) LON CRC Error Interrupt Enable More...
 
#define US_IER_LFET   (0x1u << 26)
 (US_IER) LON Frame Early Termination Interrupt Enable More...
 
#define US_IER_LINBE   (0x1u << 25)
 (US_IER) LIN Bus Error Interrupt Enable More...
 
#define US_IER_LINBK   (0x1u << 13)
 (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable More...
 
#define US_IER_LINCE   (0x1u << 28)
 (US_IER) LIN Checksum Error Interrupt Enable More...
 
#define US_IER_LINHTE   (0x1u << 31)
 (US_IER) LIN Header Timeout Error Interrupt Enable More...
 
#define US_IER_LINID   (0x1u << 14)
 (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable More...
 
#define US_IER_LINIPE   (0x1u << 27)
 (US_IER) LIN Identifier Parity Interrupt Enable More...
 
#define US_IER_LINISFE   (0x1u << 26)
 (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable More...
 
#define US_IER_LINSNRE   (0x1u << 29)
 (US_IER) LIN Slave Not Responding Error Interrupt Enable More...
 
#define US_IER_LINSTE   (0x1u << 30)
 (US_IER) LIN Synch Tolerance Error Interrupt Enable More...
 
#define US_IER_LINTC   (0x1u << 15)
 (US_IER) LIN Transfer Completed Interrupt Enable More...
 
#define US_IER_LRXD   (0x1u << 27)
 (US_IER) LON Reception Done Interrupt Enable More...
 
#define US_IER_LSFE   (0x1u << 6)
 (US_IER) LON Short Frame Error Interrupt Enable More...
 
#define US_IER_LTXD   (0x1u << 24)
 (US_IER) LON Transmission Done Interrupt Enable More...
 
#define US_IER_MANE   (0x1u << 24)
 (US_IER) Manchester Error Interrupt Enable More...
 
#define US_IER_NACK   (0x1u << 13)
 (US_IER) Non Acknowledge Interrupt Enable More...
 
#define US_IER_NSSE   (0x1u << 19)
 (US_IER) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable More...
 
#define US_IER_OVRE   (0x1u << 5)
 (US_IER) Overrun Error Interrupt Enable More...
 
#define US_IER_PARE   (0x1u << 7)
 (US_IER) Parity Error Interrupt Enable More...
 
#define US_IER_RIIC   (0x1u << 16)
 (US_IER) Ring Indicator Input Change Enable More...
 
#define US_IER_RXBRK   (0x1u << 2)
 (US_IER) Receiver Break Interrupt Enable More...
 
#define US_IER_RXRDY   (0x1u << 0)
 (US_IER) RXRDY Interrupt Enable More...
 
#define US_IER_TIMEOUT   (0x1u << 8)
 (US_IER) Time-out Interrupt Enable More...
 
#define US_IER_TXEMPTY   (0x1u << 9)
 (US_IER) TXEMPTY Interrupt Enable More...
 
#define US_IER_TXRDY   (0x1u << 1)
 (US_IER) TXRDY Interrupt Enable More...
 
#define US_IER_UNRE   (0x1u << 10)
 (US_IER) SPI Underrun Error Interrupt Enable More...
 
#define US_IF_IRDA_FILTER(value)   ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
 
#define US_IF_IRDA_FILTER_Msk   (0xffu << US_IF_IRDA_FILTER_Pos)
 (US_IF) IrDA Filter More...
 
#define US_IF_IRDA_FILTER_Pos   0
 
#define US_IMR_CTSIC   (0x1u << 19)
 (US_IMR) Clear to Send Input Change Interrupt Mask More...
 
#define US_IMR_DCDIC   (0x1u << 18)
 (US_IMR) Data Carrier Detect Input Change Interrupt Mask More...
 
#define US_IMR_DSRIC   (0x1u << 17)
 (US_IMR) Data Set Ready Input Change Mask More...
 
#define US_IMR_FRAME   (0x1u << 6)
 (US_IMR) Framing Error Interrupt Mask More...
 
#define US_IMR_ITER   (0x1u << 10)
 (US_IMR) Max Number of Repetitions Reached Interrupt Mask More...
 
#define US_IMR_LBLOVFE   (0x1u << 28)
 (US_IMR) LON Backlog Overflow Error Interrupt Mask More...
 
#define US_IMR_LCOL   (0x1u << 25)
 (US_IMR) LON Collision Interrupt Mask More...
 
#define US_IMR_LCRCE   (0x1u << 7)
 (US_IMR) LON CRC Error Interrupt Mask More...
 
#define US_IMR_LFET   (0x1u << 26)
 (US_IMR) LON Frame Early Termination Interrupt Mask More...
 
#define US_IMR_LINBE   (0x1u << 25)
 (US_IMR) LIN Bus Error Interrupt Mask More...
 
#define US_IMR_LINBK   (0x1u << 13)
 (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask More...
 
#define US_IMR_LINCE   (0x1u << 28)
 (US_IMR) LIN Checksum Error Interrupt Mask More...
 
#define US_IMR_LINHTE   (0x1u << 31)
 (US_IMR) LIN Header Timeout Error Interrupt Mask More...
 
#define US_IMR_LINID   (0x1u << 14)
 (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask More...
 
#define US_IMR_LINIPE   (0x1u << 27)
 (US_IMR) LIN Identifier Parity Interrupt Mask More...
 
#define US_IMR_LINISFE   (0x1u << 26)
 (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask More...
 
#define US_IMR_LINSNRE   (0x1u << 29)
 (US_IMR) LIN Slave Not Responding Error Interrupt Mask More...
 
#define US_IMR_LINSTE   (0x1u << 30)
 (US_IMR) LIN Synch Tolerance Error Interrupt Mask More...
 
#define US_IMR_LINTC   (0x1u << 15)
 (US_IMR) LIN Transfer Completed Interrupt Mask More...
 
#define US_IMR_LRXD   (0x1u << 27)
 (US_IMR) LON Reception Done Interrupt Mask More...
 
#define US_IMR_LSFE   (0x1u << 6)
 (US_IMR) LON Short Frame Error Interrupt Mask More...
 
#define US_IMR_LTXD   (0x1u << 24)
 (US_IMR) LON Transmission Done Interrupt Mask More...
 
#define US_IMR_MANE   (0x1u << 24)
 (US_IMR) Manchester Error Interrupt Mask More...
 
#define US_IMR_NACK   (0x1u << 13)
 (US_IMR) Non Acknowledge Interrupt Mask More...
 
#define US_IMR_NSSE   (0x1u << 19)
 (US_IMR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask More...
 
#define US_IMR_OVRE   (0x1u << 5)
 (US_IMR) Overrun Error Interrupt Mask More...
 
#define US_IMR_PARE   (0x1u << 7)
 (US_IMR) Parity Error Interrupt Mask More...
 
#define US_IMR_RIIC   (0x1u << 16)
 (US_IMR) Ring Indicator Input Change Mask More...
 
#define US_IMR_RXBRK   (0x1u << 2)
 (US_IMR) Receiver Break Interrupt Mask More...
 
#define US_IMR_RXRDY   (0x1u << 0)
 (US_IMR) RXRDY Interrupt Mask More...
 
#define US_IMR_TIMEOUT   (0x1u << 8)
 (US_IMR) Time-out Interrupt Mask More...
 
#define US_IMR_TXEMPTY   (0x1u << 9)
 (US_IMR) TXEMPTY Interrupt Mask More...
 
#define US_IMR_TXRDY   (0x1u << 1)
 (US_IMR) TXRDY Interrupt Mask More...
 
#define US_IMR_UNRE   (0x1u << 10)
 (US_IMR) SPI Underrun Error Interrupt Mask More...
 
#define US_LINBRR_LINCD_Msk   (0xffffu << US_LINBRR_LINCD_Pos)
 (US_LINBRR) Clock Divider after Synchronization More...
 
#define US_LINBRR_LINCD_Pos   0
 
#define US_LINBRR_LINFP_Msk   (0x7u << US_LINBRR_LINFP_Pos)
 (US_LINBRR) Fractional Part after Synchronization More...
 
#define US_LINBRR_LINFP_Pos   16
 
#define US_LINIR_IDCHR(value)   ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)))
 
#define US_LINIR_IDCHR_Msk   (0xffu << US_LINIR_IDCHR_Pos)
 (US_LINIR) Identifier Character More...
 
#define US_LINIR_IDCHR_Pos   0
 
#define US_LINMR_CHKDIS   (0x1u << 3)
 (US_LINMR) Checksum Disable More...
 
#define US_LINMR_CHKTYP   (0x1u << 4)
 (US_LINMR) Checksum Type More...
 
#define US_LINMR_DLC(value)   ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)))
 
#define US_LINMR_DLC_Msk   (0xffu << US_LINMR_DLC_Pos)
 (US_LINMR) Data Length Control More...
 
#define US_LINMR_DLC_Pos   8
 
#define US_LINMR_DLM   (0x1u << 5)
 (US_LINMR) Data Length Mode More...
 
#define US_LINMR_FSDIS   (0x1u << 6)
 (US_LINMR) Frame Slot Mode Disable More...
 
#define US_LINMR_NACT(value)   ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos)))
 
#define US_LINMR_NACT_IGNORE   (0x2u << 0)
 (US_LINMR) The USART does not transmit and does not receive the response. More...
 
#define US_LINMR_NACT_Msk   (0x3u << US_LINMR_NACT_Pos)
 (US_LINMR) LIN Node Action More...
 
#define US_LINMR_NACT_Pos   0
 
#define US_LINMR_NACT_PUBLISH   (0x0u << 0)
 (US_LINMR) The USART transmits the response. More...
 
#define US_LINMR_NACT_SUBSCRIBE   (0x1u << 0)
 (US_LINMR) The USART receives the response. More...
 
#define US_LINMR_PARDIS   (0x1u << 2)
 (US_LINMR) Parity Disable More...
 
#define US_LINMR_PDCM   (0x1u << 16)
 (US_LINMR) DMAC Mode More...
 
#define US_LINMR_SYNCDIS   (0x1u << 17)
 (US_LINMR) Synchronization Disable More...
 
#define US_LINMR_WKUPTYP   (0x1u << 7)
 (US_LINMR) Wakeup Signal Type More...
 
#define US_LONB1RX_BETA1RX(value)   ((US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos)))
 
#define US_LONB1RX_BETA1RX_Msk   (0xffffffu << US_LONB1RX_BETA1RX_Pos)
 (US_LONB1RX) LON Beta1 Length after Reception More...
 
#define US_LONB1RX_BETA1RX_Pos   0
 
#define US_LONB1TX_BETA1TX(value)   ((US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos)))
 
#define US_LONB1TX_BETA1TX_Msk   (0xffffffu << US_LONB1TX_BETA1TX_Pos)
 (US_LONB1TX) LON Beta1 Length after Transmission More...
 
#define US_LONB1TX_BETA1TX_Pos   0
 
#define US_LONBL_LONBL_Msk   (0x3fu << US_LONBL_LONBL_Pos)
 (US_LONBL) LON Node Backlog Value More...
 
#define US_LONBL_LONBL_Pos   0
 
#define US_LONDL_LONDL(value)   ((US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos)))
 
#define US_LONDL_LONDL_Msk   (0xffu << US_LONDL_LONDL_Pos)
 (US_LONDL) LON Data Length More...
 
#define US_LONDL_LONDL_Pos   0
 
#define US_LONL2HDR_ALTP   (0x1u << 6)
 (US_LONL2HDR) LON Alternate Path Bit More...
 
#define US_LONL2HDR_BLI(value)   ((US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos)))
 
#define US_LONL2HDR_BLI_Msk   (0x3fu << US_LONL2HDR_BLI_Pos)
 (US_LONL2HDR) LON Backlog Increment More...
 
#define US_LONL2HDR_BLI_Pos   0
 
#define US_LONL2HDR_PB   (0x1u << 7)
 (US_LONL2HDR) LON Priority Bit More...
 
#define US_LONMR_CDTAIL   (0x1u << 3)
 (US_LONMR) LON Collision Detection on Frame Tail More...
 
#define US_LONMR_COLDET   (0x1u << 1)
 (US_LONMR) LON Collision Detection Feature More...
 
#define US_LONMR_COMMT   (0x1u << 0)
 (US_LONMR) LON comm_type Parameter Value More...
 
#define US_LONMR_DMAM   (0x1u << 4)
 (US_LONMR) LON DMA Mode More...
 
#define US_LONMR_EOFS(value)   ((US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos)))
 
#define US_LONMR_EOFS_Msk   (0xffu << US_LONMR_EOFS_Pos)
 (US_LONMR) End of Frame Condition Size More...
 
#define US_LONMR_EOFS_Pos   16
 
#define US_LONMR_LCDS   (0x1u << 5)
 (US_LONMR) LON Collision Detection Source More...
 
#define US_LONMR_TCOL   (0x1u << 2)
 (US_LONMR) Terminate Frame upon Collision Notification More...
 
#define US_LONPR_LONPL(value)   ((US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos)))
 
#define US_LONPR_LONPL_Msk   (0x3fffu << US_LONPR_LONPL_Pos)
 (US_LONPR) LON Preamble Length More...
 
#define US_LONPR_LONPL_Pos   0
 
#define US_LONPRIO_NPS(value)   ((US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos)))
 
#define US_LONPRIO_NPS_Msk   (0x7fu << US_LONPRIO_NPS_Pos)
 (US_LONPRIO) LON Node Priority Slot More...
 
#define US_LONPRIO_NPS_Pos   8
 
#define US_LONPRIO_PSNB(value)   ((US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos)))
 
#define US_LONPRIO_PSNB_Msk   (0x7fu << US_LONPRIO_PSNB_Pos)
 (US_LONPRIO) LON Priority Slot Number More...
 
#define US_LONPRIO_PSNB_Pos   0
 
#define US_MAN_DRIFT   (0x1u << 30)
 (US_MAN) Drift Compensation More...
 
#define US_MAN_ONE   (0x1u << 29)
 (US_MAN) Must Be Set to 1 More...
 
#define US_MAN_RX_MPOL   (0x1u << 28)
 (US_MAN) Receiver Manchester Polarity More...
 
#define US_MAN_RX_PL(value)   ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
 
#define US_MAN_RX_PL_Msk   (0xfu << US_MAN_RX_PL_Pos)
 (US_MAN) Receiver Preamble Length More...
 
#define US_MAN_RX_PL_Pos   16
 
#define US_MAN_RX_PP(value)   ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos)))
 
#define US_MAN_RX_PP_ALL_ONE   (0x0u << 24)
 (US_MAN) The preamble is composed of '1's More...
 
#define US_MAN_RX_PP_ALL_ZERO   (0x1u << 24)
 (US_MAN) The preamble is composed of '0's More...
 
#define US_MAN_RX_PP_Msk   (0x3u << US_MAN_RX_PP_Pos)
 (US_MAN) Receiver Preamble Pattern detected More...
 
#define US_MAN_RX_PP_ONE_ZERO   (0x3u << 24)
 (US_MAN) The preamble is composed of '10's More...
 
#define US_MAN_RX_PP_Pos   24
 
#define US_MAN_RX_PP_ZERO_ONE   (0x2u << 24)
 (US_MAN) The preamble is composed of '01's More...
 
#define US_MAN_RXIDLEV   (0x1u << 31)
 (US_MAN) More...
 
#define US_MAN_TX_MPOL   (0x1u << 12)
 (US_MAN) Transmitter Manchester Polarity More...
 
#define US_MAN_TX_PL(value)   ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
 
#define US_MAN_TX_PL_Msk   (0xfu << US_MAN_TX_PL_Pos)
 (US_MAN) Transmitter Preamble Length More...
 
#define US_MAN_TX_PL_Pos   0
 
#define US_MAN_TX_PP(value)   ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos)))
 
#define US_MAN_TX_PP_ALL_ONE   (0x0u << 8)
 (US_MAN) The preamble is composed of '1's More...
 
#define US_MAN_TX_PP_ALL_ZERO   (0x1u << 8)
 (US_MAN) The preamble is composed of '0's More...
 
#define US_MAN_TX_PP_Msk   (0x3u << US_MAN_TX_PP_Pos)
 (US_MAN) Transmitter Preamble Pattern More...
 
#define US_MAN_TX_PP_ONE_ZERO   (0x3u << 8)
 (US_MAN) The preamble is composed of '10's More...
 
#define US_MAN_TX_PP_Pos   8
 
#define US_MAN_TX_PP_ZERO_ONE   (0x2u << 8)
 (US_MAN) The preamble is composed of '01's More...
 
#define US_MR_CHMODE(value)   ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos)))
 
#define US_MR_CHMODE_AUTOMATIC   (0x1u << 14)
 (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. More...
 
#define US_MR_CHMODE_LOCAL_LOOPBACK   (0x2u << 14)
 (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. More...
 
#define US_MR_CHMODE_Msk   (0x3u << US_MR_CHMODE_Pos)
 (US_MR) Channel Mode More...
 
#define US_MR_CHMODE_NORMAL   (0x0u << 14)
 (US_MR) Normal mode More...
 
#define US_MR_CHMODE_Pos   14
 
#define US_MR_CHMODE_REMOTE_LOOPBACK   (0x3u << 14)
 (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. More...
 
#define US_MR_CHRL(value)   ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos)))
 
#define US_MR_CHRL_5_BIT   (0x0u << 6)
 (US_MR) Character length is 5 bits More...
 
#define US_MR_CHRL_6_BIT   (0x1u << 6)
 (US_MR) Character length is 6 bits More...
 
#define US_MR_CHRL_7_BIT   (0x2u << 6)
 (US_MR) Character length is 7 bits More...
 
#define US_MR_CHRL_8_BIT   (0x3u << 6)
 (US_MR) Character length is 8 bits More...
 
#define US_MR_CHRL_Msk   (0x3u << US_MR_CHRL_Pos)
 (US_MR) Character Length More...
 
#define US_MR_CHRL_Pos   6
 
#define US_MR_CLKO   (0x1u << 18)
 (US_MR) Clock Output Select More...
 
#define US_MR_CPHA   (0x1u << 8)
 (US_MR) SPI Clock Phase More...
 
#define US_MR_CPOL   (0x1u << 16)
 (US_MR) SPI Clock Polarity More...
 
#define US_MR_DSNACK   (0x1u << 21)
 (US_MR) Disable Successive NACK More...
 
#define US_MR_FILTER   (0x1u << 28)
 (US_MR) Receive Line Filter More...
 
#define US_MR_INACK   (0x1u << 20)
 (US_MR) Inhibit Non Acknowledge More...
 
#define US_MR_INVDATA   (0x1u << 23)
 (US_MR) Inverted Data More...
 
#define US_MR_MAN   (0x1u << 29)
 (US_MR) Manchester Encoder/Decoder Enable More...
 
#define US_MR_MAX_ITERATION(value)   ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
 
#define US_MR_MAX_ITERATION_Msk   (0x7u << US_MR_MAX_ITERATION_Pos)
 (US_MR) Maximum Number of Automatic Iteration More...
 
#define US_MR_MAX_ITERATION_Pos   24
 
#define US_MR_MODE9   (0x1u << 17)
 (US_MR) 9-bit Character Length More...
 
#define US_MR_MODSYNC   (0x1u << 30)
 (US_MR) Manchester Synchronization Mode More...
 
#define US_MR_MSBF   (0x1u << 16)
 (US_MR) Bit Order More...
 
#define US_MR_NBSTOP(value)   ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos)))
 
#define US_MR_NBSTOP_1_5_BIT   (0x1u << 12)
 (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) More...
 
#define US_MR_NBSTOP_1_BIT   (0x0u << 12)
 (US_MR) 1 stop bit More...
 
#define US_MR_NBSTOP_2_BIT   (0x2u << 12)
 (US_MR) 2 stop bits More...
 
#define US_MR_NBSTOP_Msk   (0x3u << US_MR_NBSTOP_Pos)
 (US_MR) Number of Stop Bits More...
 
#define US_MR_NBSTOP_Pos   12
 
#define US_MR_ONEBIT   (0x1u << 31)
 (US_MR) Start Frame Delimiter Selector More...
 
#define US_MR_OVER   (0x1u << 19)
 (US_MR) Oversampling Mode More...
 
#define US_MR_PAR(value)   ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos)))
 
#define US_MR_PAR_EVEN   (0x0u << 9)
 (US_MR) Even parity More...
 
#define US_MR_PAR_MARK   (0x3u << 9)
 (US_MR) Parity forced to 1 (Mark) More...
 
#define US_MR_PAR_Msk   (0x7u << US_MR_PAR_Pos)
 (US_MR) Parity Type More...
 
#define US_MR_PAR_MULTIDROP   (0x6u << 9)
 (US_MR) Multidrop mode More...
 
#define US_MR_PAR_NO   (0x4u << 9)
 (US_MR) No parity More...
 
#define US_MR_PAR_ODD   (0x1u << 9)
 (US_MR) Odd parity More...
 
#define US_MR_PAR_Pos   9
 
#define US_MR_PAR_SPACE   (0x2u << 9)
 (US_MR) Parity forced to 0 (Space) More...
 
#define US_MR_SYNC   (0x1u << 8)
 (US_MR) Synchronous Mode Select More...
 
#define US_MR_USART_MODE(value)   ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos)))
 
#define US_MR_USART_MODE_HW_HANDSHAKING   (0x2u << 0)
 (US_MR) Hardware Handshaking More...
 
#define US_MR_USART_MODE_IRDA   (0x8u << 0)
 (US_MR) IrDA More...
 
#define US_MR_USART_MODE_IS07816_T_0   (0x4u << 0)
 (US_MR) IS07816 Protocol: T = 0 More...
 
#define US_MR_USART_MODE_IS07816_T_1   (0x6u << 0)
 (US_MR) IS07816 Protocol: T = 1 More...
 
#define US_MR_USART_MODE_LIN_MASTER   (0xAu << 0)
 (US_MR) LIN Master mode More...
 
#define US_MR_USART_MODE_LIN_SLAVE   (0xBu << 0)
 (US_MR) LIN Slave mode More...
 
#define US_MR_USART_MODE_LON   (0x9u << 0)
 (US_MR) LON More...
 
#define US_MR_USART_MODE_MODEM   (0x3u << 0)
 (US_MR) Modem More...
 
#define US_MR_USART_MODE_Msk   (0xfu << US_MR_USART_MODE_Pos)
 (US_MR) USART Mode of Operation More...
 
#define US_MR_USART_MODE_NORMAL   (0x0u << 0)
 (US_MR) Normal mode More...
 
#define US_MR_USART_MODE_Pos   0
 
#define US_MR_USART_MODE_RS485   (0x1u << 0)
 (US_MR) RS485 More...
 
#define US_MR_USART_MODE_SPI_MASTER   (0xEu << 0)
 (US_MR) SPI master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) More...
 
#define US_MR_USART_MODE_SPI_SLAVE   (0xFu << 0)
 (US_MR) SPI Slave mode More...
 
#define US_MR_USCLKS(value)   ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos)))
 
#define US_MR_USCLKS_DIV   (0x1u << 4)
 (US_MR) Peripheral clock divided (DIV=DIV=8) is selected More...
 
#define US_MR_USCLKS_MCK   (0x0u << 4)
 (US_MR) Peripheral clock is selected More...
 
#define US_MR_USCLKS_Msk   (0x3u << US_MR_USCLKS_Pos)
 (US_MR) Clock Selection More...
 
#define US_MR_USCLKS_PCK   (0x2u << 4)
 (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. More...
 
#define US_MR_USCLKS_Pos   4
 
#define US_MR_USCLKS_SCK   (0x3u << 4)
 (US_MR) Serial clock (SCK) is selected More...
 
#define US_MR_VAR_SYNC   (0x1u << 22)
 (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter More...
 
#define US_MR_WRDBT   (0x1u << 20)
 (US_MR) Wait Read Data Before Transfer More...
 
#define US_NER_NB_ERRORS_Msk   (0xffu << US_NER_NB_ERRORS_Pos)
 (US_NER) Number of Errors More...
 
#define US_NER_NB_ERRORS_Pos   0
 
#define US_RHR_RXCHR_Msk   (0x1ffu << US_RHR_RXCHR_Pos)
 (US_RHR) Received Character More...
 
#define US_RHR_RXCHR_Pos   0
 
#define US_RHR_RXSYNH   (0x1u << 15)
 (US_RHR) Received Sync More...
 
#define US_RTOR_TO(value)   ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
 
#define US_RTOR_TO_Msk   (0x1ffffu << US_RTOR_TO_Pos)
 (US_RTOR) Time-out Value More...
 
#define US_RTOR_TO_Pos   0
 
#define US_THR_TXCHR(value)   ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
 
#define US_THR_TXCHR_Msk   (0x1ffu << US_THR_TXCHR_Pos)
 (US_THR) Character to be Transmitted More...
 
#define US_THR_TXCHR_Pos   0
 
#define US_THR_TXSYNH   (0x1u << 15)
 (US_THR) Sync Field to be Transmitted More...
 
#define US_TTGR_PCYCLE(value)   ((US_TTGR_PCYCLE_Msk & ((value) << US_TTGR_PCYCLE_Pos)))
 
#define US_TTGR_PCYCLE_Msk   (0xffffffu << US_TTGR_PCYCLE_Pos)
 (US_TTGR) LON PCYCLE Length More...
 
#define US_TTGR_PCYCLE_Pos   0
 
#define US_TTGR_TG(value)   ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
 
#define US_TTGR_TG_Msk   (0xffu << US_TTGR_TG_Pos)
 (US_TTGR) Timeguard Value More...
 
#define US_TTGR_TG_Pos   0
 
#define US_VERSION_MFN_Msk   (0x7u << US_VERSION_MFN_Pos)
 (US_VERSION) Metal Fix Number More...
 
#define US_VERSION_MFN_Pos   16
 
#define US_VERSION_VERSION_Msk   (0xfffu << US_VERSION_VERSION_Pos)
 (US_VERSION) Hardware Module Version More...
 
#define US_VERSION_VERSION_Pos   0
 
#define US_WPMR_WPEN   (0x1u << 0)
 (US_WPMR) Write Protection Enable More...
 
#define US_WPMR_WPKEY(value)   ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
 
#define US_WPMR_WPKEY_Msk   (0xffffffu << US_WPMR_WPKEY_Pos)
 (US_WPMR) Write Protection Key More...
 
#define US_WPMR_WPKEY_PASSWD   (0x555341u << 8)
 (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. More...
 
#define US_WPMR_WPKEY_Pos   8
 
#define US_WPSR_WPVS   (0x1u << 0)
 (US_WPSR) Write Protection Violation Status More...
 
#define US_WPSR_WPVSRC_Msk   (0xffffu << US_WPSR_WPVSRC_Pos)
 (US_WPSR) Write Protection Violation Source More...
 
#define US_WPSR_WPVSRC_Pos   8
 

Detailed Description

SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter

Macro Definition Documentation

◆ US_BRGR_CD

#define US_BRGR_CD (   value)    ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))

◆ US_BRGR_CD_Msk

#define US_BRGR_CD_Msk   (0xffffu << US_BRGR_CD_Pos)

(US_BRGR) Clock Divider

Definition at line 336 of file utils/cmsis/same70/include/component/usart.h.

◆ US_BRGR_CD_Pos

#define US_BRGR_CD_Pos   0

◆ US_BRGR_FP

#define US_BRGR_FP (   value)    ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))

◆ US_BRGR_FP_Msk

#define US_BRGR_FP_Msk   (0x7u << US_BRGR_FP_Pos)

(US_BRGR) Fractional Part

Definition at line 339 of file utils/cmsis/same70/include/component/usart.h.

◆ US_BRGR_FP_Pos

#define US_BRGR_FP_Pos   16

◆ US_CR_DTRDIS

#define US_CR_DTRDIS   (0x1u << 17)

(US_CR) Data Terminal Ready Disable

Definition at line 101 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_DTREN

#define US_CR_DTREN   (0x1u << 16)

(US_CR) Data Terminal Ready Enable

Definition at line 100 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_FCS

#define US_CR_FCS   (0x1u << 18)

(US_CR) Force SPI Chip Select

Definition at line 106 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_LINABT

#define US_CR_LINABT   (0x1u << 20)

(US_CR) Abort LIN Transmission

Definition at line 104 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_LINWKUP

#define US_CR_LINWKUP   (0x1u << 21)

(US_CR) Send LIN Wakeup Signal

Definition at line 105 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_RCS

#define US_CR_RCS   (0x1u << 19)

(US_CR) Release SPI Chip Select

Definition at line 107 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_RETTO

#define US_CR_RETTO   (0x1u << 15)

(US_CR) Start Time-out Immediately

Definition at line 99 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_RSTIT

#define US_CR_RSTIT   (0x1u << 13)

(US_CR) Reset Iterations

Definition at line 97 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_RSTNACK

#define US_CR_RSTNACK   (0x1u << 14)

(US_CR) Reset Non Acknowledge

Definition at line 98 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_RSTRX

#define US_CR_RSTRX   (0x1u << 2)

(US_CR) Reset Receiver

Definition at line 86 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_RSTSTA

#define US_CR_RSTSTA   (0x1u << 8)

(US_CR) Reset Status Bits

Definition at line 92 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_RSTTX

#define US_CR_RSTTX   (0x1u << 3)

(US_CR) Reset Transmitter

Definition at line 87 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_RTSDIS

#define US_CR_RTSDIS   (0x1u << 19)

(US_CR) Request to Send Pin Control

Definition at line 103 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_RTSEN

#define US_CR_RTSEN   (0x1u << 18)

(US_CR) Request to Send Pin Control

Definition at line 102 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_RXDIS

#define US_CR_RXDIS   (0x1u << 5)

(US_CR) Receiver Disable

Definition at line 89 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_RXEN

#define US_CR_RXEN   (0x1u << 4)

(US_CR) Receiver Enable

Definition at line 88 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_SENDA

#define US_CR_SENDA   (0x1u << 12)

(US_CR) Send Address

Definition at line 96 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_STPBRK

#define US_CR_STPBRK   (0x1u << 10)

(US_CR) Stop Break

Definition at line 94 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_STTBRK

#define US_CR_STTBRK   (0x1u << 9)

(US_CR) Start Break

Definition at line 93 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_STTTO

#define US_CR_STTTO   (0x1u << 11)

(US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received

Definition at line 95 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_TXDIS

#define US_CR_TXDIS   (0x1u << 7)

(US_CR) Transmitter Disable

Definition at line 91 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CR_TXEN

#define US_CR_TXEN   (0x1u << 6)

(US_CR) Transmitter Enable

Definition at line 90 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_CTS

#define US_CSR_CTS   (0x1u << 23)

(US_CSR) Image of CTS Input

Definition at line 302 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_CTSIC

#define US_CSR_CTSIC   (0x1u << 19)

(US_CSR) Clear to Send Input Change Flag (cleared on read)

Definition at line 298 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_DCD

#define US_CSR_DCD   (0x1u << 22)

(US_CSR) Image of DCD Input

Definition at line 301 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_DCDIC

#define US_CSR_DCDIC   (0x1u << 18)

(US_CSR) Data Carrier Detect Input Change Flag (cleared on read)

Definition at line 297 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_DSR

#define US_CSR_DSR   (0x1u << 21)

(US_CSR) Image of DSR Input

Definition at line 300 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_DSRIC

#define US_CSR_DSRIC   (0x1u << 17)

(US_CSR) Data Set Ready Input Change Flag (cleared on read)

Definition at line 296 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_FRAME

#define US_CSR_FRAME   (0x1u << 6)

(US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 289 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_ITER

#define US_CSR_ITER   (0x1u << 10)

(US_CSR) Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT)

Definition at line 293 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_LBLOVFE

#define US_CSR_LBLOVFE   (0x1u << 28)

(US_CSR) LON Backlog Overflow Error (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 324 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_LCOL

#define US_CSR_LCOL   (0x1u << 25)

(US_CSR) LON Collision Detected Flag (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 321 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_LCRCE

#define US_CSR_LCRCE   (0x1u << 7)

(US_CSR) LON CRC Error (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 319 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_LFET

#define US_CSR_LFET   (0x1u << 26)

(US_CSR) LON Frame Early Termination (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 322 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_LINBE

#define US_CSR_LINBE   (0x1u << 25)

(US_CSR) LIN Bit Error (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 311 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_LINBK

#define US_CSR_LINBK   (0x1u << 13)

(US_CSR) LIN Break Sent or LIN Break Received (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 307 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_LINBLS

#define US_CSR_LINBLS   (0x1u << 23)

(US_CSR) LIN Bus Line Status

Definition at line 310 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_LINCE

#define US_CSR_LINCE   (0x1u << 28)

(US_CSR) LIN Checksum Error (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 314 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_LINHTE

#define US_CSR_LINHTE   (0x1u << 31)

(US_CSR) LIN Header Timeout Error (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 317 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_LINID

#define US_CSR_LINID   (0x1u << 14)

(US_CSR) LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 308 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_LINIPE

#define US_CSR_LINIPE   (0x1u << 27)

(US_CSR) LIN Identifier Parity Error (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 313 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_LINISFE

#define US_CSR_LINISFE   (0x1u << 26)

(US_CSR) LIN Inconsistent Synch Field Error (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 312 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_LINSNRE

#define US_CSR_LINSNRE   (0x1u << 29)

(US_CSR) LIN Slave Not Responding Error (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 315 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_LINSTE

#define US_CSR_LINSTE   (0x1u << 30)

(US_CSR) LIN Synch Tolerance Error (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 316 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_LINTC

#define US_CSR_LINTC   (0x1u << 15)

(US_CSR) LIN Transfer Completed (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 309 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_LRXD

#define US_CSR_LRXD   (0x1u << 27)

(US_CSR) LON Reception End Flag (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 323 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_LSFE

#define US_CSR_LSFE   (0x1u << 6)

(US_CSR) LON Short Frame Error (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 318 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_LTXD

#define US_CSR_LTXD   (0x1u << 24)

(US_CSR) LON Transmission End Flag (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 320 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_MANERR

#define US_CSR_MANERR   (0x1u << 24)

(US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA)

Definition at line 303 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_NACK

#define US_CSR_NACK   (0x1u << 13)

(US_CSR) Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK)

Definition at line 294 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_NSS

#define US_CSR_NSS   (0x1u << 23)

(US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read)

Definition at line 306 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_NSSE

#define US_CSR_NSSE   (0x1u << 19)

(US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read)

Definition at line 305 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_OVRE

#define US_CSR_OVRE   (0x1u << 5)

(US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 288 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_PARE

#define US_CSR_PARE   (0x1u << 7)

(US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 290 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_RI

#define US_CSR_RI   (0x1u << 20)

(US_CSR) Image of RI Input

Definition at line 299 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_RIIC

#define US_CSR_RIIC   (0x1u << 16)

(US_CSR) Ring Indicator Input Change Flag (cleared on read)

Definition at line 295 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_RXBRK

#define US_CSR_RXBRK   (0x1u << 2)

(US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 287 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_RXRDY

#define US_CSR_RXRDY   (0x1u << 0)

(US_CSR) Receiver Ready (cleared by reading US_RHR)

Definition at line 285 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_TIMEOUT

#define US_CSR_TIMEOUT   (0x1u << 8)

(US_CSR) Receiver Time-out (cleared by writing a one to bit US_CR.STTTO)

Definition at line 291 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_TXEMPTY

#define US_CSR_TXEMPTY   (0x1u << 9)

(US_CSR) Transmitter Empty (cleared by writing US_THR)

Definition at line 292 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_TXRDY

#define US_CSR_TXRDY   (0x1u << 1)

(US_CSR) Transmitter Ready (cleared by writing US_THR)

Definition at line 286 of file utils/cmsis/same70/include/component/usart.h.

◆ US_CSR_UNRE

#define US_CSR_UNRE   (0x1u << 10)

(US_CSR) Underrun Error (cleared by writing a one to bit US_CR.RSTSTA)

Definition at line 304 of file utils/cmsis/same70/include/component/usart.h.

◆ US_FIDI_BETA2

#define US_FIDI_BETA2 (   value)    ((US_FIDI_BETA2_Msk & ((value) << US_FIDI_BETA2_Pos)))

◆ US_FIDI_BETA2_Msk

#define US_FIDI_BETA2_Msk   (0xffffffu << US_FIDI_BETA2_Pos)

(US_FIDI) LON BETA2 Length

Definition at line 357 of file utils/cmsis/same70/include/component/usart.h.

◆ US_FIDI_BETA2_Pos

#define US_FIDI_BETA2_Pos   0

◆ US_FIDI_FI_DI_RATIO

#define US_FIDI_FI_DI_RATIO (   value)    ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))

◆ US_FIDI_FI_DI_RATIO_Msk

#define US_FIDI_FI_DI_RATIO_Msk   (0xffffu << US_FIDI_FI_DI_RATIO_Pos)

(US_FIDI) FI Over DI Ratio Value

Definition at line 354 of file utils/cmsis/same70/include/component/usart.h.

◆ US_FIDI_FI_DI_RATIO_Pos

#define US_FIDI_FI_DI_RATIO_Pos   0

◆ US_ICDIFF_ICDIFF

#define US_ICDIFF_ICDIFF (   value)    ((US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos)))

◆ US_ICDIFF_ICDIFF_Msk

#define US_ICDIFF_ICDIFF_Msk   (0xfu << US_ICDIFF_ICDIFF_Pos)

(US_ICDIFF) IC Differentiator Number

Definition at line 471 of file utils/cmsis/same70/include/component/usart.h.

◆ US_ICDIFF_ICDIFF_Pos

#define US_ICDIFF_ICDIFF_Pos   0

◆ US_IDR_CTSIC

#define US_IDR_CTSIC   (0x1u << 19)

(US_IDR) Clear to Send Input Change Interrupt Disable

Definition at line 228 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_DCDIC

#define US_IDR_DCDIC   (0x1u << 18)

(US_IDR) Data Carrier Detect Input Change Interrupt Disable

Definition at line 227 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_DSRIC

#define US_IDR_DSRIC   (0x1u << 17)

(US_IDR) Data Set Ready Input Change Disable

Definition at line 226 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_FRAME

#define US_IDR_FRAME   (0x1u << 6)

(US_IDR) Framing Error Interrupt Disable

Definition at line 219 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_ITER

#define US_IDR_ITER   (0x1u << 10)

(US_IDR) Max Number of Repetitions Reached Interrupt Disable

Definition at line 223 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_LBLOVFE

#define US_IDR_LBLOVFE   (0x1u << 28)

(US_IDR) LON Backlog Overflow Error Interrupt Disable

Definition at line 248 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_LCOL

#define US_IDR_LCOL   (0x1u << 25)

(US_IDR) LON Collision Interrupt Disable

Definition at line 245 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_LCRCE

#define US_IDR_LCRCE   (0x1u << 7)

(US_IDR) LON CRC Error Interrupt Disable

Definition at line 243 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_LFET

#define US_IDR_LFET   (0x1u << 26)

(US_IDR) LON Frame Early Termination Interrupt Disable

Definition at line 246 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_LINBE

#define US_IDR_LINBE   (0x1u << 25)

(US_IDR) LIN Bus Error Interrupt Disable

Definition at line 235 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_LINBK

#define US_IDR_LINBK   (0x1u << 13)

(US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable

Definition at line 232 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_LINCE

#define US_IDR_LINCE   (0x1u << 28)

(US_IDR) LIN Checksum Error Interrupt Disable

Definition at line 238 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_LINHTE

#define US_IDR_LINHTE   (0x1u << 31)

(US_IDR) LIN Header Timeout Error Interrupt Disable

Definition at line 241 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_LINID

#define US_IDR_LINID   (0x1u << 14)

(US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable

Definition at line 233 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_LINIPE

#define US_IDR_LINIPE   (0x1u << 27)

(US_IDR) LIN Identifier Parity Interrupt Disable

Definition at line 237 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_LINISFE

#define US_IDR_LINISFE   (0x1u << 26)

(US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable

Definition at line 236 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_LINSNRE

#define US_IDR_LINSNRE   (0x1u << 29)

(US_IDR) LIN Slave Not Responding Error Interrupt Disable

Definition at line 239 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_LINSTE

#define US_IDR_LINSTE   (0x1u << 30)

(US_IDR) LIN Synch Tolerance Error Interrupt Disable

Definition at line 240 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_LINTC

#define US_IDR_LINTC   (0x1u << 15)

(US_IDR) LIN Transfer Completed Interrupt Disable

Definition at line 234 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_LRXD

#define US_IDR_LRXD   (0x1u << 27)

(US_IDR) LON Reception Done Interrupt Disable

Definition at line 247 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_LSFE

#define US_IDR_LSFE   (0x1u << 6)

(US_IDR) LON Short Frame Error Interrupt Disable

Definition at line 242 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_LTXD

#define US_IDR_LTXD   (0x1u << 24)

(US_IDR) LON Transmission Done Interrupt Disable

Definition at line 244 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_MANE

#define US_IDR_MANE   (0x1u << 24)

(US_IDR) Manchester Error Interrupt Disable

Definition at line 229 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_NACK

#define US_IDR_NACK   (0x1u << 13)

(US_IDR) Non Acknowledge Interrupt Disable

Definition at line 224 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_NSSE

#define US_IDR_NSSE   (0x1u << 19)

(US_IDR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable

Definition at line 231 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_OVRE

#define US_IDR_OVRE   (0x1u << 5)

(US_IDR) Overrun Error Interrupt Enable

Definition at line 218 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_PARE

#define US_IDR_PARE   (0x1u << 7)

(US_IDR) Parity Error Interrupt Disable

Definition at line 220 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_RIIC

#define US_IDR_RIIC   (0x1u << 16)

(US_IDR) Ring Indicator Input Change Disable

Definition at line 225 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_RXBRK

#define US_IDR_RXBRK   (0x1u << 2)

(US_IDR) Receiver Break Interrupt Disable

Definition at line 217 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_RXRDY

#define US_IDR_RXRDY   (0x1u << 0)

(US_IDR) RXRDY Interrupt Disable

Definition at line 215 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_TIMEOUT

#define US_IDR_TIMEOUT   (0x1u << 8)

(US_IDR) Time-out Interrupt Disable

Definition at line 221 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_TXEMPTY

#define US_IDR_TXEMPTY   (0x1u << 9)

(US_IDR) TXEMPTY Interrupt Disable

Definition at line 222 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_TXRDY

#define US_IDR_TXRDY   (0x1u << 1)

(US_IDR) TXRDY Interrupt Disable

Definition at line 216 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDR_UNRE

#define US_IDR_UNRE   (0x1u << 10)

(US_IDR) SPI Underrun Error Interrupt Disable

Definition at line 230 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDTRX_IDTRX

#define US_IDTRX_IDTRX (   value)    ((US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos)))

◆ US_IDTRX_IDTRX_Msk

#define US_IDTRX_IDTRX_Msk   (0xffffffu << US_IDTRX_IDTRX_Pos)

(US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only)

Definition at line 467 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDTRX_IDTRX_Pos

#define US_IDTRX_IDTRX_Pos   0

◆ US_IDTTX_IDTTX

#define US_IDTTX_IDTTX (   value)    ((US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos)))

◆ US_IDTTX_IDTTX_Msk

#define US_IDTTX_IDTTX_Msk   (0xffffffu << US_IDTTX_IDTTX_Pos)

(US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only)

Definition at line 463 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IDTTX_IDTTX_Pos

#define US_IDTTX_IDTTX_Pos   0

◆ US_IER_CTSIC

#define US_IER_CTSIC   (0x1u << 19)

(US_IER) Clear to Send Input Change Interrupt Enable

Definition at line 193 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_DCDIC

#define US_IER_DCDIC   (0x1u << 18)

(US_IER) Data Carrier Detect Input Change Interrupt Enable

Definition at line 192 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_DSRIC

#define US_IER_DSRIC   (0x1u << 17)

(US_IER) Data Set Ready Input Change Enable

Definition at line 191 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_FRAME

#define US_IER_FRAME   (0x1u << 6)

(US_IER) Framing Error Interrupt Enable

Definition at line 184 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_ITER

#define US_IER_ITER   (0x1u << 10)

(US_IER) Max number of Repetitions Reached Interrupt Enable

Definition at line 188 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_LBLOVFE

#define US_IER_LBLOVFE   (0x1u << 28)

(US_IER) LON Backlog Overflow Error Interrupt Enable

Definition at line 213 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_LCOL

#define US_IER_LCOL   (0x1u << 25)

(US_IER) LON Collision Interrupt Enable

Definition at line 210 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_LCRCE

#define US_IER_LCRCE   (0x1u << 7)

(US_IER) LON CRC Error Interrupt Enable

Definition at line 208 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_LFET

#define US_IER_LFET   (0x1u << 26)

(US_IER) LON Frame Early Termination Interrupt Enable

Definition at line 211 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_LINBE

#define US_IER_LINBE   (0x1u << 25)

(US_IER) LIN Bus Error Interrupt Enable

Definition at line 200 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_LINBK

#define US_IER_LINBK   (0x1u << 13)

(US_IER) LIN Break Sent or LIN Break Received Interrupt Enable

Definition at line 197 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_LINCE

#define US_IER_LINCE   (0x1u << 28)

(US_IER) LIN Checksum Error Interrupt Enable

Definition at line 203 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_LINHTE

#define US_IER_LINHTE   (0x1u << 31)

(US_IER) LIN Header Timeout Error Interrupt Enable

Definition at line 206 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_LINID

#define US_IER_LINID   (0x1u << 14)

(US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable

Definition at line 198 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_LINIPE

#define US_IER_LINIPE   (0x1u << 27)

(US_IER) LIN Identifier Parity Interrupt Enable

Definition at line 202 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_LINISFE

#define US_IER_LINISFE   (0x1u << 26)

(US_IER) LIN Inconsistent Synch Field Error Interrupt Enable

Definition at line 201 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_LINSNRE

#define US_IER_LINSNRE   (0x1u << 29)

(US_IER) LIN Slave Not Responding Error Interrupt Enable

Definition at line 204 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_LINSTE

#define US_IER_LINSTE   (0x1u << 30)

(US_IER) LIN Synch Tolerance Error Interrupt Enable

Definition at line 205 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_LINTC

#define US_IER_LINTC   (0x1u << 15)

(US_IER) LIN Transfer Completed Interrupt Enable

Definition at line 199 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_LRXD

#define US_IER_LRXD   (0x1u << 27)

(US_IER) LON Reception Done Interrupt Enable

Definition at line 212 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_LSFE

#define US_IER_LSFE   (0x1u << 6)

(US_IER) LON Short Frame Error Interrupt Enable

Definition at line 207 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_LTXD

#define US_IER_LTXD   (0x1u << 24)

(US_IER) LON Transmission Done Interrupt Enable

Definition at line 209 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_MANE

#define US_IER_MANE   (0x1u << 24)

(US_IER) Manchester Error Interrupt Enable

Definition at line 194 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_NACK

#define US_IER_NACK   (0x1u << 13)

(US_IER) Non Acknowledge Interrupt Enable

Definition at line 189 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_NSSE

#define US_IER_NSSE   (0x1u << 19)

(US_IER) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable

Definition at line 196 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_OVRE

#define US_IER_OVRE   (0x1u << 5)

(US_IER) Overrun Error Interrupt Enable

Definition at line 183 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_PARE

#define US_IER_PARE   (0x1u << 7)

(US_IER) Parity Error Interrupt Enable

Definition at line 185 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_RIIC

#define US_IER_RIIC   (0x1u << 16)

(US_IER) Ring Indicator Input Change Enable

Definition at line 190 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_RXBRK

#define US_IER_RXBRK   (0x1u << 2)

(US_IER) Receiver Break Interrupt Enable

Definition at line 182 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_RXRDY

#define US_IER_RXRDY   (0x1u << 0)

(US_IER) RXRDY Interrupt Enable

Definition at line 180 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_TIMEOUT

#define US_IER_TIMEOUT   (0x1u << 8)

(US_IER) Time-out Interrupt Enable

Definition at line 186 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_TXEMPTY

#define US_IER_TXEMPTY   (0x1u << 9)

(US_IER) TXEMPTY Interrupt Enable

Definition at line 187 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_TXRDY

#define US_IER_TXRDY   (0x1u << 1)

(US_IER) TXRDY Interrupt Enable

Definition at line 181 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IER_UNRE

#define US_IER_UNRE   (0x1u << 10)

(US_IER) SPI Underrun Error Interrupt Enable

Definition at line 195 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IF_IRDA_FILTER

#define US_IF_IRDA_FILTER (   value)    ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))

◆ US_IF_IRDA_FILTER_Msk

#define US_IF_IRDA_FILTER_Msk   (0xffu << US_IF_IRDA_FILTER_Pos)

(US_IF) IrDA Filter

Definition at line 364 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IF_IRDA_FILTER_Pos

#define US_IF_IRDA_FILTER_Pos   0

◆ US_IMR_CTSIC

#define US_IMR_CTSIC   (0x1u << 19)

(US_IMR) Clear to Send Input Change Interrupt Mask

Definition at line 263 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_DCDIC

#define US_IMR_DCDIC   (0x1u << 18)

(US_IMR) Data Carrier Detect Input Change Interrupt Mask

Definition at line 262 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_DSRIC

#define US_IMR_DSRIC   (0x1u << 17)

(US_IMR) Data Set Ready Input Change Mask

Definition at line 261 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_FRAME

#define US_IMR_FRAME   (0x1u << 6)

(US_IMR) Framing Error Interrupt Mask

Definition at line 254 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_ITER

#define US_IMR_ITER   (0x1u << 10)

(US_IMR) Max Number of Repetitions Reached Interrupt Mask

Definition at line 258 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_LBLOVFE

#define US_IMR_LBLOVFE   (0x1u << 28)

(US_IMR) LON Backlog Overflow Error Interrupt Mask

Definition at line 283 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_LCOL

#define US_IMR_LCOL   (0x1u << 25)

(US_IMR) LON Collision Interrupt Mask

Definition at line 280 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_LCRCE

#define US_IMR_LCRCE   (0x1u << 7)

(US_IMR) LON CRC Error Interrupt Mask

Definition at line 278 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_LFET

#define US_IMR_LFET   (0x1u << 26)

(US_IMR) LON Frame Early Termination Interrupt Mask

Definition at line 281 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_LINBE

#define US_IMR_LINBE   (0x1u << 25)

(US_IMR) LIN Bus Error Interrupt Mask

Definition at line 270 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_LINBK

#define US_IMR_LINBK   (0x1u << 13)

(US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask

Definition at line 267 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_LINCE

#define US_IMR_LINCE   (0x1u << 28)

(US_IMR) LIN Checksum Error Interrupt Mask

Definition at line 273 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_LINHTE

#define US_IMR_LINHTE   (0x1u << 31)

(US_IMR) LIN Header Timeout Error Interrupt Mask

Definition at line 276 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_LINID

#define US_IMR_LINID   (0x1u << 14)

(US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask

Definition at line 268 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_LINIPE

#define US_IMR_LINIPE   (0x1u << 27)

(US_IMR) LIN Identifier Parity Interrupt Mask

Definition at line 272 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_LINISFE

#define US_IMR_LINISFE   (0x1u << 26)

(US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask

Definition at line 271 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_LINSNRE

#define US_IMR_LINSNRE   (0x1u << 29)

(US_IMR) LIN Slave Not Responding Error Interrupt Mask

Definition at line 274 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_LINSTE

#define US_IMR_LINSTE   (0x1u << 30)

(US_IMR) LIN Synch Tolerance Error Interrupt Mask

Definition at line 275 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_LINTC

#define US_IMR_LINTC   (0x1u << 15)

(US_IMR) LIN Transfer Completed Interrupt Mask

Definition at line 269 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_LRXD

#define US_IMR_LRXD   (0x1u << 27)

(US_IMR) LON Reception Done Interrupt Mask

Definition at line 282 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_LSFE

#define US_IMR_LSFE   (0x1u << 6)

(US_IMR) LON Short Frame Error Interrupt Mask

Definition at line 277 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_LTXD

#define US_IMR_LTXD   (0x1u << 24)

(US_IMR) LON Transmission Done Interrupt Mask

Definition at line 279 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_MANE

#define US_IMR_MANE   (0x1u << 24)

(US_IMR) Manchester Error Interrupt Mask

Definition at line 264 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_NACK

#define US_IMR_NACK   (0x1u << 13)

(US_IMR) Non Acknowledge Interrupt Mask

Definition at line 259 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_NSSE

#define US_IMR_NSSE   (0x1u << 19)

(US_IMR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask

Definition at line 266 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_OVRE

#define US_IMR_OVRE   (0x1u << 5)

(US_IMR) Overrun Error Interrupt Mask

Definition at line 253 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_PARE

#define US_IMR_PARE   (0x1u << 7)

(US_IMR) Parity Error Interrupt Mask

Definition at line 255 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_RIIC

#define US_IMR_RIIC   (0x1u << 16)

(US_IMR) Ring Indicator Input Change Mask

Definition at line 260 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_RXBRK

#define US_IMR_RXBRK   (0x1u << 2)

(US_IMR) Receiver Break Interrupt Mask

Definition at line 252 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_RXRDY

#define US_IMR_RXRDY   (0x1u << 0)

(US_IMR) RXRDY Interrupt Mask

Definition at line 250 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_TIMEOUT

#define US_IMR_TIMEOUT   (0x1u << 8)

(US_IMR) Time-out Interrupt Mask

Definition at line 256 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_TXEMPTY

#define US_IMR_TXEMPTY   (0x1u << 9)

(US_IMR) TXEMPTY Interrupt Mask

Definition at line 257 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_TXRDY

#define US_IMR_TXRDY   (0x1u << 1)

(US_IMR) TXRDY Interrupt Mask

Definition at line 251 of file utils/cmsis/same70/include/component/usart.h.

◆ US_IMR_UNRE

#define US_IMR_UNRE   (0x1u << 10)

(US_IMR) SPI Underrun Error Interrupt Mask

Definition at line 265 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LINBRR_LINCD_Msk

#define US_LINBRR_LINCD_Msk   (0xffffu << US_LINBRR_LINCD_Pos)

(US_LINBRR) Clock Divider after Synchronization

Definition at line 416 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LINBRR_LINCD_Pos

#define US_LINBRR_LINCD_Pos   0

◆ US_LINBRR_LINFP_Msk

#define US_LINBRR_LINFP_Msk   (0x7u << US_LINBRR_LINFP_Pos)

(US_LINBRR) Fractional Part after Synchronization

Definition at line 418 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LINBRR_LINFP_Pos

#define US_LINBRR_LINFP_Pos   16

◆ US_LINIR_IDCHR

#define US_LINIR_IDCHR (   value)    ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)))

◆ US_LINIR_IDCHR_Msk

#define US_LINIR_IDCHR_Msk   (0xffu << US_LINIR_IDCHR_Pos)

(US_LINIR) Identifier Character

Definition at line 412 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LINIR_IDCHR_Pos

#define US_LINIR_IDCHR_Pos   0

◆ US_LINMR_CHKDIS

#define US_LINMR_CHKDIS   (0x1u << 3)

(US_LINMR) Checksum Disable

Definition at line 400 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LINMR_CHKTYP

#define US_LINMR_CHKTYP   (0x1u << 4)

(US_LINMR) Checksum Type

Definition at line 401 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LINMR_DLC

#define US_LINMR_DLC (   value)    ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)))

◆ US_LINMR_DLC_Msk

#define US_LINMR_DLC_Msk   (0xffu << US_LINMR_DLC_Pos)

(US_LINMR) Data Length Control

Definition at line 406 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LINMR_DLC_Pos

#define US_LINMR_DLC_Pos   8

◆ US_LINMR_DLM

#define US_LINMR_DLM   (0x1u << 5)

(US_LINMR) Data Length Mode

Definition at line 402 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LINMR_FSDIS

#define US_LINMR_FSDIS   (0x1u << 6)

(US_LINMR) Frame Slot Mode Disable

Definition at line 403 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LINMR_NACT

#define US_LINMR_NACT (   value)    ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos)))

◆ US_LINMR_NACT_IGNORE

#define US_LINMR_NACT_IGNORE   (0x2u << 0)

(US_LINMR) The USART does not transmit and does not receive the response.

Definition at line 398 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LINMR_NACT_Msk

#define US_LINMR_NACT_Msk   (0x3u << US_LINMR_NACT_Pos)

(US_LINMR) LIN Node Action

Definition at line 394 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LINMR_NACT_Pos

#define US_LINMR_NACT_Pos   0

◆ US_LINMR_NACT_PUBLISH

#define US_LINMR_NACT_PUBLISH   (0x0u << 0)

(US_LINMR) The USART transmits the response.

Definition at line 396 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LINMR_NACT_SUBSCRIBE

#define US_LINMR_NACT_SUBSCRIBE   (0x1u << 0)

(US_LINMR) The USART receives the response.

Definition at line 397 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LINMR_PARDIS

#define US_LINMR_PARDIS   (0x1u << 2)

(US_LINMR) Parity Disable

Definition at line 399 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LINMR_PDCM

#define US_LINMR_PDCM   (0x1u << 16)

(US_LINMR) DMAC Mode

Definition at line 408 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LINMR_SYNCDIS

#define US_LINMR_SYNCDIS   (0x1u << 17)

(US_LINMR) Synchronization Disable

Definition at line 409 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LINMR_WKUPTYP

#define US_LINMR_WKUPTYP   (0x1u << 7)

(US_LINMR) Wakeup Signal Type

Definition at line 404 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LONB1RX_BETA1RX

#define US_LONB1RX_BETA1RX (   value)    ((US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos)))

◆ US_LONB1RX_BETA1RX_Msk

#define US_LONB1RX_BETA1RX_Msk   (0xffffffu << US_LONB1RX_BETA1RX_Pos)

(US_LONB1RX) LON Beta1 Length after Reception

Definition at line 452 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LONB1RX_BETA1RX_Pos

#define US_LONB1RX_BETA1RX_Pos   0

◆ US_LONB1TX_BETA1TX

#define US_LONB1TX_BETA1TX (   value)    ((US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos)))

◆ US_LONB1TX_BETA1TX_Msk

#define US_LONB1TX_BETA1TX_Msk   (0xffffffu << US_LONB1TX_BETA1TX_Pos)

(US_LONB1TX) LON Beta1 Length after Transmission

Definition at line 448 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LONB1TX_BETA1TX_Pos

#define US_LONB1TX_BETA1TX_Pos   0

◆ US_LONBL_LONBL_Msk

#define US_LONBL_LONBL_Msk   (0x3fu << US_LONBL_LONBL_Pos)

(US_LONBL) LON Node Backlog Value

Definition at line 445 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LONBL_LONBL_Pos

#define US_LONBL_LONBL_Pos   0

◆ US_LONDL_LONDL

#define US_LONDL_LONDL (   value)    ((US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos)))

◆ US_LONDL_LONDL_Msk

#define US_LONDL_LONDL_Msk   (0xffu << US_LONDL_LONDL_Pos)

(US_LONDL) LON Data Length

Definition at line 435 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LONDL_LONDL_Pos

#define US_LONDL_LONDL_Pos   0

◆ US_LONL2HDR_ALTP

#define US_LONL2HDR_ALTP   (0x1u << 6)

(US_LONL2HDR) LON Alternate Path Bit

Definition at line 441 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LONL2HDR_BLI

#define US_LONL2HDR_BLI (   value)    ((US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos)))

◆ US_LONL2HDR_BLI_Msk

#define US_LONL2HDR_BLI_Msk   (0x3fu << US_LONL2HDR_BLI_Pos)

(US_LONL2HDR) LON Backlog Increment

Definition at line 439 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LONL2HDR_BLI_Pos

#define US_LONL2HDR_BLI_Pos   0

◆ US_LONL2HDR_PB

#define US_LONL2HDR_PB   (0x1u << 7)

(US_LONL2HDR) LON Priority Bit

Definition at line 442 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LONMR_CDTAIL

#define US_LONMR_CDTAIL   (0x1u << 3)

(US_LONMR) LON Collision Detection on Frame Tail

Definition at line 423 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LONMR_COLDET

#define US_LONMR_COLDET   (0x1u << 1)

(US_LONMR) LON Collision Detection Feature

Definition at line 421 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LONMR_COMMT

#define US_LONMR_COMMT   (0x1u << 0)

(US_LONMR) LON comm_type Parameter Value

Definition at line 420 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LONMR_DMAM

#define US_LONMR_DMAM   (0x1u << 4)

(US_LONMR) LON DMA Mode

Definition at line 424 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LONMR_EOFS

#define US_LONMR_EOFS (   value)    ((US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos)))

◆ US_LONMR_EOFS_Msk

#define US_LONMR_EOFS_Msk   (0xffu << US_LONMR_EOFS_Pos)

(US_LONMR) End of Frame Condition Size

Definition at line 427 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LONMR_EOFS_Pos

#define US_LONMR_EOFS_Pos   16

◆ US_LONMR_LCDS

#define US_LONMR_LCDS   (0x1u << 5)

(US_LONMR) LON Collision Detection Source

Definition at line 425 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LONMR_TCOL

#define US_LONMR_TCOL   (0x1u << 2)

(US_LONMR) Terminate Frame upon Collision Notification

Definition at line 422 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LONPR_LONPL

#define US_LONPR_LONPL (   value)    ((US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos)))

◆ US_LONPR_LONPL_Msk

#define US_LONPR_LONPL_Msk   (0x3fffu << US_LONPR_LONPL_Pos)

(US_LONPR) LON Preamble Length

Definition at line 431 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LONPR_LONPL_Pos

#define US_LONPR_LONPL_Pos   0

◆ US_LONPRIO_NPS

#define US_LONPRIO_NPS (   value)    ((US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos)))

◆ US_LONPRIO_NPS_Msk

#define US_LONPRIO_NPS_Msk   (0x7fu << US_LONPRIO_NPS_Pos)

(US_LONPRIO) LON Node Priority Slot

Definition at line 459 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LONPRIO_NPS_Pos

#define US_LONPRIO_NPS_Pos   8

◆ US_LONPRIO_PSNB

#define US_LONPRIO_PSNB (   value)    ((US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos)))

◆ US_LONPRIO_PSNB_Msk

#define US_LONPRIO_PSNB_Msk   (0x7fu << US_LONPRIO_PSNB_Pos)

(US_LONPRIO) LON Priority Slot Number

Definition at line 456 of file utils/cmsis/same70/include/component/usart.h.

◆ US_LONPRIO_PSNB_Pos

#define US_LONPRIO_PSNB_Pos   0

◆ US_MAN_DRIFT

#define US_MAN_DRIFT   (0x1u << 30)

(US_MAN) Drift Compensation

Definition at line 390 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MAN_ONE

#define US_MAN_ONE   (0x1u << 29)

(US_MAN) Must Be Set to 1

Definition at line 389 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MAN_RX_MPOL

#define US_MAN_RX_MPOL   (0x1u << 28)

(US_MAN) Receiver Manchester Polarity

Definition at line 388 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MAN_RX_PL

#define US_MAN_RX_PL (   value)    ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))

◆ US_MAN_RX_PL_Msk

#define US_MAN_RX_PL_Msk   (0xfu << US_MAN_RX_PL_Pos)

(US_MAN) Receiver Preamble Length

Definition at line 379 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MAN_RX_PL_Pos

#define US_MAN_RX_PL_Pos   16

◆ US_MAN_RX_PP

#define US_MAN_RX_PP (   value)    ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos)))

◆ US_MAN_RX_PP_ALL_ONE

#define US_MAN_RX_PP_ALL_ONE   (0x0u << 24)

(US_MAN) The preamble is composed of '1's

Definition at line 384 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MAN_RX_PP_ALL_ZERO

#define US_MAN_RX_PP_ALL_ZERO   (0x1u << 24)

(US_MAN) The preamble is composed of '0's

Definition at line 385 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MAN_RX_PP_Msk

#define US_MAN_RX_PP_Msk   (0x3u << US_MAN_RX_PP_Pos)

(US_MAN) Receiver Preamble Pattern detected

Definition at line 382 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MAN_RX_PP_ONE_ZERO

#define US_MAN_RX_PP_ONE_ZERO   (0x3u << 24)

(US_MAN) The preamble is composed of '10's

Definition at line 387 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MAN_RX_PP_Pos

#define US_MAN_RX_PP_Pos   24

◆ US_MAN_RX_PP_ZERO_ONE

#define US_MAN_RX_PP_ZERO_ONE   (0x2u << 24)

(US_MAN) The preamble is composed of '01's

Definition at line 386 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MAN_RXIDLEV

#define US_MAN_RXIDLEV   (0x1u << 31)

(US_MAN)

Definition at line 391 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MAN_TX_MPOL

#define US_MAN_TX_MPOL   (0x1u << 12)

(US_MAN) Transmitter Manchester Polarity

Definition at line 377 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MAN_TX_PL

#define US_MAN_TX_PL (   value)    ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))

◆ US_MAN_TX_PL_Msk

#define US_MAN_TX_PL_Msk   (0xfu << US_MAN_TX_PL_Pos)

(US_MAN) Transmitter Preamble Length

Definition at line 368 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MAN_TX_PL_Pos

#define US_MAN_TX_PL_Pos   0

◆ US_MAN_TX_PP

#define US_MAN_TX_PP (   value)    ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos)))

◆ US_MAN_TX_PP_ALL_ONE

#define US_MAN_TX_PP_ALL_ONE   (0x0u << 8)

(US_MAN) The preamble is composed of '1's

Definition at line 373 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MAN_TX_PP_ALL_ZERO

#define US_MAN_TX_PP_ALL_ZERO   (0x1u << 8)

(US_MAN) The preamble is composed of '0's

Definition at line 374 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MAN_TX_PP_Msk

#define US_MAN_TX_PP_Msk   (0x3u << US_MAN_TX_PP_Pos)

(US_MAN) Transmitter Preamble Pattern

Definition at line 371 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MAN_TX_PP_ONE_ZERO

#define US_MAN_TX_PP_ONE_ZERO   (0x3u << 8)

(US_MAN) The preamble is composed of '10's

Definition at line 376 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MAN_TX_PP_Pos

#define US_MAN_TX_PP_Pos   8

◆ US_MAN_TX_PP_ZERO_ONE

#define US_MAN_TX_PP_ZERO_ONE   (0x2u << 8)

(US_MAN) The preamble is composed of '01's

Definition at line 375 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_CHMODE

#define US_MR_CHMODE (   value)    ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos)))

◆ US_MR_CHMODE_AUTOMATIC

#define US_MR_CHMODE_AUTOMATIC   (0x1u << 14)

(US_MR) Automatic Echo. Receiver input is connected to the TXD pin.

Definition at line 158 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_CHMODE_LOCAL_LOOPBACK

#define US_MR_CHMODE_LOCAL_LOOPBACK   (0x2u << 14)

(US_MR) Local Loopback. Transmitter output is connected to the Receiver Input.

Definition at line 159 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_CHMODE_Msk

#define US_MR_CHMODE_Msk   (0x3u << US_MR_CHMODE_Pos)

(US_MR) Channel Mode

Definition at line 155 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_CHMODE_NORMAL

#define US_MR_CHMODE_NORMAL   (0x0u << 14)

(US_MR) Normal mode

Definition at line 157 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_CHMODE_Pos

#define US_MR_CHMODE_Pos   14

◆ US_MR_CHMODE_REMOTE_LOOPBACK

#define US_MR_CHMODE_REMOTE_LOOPBACK   (0x3u << 14)

(US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin.

Definition at line 160 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_CHRL

#define US_MR_CHRL (   value)    ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos)))

◆ US_MR_CHRL_5_BIT

#define US_MR_CHRL_5_BIT   (0x0u << 6)

(US_MR) Character length is 5 bits

Definition at line 134 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_CHRL_6_BIT

#define US_MR_CHRL_6_BIT   (0x1u << 6)

(US_MR) Character length is 6 bits

Definition at line 135 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_CHRL_7_BIT

#define US_MR_CHRL_7_BIT   (0x2u << 6)

(US_MR) Character length is 7 bits

Definition at line 136 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_CHRL_8_BIT

#define US_MR_CHRL_8_BIT   (0x3u << 6)

(US_MR) Character length is 8 bits

Definition at line 137 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_CHRL_Msk

#define US_MR_CHRL_Msk   (0x3u << US_MR_CHRL_Pos)

(US_MR) Character Length

Definition at line 132 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_CHRL_Pos

#define US_MR_CHRL_Pos   6

◆ US_MR_CLKO

#define US_MR_CLKO   (0x1u << 18)

(US_MR) Clock Output Select

Definition at line 163 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_CPHA

#define US_MR_CPHA   (0x1u << 8)

(US_MR) SPI Clock Phase

Definition at line 176 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_CPOL

#define US_MR_CPOL   (0x1u << 16)

(US_MR) SPI Clock Polarity

Definition at line 177 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_DSNACK

#define US_MR_DSNACK   (0x1u << 21)

(US_MR) Disable Successive NACK

Definition at line 166 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_FILTER

#define US_MR_FILTER   (0x1u << 28)

(US_MR) Receive Line Filter

Definition at line 172 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_INACK

#define US_MR_INACK   (0x1u << 20)

(US_MR) Inhibit Non Acknowledge

Definition at line 165 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_INVDATA

#define US_MR_INVDATA   (0x1u << 23)

(US_MR) Inverted Data

Definition at line 168 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_MAN

#define US_MR_MAN   (0x1u << 29)

(US_MR) Manchester Encoder/Decoder Enable

Definition at line 173 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_MAX_ITERATION

#define US_MR_MAX_ITERATION (   value)    ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))

◆ US_MR_MAX_ITERATION_Msk

#define US_MR_MAX_ITERATION_Msk   (0x7u << US_MR_MAX_ITERATION_Pos)

(US_MR) Maximum Number of Automatic Iteration

Definition at line 170 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_MAX_ITERATION_Pos

#define US_MR_MAX_ITERATION_Pos   24

◆ US_MR_MODE9

#define US_MR_MODE9   (0x1u << 17)

(US_MR) 9-bit Character Length

Definition at line 162 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_MODSYNC

#define US_MR_MODSYNC   (0x1u << 30)

(US_MR) Manchester Synchronization Mode

Definition at line 174 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_MSBF

#define US_MR_MSBF   (0x1u << 16)

(US_MR) Bit Order

Definition at line 161 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_NBSTOP

#define US_MR_NBSTOP (   value)    ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos)))

◆ US_MR_NBSTOP_1_5_BIT

#define US_MR_NBSTOP_1_5_BIT   (0x1u << 12)

(US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)

Definition at line 152 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_NBSTOP_1_BIT

#define US_MR_NBSTOP_1_BIT   (0x0u << 12)

(US_MR) 1 stop bit

Definition at line 151 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_NBSTOP_2_BIT

#define US_MR_NBSTOP_2_BIT   (0x2u << 12)

(US_MR) 2 stop bits

Definition at line 153 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_NBSTOP_Msk

#define US_MR_NBSTOP_Msk   (0x3u << US_MR_NBSTOP_Pos)

(US_MR) Number of Stop Bits

Definition at line 149 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_NBSTOP_Pos

#define US_MR_NBSTOP_Pos   12

◆ US_MR_ONEBIT

#define US_MR_ONEBIT   (0x1u << 31)

(US_MR) Start Frame Delimiter Selector

Definition at line 175 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_OVER

#define US_MR_OVER   (0x1u << 19)

(US_MR) Oversampling Mode

Definition at line 164 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_PAR

#define US_MR_PAR (   value)    ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos)))

◆ US_MR_PAR_EVEN

#define US_MR_PAR_EVEN   (0x0u << 9)

(US_MR) Even parity

Definition at line 142 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_PAR_MARK

#define US_MR_PAR_MARK   (0x3u << 9)

(US_MR) Parity forced to 1 (Mark)

Definition at line 145 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_PAR_Msk

#define US_MR_PAR_Msk   (0x7u << US_MR_PAR_Pos)

(US_MR) Parity Type

Definition at line 140 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_PAR_MULTIDROP

#define US_MR_PAR_MULTIDROP   (0x6u << 9)

(US_MR) Multidrop mode

Definition at line 147 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_PAR_NO

#define US_MR_PAR_NO   (0x4u << 9)

(US_MR) No parity

Definition at line 146 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_PAR_ODD

#define US_MR_PAR_ODD   (0x1u << 9)

(US_MR) Odd parity

Definition at line 143 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_PAR_Pos

#define US_MR_PAR_Pos   9

◆ US_MR_PAR_SPACE

#define US_MR_PAR_SPACE   (0x2u << 9)

(US_MR) Parity forced to 0 (Space)

Definition at line 144 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_SYNC

#define US_MR_SYNC   (0x1u << 8)

(US_MR) Synchronous Mode Select

Definition at line 138 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_USART_MODE

#define US_MR_USART_MODE (   value)    ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos)))

◆ US_MR_USART_MODE_HW_HANDSHAKING

#define US_MR_USART_MODE_HW_HANDSHAKING   (0x2u << 0)

(US_MR) Hardware Handshaking

Definition at line 114 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_USART_MODE_IRDA

#define US_MR_USART_MODE_IRDA   (0x8u << 0)

(US_MR) IrDA

Definition at line 118 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_USART_MODE_IS07816_T_0

#define US_MR_USART_MODE_IS07816_T_0   (0x4u << 0)

(US_MR) IS07816 Protocol: T = 0

Definition at line 116 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_USART_MODE_IS07816_T_1

#define US_MR_USART_MODE_IS07816_T_1   (0x6u << 0)

(US_MR) IS07816 Protocol: T = 1

Definition at line 117 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_USART_MODE_LIN_MASTER

#define US_MR_USART_MODE_LIN_MASTER   (0xAu << 0)

(US_MR) LIN Master mode

Definition at line 120 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_USART_MODE_LIN_SLAVE

#define US_MR_USART_MODE_LIN_SLAVE   (0xBu << 0)

(US_MR) LIN Slave mode

Definition at line 121 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_USART_MODE_LON

#define US_MR_USART_MODE_LON   (0x9u << 0)

(US_MR) LON

Definition at line 119 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_USART_MODE_MODEM

#define US_MR_USART_MODE_MODEM   (0x3u << 0)

(US_MR) Modem

Definition at line 115 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_USART_MODE_Msk

#define US_MR_USART_MODE_Msk   (0xfu << US_MR_USART_MODE_Pos)

(US_MR) USART Mode of Operation

Definition at line 110 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_USART_MODE_NORMAL

#define US_MR_USART_MODE_NORMAL   (0x0u << 0)

(US_MR) Normal mode

Definition at line 112 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_USART_MODE_Pos

#define US_MR_USART_MODE_Pos   0

◆ US_MR_USART_MODE_RS485

#define US_MR_USART_MODE_RS485   (0x1u << 0)

(US_MR) RS485

Definition at line 113 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_USART_MODE_SPI_MASTER

#define US_MR_USART_MODE_SPI_MASTER   (0xEu << 0)

(US_MR) SPI master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2)

Definition at line 122 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_USART_MODE_SPI_SLAVE

#define US_MR_USART_MODE_SPI_SLAVE   (0xFu << 0)

(US_MR) SPI Slave mode

Definition at line 123 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_USCLKS

#define US_MR_USCLKS (   value)    ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos)))

◆ US_MR_USCLKS_DIV

#define US_MR_USCLKS_DIV   (0x1u << 4)

(US_MR) Peripheral clock divided (DIV=DIV=8) is selected

Definition at line 128 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_USCLKS_MCK

#define US_MR_USCLKS_MCK   (0x0u << 4)

(US_MR) Peripheral clock is selected

Definition at line 127 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_USCLKS_Msk

#define US_MR_USCLKS_Msk   (0x3u << US_MR_USCLKS_Pos)

(US_MR) Clock Selection

Definition at line 125 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_USCLKS_PCK

#define US_MR_USCLKS_PCK   (0x2u << 4)

(US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1.

Definition at line 129 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_USCLKS_Pos

#define US_MR_USCLKS_Pos   4

◆ US_MR_USCLKS_SCK

#define US_MR_USCLKS_SCK   (0x3u << 4)

(US_MR) Serial clock (SCK) is selected

Definition at line 130 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_VAR_SYNC

#define US_MR_VAR_SYNC   (0x1u << 22)

(US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter

Definition at line 167 of file utils/cmsis/same70/include/component/usart.h.

◆ US_MR_WRDBT

#define US_MR_WRDBT   (0x1u << 20)

(US_MR) Wait Read Data Before Transfer

Definition at line 178 of file utils/cmsis/same70/include/component/usart.h.

◆ US_NER_NB_ERRORS_Msk

#define US_NER_NB_ERRORS_Msk   (0xffu << US_NER_NB_ERRORS_Pos)

(US_NER) Number of Errors

Definition at line 361 of file utils/cmsis/same70/include/component/usart.h.

◆ US_NER_NB_ERRORS_Pos

#define US_NER_NB_ERRORS_Pos   0

◆ US_RHR_RXCHR_Msk

#define US_RHR_RXCHR_Msk   (0x1ffu << US_RHR_RXCHR_Pos)

(US_RHR) Received Character

Definition at line 327 of file utils/cmsis/same70/include/component/usart.h.

◆ US_RHR_RXCHR_Pos

#define US_RHR_RXCHR_Pos   0

◆ US_RHR_RXSYNH

#define US_RHR_RXSYNH   (0x1u << 15)

(US_RHR) Received Sync

Definition at line 328 of file utils/cmsis/same70/include/component/usart.h.

◆ US_RTOR_TO

#define US_RTOR_TO (   value)    ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))

◆ US_RTOR_TO_Msk

#define US_RTOR_TO_Msk   (0x1ffffu << US_RTOR_TO_Pos)

(US_RTOR) Time-out Value

Definition at line 343 of file utils/cmsis/same70/include/component/usart.h.

◆ US_RTOR_TO_Pos

#define US_RTOR_TO_Pos   0

◆ US_THR_TXCHR

#define US_THR_TXCHR (   value)    ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))

◆ US_THR_TXCHR_Msk

#define US_THR_TXCHR_Msk   (0x1ffu << US_THR_TXCHR_Pos)

(US_THR) Character to be Transmitted

Definition at line 331 of file utils/cmsis/same70/include/component/usart.h.

◆ US_THR_TXCHR_Pos

#define US_THR_TXCHR_Pos   0

◆ US_THR_TXSYNH

#define US_THR_TXSYNH   (0x1u << 15)

(US_THR) Sync Field to be Transmitted

Definition at line 333 of file utils/cmsis/same70/include/component/usart.h.

◆ US_TTGR_PCYCLE

#define US_TTGR_PCYCLE (   value)    ((US_TTGR_PCYCLE_Msk & ((value) << US_TTGR_PCYCLE_Pos)))

◆ US_TTGR_PCYCLE_Msk

#define US_TTGR_PCYCLE_Msk   (0xffffffu << US_TTGR_PCYCLE_Pos)

(US_TTGR) LON PCYCLE Length

Definition at line 350 of file utils/cmsis/same70/include/component/usart.h.

◆ US_TTGR_PCYCLE_Pos

#define US_TTGR_PCYCLE_Pos   0

◆ US_TTGR_TG

#define US_TTGR_TG (   value)    ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))

◆ US_TTGR_TG_Msk

#define US_TTGR_TG_Msk   (0xffu << US_TTGR_TG_Pos)

(US_TTGR) Timeguard Value

Definition at line 347 of file utils/cmsis/same70/include/component/usart.h.

◆ US_TTGR_TG_Pos

#define US_TTGR_TG_Pos   0

◆ US_VERSION_MFN_Msk

#define US_VERSION_MFN_Msk   (0x7u << US_VERSION_MFN_Pos)

(US_VERSION) Metal Fix Number

Definition at line 487 of file utils/cmsis/same70/include/component/usart.h.

◆ US_VERSION_MFN_Pos

#define US_VERSION_MFN_Pos   16

◆ US_VERSION_VERSION_Msk

#define US_VERSION_VERSION_Msk   (0xfffu << US_VERSION_VERSION_Pos)

(US_VERSION) Hardware Module Version

Definition at line 485 of file utils/cmsis/same70/include/component/usart.h.

◆ US_VERSION_VERSION_Pos

#define US_VERSION_VERSION_Pos   0

◆ US_WPMR_WPEN

#define US_WPMR_WPEN   (0x1u << 0)

(US_WPMR) Write Protection Enable

Definition at line 474 of file utils/cmsis/same70/include/component/usart.h.

◆ US_WPMR_WPKEY

#define US_WPMR_WPKEY (   value)    ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))

◆ US_WPMR_WPKEY_Msk

#define US_WPMR_WPKEY_Msk   (0xffffffu << US_WPMR_WPKEY_Pos)

(US_WPMR) Write Protection Key

Definition at line 476 of file utils/cmsis/same70/include/component/usart.h.

◆ US_WPMR_WPKEY_PASSWD

#define US_WPMR_WPKEY_PASSWD   (0x555341u << 8)

(US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

Definition at line 478 of file utils/cmsis/same70/include/component/usart.h.

◆ US_WPMR_WPKEY_Pos

#define US_WPMR_WPKEY_Pos   8

◆ US_WPSR_WPVS

#define US_WPSR_WPVS   (0x1u << 0)

(US_WPSR) Write Protection Violation Status

Definition at line 480 of file utils/cmsis/same70/include/component/usart.h.

◆ US_WPSR_WPVSRC_Msk

#define US_WPSR_WPVSRC_Msk   (0xffffu << US_WPSR_WPVSRC_Pos)

(US_WPSR) Write Protection Violation Source

Definition at line 482 of file utils/cmsis/same70/include/component/usart.h.

◆ US_WPSR_WPVSRC_Pos

#define US_WPSR_WPVSRC_Pos   8


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Author(s):
autogenerated on Sat Sep 19 2020 03:19:08