utils/cmsis/same70/include/component/usart.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_USART_COMPONENT_
36 #define _SAME70_USART_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __O uint32_t US_CR;
48  __IO uint32_t US_MR;
49  __O uint32_t US_IER;
50  __O uint32_t US_IDR;
51  __I uint32_t US_IMR;
52  __I uint32_t US_CSR;
53  __I uint32_t US_RHR;
54  __O uint32_t US_THR;
55  __IO uint32_t US_BRGR;
56  __IO uint32_t US_RTOR;
57  __IO uint32_t US_TTGR;
58  __I uint32_t Reserved1[5];
59  __IO uint32_t US_FIDI;
60  __I uint32_t US_NER;
61  __I uint32_t Reserved2[1];
62  __IO uint32_t US_IF;
63  __IO uint32_t US_MAN;
64  __IO uint32_t US_LINMR;
65  __IO uint32_t US_LINIR;
66  __I uint32_t US_LINBRR;
67  __IO uint32_t US_LONMR;
68  __IO uint32_t US_LONPR;
69  __IO uint32_t US_LONDL;
70  __IO uint32_t US_LONL2HDR;
71  __I uint32_t US_LONBL;
72  __IO uint32_t US_LONB1TX;
73  __IO uint32_t US_LONB1RX;
74  __IO uint32_t US_LONPRIO;
75  __IO uint32_t US_IDTTX;
76  __IO uint32_t US_IDTRX;
77  __IO uint32_t US_ICDIFF;
78  __I uint32_t Reserved3[22];
79  __IO uint32_t US_WPMR;
80  __I uint32_t US_WPSR;
81  __I uint32_t Reserved4[4];
82  __I uint32_t US_VERSION;
83 } Usart;
84 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
85 /* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
86 #define US_CR_RSTRX (0x1u << 2)
87 #define US_CR_RSTTX (0x1u << 3)
88 #define US_CR_RXEN (0x1u << 4)
89 #define US_CR_RXDIS (0x1u << 5)
90 #define US_CR_TXEN (0x1u << 6)
91 #define US_CR_TXDIS (0x1u << 7)
92 #define US_CR_RSTSTA (0x1u << 8)
93 #define US_CR_STTBRK (0x1u << 9)
94 #define US_CR_STPBRK (0x1u << 10)
95 #define US_CR_STTTO (0x1u << 11)
96 #define US_CR_SENDA (0x1u << 12)
97 #define US_CR_RSTIT (0x1u << 13)
98 #define US_CR_RSTNACK (0x1u << 14)
99 #define US_CR_RETTO (0x1u << 15)
100 #define US_CR_DTREN (0x1u << 16)
101 #define US_CR_DTRDIS (0x1u << 17)
102 #define US_CR_RTSEN (0x1u << 18)
103 #define US_CR_RTSDIS (0x1u << 19)
104 #define US_CR_LINABT (0x1u << 20)
105 #define US_CR_LINWKUP (0x1u << 21)
106 #define US_CR_FCS (0x1u << 18)
107 #define US_CR_RCS (0x1u << 19)
108 /* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
109 #define US_MR_USART_MODE_Pos 0
110 #define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos)
111 #define US_MR_USART_MODE(value) ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos)))
112 #define US_MR_USART_MODE_NORMAL (0x0u << 0)
113 #define US_MR_USART_MODE_RS485 (0x1u << 0)
114 #define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0)
115 #define US_MR_USART_MODE_MODEM (0x3u << 0)
116 #define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0)
117 #define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0)
118 #define US_MR_USART_MODE_IRDA (0x8u << 0)
119 #define US_MR_USART_MODE_LON (0x9u << 0)
120 #define US_MR_USART_MODE_LIN_MASTER (0xAu << 0)
121 #define US_MR_USART_MODE_LIN_SLAVE (0xBu << 0)
122 #define US_MR_USART_MODE_SPI_MASTER (0xEu << 0)
123 #define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0)
124 #define US_MR_USCLKS_Pos 4
125 #define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos)
126 #define US_MR_USCLKS(value) ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos)))
127 #define US_MR_USCLKS_MCK (0x0u << 4)
128 #define US_MR_USCLKS_DIV (0x1u << 4)
129 #define US_MR_USCLKS_PCK (0x2u << 4)
130 #define US_MR_USCLKS_SCK (0x3u << 4)
131 #define US_MR_CHRL_Pos 6
132 #define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos)
133 #define US_MR_CHRL(value) ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos)))
134 #define US_MR_CHRL_5_BIT (0x0u << 6)
135 #define US_MR_CHRL_6_BIT (0x1u << 6)
136 #define US_MR_CHRL_7_BIT (0x2u << 6)
137 #define US_MR_CHRL_8_BIT (0x3u << 6)
138 #define US_MR_SYNC (0x1u << 8)
139 #define US_MR_PAR_Pos 9
140 #define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos)
141 #define US_MR_PAR(value) ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos)))
142 #define US_MR_PAR_EVEN (0x0u << 9)
143 #define US_MR_PAR_ODD (0x1u << 9)
144 #define US_MR_PAR_SPACE (0x2u << 9)
145 #define US_MR_PAR_MARK (0x3u << 9)
146 #define US_MR_PAR_NO (0x4u << 9)
147 #define US_MR_PAR_MULTIDROP (0x6u << 9)
148 #define US_MR_NBSTOP_Pos 12
149 #define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos)
150 #define US_MR_NBSTOP(value) ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos)))
151 #define US_MR_NBSTOP_1_BIT (0x0u << 12)
152 #define US_MR_NBSTOP_1_5_BIT (0x1u << 12)
153 #define US_MR_NBSTOP_2_BIT (0x2u << 12)
154 #define US_MR_CHMODE_Pos 14
155 #define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos)
156 #define US_MR_CHMODE(value) ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos)))
157 #define US_MR_CHMODE_NORMAL (0x0u << 14)
158 #define US_MR_CHMODE_AUTOMATIC (0x1u << 14)
159 #define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14)
160 #define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14)
161 #define US_MR_MSBF (0x1u << 16)
162 #define US_MR_MODE9 (0x1u << 17)
163 #define US_MR_CLKO (0x1u << 18)
164 #define US_MR_OVER (0x1u << 19)
165 #define US_MR_INACK (0x1u << 20)
166 #define US_MR_DSNACK (0x1u << 21)
167 #define US_MR_VAR_SYNC (0x1u << 22)
168 #define US_MR_INVDATA (0x1u << 23)
169 #define US_MR_MAX_ITERATION_Pos 24
170 #define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos)
171 #define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
172 #define US_MR_FILTER (0x1u << 28)
173 #define US_MR_MAN (0x1u << 29)
174 #define US_MR_MODSYNC (0x1u << 30)
175 #define US_MR_ONEBIT (0x1u << 31)
176 #define US_MR_CPHA (0x1u << 8)
177 #define US_MR_CPOL (0x1u << 16)
178 #define US_MR_WRDBT (0x1u << 20)
179 /* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
180 #define US_IER_RXRDY (0x1u << 0)
181 #define US_IER_TXRDY (0x1u << 1)
182 #define US_IER_RXBRK (0x1u << 2)
183 #define US_IER_OVRE (0x1u << 5)
184 #define US_IER_FRAME (0x1u << 6)
185 #define US_IER_PARE (0x1u << 7)
186 #define US_IER_TIMEOUT (0x1u << 8)
187 #define US_IER_TXEMPTY (0x1u << 9)
188 #define US_IER_ITER (0x1u << 10)
189 #define US_IER_NACK (0x1u << 13)
190 #define US_IER_RIIC (0x1u << 16)
191 #define US_IER_DSRIC (0x1u << 17)
192 #define US_IER_DCDIC (0x1u << 18)
193 #define US_IER_CTSIC (0x1u << 19)
194 #define US_IER_MANE (0x1u << 24)
195 #define US_IER_UNRE (0x1u << 10)
196 #define US_IER_NSSE (0x1u << 19)
197 #define US_IER_LINBK (0x1u << 13)
198 #define US_IER_LINID (0x1u << 14)
199 #define US_IER_LINTC (0x1u << 15)
200 #define US_IER_LINBE (0x1u << 25)
201 #define US_IER_LINISFE (0x1u << 26)
202 #define US_IER_LINIPE (0x1u << 27)
203 #define US_IER_LINCE (0x1u << 28)
204 #define US_IER_LINSNRE (0x1u << 29)
205 #define US_IER_LINSTE (0x1u << 30)
206 #define US_IER_LINHTE (0x1u << 31)
207 #define US_IER_LSFE (0x1u << 6)
208 #define US_IER_LCRCE (0x1u << 7)
209 #define US_IER_LTXD (0x1u << 24)
210 #define US_IER_LCOL (0x1u << 25)
211 #define US_IER_LFET (0x1u << 26)
212 #define US_IER_LRXD (0x1u << 27)
213 #define US_IER_LBLOVFE (0x1u << 28)
214 /* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
215 #define US_IDR_RXRDY (0x1u << 0)
216 #define US_IDR_TXRDY (0x1u << 1)
217 #define US_IDR_RXBRK (0x1u << 2)
218 #define US_IDR_OVRE (0x1u << 5)
219 #define US_IDR_FRAME (0x1u << 6)
220 #define US_IDR_PARE (0x1u << 7)
221 #define US_IDR_TIMEOUT (0x1u << 8)
222 #define US_IDR_TXEMPTY (0x1u << 9)
223 #define US_IDR_ITER (0x1u << 10)
224 #define US_IDR_NACK (0x1u << 13)
225 #define US_IDR_RIIC (0x1u << 16)
226 #define US_IDR_DSRIC (0x1u << 17)
227 #define US_IDR_DCDIC (0x1u << 18)
228 #define US_IDR_CTSIC (0x1u << 19)
229 #define US_IDR_MANE (0x1u << 24)
230 #define US_IDR_UNRE (0x1u << 10)
231 #define US_IDR_NSSE (0x1u << 19)
232 #define US_IDR_LINBK (0x1u << 13)
233 #define US_IDR_LINID (0x1u << 14)
234 #define US_IDR_LINTC (0x1u << 15)
235 #define US_IDR_LINBE (0x1u << 25)
236 #define US_IDR_LINISFE (0x1u << 26)
237 #define US_IDR_LINIPE (0x1u << 27)
238 #define US_IDR_LINCE (0x1u << 28)
239 #define US_IDR_LINSNRE (0x1u << 29)
240 #define US_IDR_LINSTE (0x1u << 30)
241 #define US_IDR_LINHTE (0x1u << 31)
242 #define US_IDR_LSFE (0x1u << 6)
243 #define US_IDR_LCRCE (0x1u << 7)
244 #define US_IDR_LTXD (0x1u << 24)
245 #define US_IDR_LCOL (0x1u << 25)
246 #define US_IDR_LFET (0x1u << 26)
247 #define US_IDR_LRXD (0x1u << 27)
248 #define US_IDR_LBLOVFE (0x1u << 28)
249 /* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
250 #define US_IMR_RXRDY (0x1u << 0)
251 #define US_IMR_TXRDY (0x1u << 1)
252 #define US_IMR_RXBRK (0x1u << 2)
253 #define US_IMR_OVRE (0x1u << 5)
254 #define US_IMR_FRAME (0x1u << 6)
255 #define US_IMR_PARE (0x1u << 7)
256 #define US_IMR_TIMEOUT (0x1u << 8)
257 #define US_IMR_TXEMPTY (0x1u << 9)
258 #define US_IMR_ITER (0x1u << 10)
259 #define US_IMR_NACK (0x1u << 13)
260 #define US_IMR_RIIC (0x1u << 16)
261 #define US_IMR_DSRIC (0x1u << 17)
262 #define US_IMR_DCDIC (0x1u << 18)
263 #define US_IMR_CTSIC (0x1u << 19)
264 #define US_IMR_MANE (0x1u << 24)
265 #define US_IMR_UNRE (0x1u << 10)
266 #define US_IMR_NSSE (0x1u << 19)
267 #define US_IMR_LINBK (0x1u << 13)
268 #define US_IMR_LINID (0x1u << 14)
269 #define US_IMR_LINTC (0x1u << 15)
270 #define US_IMR_LINBE (0x1u << 25)
271 #define US_IMR_LINISFE (0x1u << 26)
272 #define US_IMR_LINIPE (0x1u << 27)
273 #define US_IMR_LINCE (0x1u << 28)
274 #define US_IMR_LINSNRE (0x1u << 29)
275 #define US_IMR_LINSTE (0x1u << 30)
276 #define US_IMR_LINHTE (0x1u << 31)
277 #define US_IMR_LSFE (0x1u << 6)
278 #define US_IMR_LCRCE (0x1u << 7)
279 #define US_IMR_LTXD (0x1u << 24)
280 #define US_IMR_LCOL (0x1u << 25)
281 #define US_IMR_LFET (0x1u << 26)
282 #define US_IMR_LRXD (0x1u << 27)
283 #define US_IMR_LBLOVFE (0x1u << 28)
284 /* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
285 #define US_CSR_RXRDY (0x1u << 0)
286 #define US_CSR_TXRDY (0x1u << 1)
287 #define US_CSR_RXBRK (0x1u << 2)
288 #define US_CSR_OVRE (0x1u << 5)
289 #define US_CSR_FRAME (0x1u << 6)
290 #define US_CSR_PARE (0x1u << 7)
291 #define US_CSR_TIMEOUT (0x1u << 8)
292 #define US_CSR_TXEMPTY (0x1u << 9)
293 #define US_CSR_ITER (0x1u << 10)
294 #define US_CSR_NACK (0x1u << 13)
295 #define US_CSR_RIIC (0x1u << 16)
296 #define US_CSR_DSRIC (0x1u << 17)
297 #define US_CSR_DCDIC (0x1u << 18)
298 #define US_CSR_CTSIC (0x1u << 19)
299 #define US_CSR_RI (0x1u << 20)
300 #define US_CSR_DSR (0x1u << 21)
301 #define US_CSR_DCD (0x1u << 22)
302 #define US_CSR_CTS (0x1u << 23)
303 #define US_CSR_MANERR (0x1u << 24)
304 #define US_CSR_UNRE (0x1u << 10)
305 #define US_CSR_NSSE (0x1u << 19)
306 #define US_CSR_NSS (0x1u << 23)
307 #define US_CSR_LINBK (0x1u << 13)
308 #define US_CSR_LINID (0x1u << 14)
309 #define US_CSR_LINTC (0x1u << 15)
310 #define US_CSR_LINBLS (0x1u << 23)
311 #define US_CSR_LINBE (0x1u << 25)
312 #define US_CSR_LINISFE (0x1u << 26)
313 #define US_CSR_LINIPE (0x1u << 27)
314 #define US_CSR_LINCE (0x1u << 28)
315 #define US_CSR_LINSNRE (0x1u << 29)
316 #define US_CSR_LINSTE (0x1u << 30)
317 #define US_CSR_LINHTE (0x1u << 31)
318 #define US_CSR_LSFE (0x1u << 6)
319 #define US_CSR_LCRCE (0x1u << 7)
320 #define US_CSR_LTXD (0x1u << 24)
321 #define US_CSR_LCOL (0x1u << 25)
322 #define US_CSR_LFET (0x1u << 26)
323 #define US_CSR_LRXD (0x1u << 27)
324 #define US_CSR_LBLOVFE (0x1u << 28)
325 /* -------- US_RHR : (USART Offset: 0x0018) Receive Holding Register -------- */
326 #define US_RHR_RXCHR_Pos 0
327 #define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos)
328 #define US_RHR_RXSYNH (0x1u << 15)
329 /* -------- US_THR : (USART Offset: 0x001C) Transmit Holding Register -------- */
330 #define US_THR_TXCHR_Pos 0
331 #define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos)
332 #define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
333 #define US_THR_TXSYNH (0x1u << 15)
334 /* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
335 #define US_BRGR_CD_Pos 0
336 #define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos)
337 #define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
338 #define US_BRGR_FP_Pos 16
339 #define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos)
340 #define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
341 /* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
342 #define US_RTOR_TO_Pos 0
343 #define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos)
344 #define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
345 /* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
346 #define US_TTGR_TG_Pos 0
347 #define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos)
348 #define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
349 #define US_TTGR_PCYCLE_Pos 0
350 #define US_TTGR_PCYCLE_Msk (0xffffffu << US_TTGR_PCYCLE_Pos)
351 #define US_TTGR_PCYCLE(value) ((US_TTGR_PCYCLE_Msk & ((value) << US_TTGR_PCYCLE_Pos)))
352 /* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
353 #define US_FIDI_FI_DI_RATIO_Pos 0
354 #define US_FIDI_FI_DI_RATIO_Msk (0xffffu << US_FIDI_FI_DI_RATIO_Pos)
355 #define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
356 #define US_FIDI_BETA2_Pos 0
357 #define US_FIDI_BETA2_Msk (0xffffffu << US_FIDI_BETA2_Pos)
358 #define US_FIDI_BETA2(value) ((US_FIDI_BETA2_Msk & ((value) << US_FIDI_BETA2_Pos)))
359 /* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
360 #define US_NER_NB_ERRORS_Pos 0
361 #define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos)
362 /* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
363 #define US_IF_IRDA_FILTER_Pos 0
364 #define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos)
365 #define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
366 /* -------- US_MAN : (USART Offset: 0x0050) Manchester Configuration Register -------- */
367 #define US_MAN_TX_PL_Pos 0
368 #define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos)
369 #define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
370 #define US_MAN_TX_PP_Pos 8
371 #define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos)
372 #define US_MAN_TX_PP(value) ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos)))
373 #define US_MAN_TX_PP_ALL_ONE (0x0u << 8)
374 #define US_MAN_TX_PP_ALL_ZERO (0x1u << 8)
375 #define US_MAN_TX_PP_ZERO_ONE (0x2u << 8)
376 #define US_MAN_TX_PP_ONE_ZERO (0x3u << 8)
377 #define US_MAN_TX_MPOL (0x1u << 12)
378 #define US_MAN_RX_PL_Pos 16
379 #define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos)
380 #define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
381 #define US_MAN_RX_PP_Pos 24
382 #define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos)
383 #define US_MAN_RX_PP(value) ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos)))
384 #define US_MAN_RX_PP_ALL_ONE (0x0u << 24)
385 #define US_MAN_RX_PP_ALL_ZERO (0x1u << 24)
386 #define US_MAN_RX_PP_ZERO_ONE (0x2u << 24)
387 #define US_MAN_RX_PP_ONE_ZERO (0x3u << 24)
388 #define US_MAN_RX_MPOL (0x1u << 28)
389 #define US_MAN_ONE (0x1u << 29)
390 #define US_MAN_DRIFT (0x1u << 30)
391 #define US_MAN_RXIDLEV (0x1u << 31)
392 /* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */
393 #define US_LINMR_NACT_Pos 0
394 #define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos)
395 #define US_LINMR_NACT(value) ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos)))
396 #define US_LINMR_NACT_PUBLISH (0x0u << 0)
397 #define US_LINMR_NACT_SUBSCRIBE (0x1u << 0)
398 #define US_LINMR_NACT_IGNORE (0x2u << 0)
399 #define US_LINMR_PARDIS (0x1u << 2)
400 #define US_LINMR_CHKDIS (0x1u << 3)
401 #define US_LINMR_CHKTYP (0x1u << 4)
402 #define US_LINMR_DLM (0x1u << 5)
403 #define US_LINMR_FSDIS (0x1u << 6)
404 #define US_LINMR_WKUPTYP (0x1u << 7)
405 #define US_LINMR_DLC_Pos 8
406 #define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos)
407 #define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)))
408 #define US_LINMR_PDCM (0x1u << 16)
409 #define US_LINMR_SYNCDIS (0x1u << 17)
410 /* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */
411 #define US_LINIR_IDCHR_Pos 0
412 #define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos)
413 #define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)))
414 /* -------- US_LINBRR : (USART Offset: 0x005C) LIN Baud Rate Register -------- */
415 #define US_LINBRR_LINCD_Pos 0
416 #define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos)
417 #define US_LINBRR_LINFP_Pos 16
418 #define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos)
419 /* -------- US_LONMR : (USART Offset: 0x0060) LON Mode Register -------- */
420 #define US_LONMR_COMMT (0x1u << 0)
421 #define US_LONMR_COLDET (0x1u << 1)
422 #define US_LONMR_TCOL (0x1u << 2)
423 #define US_LONMR_CDTAIL (0x1u << 3)
424 #define US_LONMR_DMAM (0x1u << 4)
425 #define US_LONMR_LCDS (0x1u << 5)
426 #define US_LONMR_EOFS_Pos 16
427 #define US_LONMR_EOFS_Msk (0xffu << US_LONMR_EOFS_Pos)
428 #define US_LONMR_EOFS(value) ((US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos)))
429 /* -------- US_LONPR : (USART Offset: 0x0064) LON Preamble Register -------- */
430 #define US_LONPR_LONPL_Pos 0
431 #define US_LONPR_LONPL_Msk (0x3fffu << US_LONPR_LONPL_Pos)
432 #define US_LONPR_LONPL(value) ((US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos)))
433 /* -------- US_LONDL : (USART Offset: 0x0068) LON Data Length Register -------- */
434 #define US_LONDL_LONDL_Pos 0
435 #define US_LONDL_LONDL_Msk (0xffu << US_LONDL_LONDL_Pos)
436 #define US_LONDL_LONDL(value) ((US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos)))
437 /* -------- US_LONL2HDR : (USART Offset: 0x006C) LON L2HDR Register -------- */
438 #define US_LONL2HDR_BLI_Pos 0
439 #define US_LONL2HDR_BLI_Msk (0x3fu << US_LONL2HDR_BLI_Pos)
440 #define US_LONL2HDR_BLI(value) ((US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos)))
441 #define US_LONL2HDR_ALTP (0x1u << 6)
442 #define US_LONL2HDR_PB (0x1u << 7)
443 /* -------- US_LONBL : (USART Offset: 0x0070) LON Backlog Register -------- */
444 #define US_LONBL_LONBL_Pos 0
445 #define US_LONBL_LONBL_Msk (0x3fu << US_LONBL_LONBL_Pos)
446 /* -------- US_LONB1TX : (USART Offset: 0x0074) LON Beta1 Tx Register -------- */
447 #define US_LONB1TX_BETA1TX_Pos 0
448 #define US_LONB1TX_BETA1TX_Msk (0xffffffu << US_LONB1TX_BETA1TX_Pos)
449 #define US_LONB1TX_BETA1TX(value) ((US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos)))
450 /* -------- US_LONB1RX : (USART Offset: 0x0078) LON Beta1 Rx Register -------- */
451 #define US_LONB1RX_BETA1RX_Pos 0
452 #define US_LONB1RX_BETA1RX_Msk (0xffffffu << US_LONB1RX_BETA1RX_Pos)
453 #define US_LONB1RX_BETA1RX(value) ((US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos)))
454 /* -------- US_LONPRIO : (USART Offset: 0x007C) LON Priority Register -------- */
455 #define US_LONPRIO_PSNB_Pos 0
456 #define US_LONPRIO_PSNB_Msk (0x7fu << US_LONPRIO_PSNB_Pos)
457 #define US_LONPRIO_PSNB(value) ((US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos)))
458 #define US_LONPRIO_NPS_Pos 8
459 #define US_LONPRIO_NPS_Msk (0x7fu << US_LONPRIO_NPS_Pos)
460 #define US_LONPRIO_NPS(value) ((US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos)))
461 /* -------- US_IDTTX : (USART Offset: 0x0080) LON IDT Tx Register -------- */
462 #define US_IDTTX_IDTTX_Pos 0
463 #define US_IDTTX_IDTTX_Msk (0xffffffu << US_IDTTX_IDTTX_Pos)
464 #define US_IDTTX_IDTTX(value) ((US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos)))
465 /* -------- US_IDTRX : (USART Offset: 0x0084) LON IDT Rx Register -------- */
466 #define US_IDTRX_IDTRX_Pos 0
467 #define US_IDTRX_IDTRX_Msk (0xffffffu << US_IDTRX_IDTRX_Pos)
468 #define US_IDTRX_IDTRX(value) ((US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos)))
469 /* -------- US_ICDIFF : (USART Offset: 0x0088) IC DIFF Register -------- */
470 #define US_ICDIFF_ICDIFF_Pos 0
471 #define US_ICDIFF_ICDIFF_Msk (0xfu << US_ICDIFF_ICDIFF_Pos)
472 #define US_ICDIFF_ICDIFF(value) ((US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos)))
473 /* -------- US_WPMR : (USART Offset: 0x00E4) Write Protection Mode Register -------- */
474 #define US_WPMR_WPEN (0x1u << 0)
475 #define US_WPMR_WPKEY_Pos 8
476 #define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos)
477 #define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
478 #define US_WPMR_WPKEY_PASSWD (0x555341u << 8)
479 /* -------- US_WPSR : (USART Offset: 0x00E8) Write Protection Status Register -------- */
480 #define US_WPSR_WPVS (0x1u << 0)
481 #define US_WPSR_WPVSRC_Pos 8
482 #define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos)
483 /* -------- US_VERSION : (USART Offset: 0x00FC) Version Register -------- */
484 #define US_VERSION_VERSION_Pos 0
485 #define US_VERSION_VERSION_Msk (0xfffu << US_VERSION_VERSION_Pos)
486 #define US_VERSION_MFN_Pos 16
487 #define US_VERSION_MFN_Msk (0x7u << US_VERSION_MFN_Pos)
490 
491 
492 #endif /* _SAME70_USART_COMPONENT_ */
__IO uint32_t US_IDTRX
(Usart Offset: 0x0084) LON IDT Rx Register
__IO uint32_t US_BRGR
(Usart Offset: 0x0020) Baud Rate Generator Register
__IO uint32_t US_LINMR
(Usart Offset: 0x0054) LIN Mode Register
__IO uint32_t US_ICDIFF
(Usart Offset: 0x0088) IC DIFF Register
__IO uint32_t US_LINIR
(Usart Offset: 0x0058) LIN Identifier Register
__I uint32_t US_VERSION
(Usart Offset: 0x00FC) Version Register
Usart hardware registers.
#define __IO
Definition: core_cm7.h:266
__I uint32_t US_LINBRR
(Usart Offset: 0x005C) LIN Baud Rate Register
#define __O
Definition: core_cm7.h:265
__I uint32_t US_LONBL
(Usart Offset: 0x0070) LON Backlog Register
__IO uint32_t US_RTOR
(Usart Offset: 0x0024) Receiver Time-out Register
__IO uint32_t US_TTGR
(Usart Offset: 0x0028) Transmitter Timeguard Register
__IO uint32_t US_LONPR
(Usart Offset: 0x0064) LON Preamble Register
__IO uint32_t US_LONB1TX
(Usart Offset: 0x0074) LON Beta1 Tx Register
__IO uint32_t US_MAN
(Usart Offset: 0x0050) Manchester Configuration Register
__IO uint32_t US_LONL2HDR
(Usart Offset: 0x006C) LON L2HDR Register
__I uint32_t US_CSR
(Usart Offset: 0x0014) Channel Status Register
__I uint32_t US_IMR
(Usart Offset: 0x0010) Interrupt Mask Register
__O uint32_t US_CR
(Usart Offset: 0x0000) Control Register
__O uint32_t US_IDR
(Usart Offset: 0x000C) Interrupt Disable Register
__O uint32_t US_IER
(Usart Offset: 0x0008) Interrupt Enable Register
__IO uint32_t US_IF
(Usart Offset: 0x004C) IrDA Filter Register
__I uint32_t US_RHR
(Usart Offset: 0x0018) Receive Holding Register
__I uint32_t US_WPSR
(Usart Offset: 0x00E8) Write Protection Status Register
__IO uint32_t US_MR
(Usart Offset: 0x0004) Mode Register
__IO uint32_t US_LONMR
(Usart Offset: 0x0060) LON Mode Register
__IO uint32_t US_LONPRIO
(Usart Offset: 0x007C) LON Priority Register
__IO uint32_t US_LONDL
(Usart Offset: 0x0068) LON Data Length Register
__O uint32_t US_THR
(Usart Offset: 0x001C) Transmit Holding Register
__IO uint32_t US_IDTTX
(Usart Offset: 0x0080) LON IDT Tx Register
__IO uint32_t US_WPMR
(Usart Offset: 0x00E4) Write Protection Mode Register
__IO uint32_t US_LONB1RX
(Usart Offset: 0x0078) LON Beta1 Rx Register
#define __I
Definition: core_cm7.h:263
__IO uint32_t US_FIDI
(Usart Offset: 0x0040) FI DI Ratio Register
__I uint32_t US_NER
(Usart Offset: 0x0044) Number of Errors Register


inertial_sense_ros
Author(s):
autogenerated on Sat Sep 19 2020 03:19:05