system_same70.c
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #include "same70.h"
36 
37 /* @cond 0 */
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42 
43 /* @endcond */
44 
45 /* %ATMEL_SYSTEM% */
46 /* Clock Settings (600MHz PLL VDDIO 3.3V and VDDCORE 1.2V) */
47 /* Clock Settings (300MHz HCLK, 150MHz MCK)=> PRESC = 2, MDIV = 2 */
48 #define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8U))
49 #define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x31U) | \
50  CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U))
51 #define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK | (1<<8))
52 
54 
59  void SystemInit( void )
60 {
61  /* Set FWS according to SYS_BOARD_MCKR configuration */
62  EFC->EEFC_FMR = EEFC_FMR_FWS(5);
63 
64  /* Initialize main oscillator */
65  if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) )
66  {
68 
69  while ( !(PMC->PMC_SR & PMC_SR_MOSCXTS) )
70  {
71  }
72  }
73 
74  /* Switch to 3-20MHz Xtal oscillator */
76 
77  while ( !(PMC->PMC_SR & PMC_SR_MOSCSELS) )
78  {
79  }
80 
81  PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
82 
83  while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) )
84  {
85  }
86 
87  /* Initialize PLLA */
88  PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
89  while ( !(PMC->PMC_SR & PMC_SR_LOCKA) )
90  {
91  }
92 
93  /* Switch to main clock */
95  while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) )
96  {
97  }
98 
99  /* Switch to PLLA */
100  PMC->PMC_MCKR = SYS_BOARD_MCKR;
101  while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) )
102  {
103  }
104 
105  SystemCoreClock = CHIP_FREQ_CPU_MAX;
106 }
107 
109 {
110  /* Determine clock frequency according to clock register values */
111  switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk)
112  {
113  case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
114  if ( SUPC->SUPC_SR & SUPC_SR_OSCSEL )
115  {
116  SystemCoreClock = CHIP_FREQ_XTAL_32K;
117  }
118  else
119  {
120  SystemCoreClock = CHIP_FREQ_SLCK_RC;
121  }
122  break;
123 
124  case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
125  if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL )
126  {
127  SystemCoreClock = CHIP_FREQ_XTAL_12M;
128  }
129  else
130  {
131  SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
132 
133  switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk )
134  {
136  break;
137 
139  SystemCoreClock *= 2U;
140  break;
141 
143  SystemCoreClock *= 3U;
144  break;
145 
146  default:
147  break;
148  }
149  }
150  break;
151 
152  case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
153  if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL )
154  {
155  SystemCoreClock = CHIP_FREQ_XTAL_12M ;
156  }
157  else
158  {
159  SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
160 
161  switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk )
162  {
164  break;
165 
167  SystemCoreClock *= 2U;
168  break;
169 
171  SystemCoreClock *= 3U;
172  break;
173 
174  default:
175  break;
176  }
177  }
178 
179  if ( (uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK )
180  {
181  SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> CKGR_PLLAR_MULA_Pos) + 1U);
182  SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> CKGR_PLLAR_DIVA_Pos));
183  }
184  break;
185 
186  default:
187  break;
188  }
189 
190  if ( (PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3 )
191  {
192  SystemCoreClock /= 3U;
193  }
194  else
195  {
196  SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
197  }
198 }
202 void system_init_flash( uint32_t ul_clk )
203 {
204  /* Set FWS for embedded Flash access according to operating frequency */
205  if ( ul_clk < CHIP_FREQ_FWS_0 )
206  {
207  EFC->EEFC_FMR = EEFC_FMR_FWS(0)|EEFC_FMR_CLOE;
208  }
209  else
210  {
211  if (ul_clk < CHIP_FREQ_FWS_1)
212  {
213  EFC->EEFC_FMR = EEFC_FMR_FWS(1)|EEFC_FMR_CLOE;
214  }
215  else
216  {
217  if (ul_clk < CHIP_FREQ_FWS_2)
218  {
219  EFC->EEFC_FMR = EEFC_FMR_FWS(2)|EEFC_FMR_CLOE;
220  }
221  else
222  {
223  if ( ul_clk < CHIP_FREQ_FWS_3 )
224  {
225  EFC->EEFC_FMR = EEFC_FMR_FWS(3)|EEFC_FMR_CLOE;
226  }
227  else
228  {
229  if ( ul_clk < CHIP_FREQ_FWS_4 )
230  {
231  EFC->EEFC_FMR = EEFC_FMR_FWS(4)|EEFC_FMR_CLOE;
232  }
233  else
234  {
235  if ( ul_clk < CHIP_FREQ_FWS_5 )
236  {
237  EFC->EEFC_FMR = EEFC_FMR_FWS(5)|EEFC_FMR_CLOE;
238  }
239  else
240  {
241  EFC->EEFC_FMR = EEFC_FMR_FWS(6)|EEFC_FMR_CLOE;
242  }
243  }
244  }
245  }
246  }
247  }
248 }
249 /* @cond 0 */
251 #ifdef __cplusplus
252 }
253 #endif
254 
255 /* @endcond */
#define CKGR_MOR_MOSCSEL
(CKGR_MOR) Main Oscillator Selection
#define PMC
(PMC ) Base Address
Definition: same70j19.h:524
#define CKGR_MOR_MOSCRCF_4_MHz
(CKGR_MOR) Fast RC oscillator frequency is at 4 MHz (default)
#define CKGR_MOR_MOSCRCF_Msk
(CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection
#define CHIP_FREQ_CPU_MAX
Definition: same70j19.h:592
#define CKGR_PLLAR_MULA_Msk
(CKGR_PLLAR) PLLA Multiplier
#define PMC_MCKR_CSS_SLOW_CLK
(PMC_MCKR) Slow Clock is selected
#define CKGR_MOR_MOSCRCEN
(CKGR_MOR) Main On-Chip RC Oscillator Enable
#define CHIP_FREQ_XTAL_32K
Definition: same70j19.h:593
void SystemInit(void)
Setup the microcontroller system. Initialize the System and update the SystemFrequency variable...
Definition: system_same70.c:59
#define PMC_SR_MOSCXTS
(PMC_SR) Main Crystal Oscillator Status
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock with current core Clock retrieved from cpu registers. ...
#define SYS_BOARD_MCKR
Definition: system_same70.c:51
#define CHIP_FREQ_FWS_0
Maximum operating frequency when FWS is 0.
Definition: same70j19.h:597
#define PMC_MCKR_PRES_CLK_3
(PMC_MCKR) Selected clock divided by 3
#define CHIP_FREQ_XTAL_12M
Definition: same70j19.h:594
#define EEFC_FMR_FWS(value)
#define PMC_MCKR_CSS_MAIN_CLK
(PMC_MCKR) Main Clock is selected
#define CHIP_FREQ_FWS_5
Maximum operating frequency when FWS is 5.
Definition: same70j19.h:602
#define CKGR_MOR_MOSCXTEN
(CKGR_MOR) Main Crystal Oscillator Enable
#define CKGR_PLLAR_DIVA_Msk
(CKGR_PLLAR) PLLA Front End Divider
#define CKGR_MOR_MOSCRCF_12_MHz
(CKGR_MOR) Fast RC oscillator frequency is at 12 MHz
#define PMC_SR_LOCKA
(PMC_SR) PLLA Lock Status
void system_init_flash(uint32_t ul_clk)
#define CHIP_FREQ_FWS_3
Maximum operating frequency when FWS is 3.
Definition: same70j19.h:600
#define EFC
(EFC ) Base Address
Definition: same70j19.h:528
#define PMC_SR_MOSCSELS
(PMC_SR) Main Oscillator Selection Status
#define PMC_SR_MCKRDY
(PMC_SR) Master Clock Status
#define CHIP_FREQ_SLCK_RC
Definition: same70j19.h:587
#define SYS_BOARD_PLLAR
Definition: system_same70.c:49
#define CHIP_FREQ_FWS_2
Maximum operating frequency when FWS is 2.
Definition: same70j19.h:599
#define CHIP_FREQ_FWS_4
Maximum operating frequency when FWS is 4.
Definition: same70j19.h:601
#define PMC_MCKR_CSS_PLLA_CLK
(PMC_MCKR) PLLA Clock is selected
#define SUPC
(SUPC ) Base Address
Definition: same70j19.h:533
#define SYS_BOARD_OSCOUNT
Definition: system_same70.c:48
#define PMC_MCKR_PRES_Msk
(PMC_MCKR) Processor Clock Prescaler
#define CKGR_MOR_MOSCRCF_8_MHz
(CKGR_MOR) Fast RC oscillator frequency is at 8 MHz
#define PMC_MCKR_CSS_Msk
(PMC_MCKR) Master Clock Source Selection
#define CHIP_FREQ_FWS_1
Maximum operating frequency when FWS is 1.
Definition: same70j19.h:598
#define CHIP_FREQ_MAINCK_RC_4MHZ
Definition: same70j19.h:589
uint32_t SystemCoreClock
Definition: system_same70.c:53
#define SUPC_SR_OSCSEL
(SUPC_SR) 32-kHz Oscillator Selection Status
#define EEFC_FMR_CLOE
(EEFC_FMR) Code Loop Optimization Enable
#define CKGR_MOR_KEY_PASSWD


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:05