utils/cmsis/same70/include/component/pmc.h

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/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */

#ifndef _SAME70_PMC_COMPONENT_
#define _SAME70_PMC_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  __O  uint32_t PMC_SCER;       
  __O  uint32_t PMC_SCDR;       
  __I  uint32_t PMC_SCSR;       
  __I  uint32_t Reserved1[1];
  __O  uint32_t PMC_PCER0;      
  __O  uint32_t PMC_PCDR0;      
  __I  uint32_t PMC_PCSR0;      
  __IO uint32_t CKGR_UCKR;      
  __IO uint32_t CKGR_MOR;       
  __IO uint32_t CKGR_MCFR;      
  __IO uint32_t CKGR_PLLAR;     
  __I  uint32_t Reserved2[1];
  __IO uint32_t PMC_MCKR;       
  __I  uint32_t Reserved3[1];
  __IO uint32_t PMC_USB;        
  __I  uint32_t Reserved4[1];
  __IO uint32_t PMC_PCK[8];     
  __O  uint32_t PMC_IER;        
  __O  uint32_t PMC_IDR;        
  __I  uint32_t PMC_SR;         
  __I  uint32_t PMC_IMR;        
  __IO uint32_t PMC_FSMR;       
  __IO uint32_t PMC_FSPR;       
  __O  uint32_t PMC_FOCR;       
  __I  uint32_t Reserved5[26];
  __IO uint32_t PMC_WPMR;       
  __I  uint32_t PMC_WPSR;       
  __I  uint32_t Reserved6[4];
  __I  uint32_t PMC_VERSION;    
  __O  uint32_t PMC_PCER1;      
  __O  uint32_t PMC_PCDR1;      
  __I  uint32_t PMC_PCSR1;      
  __IO uint32_t PMC_PCR;        
  __IO uint32_t PMC_OCR;        
  __O  uint32_t PMC_SLPWK_ER0;  
  __O  uint32_t PMC_SLPWK_DR0;  
  __I  uint32_t PMC_SLPWK_SR0;  
  __I  uint32_t PMC_SLPWK_ASR0; 
  __I  uint32_t Reserved7[3];
  __IO uint32_t PMC_PMMR;       
  __O  uint32_t PMC_SLPWK_ER1;  
  __O  uint32_t PMC_SLPWK_DR1;  
  __I  uint32_t PMC_SLPWK_SR1;  
  __I  uint32_t PMC_SLPWK_ASR1; 
  __I  uint32_t PMC_SLPWK_AIPR; 
  __I  uint32_t Reserved8[4];
  __IO uint32_t PMC_APLLACR;    
  __IO uint32_t PMC_WMST;       
} Pmc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
#define PMC_SCER_USBCLK (0x1u << 5) 
#define PMC_SCER_PCK0 (0x1u << 8) 
#define PMC_SCER_PCK1 (0x1u << 9) 
#define PMC_SCER_PCK2 (0x1u << 10) 
#define PMC_SCER_PCK3 (0x1u << 11) 
#define PMC_SCER_PCK4 (0x1u << 12) 
#define PMC_SCER_PCK5 (0x1u << 13) 
#define PMC_SCER_PCK6 (0x1u << 14) 
/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
#define PMC_SCDR_USBCLK (0x1u << 5) 
#define PMC_SCDR_PCK0 (0x1u << 8) 
#define PMC_SCDR_PCK1 (0x1u << 9) 
#define PMC_SCDR_PCK2 (0x1u << 10) 
#define PMC_SCDR_PCK3 (0x1u << 11) 
#define PMC_SCDR_PCK4 (0x1u << 12) 
#define PMC_SCDR_PCK5 (0x1u << 13) 
#define PMC_SCDR_PCK6 (0x1u << 14) 
/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
#define PMC_SCSR_HCLKS (0x1u << 0) 
#define PMC_SCSR_USBCLK (0x1u << 5) 
#define PMC_SCSR_PCK0 (0x1u << 8) 
#define PMC_SCSR_PCK1 (0x1u << 9) 
#define PMC_SCSR_PCK2 (0x1u << 10) 
#define PMC_SCSR_PCK3 (0x1u << 11) 
#define PMC_SCSR_PCK4 (0x1u << 12) 
#define PMC_SCSR_PCK5 (0x1u << 13) 
#define PMC_SCSR_PCK6 (0x1u << 14) 
/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
#define PMC_PCER0_PID7 (0x1u << 7) 
#define PMC_PCER0_PID8 (0x1u << 8) 
#define PMC_PCER0_PID9 (0x1u << 9) 
#define PMC_PCER0_PID10 (0x1u << 10) 
#define PMC_PCER0_PID11 (0x1u << 11) 
#define PMC_PCER0_PID12 (0x1u << 12) 
#define PMC_PCER0_PID13 (0x1u << 13) 
#define PMC_PCER0_PID14 (0x1u << 14) 
#define PMC_PCER0_PID15 (0x1u << 15) 
#define PMC_PCER0_PID16 (0x1u << 16) 
#define PMC_PCER0_PID17 (0x1u << 17) 
#define PMC_PCER0_PID18 (0x1u << 18) 
#define PMC_PCER0_PID19 (0x1u << 19) 
#define PMC_PCER0_PID20 (0x1u << 20) 
#define PMC_PCER0_PID21 (0x1u << 21) 
#define PMC_PCER0_PID22 (0x1u << 22) 
#define PMC_PCER0_PID23 (0x1u << 23) 
#define PMC_PCER0_PID24 (0x1u << 24) 
#define PMC_PCER0_PID25 (0x1u << 25) 
#define PMC_PCER0_PID26 (0x1u << 26) 
#define PMC_PCER0_PID27 (0x1u << 27) 
#define PMC_PCER0_PID28 (0x1u << 28) 
#define PMC_PCER0_PID29 (0x1u << 29) 
#define PMC_PCER0_PID30 (0x1u << 30) 
#define PMC_PCER0_PID31 (0x1u << 31) 
/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
#define PMC_PCDR0_PID7 (0x1u << 7) 
#define PMC_PCDR0_PID8 (0x1u << 8) 
#define PMC_PCDR0_PID9 (0x1u << 9) 
#define PMC_PCDR0_PID10 (0x1u << 10) 
#define PMC_PCDR0_PID11 (0x1u << 11) 
#define PMC_PCDR0_PID12 (0x1u << 12) 
#define PMC_PCDR0_PID13 (0x1u << 13) 
#define PMC_PCDR0_PID14 (0x1u << 14) 
#define PMC_PCDR0_PID15 (0x1u << 15) 
#define PMC_PCDR0_PID16 (0x1u << 16) 
#define PMC_PCDR0_PID17 (0x1u << 17) 
#define PMC_PCDR0_PID18 (0x1u << 18) 
#define PMC_PCDR0_PID19 (0x1u << 19) 
#define PMC_PCDR0_PID20 (0x1u << 20) 
#define PMC_PCDR0_PID21 (0x1u << 21) 
#define PMC_PCDR0_PID22 (0x1u << 22) 
#define PMC_PCDR0_PID23 (0x1u << 23) 
#define PMC_PCDR0_PID24 (0x1u << 24) 
#define PMC_PCDR0_PID25 (0x1u << 25) 
#define PMC_PCDR0_PID26 (0x1u << 26) 
#define PMC_PCDR0_PID27 (0x1u << 27) 
#define PMC_PCDR0_PID28 (0x1u << 28) 
#define PMC_PCDR0_PID29 (0x1u << 29) 
#define PMC_PCDR0_PID30 (0x1u << 30) 
#define PMC_PCDR0_PID31 (0x1u << 31) 
/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
#define PMC_PCSR0_PID7 (0x1u << 7) 
#define PMC_PCSR0_PID8 (0x1u << 8) 
#define PMC_PCSR0_PID9 (0x1u << 9) 
#define PMC_PCSR0_PID10 (0x1u << 10) 
#define PMC_PCSR0_PID11 (0x1u << 11) 
#define PMC_PCSR0_PID12 (0x1u << 12) 
#define PMC_PCSR0_PID13 (0x1u << 13) 
#define PMC_PCSR0_PID14 (0x1u << 14) 
#define PMC_PCSR0_PID15 (0x1u << 15) 
#define PMC_PCSR0_PID16 (0x1u << 16) 
#define PMC_PCSR0_PID17 (0x1u << 17) 
#define PMC_PCSR0_PID18 (0x1u << 18) 
#define PMC_PCSR0_PID19 (0x1u << 19) 
#define PMC_PCSR0_PID20 (0x1u << 20) 
#define PMC_PCSR0_PID21 (0x1u << 21) 
#define PMC_PCSR0_PID22 (0x1u << 22) 
#define PMC_PCSR0_PID23 (0x1u << 23) 
#define PMC_PCSR0_PID24 (0x1u << 24) 
#define PMC_PCSR0_PID25 (0x1u << 25) 
#define PMC_PCSR0_PID26 (0x1u << 26) 
#define PMC_PCSR0_PID27 (0x1u << 27) 
#define PMC_PCSR0_PID28 (0x1u << 28) 
#define PMC_PCSR0_PID29 (0x1u << 29) 
#define PMC_PCSR0_PID30 (0x1u << 30) 
#define PMC_PCSR0_PID31 (0x1u << 31) 
/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */
#define CKGR_UCKR_UPLLEN (0x1u << 16) 
#define CKGR_UCKR_UPLLCOUNT_Pos 20
#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) 
#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))
/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
#define CKGR_MOR_MOSCXTEN (0x1u << 0) 
#define CKGR_MOR_MOSCXTBY (0x1u << 1) 
#define CKGR_MOR_WAITMODE (0x1u << 2) 
#define CKGR_MOR_MOSCRCEN (0x1u << 3) 
#define CKGR_MOR_MOSCRCF_Pos 4
#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) 
#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos)))
#define   CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) 
#define   CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) 
#define   CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) 
#define CKGR_MOR_MOSCXTST_Pos 8
#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) 
#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
#define CKGR_MOR_KEY_Pos 16
#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) 
#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
#define   CKGR_MOR_KEY_PASSWD (0x37u << 16) 
#define CKGR_MOR_MOSCSEL (0x1u << 24) 
#define CKGR_MOR_CFDEN (0x1u << 25) 
#define CKGR_MOR_XT32KFME (0x1u << 26) 
/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
#define CKGR_MCFR_MAINF_Pos 0
#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) 
#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)))
#define CKGR_MCFR_MAINFRDY (0x1u << 16) 
#define CKGR_MCFR_RCMEAS (0x1u << 20) 
#define CKGR_MCFR_CCSS (0x1u << 24) 
/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
#define CKGR_PLLAR_DIVA_Pos 0
#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) 
#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
#define   CKGR_PLLAR_DIVA_0 (0x0u << 0) 
#define   CKGR_PLLAR_DIVA_BYPASS (0x1u << 0) 
#define CKGR_PLLAR_PLLACOUNT_Pos 8
#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) 
#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
#define CKGR_PLLAR_MULA_Pos 16
#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) 
#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
#define CKGR_PLLAR_ONE (0x1u << 29) 
/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
#define PMC_MCKR_CSS_Pos 0
#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) 
#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos)))
#define   PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) 
#define   PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) 
#define   PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) 
#define   PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) 
#define PMC_MCKR_PRES_Pos 4
#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) 
#define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos)))
#define   PMC_MCKR_PRES_CLK_1 (0x0u << 4) 
#define   PMC_MCKR_PRES_CLK_2 (0x1u << 4) 
#define   PMC_MCKR_PRES_CLK_4 (0x2u << 4) 
#define   PMC_MCKR_PRES_CLK_8 (0x3u << 4) 
#define   PMC_MCKR_PRES_CLK_16 (0x4u << 4) 
#define   PMC_MCKR_PRES_CLK_32 (0x5u << 4) 
#define   PMC_MCKR_PRES_CLK_64 (0x6u << 4) 
#define   PMC_MCKR_PRES_CLK_3 (0x7u << 4) 
#define PMC_MCKR_MDIV_Pos 8
#define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos) 
#define PMC_MCKR_MDIV(value) ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos)))
#define   PMC_MCKR_MDIV_EQ_PCK (0x0u << 8) 
#define   PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8) 
#define   PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8) 
#define   PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8) 
#define PMC_MCKR_UPLLDIV2 (0x1u << 13) 
/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
#define PMC_USB_USBS (0x1u << 0) 
#define PMC_USB_USBDIV_Pos 8
#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) 
#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
/* -------- PMC_PCK[8] : (PMC Offset: 0x40) Programmable Clock Register (chid = 0) -------- */
#define PMC_PCK_CSS_Pos 0
#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) 
#define PMC_PCK_CSS(value) ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos)))
#define   PMC_PCK_CSS_SLOW_CLK (0x0u << 0) 
#define   PMC_PCK_CSS_MAIN_CLK (0x1u << 0) 
#define   PMC_PCK_CSS_PLLA_CLK (0x2u << 0) 
#define   PMC_PCK_CSS_UPLL_CLK (0x3u << 0) 
#define   PMC_PCK_CSS_MCK (0x4u << 0) 
#define PMC_PCK_PRES_Pos 4
#define PMC_PCK_PRES_Msk (0xffu << PMC_PCK_PRES_Pos) 
#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)))
/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
#define PMC_IER_MOSCXTS (0x1u << 0) 
#define PMC_IER_LOCKA (0x1u << 1) 
#define PMC_IER_MCKRDY (0x1u << 3) 
#define PMC_IER_LOCKU (0x1u << 6) 
#define PMC_IER_PCKRDY0 (0x1u << 8) 
#define PMC_IER_PCKRDY1 (0x1u << 9) 
#define PMC_IER_PCKRDY2 (0x1u << 10) 
#define PMC_IER_PCKRDY3 (0x1u << 11) 
#define PMC_IER_PCKRDY4 (0x1u << 12) 
#define PMC_IER_PCKRDY5 (0x1u << 13) 
#define PMC_IER_PCKRDY6 (0x1u << 14) 
#define PMC_IER_MOSCSELS (0x1u << 16) 
#define PMC_IER_MOSCRCS (0x1u << 17) 
#define PMC_IER_CFDEV (0x1u << 18) 
#define PMC_IER_XT32KERR (0x1u << 21) 
/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
#define PMC_IDR_MOSCXTS (0x1u << 0) 
#define PMC_IDR_LOCKA (0x1u << 1) 
#define PMC_IDR_MCKRDY (0x1u << 3) 
#define PMC_IDR_LOCKU (0x1u << 6) 
#define PMC_IDR_PCKRDY0 (0x1u << 8) 
#define PMC_IDR_PCKRDY1 (0x1u << 9) 
#define PMC_IDR_PCKRDY2 (0x1u << 10) 
#define PMC_IDR_PCKRDY3 (0x1u << 11) 
#define PMC_IDR_PCKRDY4 (0x1u << 12) 
#define PMC_IDR_PCKRDY5 (0x1u << 13) 
#define PMC_IDR_PCKRDY6 (0x1u << 14) 
#define PMC_IDR_MOSCSELS (0x1u << 16) 
#define PMC_IDR_MOSCRCS (0x1u << 17) 
#define PMC_IDR_CFDEV (0x1u << 18) 
#define PMC_IDR_XT32KERR (0x1u << 21) 
/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
#define PMC_SR_MOSCXTS (0x1u << 0) 
#define PMC_SR_LOCKA (0x1u << 1) 
#define PMC_SR_MCKRDY (0x1u << 3) 
#define PMC_SR_LOCKU (0x1u << 6) 
#define PMC_SR_OSCSELS (0x1u << 7) 
#define PMC_SR_PCKRDY0 (0x1u << 8) 
#define PMC_SR_PCKRDY1 (0x1u << 9) 
#define PMC_SR_PCKRDY2 (0x1u << 10) 
#define PMC_SR_PCKRDY3 (0x1u << 11) 
#define PMC_SR_PCKRDY4 (0x1u << 12) 
#define PMC_SR_PCKRDY5 (0x1u << 13) 
#define PMC_SR_PCKRDY6 (0x1u << 14) 
#define PMC_SR_MOSCSELS (0x1u << 16) 
#define PMC_SR_MOSCRCS (0x1u << 17) 
#define PMC_SR_CFDEV (0x1u << 18) 
#define PMC_SR_CFDS (0x1u << 19) 
#define PMC_SR_FOS (0x1u << 20) 
#define PMC_SR_XT32KERR (0x1u << 21) 
/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
#define PMC_IMR_MOSCXTS (0x1u << 0) 
#define PMC_IMR_LOCKA (0x1u << 1) 
#define PMC_IMR_MCKRDY (0x1u << 3) 
#define PMC_IMR_LOCKU (0x1u << 6) 
#define PMC_IMR_PCKRDY0 (0x1u << 8) 
#define PMC_IMR_PCKRDY1 (0x1u << 9) 
#define PMC_IMR_PCKRDY2 (0x1u << 10) 
#define PMC_IMR_PCKRDY3 (0x1u << 11) 
#define PMC_IMR_PCKRDY4 (0x1u << 12) 
#define PMC_IMR_PCKRDY5 (0x1u << 13) 
#define PMC_IMR_PCKRDY6 (0x1u << 14) 
#define PMC_IMR_MOSCSELS (0x1u << 16) 
#define PMC_IMR_MOSCRCS (0x1u << 17) 
#define PMC_IMR_CFDEV (0x1u << 18) 
#define PMC_IMR_XT32KERR (0x1u << 21) 
/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
#define PMC_FSMR_FSTT0 (0x1u << 0) 
#define PMC_FSMR_FSTT1 (0x1u << 1) 
#define PMC_FSMR_FSTT2 (0x1u << 2) 
#define PMC_FSMR_FSTT3 (0x1u << 3) 
#define PMC_FSMR_FSTT4 (0x1u << 4) 
#define PMC_FSMR_FSTT5 (0x1u << 5) 
#define PMC_FSMR_FSTT6 (0x1u << 6) 
#define PMC_FSMR_FSTT7 (0x1u << 7) 
#define PMC_FSMR_FSTT8 (0x1u << 8) 
#define PMC_FSMR_FSTT9 (0x1u << 9) 
#define PMC_FSMR_FSTT10 (0x1u << 10) 
#define PMC_FSMR_FSTT11 (0x1u << 11) 
#define PMC_FSMR_FSTT12 (0x1u << 12) 
#define PMC_FSMR_FSTT13 (0x1u << 13) 
#define PMC_FSMR_FSTT14 (0x1u << 14) 
#define PMC_FSMR_FSTT15 (0x1u << 15) 
#define PMC_FSMR_RTTAL (0x1u << 16) 
#define PMC_FSMR_RTCAL (0x1u << 17) 
#define PMC_FSMR_USBAL (0x1u << 18) 
#define PMC_FSMR_LPM (0x1u << 20) 
#define PMC_FSMR_FLPM_Pos 21
#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) 
#define PMC_FSMR_FLPM(value) ((PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos)))
#define   PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) 
#define   PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) 
#define   PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) 
#define PMC_FSMR_FFLPM (0x1u << 23) 
/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
#define PMC_FSPR_FSTP0 (0x1u << 0) 
#define PMC_FSPR_FSTP1 (0x1u << 1) 
#define PMC_FSPR_FSTP2 (0x1u << 2) 
#define PMC_FSPR_FSTP3 (0x1u << 3) 
#define PMC_FSPR_FSTP4 (0x1u << 4) 
#define PMC_FSPR_FSTP5 (0x1u << 5) 
#define PMC_FSPR_FSTP6 (0x1u << 6) 
#define PMC_FSPR_FSTP7 (0x1u << 7) 
#define PMC_FSPR_FSTP8 (0x1u << 8) 
#define PMC_FSPR_FSTP9 (0x1u << 9) 
#define PMC_FSPR_FSTP10 (0x1u << 10) 
#define PMC_FSPR_FSTP11 (0x1u << 11) 
#define PMC_FSPR_FSTP12 (0x1u << 12) 
#define PMC_FSPR_FSTP13 (0x1u << 13) 
#define PMC_FSPR_FSTP14 (0x1u << 14) 
#define PMC_FSPR_FSTP15 (0x1u << 15) 
/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
#define PMC_FOCR_FOCLR (0x1u << 0) 
/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */
#define PMC_WPMR_WPEN (0x1u << 0) 
#define PMC_WPMR_WPKEY_Pos 8
#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) 
#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
#define   PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) 
/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */
#define PMC_WPSR_WPVS (0x1u << 0) 
#define PMC_WPSR_WPVSRC_Pos 8
#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) 
/* -------- PMC_VERSION : (PMC Offset: 0x00FC) Version Register -------- */
#define PMC_VERSION_VERSION_Pos 0
#define PMC_VERSION_VERSION_Msk (0xfffu << PMC_VERSION_VERSION_Pos) 
#define PMC_VERSION_MFN_Pos 16
#define PMC_VERSION_MFN_Msk (0x7u << PMC_VERSION_MFN_Pos) 
/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
#define PMC_PCER1_PID32 (0x1u << 0) 
#define PMC_PCER1_PID33 (0x1u << 1) 
#define PMC_PCER1_PID34 (0x1u << 2) 
#define PMC_PCER1_PID35 (0x1u << 3) 
#define PMC_PCER1_PID37 (0x1u << 5) 
#define PMC_PCER1_PID39 (0x1u << 7) 
#define PMC_PCER1_PID40 (0x1u << 8) 
#define PMC_PCER1_PID41 (0x1u << 9) 
#define PMC_PCER1_PID42 (0x1u << 10) 
#define PMC_PCER1_PID43 (0x1u << 11) 
#define PMC_PCER1_PID44 (0x1u << 12) 
#define PMC_PCER1_PID45 (0x1u << 13) 
#define PMC_PCER1_PID46 (0x1u << 14) 
#define PMC_PCER1_PID47 (0x1u << 15) 
#define PMC_PCER1_PID48 (0x1u << 16) 
#define PMC_PCER1_PID49 (0x1u << 17) 
#define PMC_PCER1_PID50 (0x1u << 18) 
#define PMC_PCER1_PID51 (0x1u << 19) 
#define PMC_PCER1_PID52 (0x1u << 20) 
#define PMC_PCER1_PID53 (0x1u << 21) 
#define PMC_PCER1_PID56 (0x1u << 24) 
#define PMC_PCER1_PID57 (0x1u << 25) 
#define PMC_PCER1_PID58 (0x1u << 26) 
#define PMC_PCER1_PID59 (0x1u << 27) 
#define PMC_PCER1_PID60 (0x1u << 28) 
/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
#define PMC_PCDR1_PID32 (0x1u << 0) 
#define PMC_PCDR1_PID33 (0x1u << 1) 
#define PMC_PCDR1_PID34 (0x1u << 2) 
#define PMC_PCDR1_PID35 (0x1u << 3) 
#define PMC_PCDR1_PID37 (0x1u << 5) 
#define PMC_PCDR1_PID39 (0x1u << 7) 
#define PMC_PCDR1_PID40 (0x1u << 8) 
#define PMC_PCDR1_PID41 (0x1u << 9) 
#define PMC_PCDR1_PID42 (0x1u << 10) 
#define PMC_PCDR1_PID43 (0x1u << 11) 
#define PMC_PCDR1_PID44 (0x1u << 12) 
#define PMC_PCDR1_PID45 (0x1u << 13) 
#define PMC_PCDR1_PID46 (0x1u << 14) 
#define PMC_PCDR1_PID47 (0x1u << 15) 
#define PMC_PCDR1_PID48 (0x1u << 16) 
#define PMC_PCDR1_PID49 (0x1u << 17) 
#define PMC_PCDR1_PID50 (0x1u << 18) 
#define PMC_PCDR1_PID51 (0x1u << 19) 
#define PMC_PCDR1_PID52 (0x1u << 20) 
#define PMC_PCDR1_PID53 (0x1u << 21) 
#define PMC_PCDR1_PID56 (0x1u << 24) 
#define PMC_PCDR1_PID57 (0x1u << 25) 
#define PMC_PCDR1_PID58 (0x1u << 26) 
#define PMC_PCDR1_PID59 (0x1u << 27) 
#define PMC_PCDR1_PID60 (0x1u << 28) 
/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
#define PMC_PCSR1_PID32 (0x1u << 0) 
#define PMC_PCSR1_PID33 (0x1u << 1) 
#define PMC_PCSR1_PID34 (0x1u << 2) 
#define PMC_PCSR1_PID35 (0x1u << 3) 
#define PMC_PCSR1_PID37 (0x1u << 5) 
#define PMC_PCSR1_PID39 (0x1u << 7) 
#define PMC_PCSR1_PID40 (0x1u << 8) 
#define PMC_PCSR1_PID41 (0x1u << 9) 
#define PMC_PCSR1_PID42 (0x1u << 10) 
#define PMC_PCSR1_PID43 (0x1u << 11) 
#define PMC_PCSR1_PID44 (0x1u << 12) 
#define PMC_PCSR1_PID45 (0x1u << 13) 
#define PMC_PCSR1_PID46 (0x1u << 14) 
#define PMC_PCSR1_PID47 (0x1u << 15) 
#define PMC_PCSR1_PID48 (0x1u << 16) 
#define PMC_PCSR1_PID49 (0x1u << 17) 
#define PMC_PCSR1_PID50 (0x1u << 18) 
#define PMC_PCSR1_PID51 (0x1u << 19) 
#define PMC_PCSR1_PID52 (0x1u << 20) 
#define PMC_PCSR1_PID53 (0x1u << 21) 
#define PMC_PCSR1_PID56 (0x1u << 24) 
#define PMC_PCSR1_PID57 (0x1u << 25) 
#define PMC_PCSR1_PID58 (0x1u << 26) 
#define PMC_PCSR1_PID59 (0x1u << 27) 
#define PMC_PCSR1_PID60 (0x1u << 28) 
/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */
#define PMC_PCR_PID_Pos 0
#define PMC_PCR_PID_Msk (0x7fu << PMC_PCR_PID_Pos) 
#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)))
#define PMC_PCR_GCLKCSS_Pos 8
#define PMC_PCR_GCLKCSS_Msk (0x7u << PMC_PCR_GCLKCSS_Pos) 
#define PMC_PCR_GCLKCSS(value) ((PMC_PCR_GCLKCSS_Msk & ((value) << PMC_PCR_GCLKCSS_Pos)))
#define   PMC_PCR_GCLKCSS_SLOW_CLK (0x0u << 8) 
#define   PMC_PCR_GCLKCSS_MAIN_CLK (0x1u << 8) 
#define   PMC_PCR_GCLKCSS_PLLA_CLK (0x2u << 8) 
#define   PMC_PCR_GCLKCSS_UPLL_CLK (0x3u << 8) 
#define   PMC_PCR_GCLKCSS_MCK_CLK (0x4u << 8) 
#define PMC_PCR_CMD (0x1u << 12) 
#define PMC_PCR_DIV_Pos 16
#define PMC_PCR_DIV_Msk (0x3u << PMC_PCR_DIV_Pos) 
#define PMC_PCR_DIV(value) ((PMC_PCR_DIV_Msk & ((value) << PMC_PCR_DIV_Pos)))
#define   PMC_PCR_DIV_PERIPH_DIV_MCK (0x0u << 16) 
#define   PMC_PCR_DIV_PERIPH_DIV2_MCK (0x1u << 16) 
#define   PMC_PCR_DIV_PERIPH_DIV4_MCK (0x2u << 16) 
#define   PMC_PCR_DIV_PERIPH_DIV8_MCK (0x3u << 16) 
#define PMC_PCR_GCLKDIV_Pos 20
#define PMC_PCR_GCLKDIV_Msk (0xffu << PMC_PCR_GCLKDIV_Pos) 
#define PMC_PCR_GCLKDIV(value) ((PMC_PCR_GCLKDIV_Msk & ((value) << PMC_PCR_GCLKDIV_Pos)))
#define PMC_PCR_EN (0x1u << 28) 
#define PMC_PCR_GCLKEN (0x1u << 29) 
/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */
#define PMC_OCR_CAL4_Pos 0
#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) 
#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))
#define PMC_OCR_SEL4 (0x1u << 7) 
#define PMC_OCR_CAL8_Pos 8
#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) 
#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))
#define PMC_OCR_SEL8 (0x1u << 15) 
#define PMC_OCR_CAL12_Pos 16
#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) 
#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))
#define PMC_OCR_SEL12 (0x1u << 23) 
/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x0114) SleepWalking Enable Register 0 -------- */
#define PMC_SLPWK_ER0_PID7 (0x1u << 7) 
#define PMC_SLPWK_ER0_PID8 (0x1u << 8) 
#define PMC_SLPWK_ER0_PID9 (0x1u << 9) 
#define PMC_SLPWK_ER0_PID10 (0x1u << 10) 
#define PMC_SLPWK_ER0_PID11 (0x1u << 11) 
#define PMC_SLPWK_ER0_PID12 (0x1u << 12) 
#define PMC_SLPWK_ER0_PID13 (0x1u << 13) 
#define PMC_SLPWK_ER0_PID14 (0x1u << 14) 
#define PMC_SLPWK_ER0_PID15 (0x1u << 15) 
#define PMC_SLPWK_ER0_PID16 (0x1u << 16) 
#define PMC_SLPWK_ER0_PID17 (0x1u << 17) 
#define PMC_SLPWK_ER0_PID18 (0x1u << 18) 
#define PMC_SLPWK_ER0_PID19 (0x1u << 19) 
#define PMC_SLPWK_ER0_PID20 (0x1u << 20) 
#define PMC_SLPWK_ER0_PID21 (0x1u << 21) 
#define PMC_SLPWK_ER0_PID22 (0x1u << 22) 
#define PMC_SLPWK_ER0_PID23 (0x1u << 23) 
#define PMC_SLPWK_ER0_PID24 (0x1u << 24) 
#define PMC_SLPWK_ER0_PID25 (0x1u << 25) 
#define PMC_SLPWK_ER0_PID26 (0x1u << 26) 
#define PMC_SLPWK_ER0_PID27 (0x1u << 27) 
#define PMC_SLPWK_ER0_PID28 (0x1u << 28) 
#define PMC_SLPWK_ER0_PID29 (0x1u << 29) 
#define PMC_SLPWK_ER0_PID30 (0x1u << 30) 
#define PMC_SLPWK_ER0_PID31 (0x1u << 31) 
/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x0118) SleepWalking Disable Register 0 -------- */
#define PMC_SLPWK_DR0_PID7 (0x1u << 7) 
#define PMC_SLPWK_DR0_PID8 (0x1u << 8) 
#define PMC_SLPWK_DR0_PID9 (0x1u << 9) 
#define PMC_SLPWK_DR0_PID10 (0x1u << 10) 
#define PMC_SLPWK_DR0_PID11 (0x1u << 11) 
#define PMC_SLPWK_DR0_PID12 (0x1u << 12) 
#define PMC_SLPWK_DR0_PID13 (0x1u << 13) 
#define PMC_SLPWK_DR0_PID14 (0x1u << 14) 
#define PMC_SLPWK_DR0_PID15 (0x1u << 15) 
#define PMC_SLPWK_DR0_PID16 (0x1u << 16) 
#define PMC_SLPWK_DR0_PID17 (0x1u << 17) 
#define PMC_SLPWK_DR0_PID18 (0x1u << 18) 
#define PMC_SLPWK_DR0_PID19 (0x1u << 19) 
#define PMC_SLPWK_DR0_PID20 (0x1u << 20) 
#define PMC_SLPWK_DR0_PID21 (0x1u << 21) 
#define PMC_SLPWK_DR0_PID22 (0x1u << 22) 
#define PMC_SLPWK_DR0_PID23 (0x1u << 23) 
#define PMC_SLPWK_DR0_PID24 (0x1u << 24) 
#define PMC_SLPWK_DR0_PID25 (0x1u << 25) 
#define PMC_SLPWK_DR0_PID26 (0x1u << 26) 
#define PMC_SLPWK_DR0_PID27 (0x1u << 27) 
#define PMC_SLPWK_DR0_PID28 (0x1u << 28) 
#define PMC_SLPWK_DR0_PID29 (0x1u << 29) 
#define PMC_SLPWK_DR0_PID30 (0x1u << 30) 
#define PMC_SLPWK_DR0_PID31 (0x1u << 31) 
/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x011C) SleepWalking Status Register 0 -------- */
#define PMC_SLPWK_SR0_PID7 (0x1u << 7) 
#define PMC_SLPWK_SR0_PID8 (0x1u << 8) 
#define PMC_SLPWK_SR0_PID9 (0x1u << 9) 
#define PMC_SLPWK_SR0_PID10 (0x1u << 10) 
#define PMC_SLPWK_SR0_PID11 (0x1u << 11) 
#define PMC_SLPWK_SR0_PID12 (0x1u << 12) 
#define PMC_SLPWK_SR0_PID13 (0x1u << 13) 
#define PMC_SLPWK_SR0_PID14 (0x1u << 14) 
#define PMC_SLPWK_SR0_PID15 (0x1u << 15) 
#define PMC_SLPWK_SR0_PID16 (0x1u << 16) 
#define PMC_SLPWK_SR0_PID17 (0x1u << 17) 
#define PMC_SLPWK_SR0_PID18 (0x1u << 18) 
#define PMC_SLPWK_SR0_PID19 (0x1u << 19) 
#define PMC_SLPWK_SR0_PID20 (0x1u << 20) 
#define PMC_SLPWK_SR0_PID21 (0x1u << 21) 
#define PMC_SLPWK_SR0_PID22 (0x1u << 22) 
#define PMC_SLPWK_SR0_PID23 (0x1u << 23) 
#define PMC_SLPWK_SR0_PID24 (0x1u << 24) 
#define PMC_SLPWK_SR0_PID25 (0x1u << 25) 
#define PMC_SLPWK_SR0_PID26 (0x1u << 26) 
#define PMC_SLPWK_SR0_PID27 (0x1u << 27) 
#define PMC_SLPWK_SR0_PID28 (0x1u << 28) 
#define PMC_SLPWK_SR0_PID29 (0x1u << 29) 
#define PMC_SLPWK_SR0_PID30 (0x1u << 30) 
#define PMC_SLPWK_SR0_PID31 (0x1u << 31) 
/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x0120) SleepWalking Activity Status Register 0 -------- */
#define PMC_SLPWK_ASR0_PID7 (0x1u << 7) 
#define PMC_SLPWK_ASR0_PID8 (0x1u << 8) 
#define PMC_SLPWK_ASR0_PID9 (0x1u << 9) 
#define PMC_SLPWK_ASR0_PID10 (0x1u << 10) 
#define PMC_SLPWK_ASR0_PID11 (0x1u << 11) 
#define PMC_SLPWK_ASR0_PID12 (0x1u << 12) 
#define PMC_SLPWK_ASR0_PID13 (0x1u << 13) 
#define PMC_SLPWK_ASR0_PID14 (0x1u << 14) 
#define PMC_SLPWK_ASR0_PID15 (0x1u << 15) 
#define PMC_SLPWK_ASR0_PID16 (0x1u << 16) 
#define PMC_SLPWK_ASR0_PID17 (0x1u << 17) 
#define PMC_SLPWK_ASR0_PID18 (0x1u << 18) 
#define PMC_SLPWK_ASR0_PID19 (0x1u << 19) 
#define PMC_SLPWK_ASR0_PID20 (0x1u << 20) 
#define PMC_SLPWK_ASR0_PID21 (0x1u << 21) 
#define PMC_SLPWK_ASR0_PID22 (0x1u << 22) 
#define PMC_SLPWK_ASR0_PID23 (0x1u << 23) 
#define PMC_SLPWK_ASR0_PID24 (0x1u << 24) 
#define PMC_SLPWK_ASR0_PID25 (0x1u << 25) 
#define PMC_SLPWK_ASR0_PID26 (0x1u << 26) 
#define PMC_SLPWK_ASR0_PID27 (0x1u << 27) 
#define PMC_SLPWK_ASR0_PID28 (0x1u << 28) 
#define PMC_SLPWK_ASR0_PID29 (0x1u << 29) 
#define PMC_SLPWK_ASR0_PID30 (0x1u << 30) 
#define PMC_SLPWK_ASR0_PID31 (0x1u << 31) 
/* -------- PMC_PMMR : (PMC Offset: 0x0130) PLL Maximum Multiplier Value Register -------- */
#define PMC_PMMR_PLLA_MMAX_Pos 0
#define PMC_PMMR_PLLA_MMAX_Msk (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos) 
#define PMC_PMMR_PLLA_MMAX(value) ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos)))
/* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x0134) SleepWalking Enable Register 1 -------- */
#define PMC_SLPWK_ER1_PID32 (0x1u << 0) 
#define PMC_SLPWK_ER1_PID33 (0x1u << 1) 
#define PMC_SLPWK_ER1_PID34 (0x1u << 2) 
#define PMC_SLPWK_ER1_PID35 (0x1u << 3) 
#define PMC_SLPWK_ER1_PID37 (0x1u << 5) 
#define PMC_SLPWK_ER1_PID39 (0x1u << 7) 
#define PMC_SLPWK_ER1_PID40 (0x1u << 8) 
#define PMC_SLPWK_ER1_PID41 (0x1u << 9) 
#define PMC_SLPWK_ER1_PID42 (0x1u << 10) 
#define PMC_SLPWK_ER1_PID43 (0x1u << 11) 
#define PMC_SLPWK_ER1_PID44 (0x1u << 12) 
#define PMC_SLPWK_ER1_PID45 (0x1u << 13) 
#define PMC_SLPWK_ER1_PID46 (0x1u << 14) 
#define PMC_SLPWK_ER1_PID47 (0x1u << 15) 
#define PMC_SLPWK_ER1_PID48 (0x1u << 16) 
#define PMC_SLPWK_ER1_PID49 (0x1u << 17) 
#define PMC_SLPWK_ER1_PID50 (0x1u << 18) 
#define PMC_SLPWK_ER1_PID51 (0x1u << 19) 
#define PMC_SLPWK_ER1_PID52 (0x1u << 20) 
#define PMC_SLPWK_ER1_PID53 (0x1u << 21) 
#define PMC_SLPWK_ER1_PID56 (0x1u << 24) 
#define PMC_SLPWK_ER1_PID57 (0x1u << 25) 
#define PMC_SLPWK_ER1_PID58 (0x1u << 26) 
#define PMC_SLPWK_ER1_PID59 (0x1u << 27) 
#define PMC_SLPWK_ER1_PID60 (0x1u << 28) 
/* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x0138) SleepWalking Disable Register 1 -------- */
#define PMC_SLPWK_DR1_PID32 (0x1u << 0) 
#define PMC_SLPWK_DR1_PID33 (0x1u << 1) 
#define PMC_SLPWK_DR1_PID34 (0x1u << 2) 
#define PMC_SLPWK_DR1_PID35 (0x1u << 3) 
#define PMC_SLPWK_DR1_PID37 (0x1u << 5) 
#define PMC_SLPWK_DR1_PID39 (0x1u << 7) 
#define PMC_SLPWK_DR1_PID40 (0x1u << 8) 
#define PMC_SLPWK_DR1_PID41 (0x1u << 9) 
#define PMC_SLPWK_DR1_PID42 (0x1u << 10) 
#define PMC_SLPWK_DR1_PID43 (0x1u << 11) 
#define PMC_SLPWK_DR1_PID44 (0x1u << 12) 
#define PMC_SLPWK_DR1_PID45 (0x1u << 13) 
#define PMC_SLPWK_DR1_PID46 (0x1u << 14) 
#define PMC_SLPWK_DR1_PID47 (0x1u << 15) 
#define PMC_SLPWK_DR1_PID48 (0x1u << 16) 
#define PMC_SLPWK_DR1_PID49 (0x1u << 17) 
#define PMC_SLPWK_DR1_PID50 (0x1u << 18) 
#define PMC_SLPWK_DR1_PID51 (0x1u << 19) 
#define PMC_SLPWK_DR1_PID52 (0x1u << 20) 
#define PMC_SLPWK_DR1_PID53 (0x1u << 21) 
#define PMC_SLPWK_DR1_PID56 (0x1u << 24) 
#define PMC_SLPWK_DR1_PID57 (0x1u << 25) 
#define PMC_SLPWK_DR1_PID58 (0x1u << 26) 
#define PMC_SLPWK_DR1_PID59 (0x1u << 27) 
#define PMC_SLPWK_DR1_PID60 (0x1u << 28) 
/* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x013C) SleepWalking Status Register 1 -------- */
#define PMC_SLPWK_SR1_PID32 (0x1u << 0) 
#define PMC_SLPWK_SR1_PID33 (0x1u << 1) 
#define PMC_SLPWK_SR1_PID34 (0x1u << 2) 
#define PMC_SLPWK_SR1_PID35 (0x1u << 3) 
#define PMC_SLPWK_SR1_PID37 (0x1u << 5) 
#define PMC_SLPWK_SR1_PID39 (0x1u << 7) 
#define PMC_SLPWK_SR1_PID40 (0x1u << 8) 
#define PMC_SLPWK_SR1_PID41 (0x1u << 9) 
#define PMC_SLPWK_SR1_PID42 (0x1u << 10) 
#define PMC_SLPWK_SR1_PID43 (0x1u << 11) 
#define PMC_SLPWK_SR1_PID44 (0x1u << 12) 
#define PMC_SLPWK_SR1_PID45 (0x1u << 13) 
#define PMC_SLPWK_SR1_PID46 (0x1u << 14) 
#define PMC_SLPWK_SR1_PID47 (0x1u << 15) 
#define PMC_SLPWK_SR1_PID48 (0x1u << 16) 
#define PMC_SLPWK_SR1_PID49 (0x1u << 17) 
#define PMC_SLPWK_SR1_PID50 (0x1u << 18) 
#define PMC_SLPWK_SR1_PID51 (0x1u << 19) 
#define PMC_SLPWK_SR1_PID52 (0x1u << 20) 
#define PMC_SLPWK_SR1_PID53 (0x1u << 21) 
#define PMC_SLPWK_SR1_PID56 (0x1u << 24) 
#define PMC_SLPWK_SR1_PID57 (0x1u << 25) 
#define PMC_SLPWK_SR1_PID58 (0x1u << 26) 
#define PMC_SLPWK_SR1_PID59 (0x1u << 27) 
#define PMC_SLPWK_SR1_PID60 (0x1u << 28) 
/* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x0140) SleepWalking Activity Status Register 1 -------- */
#define PMC_SLPWK_ASR1_PID32 (0x1u << 0) 
#define PMC_SLPWK_ASR1_PID33 (0x1u << 1) 
#define PMC_SLPWK_ASR1_PID34 (0x1u << 2) 
#define PMC_SLPWK_ASR1_PID35 (0x1u << 3) 
#define PMC_SLPWK_ASR1_PID37 (0x1u << 5) 
#define PMC_SLPWK_ASR1_PID39 (0x1u << 7) 
#define PMC_SLPWK_ASR1_PID40 (0x1u << 8) 
#define PMC_SLPWK_ASR1_PID41 (0x1u << 9) 
#define PMC_SLPWK_ASR1_PID42 (0x1u << 10) 
#define PMC_SLPWK_ASR1_PID43 (0x1u << 11) 
#define PMC_SLPWK_ASR1_PID44 (0x1u << 12) 
#define PMC_SLPWK_ASR1_PID45 (0x1u << 13) 
#define PMC_SLPWK_ASR1_PID46 (0x1u << 14) 
#define PMC_SLPWK_ASR1_PID47 (0x1u << 15) 
#define PMC_SLPWK_ASR1_PID48 (0x1u << 16) 
#define PMC_SLPWK_ASR1_PID49 (0x1u << 17) 
#define PMC_SLPWK_ASR1_PID50 (0x1u << 18) 
#define PMC_SLPWK_ASR1_PID51 (0x1u << 19) 
#define PMC_SLPWK_ASR1_PID52 (0x1u << 20) 
#define PMC_SLPWK_ASR1_PID53 (0x1u << 21) 
#define PMC_SLPWK_ASR1_PID56 (0x1u << 24) 
#define PMC_SLPWK_ASR1_PID57 (0x1u << 25) 
#define PMC_SLPWK_ASR1_PID58 (0x1u << 26) 
#define PMC_SLPWK_ASR1_PID59 (0x1u << 27) 
#define PMC_SLPWK_ASR1_PID60 (0x1u << 28) 
/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x0144) SleepWalking Activity In Progress Register -------- */
#define PMC_SLPWK_AIPR_AIP (0x1u << 0) 
/* -------- PMC_APLLACR : (PMC Offset: 0x0158) Audio PLL Analog Configuration Register -------- */
#define PMC_APLLACR_DCOFLTSEL_Pos 0
#define PMC_APLLACR_DCOFLTSEL_Msk (0xfu << PMC_APLLACR_DCOFLTSEL_Pos) 
#define PMC_APLLACR_DCOFLTSEL(value) ((PMC_APLLACR_DCOFLTSEL_Msk & ((value) << PMC_APLLACR_DCOFLTSEL_Pos)))
#define PMC_APLLACR_FLTSEL_Pos 4
#define PMC_APLLACR_FLTSEL_Msk (0xfu << PMC_APLLACR_FLTSEL_Pos) 
#define PMC_APLLACR_FLTSEL(value) ((PMC_APLLACR_FLTSEL_Msk & ((value) << PMC_APLLACR_FLTSEL_Pos)))
#define PMC_APLLACR_BIAS_Pos 8
#define PMC_APLLACR_BIAS_Msk (0x3u << PMC_APLLACR_BIAS_Pos) 
#define PMC_APLLACR_BIAS(value) ((PMC_APLLACR_BIAS_Msk & ((value) << PMC_APLLACR_BIAS_Pos)))
/* -------- PMC_WMST : (PMC Offset: 0x015C) Wait Mode Startup Time Register -------- */
#define PMC_WMST_WMST_Pos 0
#define PMC_WMST_WMST_Msk (0xffu << PMC_WMST_WMST_Pos) 
#define PMC_WMST_WMST(value) ((PMC_WMST_WMST_Msk & ((value) << PMC_WMST_WMST_Pos)))
#define PMC_WMST_KEY_Pos 24
#define PMC_WMST_KEY_Msk (0xffu << PMC_WMST_KEY_Pos) 
#define PMC_WMST_KEY(value) ((PMC_WMST_KEY_Msk & ((value) << PMC_WMST_KEY_Pos)))
#define   PMC_WMST_KEY_PASSWD (0x5Au << 24) 


#endif /* _SAME70_PMC_COMPONENT_ */