utils/cmsis/same70/include/component/pmc.h
Go to the documentation of this file.
1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_PMC_COMPONENT_
36 #define _SAME70_PMC_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __O uint32_t PMC_SCER;
48  __O uint32_t PMC_SCDR;
49  __I uint32_t PMC_SCSR;
50  __I uint32_t Reserved1[1];
51  __O uint32_t PMC_PCER0;
52  __O uint32_t PMC_PCDR0;
53  __I uint32_t PMC_PCSR0;
54  __IO uint32_t CKGR_UCKR;
55  __IO uint32_t CKGR_MOR;
56  __IO uint32_t CKGR_MCFR;
57  __IO uint32_t CKGR_PLLAR;
58  __I uint32_t Reserved2[1];
59  __IO uint32_t PMC_MCKR;
60  __I uint32_t Reserved3[1];
61  __IO uint32_t PMC_USB;
62  __I uint32_t Reserved4[1];
63  __IO uint32_t PMC_PCK[8];
64  __O uint32_t PMC_IER;
65  __O uint32_t PMC_IDR;
66  __I uint32_t PMC_SR;
67  __I uint32_t PMC_IMR;
68  __IO uint32_t PMC_FSMR;
69  __IO uint32_t PMC_FSPR;
70  __O uint32_t PMC_FOCR;
71  __I uint32_t Reserved5[26];
72  __IO uint32_t PMC_WPMR;
73  __I uint32_t PMC_WPSR;
74  __I uint32_t Reserved6[4];
75  __I uint32_t PMC_VERSION;
76  __O uint32_t PMC_PCER1;
77  __O uint32_t PMC_PCDR1;
78  __I uint32_t PMC_PCSR1;
79  __IO uint32_t PMC_PCR;
80  __IO uint32_t PMC_OCR;
81  __O uint32_t PMC_SLPWK_ER0;
82  __O uint32_t PMC_SLPWK_DR0;
83  __I uint32_t PMC_SLPWK_SR0;
84  __I uint32_t PMC_SLPWK_ASR0;
85  __I uint32_t Reserved7[3];
86  __IO uint32_t PMC_PMMR;
87  __O uint32_t PMC_SLPWK_ER1;
88  __O uint32_t PMC_SLPWK_DR1;
89  __I uint32_t PMC_SLPWK_SR1;
90  __I uint32_t PMC_SLPWK_ASR1;
91  __I uint32_t PMC_SLPWK_AIPR;
92  __I uint32_t Reserved8[4];
93  __IO uint32_t PMC_APLLACR;
94  __IO uint32_t PMC_WMST;
95 } Pmc;
96 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
97 /* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
98 #define PMC_SCER_USBCLK (0x1u << 5)
99 #define PMC_SCER_PCK0 (0x1u << 8)
100 #define PMC_SCER_PCK1 (0x1u << 9)
101 #define PMC_SCER_PCK2 (0x1u << 10)
102 #define PMC_SCER_PCK3 (0x1u << 11)
103 #define PMC_SCER_PCK4 (0x1u << 12)
104 #define PMC_SCER_PCK5 (0x1u << 13)
105 #define PMC_SCER_PCK6 (0x1u << 14)
106 /* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
107 #define PMC_SCDR_USBCLK (0x1u << 5)
108 #define PMC_SCDR_PCK0 (0x1u << 8)
109 #define PMC_SCDR_PCK1 (0x1u << 9)
110 #define PMC_SCDR_PCK2 (0x1u << 10)
111 #define PMC_SCDR_PCK3 (0x1u << 11)
112 #define PMC_SCDR_PCK4 (0x1u << 12)
113 #define PMC_SCDR_PCK5 (0x1u << 13)
114 #define PMC_SCDR_PCK6 (0x1u << 14)
115 /* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
116 #define PMC_SCSR_HCLKS (0x1u << 0)
117 #define PMC_SCSR_USBCLK (0x1u << 5)
118 #define PMC_SCSR_PCK0 (0x1u << 8)
119 #define PMC_SCSR_PCK1 (0x1u << 9)
120 #define PMC_SCSR_PCK2 (0x1u << 10)
121 #define PMC_SCSR_PCK3 (0x1u << 11)
122 #define PMC_SCSR_PCK4 (0x1u << 12)
123 #define PMC_SCSR_PCK5 (0x1u << 13)
124 #define PMC_SCSR_PCK6 (0x1u << 14)
125 /* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
126 #define PMC_PCER0_PID7 (0x1u << 7)
127 #define PMC_PCER0_PID8 (0x1u << 8)
128 #define PMC_PCER0_PID9 (0x1u << 9)
129 #define PMC_PCER0_PID10 (0x1u << 10)
130 #define PMC_PCER0_PID11 (0x1u << 11)
131 #define PMC_PCER0_PID12 (0x1u << 12)
132 #define PMC_PCER0_PID13 (0x1u << 13)
133 #define PMC_PCER0_PID14 (0x1u << 14)
134 #define PMC_PCER0_PID15 (0x1u << 15)
135 #define PMC_PCER0_PID16 (0x1u << 16)
136 #define PMC_PCER0_PID17 (0x1u << 17)
137 #define PMC_PCER0_PID18 (0x1u << 18)
138 #define PMC_PCER0_PID19 (0x1u << 19)
139 #define PMC_PCER0_PID20 (0x1u << 20)
140 #define PMC_PCER0_PID21 (0x1u << 21)
141 #define PMC_PCER0_PID22 (0x1u << 22)
142 #define PMC_PCER0_PID23 (0x1u << 23)
143 #define PMC_PCER0_PID24 (0x1u << 24)
144 #define PMC_PCER0_PID25 (0x1u << 25)
145 #define PMC_PCER0_PID26 (0x1u << 26)
146 #define PMC_PCER0_PID27 (0x1u << 27)
147 #define PMC_PCER0_PID28 (0x1u << 28)
148 #define PMC_PCER0_PID29 (0x1u << 29)
149 #define PMC_PCER0_PID30 (0x1u << 30)
150 #define PMC_PCER0_PID31 (0x1u << 31)
151 /* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
152 #define PMC_PCDR0_PID7 (0x1u << 7)
153 #define PMC_PCDR0_PID8 (0x1u << 8)
154 #define PMC_PCDR0_PID9 (0x1u << 9)
155 #define PMC_PCDR0_PID10 (0x1u << 10)
156 #define PMC_PCDR0_PID11 (0x1u << 11)
157 #define PMC_PCDR0_PID12 (0x1u << 12)
158 #define PMC_PCDR0_PID13 (0x1u << 13)
159 #define PMC_PCDR0_PID14 (0x1u << 14)
160 #define PMC_PCDR0_PID15 (0x1u << 15)
161 #define PMC_PCDR0_PID16 (0x1u << 16)
162 #define PMC_PCDR0_PID17 (0x1u << 17)
163 #define PMC_PCDR0_PID18 (0x1u << 18)
164 #define PMC_PCDR0_PID19 (0x1u << 19)
165 #define PMC_PCDR0_PID20 (0x1u << 20)
166 #define PMC_PCDR0_PID21 (0x1u << 21)
167 #define PMC_PCDR0_PID22 (0x1u << 22)
168 #define PMC_PCDR0_PID23 (0x1u << 23)
169 #define PMC_PCDR0_PID24 (0x1u << 24)
170 #define PMC_PCDR0_PID25 (0x1u << 25)
171 #define PMC_PCDR0_PID26 (0x1u << 26)
172 #define PMC_PCDR0_PID27 (0x1u << 27)
173 #define PMC_PCDR0_PID28 (0x1u << 28)
174 #define PMC_PCDR0_PID29 (0x1u << 29)
175 #define PMC_PCDR0_PID30 (0x1u << 30)
176 #define PMC_PCDR0_PID31 (0x1u << 31)
177 /* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
178 #define PMC_PCSR0_PID7 (0x1u << 7)
179 #define PMC_PCSR0_PID8 (0x1u << 8)
180 #define PMC_PCSR0_PID9 (0x1u << 9)
181 #define PMC_PCSR0_PID10 (0x1u << 10)
182 #define PMC_PCSR0_PID11 (0x1u << 11)
183 #define PMC_PCSR0_PID12 (0x1u << 12)
184 #define PMC_PCSR0_PID13 (0x1u << 13)
185 #define PMC_PCSR0_PID14 (0x1u << 14)
186 #define PMC_PCSR0_PID15 (0x1u << 15)
187 #define PMC_PCSR0_PID16 (0x1u << 16)
188 #define PMC_PCSR0_PID17 (0x1u << 17)
189 #define PMC_PCSR0_PID18 (0x1u << 18)
190 #define PMC_PCSR0_PID19 (0x1u << 19)
191 #define PMC_PCSR0_PID20 (0x1u << 20)
192 #define PMC_PCSR0_PID21 (0x1u << 21)
193 #define PMC_PCSR0_PID22 (0x1u << 22)
194 #define PMC_PCSR0_PID23 (0x1u << 23)
195 #define PMC_PCSR0_PID24 (0x1u << 24)
196 #define PMC_PCSR0_PID25 (0x1u << 25)
197 #define PMC_PCSR0_PID26 (0x1u << 26)
198 #define PMC_PCSR0_PID27 (0x1u << 27)
199 #define PMC_PCSR0_PID28 (0x1u << 28)
200 #define PMC_PCSR0_PID29 (0x1u << 29)
201 #define PMC_PCSR0_PID30 (0x1u << 30)
202 #define PMC_PCSR0_PID31 (0x1u << 31)
203 /* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */
204 #define CKGR_UCKR_UPLLEN (0x1u << 16)
205 #define CKGR_UCKR_UPLLCOUNT_Pos 20
206 #define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos)
207 #define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))
208 /* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
209 #define CKGR_MOR_MOSCXTEN (0x1u << 0)
210 #define CKGR_MOR_MOSCXTBY (0x1u << 1)
211 #define CKGR_MOR_WAITMODE (0x1u << 2)
212 #define CKGR_MOR_MOSCRCEN (0x1u << 3)
213 #define CKGR_MOR_MOSCRCF_Pos 4
214 #define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos)
215 #define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos)))
216 #define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4)
217 #define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4)
218 #define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4)
219 #define CKGR_MOR_MOSCXTST_Pos 8
220 #define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos)
221 #define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
222 #define CKGR_MOR_KEY_Pos 16
223 #define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos)
224 #define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
225 #define CKGR_MOR_KEY_PASSWD (0x37u << 16)
226 #define CKGR_MOR_MOSCSEL (0x1u << 24)
227 #define CKGR_MOR_CFDEN (0x1u << 25)
228 #define CKGR_MOR_XT32KFME (0x1u << 26)
229 /* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
230 #define CKGR_MCFR_MAINF_Pos 0
231 #define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos)
232 #define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)))
233 #define CKGR_MCFR_MAINFRDY (0x1u << 16)
234 #define CKGR_MCFR_RCMEAS (0x1u << 20)
235 #define CKGR_MCFR_CCSS (0x1u << 24)
236 /* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
237 #define CKGR_PLLAR_DIVA_Pos 0
238 #define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos)
239 #define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
240 #define CKGR_PLLAR_DIVA_0 (0x0u << 0)
241 #define CKGR_PLLAR_DIVA_BYPASS (0x1u << 0)
242 #define CKGR_PLLAR_PLLACOUNT_Pos 8
243 #define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos)
244 #define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
245 #define CKGR_PLLAR_MULA_Pos 16
246 #define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos)
247 #define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
248 #define CKGR_PLLAR_ONE (0x1u << 29)
249 /* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
250 #define PMC_MCKR_CSS_Pos 0
251 #define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos)
252 #define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos)))
253 #define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0)
254 #define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0)
255 #define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0)
256 #define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0)
257 #define PMC_MCKR_PRES_Pos 4
258 #define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos)
259 #define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos)))
260 #define PMC_MCKR_PRES_CLK_1 (0x0u << 4)
261 #define PMC_MCKR_PRES_CLK_2 (0x1u << 4)
262 #define PMC_MCKR_PRES_CLK_4 (0x2u << 4)
263 #define PMC_MCKR_PRES_CLK_8 (0x3u << 4)
264 #define PMC_MCKR_PRES_CLK_16 (0x4u << 4)
265 #define PMC_MCKR_PRES_CLK_32 (0x5u << 4)
266 #define PMC_MCKR_PRES_CLK_64 (0x6u << 4)
267 #define PMC_MCKR_PRES_CLK_3 (0x7u << 4)
268 #define PMC_MCKR_MDIV_Pos 8
269 #define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos)
270 #define PMC_MCKR_MDIV(value) ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos)))
271 #define PMC_MCKR_MDIV_EQ_PCK (0x0u << 8)
272 #define PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8)
273 #define PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8)
274 #define PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8)
275 #define PMC_MCKR_UPLLDIV2 (0x1u << 13)
276 /* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
277 #define PMC_USB_USBS (0x1u << 0)
278 #define PMC_USB_USBDIV_Pos 8
279 #define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos)
280 #define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
281 /* -------- PMC_PCK[8] : (PMC Offset: 0x40) Programmable Clock Register (chid = 0) -------- */
282 #define PMC_PCK_CSS_Pos 0
283 #define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos)
284 #define PMC_PCK_CSS(value) ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos)))
285 #define PMC_PCK_CSS_SLOW_CLK (0x0u << 0)
286 #define PMC_PCK_CSS_MAIN_CLK (0x1u << 0)
287 #define PMC_PCK_CSS_PLLA_CLK (0x2u << 0)
288 #define PMC_PCK_CSS_UPLL_CLK (0x3u << 0)
289 #define PMC_PCK_CSS_MCK (0x4u << 0)
290 #define PMC_PCK_PRES_Pos 4
291 #define PMC_PCK_PRES_Msk (0xffu << PMC_PCK_PRES_Pos)
292 #define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)))
293 /* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
294 #define PMC_IER_MOSCXTS (0x1u << 0)
295 #define PMC_IER_LOCKA (0x1u << 1)
296 #define PMC_IER_MCKRDY (0x1u << 3)
297 #define PMC_IER_LOCKU (0x1u << 6)
298 #define PMC_IER_PCKRDY0 (0x1u << 8)
299 #define PMC_IER_PCKRDY1 (0x1u << 9)
300 #define PMC_IER_PCKRDY2 (0x1u << 10)
301 #define PMC_IER_PCKRDY3 (0x1u << 11)
302 #define PMC_IER_PCKRDY4 (0x1u << 12)
303 #define PMC_IER_PCKRDY5 (0x1u << 13)
304 #define PMC_IER_PCKRDY6 (0x1u << 14)
305 #define PMC_IER_MOSCSELS (0x1u << 16)
306 #define PMC_IER_MOSCRCS (0x1u << 17)
307 #define PMC_IER_CFDEV (0x1u << 18)
308 #define PMC_IER_XT32KERR (0x1u << 21)
309 /* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
310 #define PMC_IDR_MOSCXTS (0x1u << 0)
311 #define PMC_IDR_LOCKA (0x1u << 1)
312 #define PMC_IDR_MCKRDY (0x1u << 3)
313 #define PMC_IDR_LOCKU (0x1u << 6)
314 #define PMC_IDR_PCKRDY0 (0x1u << 8)
315 #define PMC_IDR_PCKRDY1 (0x1u << 9)
316 #define PMC_IDR_PCKRDY2 (0x1u << 10)
317 #define PMC_IDR_PCKRDY3 (0x1u << 11)
318 #define PMC_IDR_PCKRDY4 (0x1u << 12)
319 #define PMC_IDR_PCKRDY5 (0x1u << 13)
320 #define PMC_IDR_PCKRDY6 (0x1u << 14)
321 #define PMC_IDR_MOSCSELS (0x1u << 16)
322 #define PMC_IDR_MOSCRCS (0x1u << 17)
323 #define PMC_IDR_CFDEV (0x1u << 18)
324 #define PMC_IDR_XT32KERR (0x1u << 21)
325 /* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
326 #define PMC_SR_MOSCXTS (0x1u << 0)
327 #define PMC_SR_LOCKA (0x1u << 1)
328 #define PMC_SR_MCKRDY (0x1u << 3)
329 #define PMC_SR_LOCKU (0x1u << 6)
330 #define PMC_SR_OSCSELS (0x1u << 7)
331 #define PMC_SR_PCKRDY0 (0x1u << 8)
332 #define PMC_SR_PCKRDY1 (0x1u << 9)
333 #define PMC_SR_PCKRDY2 (0x1u << 10)
334 #define PMC_SR_PCKRDY3 (0x1u << 11)
335 #define PMC_SR_PCKRDY4 (0x1u << 12)
336 #define PMC_SR_PCKRDY5 (0x1u << 13)
337 #define PMC_SR_PCKRDY6 (0x1u << 14)
338 #define PMC_SR_MOSCSELS (0x1u << 16)
339 #define PMC_SR_MOSCRCS (0x1u << 17)
340 #define PMC_SR_CFDEV (0x1u << 18)
341 #define PMC_SR_CFDS (0x1u << 19)
342 #define PMC_SR_FOS (0x1u << 20)
343 #define PMC_SR_XT32KERR (0x1u << 21)
344 /* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
345 #define PMC_IMR_MOSCXTS (0x1u << 0)
346 #define PMC_IMR_LOCKA (0x1u << 1)
347 #define PMC_IMR_MCKRDY (0x1u << 3)
348 #define PMC_IMR_LOCKU (0x1u << 6)
349 #define PMC_IMR_PCKRDY0 (0x1u << 8)
350 #define PMC_IMR_PCKRDY1 (0x1u << 9)
351 #define PMC_IMR_PCKRDY2 (0x1u << 10)
352 #define PMC_IMR_PCKRDY3 (0x1u << 11)
353 #define PMC_IMR_PCKRDY4 (0x1u << 12)
354 #define PMC_IMR_PCKRDY5 (0x1u << 13)
355 #define PMC_IMR_PCKRDY6 (0x1u << 14)
356 #define PMC_IMR_MOSCSELS (0x1u << 16)
357 #define PMC_IMR_MOSCRCS (0x1u << 17)
358 #define PMC_IMR_CFDEV (0x1u << 18)
359 #define PMC_IMR_XT32KERR (0x1u << 21)
360 /* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
361 #define PMC_FSMR_FSTT0 (0x1u << 0)
362 #define PMC_FSMR_FSTT1 (0x1u << 1)
363 #define PMC_FSMR_FSTT2 (0x1u << 2)
364 #define PMC_FSMR_FSTT3 (0x1u << 3)
365 #define PMC_FSMR_FSTT4 (0x1u << 4)
366 #define PMC_FSMR_FSTT5 (0x1u << 5)
367 #define PMC_FSMR_FSTT6 (0x1u << 6)
368 #define PMC_FSMR_FSTT7 (0x1u << 7)
369 #define PMC_FSMR_FSTT8 (0x1u << 8)
370 #define PMC_FSMR_FSTT9 (0x1u << 9)
371 #define PMC_FSMR_FSTT10 (0x1u << 10)
372 #define PMC_FSMR_FSTT11 (0x1u << 11)
373 #define PMC_FSMR_FSTT12 (0x1u << 12)
374 #define PMC_FSMR_FSTT13 (0x1u << 13)
375 #define PMC_FSMR_FSTT14 (0x1u << 14)
376 #define PMC_FSMR_FSTT15 (0x1u << 15)
377 #define PMC_FSMR_RTTAL (0x1u << 16)
378 #define PMC_FSMR_RTCAL (0x1u << 17)
379 #define PMC_FSMR_USBAL (0x1u << 18)
380 #define PMC_FSMR_LPM (0x1u << 20)
381 #define PMC_FSMR_FLPM_Pos 21
382 #define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos)
383 #define PMC_FSMR_FLPM(value) ((PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos)))
384 #define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21)
385 #define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21)
386 #define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21)
387 #define PMC_FSMR_FFLPM (0x1u << 23)
388 /* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
389 #define PMC_FSPR_FSTP0 (0x1u << 0)
390 #define PMC_FSPR_FSTP1 (0x1u << 1)
391 #define PMC_FSPR_FSTP2 (0x1u << 2)
392 #define PMC_FSPR_FSTP3 (0x1u << 3)
393 #define PMC_FSPR_FSTP4 (0x1u << 4)
394 #define PMC_FSPR_FSTP5 (0x1u << 5)
395 #define PMC_FSPR_FSTP6 (0x1u << 6)
396 #define PMC_FSPR_FSTP7 (0x1u << 7)
397 #define PMC_FSPR_FSTP8 (0x1u << 8)
398 #define PMC_FSPR_FSTP9 (0x1u << 9)
399 #define PMC_FSPR_FSTP10 (0x1u << 10)
400 #define PMC_FSPR_FSTP11 (0x1u << 11)
401 #define PMC_FSPR_FSTP12 (0x1u << 12)
402 #define PMC_FSPR_FSTP13 (0x1u << 13)
403 #define PMC_FSPR_FSTP14 (0x1u << 14)
404 #define PMC_FSPR_FSTP15 (0x1u << 15)
405 /* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
406 #define PMC_FOCR_FOCLR (0x1u << 0)
407 /* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */
408 #define PMC_WPMR_WPEN (0x1u << 0)
409 #define PMC_WPMR_WPKEY_Pos 8
410 #define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos)
411 #define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
412 #define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8)
413 /* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */
414 #define PMC_WPSR_WPVS (0x1u << 0)
415 #define PMC_WPSR_WPVSRC_Pos 8
416 #define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos)
417 /* -------- PMC_VERSION : (PMC Offset: 0x00FC) Version Register -------- */
418 #define PMC_VERSION_VERSION_Pos 0
419 #define PMC_VERSION_VERSION_Msk (0xfffu << PMC_VERSION_VERSION_Pos)
420 #define PMC_VERSION_MFN_Pos 16
421 #define PMC_VERSION_MFN_Msk (0x7u << PMC_VERSION_MFN_Pos)
422 /* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
423 #define PMC_PCER1_PID32 (0x1u << 0)
424 #define PMC_PCER1_PID33 (0x1u << 1)
425 #define PMC_PCER1_PID34 (0x1u << 2)
426 #define PMC_PCER1_PID35 (0x1u << 3)
427 #define PMC_PCER1_PID37 (0x1u << 5)
428 #define PMC_PCER1_PID39 (0x1u << 7)
429 #define PMC_PCER1_PID40 (0x1u << 8)
430 #define PMC_PCER1_PID41 (0x1u << 9)
431 #define PMC_PCER1_PID42 (0x1u << 10)
432 #define PMC_PCER1_PID43 (0x1u << 11)
433 #define PMC_PCER1_PID44 (0x1u << 12)
434 #define PMC_PCER1_PID45 (0x1u << 13)
435 #define PMC_PCER1_PID46 (0x1u << 14)
436 #define PMC_PCER1_PID47 (0x1u << 15)
437 #define PMC_PCER1_PID48 (0x1u << 16)
438 #define PMC_PCER1_PID49 (0x1u << 17)
439 #define PMC_PCER1_PID50 (0x1u << 18)
440 #define PMC_PCER1_PID51 (0x1u << 19)
441 #define PMC_PCER1_PID52 (0x1u << 20)
442 #define PMC_PCER1_PID53 (0x1u << 21)
443 #define PMC_PCER1_PID56 (0x1u << 24)
444 #define PMC_PCER1_PID57 (0x1u << 25)
445 #define PMC_PCER1_PID58 (0x1u << 26)
446 #define PMC_PCER1_PID59 (0x1u << 27)
447 #define PMC_PCER1_PID60 (0x1u << 28)
448 /* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
449 #define PMC_PCDR1_PID32 (0x1u << 0)
450 #define PMC_PCDR1_PID33 (0x1u << 1)
451 #define PMC_PCDR1_PID34 (0x1u << 2)
452 #define PMC_PCDR1_PID35 (0x1u << 3)
453 #define PMC_PCDR1_PID37 (0x1u << 5)
454 #define PMC_PCDR1_PID39 (0x1u << 7)
455 #define PMC_PCDR1_PID40 (0x1u << 8)
456 #define PMC_PCDR1_PID41 (0x1u << 9)
457 #define PMC_PCDR1_PID42 (0x1u << 10)
458 #define PMC_PCDR1_PID43 (0x1u << 11)
459 #define PMC_PCDR1_PID44 (0x1u << 12)
460 #define PMC_PCDR1_PID45 (0x1u << 13)
461 #define PMC_PCDR1_PID46 (0x1u << 14)
462 #define PMC_PCDR1_PID47 (0x1u << 15)
463 #define PMC_PCDR1_PID48 (0x1u << 16)
464 #define PMC_PCDR1_PID49 (0x1u << 17)
465 #define PMC_PCDR1_PID50 (0x1u << 18)
466 #define PMC_PCDR1_PID51 (0x1u << 19)
467 #define PMC_PCDR1_PID52 (0x1u << 20)
468 #define PMC_PCDR1_PID53 (0x1u << 21)
469 #define PMC_PCDR1_PID56 (0x1u << 24)
470 #define PMC_PCDR1_PID57 (0x1u << 25)
471 #define PMC_PCDR1_PID58 (0x1u << 26)
472 #define PMC_PCDR1_PID59 (0x1u << 27)
473 #define PMC_PCDR1_PID60 (0x1u << 28)
474 /* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
475 #define PMC_PCSR1_PID32 (0x1u << 0)
476 #define PMC_PCSR1_PID33 (0x1u << 1)
477 #define PMC_PCSR1_PID34 (0x1u << 2)
478 #define PMC_PCSR1_PID35 (0x1u << 3)
479 #define PMC_PCSR1_PID37 (0x1u << 5)
480 #define PMC_PCSR1_PID39 (0x1u << 7)
481 #define PMC_PCSR1_PID40 (0x1u << 8)
482 #define PMC_PCSR1_PID41 (0x1u << 9)
483 #define PMC_PCSR1_PID42 (0x1u << 10)
484 #define PMC_PCSR1_PID43 (0x1u << 11)
485 #define PMC_PCSR1_PID44 (0x1u << 12)
486 #define PMC_PCSR1_PID45 (0x1u << 13)
487 #define PMC_PCSR1_PID46 (0x1u << 14)
488 #define PMC_PCSR1_PID47 (0x1u << 15)
489 #define PMC_PCSR1_PID48 (0x1u << 16)
490 #define PMC_PCSR1_PID49 (0x1u << 17)
491 #define PMC_PCSR1_PID50 (0x1u << 18)
492 #define PMC_PCSR1_PID51 (0x1u << 19)
493 #define PMC_PCSR1_PID52 (0x1u << 20)
494 #define PMC_PCSR1_PID53 (0x1u << 21)
495 #define PMC_PCSR1_PID56 (0x1u << 24)
496 #define PMC_PCSR1_PID57 (0x1u << 25)
497 #define PMC_PCSR1_PID58 (0x1u << 26)
498 #define PMC_PCSR1_PID59 (0x1u << 27)
499 #define PMC_PCSR1_PID60 (0x1u << 28)
500 /* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */
501 #define PMC_PCR_PID_Pos 0
502 #define PMC_PCR_PID_Msk (0x7fu << PMC_PCR_PID_Pos)
503 #define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)))
504 #define PMC_PCR_GCLKCSS_Pos 8
505 #define PMC_PCR_GCLKCSS_Msk (0x7u << PMC_PCR_GCLKCSS_Pos)
506 #define PMC_PCR_GCLKCSS(value) ((PMC_PCR_GCLKCSS_Msk & ((value) << PMC_PCR_GCLKCSS_Pos)))
507 #define PMC_PCR_GCLKCSS_SLOW_CLK (0x0u << 8)
508 #define PMC_PCR_GCLKCSS_MAIN_CLK (0x1u << 8)
509 #define PMC_PCR_GCLKCSS_PLLA_CLK (0x2u << 8)
510 #define PMC_PCR_GCLKCSS_UPLL_CLK (0x3u << 8)
511 #define PMC_PCR_GCLKCSS_MCK_CLK (0x4u << 8)
512 #define PMC_PCR_CMD (0x1u << 12)
513 #define PMC_PCR_DIV_Pos 16
514 #define PMC_PCR_DIV_Msk (0x3u << PMC_PCR_DIV_Pos)
515 #define PMC_PCR_DIV(value) ((PMC_PCR_DIV_Msk & ((value) << PMC_PCR_DIV_Pos)))
516 #define PMC_PCR_DIV_PERIPH_DIV_MCK (0x0u << 16)
517 #define PMC_PCR_DIV_PERIPH_DIV2_MCK (0x1u << 16)
518 #define PMC_PCR_DIV_PERIPH_DIV4_MCK (0x2u << 16)
519 #define PMC_PCR_DIV_PERIPH_DIV8_MCK (0x3u << 16)
520 #define PMC_PCR_GCLKDIV_Pos 20
521 #define PMC_PCR_GCLKDIV_Msk (0xffu << PMC_PCR_GCLKDIV_Pos)
522 #define PMC_PCR_GCLKDIV(value) ((PMC_PCR_GCLKDIV_Msk & ((value) << PMC_PCR_GCLKDIV_Pos)))
523 #define PMC_PCR_EN (0x1u << 28)
524 #define PMC_PCR_GCLKEN (0x1u << 29)
525 /* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */
526 #define PMC_OCR_CAL4_Pos 0
527 #define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos)
528 #define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))
529 #define PMC_OCR_SEL4 (0x1u << 7)
530 #define PMC_OCR_CAL8_Pos 8
531 #define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos)
532 #define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))
533 #define PMC_OCR_SEL8 (0x1u << 15)
534 #define PMC_OCR_CAL12_Pos 16
535 #define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos)
536 #define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))
537 #define PMC_OCR_SEL12 (0x1u << 23)
538 /* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x0114) SleepWalking Enable Register 0 -------- */
539 #define PMC_SLPWK_ER0_PID7 (0x1u << 7)
540 #define PMC_SLPWK_ER0_PID8 (0x1u << 8)
541 #define PMC_SLPWK_ER0_PID9 (0x1u << 9)
542 #define PMC_SLPWK_ER0_PID10 (0x1u << 10)
543 #define PMC_SLPWK_ER0_PID11 (0x1u << 11)
544 #define PMC_SLPWK_ER0_PID12 (0x1u << 12)
545 #define PMC_SLPWK_ER0_PID13 (0x1u << 13)
546 #define PMC_SLPWK_ER0_PID14 (0x1u << 14)
547 #define PMC_SLPWK_ER0_PID15 (0x1u << 15)
548 #define PMC_SLPWK_ER0_PID16 (0x1u << 16)
549 #define PMC_SLPWK_ER0_PID17 (0x1u << 17)
550 #define PMC_SLPWK_ER0_PID18 (0x1u << 18)
551 #define PMC_SLPWK_ER0_PID19 (0x1u << 19)
552 #define PMC_SLPWK_ER0_PID20 (0x1u << 20)
553 #define PMC_SLPWK_ER0_PID21 (0x1u << 21)
554 #define PMC_SLPWK_ER0_PID22 (0x1u << 22)
555 #define PMC_SLPWK_ER0_PID23 (0x1u << 23)
556 #define PMC_SLPWK_ER0_PID24 (0x1u << 24)
557 #define PMC_SLPWK_ER0_PID25 (0x1u << 25)
558 #define PMC_SLPWK_ER0_PID26 (0x1u << 26)
559 #define PMC_SLPWK_ER0_PID27 (0x1u << 27)
560 #define PMC_SLPWK_ER0_PID28 (0x1u << 28)
561 #define PMC_SLPWK_ER0_PID29 (0x1u << 29)
562 #define PMC_SLPWK_ER0_PID30 (0x1u << 30)
563 #define PMC_SLPWK_ER0_PID31 (0x1u << 31)
564 /* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x0118) SleepWalking Disable Register 0 -------- */
565 #define PMC_SLPWK_DR0_PID7 (0x1u << 7)
566 #define PMC_SLPWK_DR0_PID8 (0x1u << 8)
567 #define PMC_SLPWK_DR0_PID9 (0x1u << 9)
568 #define PMC_SLPWK_DR0_PID10 (0x1u << 10)
569 #define PMC_SLPWK_DR0_PID11 (0x1u << 11)
570 #define PMC_SLPWK_DR0_PID12 (0x1u << 12)
571 #define PMC_SLPWK_DR0_PID13 (0x1u << 13)
572 #define PMC_SLPWK_DR0_PID14 (0x1u << 14)
573 #define PMC_SLPWK_DR0_PID15 (0x1u << 15)
574 #define PMC_SLPWK_DR0_PID16 (0x1u << 16)
575 #define PMC_SLPWK_DR0_PID17 (0x1u << 17)
576 #define PMC_SLPWK_DR0_PID18 (0x1u << 18)
577 #define PMC_SLPWK_DR0_PID19 (0x1u << 19)
578 #define PMC_SLPWK_DR0_PID20 (0x1u << 20)
579 #define PMC_SLPWK_DR0_PID21 (0x1u << 21)
580 #define PMC_SLPWK_DR0_PID22 (0x1u << 22)
581 #define PMC_SLPWK_DR0_PID23 (0x1u << 23)
582 #define PMC_SLPWK_DR0_PID24 (0x1u << 24)
583 #define PMC_SLPWK_DR0_PID25 (0x1u << 25)
584 #define PMC_SLPWK_DR0_PID26 (0x1u << 26)
585 #define PMC_SLPWK_DR0_PID27 (0x1u << 27)
586 #define PMC_SLPWK_DR0_PID28 (0x1u << 28)
587 #define PMC_SLPWK_DR0_PID29 (0x1u << 29)
588 #define PMC_SLPWK_DR0_PID30 (0x1u << 30)
589 #define PMC_SLPWK_DR0_PID31 (0x1u << 31)
590 /* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x011C) SleepWalking Status Register 0 -------- */
591 #define PMC_SLPWK_SR0_PID7 (0x1u << 7)
592 #define PMC_SLPWK_SR0_PID8 (0x1u << 8)
593 #define PMC_SLPWK_SR0_PID9 (0x1u << 9)
594 #define PMC_SLPWK_SR0_PID10 (0x1u << 10)
595 #define PMC_SLPWK_SR0_PID11 (0x1u << 11)
596 #define PMC_SLPWK_SR0_PID12 (0x1u << 12)
597 #define PMC_SLPWK_SR0_PID13 (0x1u << 13)
598 #define PMC_SLPWK_SR0_PID14 (0x1u << 14)
599 #define PMC_SLPWK_SR0_PID15 (0x1u << 15)
600 #define PMC_SLPWK_SR0_PID16 (0x1u << 16)
601 #define PMC_SLPWK_SR0_PID17 (0x1u << 17)
602 #define PMC_SLPWK_SR0_PID18 (0x1u << 18)
603 #define PMC_SLPWK_SR0_PID19 (0x1u << 19)
604 #define PMC_SLPWK_SR0_PID20 (0x1u << 20)
605 #define PMC_SLPWK_SR0_PID21 (0x1u << 21)
606 #define PMC_SLPWK_SR0_PID22 (0x1u << 22)
607 #define PMC_SLPWK_SR0_PID23 (0x1u << 23)
608 #define PMC_SLPWK_SR0_PID24 (0x1u << 24)
609 #define PMC_SLPWK_SR0_PID25 (0x1u << 25)
610 #define PMC_SLPWK_SR0_PID26 (0x1u << 26)
611 #define PMC_SLPWK_SR0_PID27 (0x1u << 27)
612 #define PMC_SLPWK_SR0_PID28 (0x1u << 28)
613 #define PMC_SLPWK_SR0_PID29 (0x1u << 29)
614 #define PMC_SLPWK_SR0_PID30 (0x1u << 30)
615 #define PMC_SLPWK_SR0_PID31 (0x1u << 31)
616 /* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x0120) SleepWalking Activity Status Register 0 -------- */
617 #define PMC_SLPWK_ASR0_PID7 (0x1u << 7)
618 #define PMC_SLPWK_ASR0_PID8 (0x1u << 8)
619 #define PMC_SLPWK_ASR0_PID9 (0x1u << 9)
620 #define PMC_SLPWK_ASR0_PID10 (0x1u << 10)
621 #define PMC_SLPWK_ASR0_PID11 (0x1u << 11)
622 #define PMC_SLPWK_ASR0_PID12 (0x1u << 12)
623 #define PMC_SLPWK_ASR0_PID13 (0x1u << 13)
624 #define PMC_SLPWK_ASR0_PID14 (0x1u << 14)
625 #define PMC_SLPWK_ASR0_PID15 (0x1u << 15)
626 #define PMC_SLPWK_ASR0_PID16 (0x1u << 16)
627 #define PMC_SLPWK_ASR0_PID17 (0x1u << 17)
628 #define PMC_SLPWK_ASR0_PID18 (0x1u << 18)
629 #define PMC_SLPWK_ASR0_PID19 (0x1u << 19)
630 #define PMC_SLPWK_ASR0_PID20 (0x1u << 20)
631 #define PMC_SLPWK_ASR0_PID21 (0x1u << 21)
632 #define PMC_SLPWK_ASR0_PID22 (0x1u << 22)
633 #define PMC_SLPWK_ASR0_PID23 (0x1u << 23)
634 #define PMC_SLPWK_ASR0_PID24 (0x1u << 24)
635 #define PMC_SLPWK_ASR0_PID25 (0x1u << 25)
636 #define PMC_SLPWK_ASR0_PID26 (0x1u << 26)
637 #define PMC_SLPWK_ASR0_PID27 (0x1u << 27)
638 #define PMC_SLPWK_ASR0_PID28 (0x1u << 28)
639 #define PMC_SLPWK_ASR0_PID29 (0x1u << 29)
640 #define PMC_SLPWK_ASR0_PID30 (0x1u << 30)
641 #define PMC_SLPWK_ASR0_PID31 (0x1u << 31)
642 /* -------- PMC_PMMR : (PMC Offset: 0x0130) PLL Maximum Multiplier Value Register -------- */
643 #define PMC_PMMR_PLLA_MMAX_Pos 0
644 #define PMC_PMMR_PLLA_MMAX_Msk (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos)
645 #define PMC_PMMR_PLLA_MMAX(value) ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos)))
646 /* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x0134) SleepWalking Enable Register 1 -------- */
647 #define PMC_SLPWK_ER1_PID32 (0x1u << 0)
648 #define PMC_SLPWK_ER1_PID33 (0x1u << 1)
649 #define PMC_SLPWK_ER1_PID34 (0x1u << 2)
650 #define PMC_SLPWK_ER1_PID35 (0x1u << 3)
651 #define PMC_SLPWK_ER1_PID37 (0x1u << 5)
652 #define PMC_SLPWK_ER1_PID39 (0x1u << 7)
653 #define PMC_SLPWK_ER1_PID40 (0x1u << 8)
654 #define PMC_SLPWK_ER1_PID41 (0x1u << 9)
655 #define PMC_SLPWK_ER1_PID42 (0x1u << 10)
656 #define PMC_SLPWK_ER1_PID43 (0x1u << 11)
657 #define PMC_SLPWK_ER1_PID44 (0x1u << 12)
658 #define PMC_SLPWK_ER1_PID45 (0x1u << 13)
659 #define PMC_SLPWK_ER1_PID46 (0x1u << 14)
660 #define PMC_SLPWK_ER1_PID47 (0x1u << 15)
661 #define PMC_SLPWK_ER1_PID48 (0x1u << 16)
662 #define PMC_SLPWK_ER1_PID49 (0x1u << 17)
663 #define PMC_SLPWK_ER1_PID50 (0x1u << 18)
664 #define PMC_SLPWK_ER1_PID51 (0x1u << 19)
665 #define PMC_SLPWK_ER1_PID52 (0x1u << 20)
666 #define PMC_SLPWK_ER1_PID53 (0x1u << 21)
667 #define PMC_SLPWK_ER1_PID56 (0x1u << 24)
668 #define PMC_SLPWK_ER1_PID57 (0x1u << 25)
669 #define PMC_SLPWK_ER1_PID58 (0x1u << 26)
670 #define PMC_SLPWK_ER1_PID59 (0x1u << 27)
671 #define PMC_SLPWK_ER1_PID60 (0x1u << 28)
672 /* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x0138) SleepWalking Disable Register 1 -------- */
673 #define PMC_SLPWK_DR1_PID32 (0x1u << 0)
674 #define PMC_SLPWK_DR1_PID33 (0x1u << 1)
675 #define PMC_SLPWK_DR1_PID34 (0x1u << 2)
676 #define PMC_SLPWK_DR1_PID35 (0x1u << 3)
677 #define PMC_SLPWK_DR1_PID37 (0x1u << 5)
678 #define PMC_SLPWK_DR1_PID39 (0x1u << 7)
679 #define PMC_SLPWK_DR1_PID40 (0x1u << 8)
680 #define PMC_SLPWK_DR1_PID41 (0x1u << 9)
681 #define PMC_SLPWK_DR1_PID42 (0x1u << 10)
682 #define PMC_SLPWK_DR1_PID43 (0x1u << 11)
683 #define PMC_SLPWK_DR1_PID44 (0x1u << 12)
684 #define PMC_SLPWK_DR1_PID45 (0x1u << 13)
685 #define PMC_SLPWK_DR1_PID46 (0x1u << 14)
686 #define PMC_SLPWK_DR1_PID47 (0x1u << 15)
687 #define PMC_SLPWK_DR1_PID48 (0x1u << 16)
688 #define PMC_SLPWK_DR1_PID49 (0x1u << 17)
689 #define PMC_SLPWK_DR1_PID50 (0x1u << 18)
690 #define PMC_SLPWK_DR1_PID51 (0x1u << 19)
691 #define PMC_SLPWK_DR1_PID52 (0x1u << 20)
692 #define PMC_SLPWK_DR1_PID53 (0x1u << 21)
693 #define PMC_SLPWK_DR1_PID56 (0x1u << 24)
694 #define PMC_SLPWK_DR1_PID57 (0x1u << 25)
695 #define PMC_SLPWK_DR1_PID58 (0x1u << 26)
696 #define PMC_SLPWK_DR1_PID59 (0x1u << 27)
697 #define PMC_SLPWK_DR1_PID60 (0x1u << 28)
698 /* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x013C) SleepWalking Status Register 1 -------- */
699 #define PMC_SLPWK_SR1_PID32 (0x1u << 0)
700 #define PMC_SLPWK_SR1_PID33 (0x1u << 1)
701 #define PMC_SLPWK_SR1_PID34 (0x1u << 2)
702 #define PMC_SLPWK_SR1_PID35 (0x1u << 3)
703 #define PMC_SLPWK_SR1_PID37 (0x1u << 5)
704 #define PMC_SLPWK_SR1_PID39 (0x1u << 7)
705 #define PMC_SLPWK_SR1_PID40 (0x1u << 8)
706 #define PMC_SLPWK_SR1_PID41 (0x1u << 9)
707 #define PMC_SLPWK_SR1_PID42 (0x1u << 10)
708 #define PMC_SLPWK_SR1_PID43 (0x1u << 11)
709 #define PMC_SLPWK_SR1_PID44 (0x1u << 12)
710 #define PMC_SLPWK_SR1_PID45 (0x1u << 13)
711 #define PMC_SLPWK_SR1_PID46 (0x1u << 14)
712 #define PMC_SLPWK_SR1_PID47 (0x1u << 15)
713 #define PMC_SLPWK_SR1_PID48 (0x1u << 16)
714 #define PMC_SLPWK_SR1_PID49 (0x1u << 17)
715 #define PMC_SLPWK_SR1_PID50 (0x1u << 18)
716 #define PMC_SLPWK_SR1_PID51 (0x1u << 19)
717 #define PMC_SLPWK_SR1_PID52 (0x1u << 20)
718 #define PMC_SLPWK_SR1_PID53 (0x1u << 21)
719 #define PMC_SLPWK_SR1_PID56 (0x1u << 24)
720 #define PMC_SLPWK_SR1_PID57 (0x1u << 25)
721 #define PMC_SLPWK_SR1_PID58 (0x1u << 26)
722 #define PMC_SLPWK_SR1_PID59 (0x1u << 27)
723 #define PMC_SLPWK_SR1_PID60 (0x1u << 28)
724 /* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x0140) SleepWalking Activity Status Register 1 -------- */
725 #define PMC_SLPWK_ASR1_PID32 (0x1u << 0)
726 #define PMC_SLPWK_ASR1_PID33 (0x1u << 1)
727 #define PMC_SLPWK_ASR1_PID34 (0x1u << 2)
728 #define PMC_SLPWK_ASR1_PID35 (0x1u << 3)
729 #define PMC_SLPWK_ASR1_PID37 (0x1u << 5)
730 #define PMC_SLPWK_ASR1_PID39 (0x1u << 7)
731 #define PMC_SLPWK_ASR1_PID40 (0x1u << 8)
732 #define PMC_SLPWK_ASR1_PID41 (0x1u << 9)
733 #define PMC_SLPWK_ASR1_PID42 (0x1u << 10)
734 #define PMC_SLPWK_ASR1_PID43 (0x1u << 11)
735 #define PMC_SLPWK_ASR1_PID44 (0x1u << 12)
736 #define PMC_SLPWK_ASR1_PID45 (0x1u << 13)
737 #define PMC_SLPWK_ASR1_PID46 (0x1u << 14)
738 #define PMC_SLPWK_ASR1_PID47 (0x1u << 15)
739 #define PMC_SLPWK_ASR1_PID48 (0x1u << 16)
740 #define PMC_SLPWK_ASR1_PID49 (0x1u << 17)
741 #define PMC_SLPWK_ASR1_PID50 (0x1u << 18)
742 #define PMC_SLPWK_ASR1_PID51 (0x1u << 19)
743 #define PMC_SLPWK_ASR1_PID52 (0x1u << 20)
744 #define PMC_SLPWK_ASR1_PID53 (0x1u << 21)
745 #define PMC_SLPWK_ASR1_PID56 (0x1u << 24)
746 #define PMC_SLPWK_ASR1_PID57 (0x1u << 25)
747 #define PMC_SLPWK_ASR1_PID58 (0x1u << 26)
748 #define PMC_SLPWK_ASR1_PID59 (0x1u << 27)
749 #define PMC_SLPWK_ASR1_PID60 (0x1u << 28)
750 /* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x0144) SleepWalking Activity In Progress Register -------- */
751 #define PMC_SLPWK_AIPR_AIP (0x1u << 0)
752 /* -------- PMC_APLLACR : (PMC Offset: 0x0158) Audio PLL Analog Configuration Register -------- */
753 #define PMC_APLLACR_DCOFLTSEL_Pos 0
754 #define PMC_APLLACR_DCOFLTSEL_Msk (0xfu << PMC_APLLACR_DCOFLTSEL_Pos)
755 #define PMC_APLLACR_DCOFLTSEL(value) ((PMC_APLLACR_DCOFLTSEL_Msk & ((value) << PMC_APLLACR_DCOFLTSEL_Pos)))
756 #define PMC_APLLACR_FLTSEL_Pos 4
757 #define PMC_APLLACR_FLTSEL_Msk (0xfu << PMC_APLLACR_FLTSEL_Pos)
758 #define PMC_APLLACR_FLTSEL(value) ((PMC_APLLACR_FLTSEL_Msk & ((value) << PMC_APLLACR_FLTSEL_Pos)))
759 #define PMC_APLLACR_BIAS_Pos 8
760 #define PMC_APLLACR_BIAS_Msk (0x3u << PMC_APLLACR_BIAS_Pos)
761 #define PMC_APLLACR_BIAS(value) ((PMC_APLLACR_BIAS_Msk & ((value) << PMC_APLLACR_BIAS_Pos)))
762 /* -------- PMC_WMST : (PMC Offset: 0x015C) Wait Mode Startup Time Register -------- */
763 #define PMC_WMST_WMST_Pos 0
764 #define PMC_WMST_WMST_Msk (0xffu << PMC_WMST_WMST_Pos)
765 #define PMC_WMST_WMST(value) ((PMC_WMST_WMST_Msk & ((value) << PMC_WMST_WMST_Pos)))
766 #define PMC_WMST_KEY_Pos 24
767 #define PMC_WMST_KEY_Msk (0xffu << PMC_WMST_KEY_Pos)
768 #define PMC_WMST_KEY(value) ((PMC_WMST_KEY_Msk & ((value) << PMC_WMST_KEY_Pos)))
769 #define PMC_WMST_KEY_PASSWD (0x5Au << 24)
772 
773 
774 #endif /* _SAME70_PMC_COMPONENT_ */
__IO uint32_t PMC_APLLACR
(Pmc Offset: 0x0158) Audio PLL Analog Configuration Register
__IO uint32_t CKGR_PLLAR
(Pmc Offset: 0x0028) PLLA Register
__I uint32_t PMC_SCSR
(Pmc Offset: 0x0008) System Clock Status Register
__IO uint32_t PMC_PMMR
(Pmc Offset: 0x0130) PLL Maximum Multiplier Value Register
__I uint32_t PMC_WPSR
(Pmc Offset: 0x00E8) Write Protection Status Register
#define __IO
Definition: core_cm7.h:266
__IO uint32_t PMC_USB
(Pmc Offset: 0x0038) USB Clock Register
__O uint32_t PMC_SLPWK_DR0
(Pmc Offset: 0x0118) SleepWalking Disable Register 0
#define __O
Definition: core_cm7.h:265
__O uint32_t PMC_FOCR
(Pmc Offset: 0x0078) Fault Output Clear Register
__I uint32_t PMC_PCSR1
(Pmc Offset: 0x0108) Peripheral Clock Status Register 1
__O uint32_t PMC_SLPWK_ER0
(Pmc Offset: 0x0114) SleepWalking Enable Register 0
__I uint32_t PMC_SLPWK_ASR1
(Pmc Offset: 0x0140) SleepWalking Activity Status Register 1
__O uint32_t PMC_PCDR1
(Pmc Offset: 0x0104) Peripheral Clock Disable Register 1
__O uint32_t PMC_SCER
(Pmc Offset: 0x0000) System Clock Enable Register
__O uint32_t PMC_SLPWK_DR1
(Pmc Offset: 0x0138) SleepWalking Disable Register 1
__I uint32_t PMC_VERSION
(Pmc Offset: 0x00FC) Version Register
__I uint32_t PMC_SR
(Pmc Offset: 0x0068) Status Register
__IO uint32_t PMC_PCR
(Pmc Offset: 0x010C) Peripheral Control Register
__I uint32_t PMC_SLPWK_SR1
(Pmc Offset: 0x013C) SleepWalking Status Register 1
__I uint32_t PMC_IMR
(Pmc Offset: 0x006C) Interrupt Mask Register
__O uint32_t PMC_PCER0
(Pmc Offset: 0x0010) Peripheral Clock Enable Register 0
__O uint32_t PMC_SLPWK_ER1
(Pmc Offset: 0x0134) SleepWalking Enable Register 1
__IO uint32_t PMC_WPMR
(Pmc Offset: 0x00E4) Write Protection Mode Register
__I uint32_t PMC_SLPWK_SR0
(Pmc Offset: 0x011C) SleepWalking Status Register 0
__IO uint32_t CKGR_MOR
(Pmc Offset: 0x0020) Main Oscillator Register
__O uint32_t PMC_IDR
(Pmc Offset: 0x0064) Interrupt Disable Register
__I uint32_t PMC_PCSR0
(Pmc Offset: 0x0018) Peripheral Clock Status Register 0
__IO uint32_t PMC_FSPR
(Pmc Offset: 0x0074) Fast Startup Polarity Register
__I uint32_t PMC_SLPWK_AIPR
(Pmc Offset: 0x0144) SleepWalking Activity In Progress Register
__O uint32_t PMC_SCDR
(Pmc Offset: 0x0004) System Clock Disable Register
__IO uint32_t CKGR_UCKR
(Pmc Offset: 0x001C) UTMI Clock Register
__O uint32_t PMC_PCER1
(Pmc Offset: 0x0100) Peripheral Clock Enable Register 1
__O uint32_t PMC_PCDR0
(Pmc Offset: 0x0014) Peripheral Clock Disable Register 0
Pmc hardware registers.
__IO uint32_t CKGR_MCFR
(Pmc Offset: 0x0024) Main Clock Frequency Register
__I uint32_t PMC_SLPWK_ASR0
(Pmc Offset: 0x0120) SleepWalking Activity Status Register 0
__O uint32_t PMC_IER
(Pmc Offset: 0x0060) Interrupt Enable Register
__IO uint32_t PMC_MCKR
(Pmc Offset: 0x0030) Master Clock Register
__IO uint32_t PMC_FSMR
(Pmc Offset: 0x0070) Fast Startup Mode Register
#define __I
Definition: core_cm7.h:263
__IO uint32_t PMC_WMST
(Pmc Offset: 0x015C) Wait Mode Startup Time Register
__IO uint32_t PMC_OCR
(Pmc Offset: 0x0110) Oscillator Calibration Register


inertial_sense_ros
Author(s):
autogenerated on Sat Sep 19 2020 03:19:04