utils/cmsis/same70/include/component/efc.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_EFC_COMPONENT_
36 #define _SAME70_EFC_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __IO uint32_t EEFC_FMR;
48  __O uint32_t EEFC_FCR;
49  __I uint32_t EEFC_FSR;
50  __I uint32_t EEFC_FRR;
51  __I uint32_t Reserved1[1];
52  __I uint32_t EEFC_VERSION;
53  __I uint32_t Reserved2[51];
54  __IO uint32_t EEFC_WPMR;
55 } Efc;
56 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
57 /* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
58 #define EEFC_FMR_FRDY (0x1u << 0)
59 #define EEFC_FMR_FWS_Pos 8
60 #define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos)
61 #define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
62 #define EEFC_FMR_SCOD (0x1u << 16)
63 #define EEFC_FMR_CLOE (0x1u << 26)
64 /* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
65 #define EEFC_FCR_FCMD_Pos 0
66 #define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos)
67 #define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
68 #define EEFC_FCR_FCMD_GETD (0x0u << 0)
69 #define EEFC_FCR_FCMD_WP (0x1u << 0)
70 #define EEFC_FCR_FCMD_WPL (0x2u << 0)
71 #define EEFC_FCR_FCMD_EWP (0x3u << 0)
72 #define EEFC_FCR_FCMD_EWPL (0x4u << 0)
73 #define EEFC_FCR_FCMD_EA (0x5u << 0)
74 #define EEFC_FCR_FCMD_EPA (0x7u << 0)
75 #define EEFC_FCR_FCMD_SLB (0x8u << 0)
76 #define EEFC_FCR_FCMD_CLB (0x9u << 0)
77 #define EEFC_FCR_FCMD_GLB (0xAu << 0)
78 #define EEFC_FCR_FCMD_SGPB (0xBu << 0)
79 #define EEFC_FCR_FCMD_CGPB (0xCu << 0)
80 #define EEFC_FCR_FCMD_GGPB (0xDu << 0)
81 #define EEFC_FCR_FCMD_STUI (0xEu << 0)
82 #define EEFC_FCR_FCMD_SPUI (0xFu << 0)
83 #define EEFC_FCR_FCMD_GCALB (0x10u << 0)
84 #define EEFC_FCR_FCMD_ES (0x11u << 0)
85 #define EEFC_FCR_FCMD_WUS (0x12u << 0)
86 #define EEFC_FCR_FCMD_EUS (0x13u << 0)
87 #define EEFC_FCR_FCMD_STUS (0x14u << 0)
88 #define EEFC_FCR_FCMD_SPUS (0x15u << 0)
89 #define EEFC_FCR_FARG_Pos 8
90 #define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos)
91 #define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
92 #define EEFC_FCR_FKEY_Pos 24
93 #define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos)
94 #define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
95 #define EEFC_FCR_FKEY_PASSWD (0x5Au << 24)
96 /* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
97 #define EEFC_FSR_FRDY (0x1u << 0)
98 #define EEFC_FSR_FCMDE (0x1u << 1)
99 #define EEFC_FSR_FLOCKE (0x1u << 2)
100 #define EEFC_FSR_FLERR (0x1u << 3)
101 #define EEFC_FSR_UECCELSB (0x1u << 16)
102 #define EEFC_FSR_MECCELSB (0x1u << 17)
103 #define EEFC_FSR_UECCEMSB (0x1u << 18)
104 #define EEFC_FSR_MECCEMSB (0x1u << 19)
105 /* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
106 #define EEFC_FRR_FVALUE_Pos 0
107 #define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos)
108 /* -------- EEFC_VERSION : (EFC Offset: 0x14) EEFC Version Register -------- */
109 #define EEFC_VERSION_VERSION_Pos 0
110 #define EEFC_VERSION_VERSION_Msk (0xfffu << EEFC_VERSION_VERSION_Pos)
111 #define EEFC_VERSION_MFN_Pos 16
112 #define EEFC_VERSION_MFN_Msk (0x7u << EEFC_VERSION_MFN_Pos)
113 /* -------- EEFC_WPMR : (EFC Offset: 0xE4) Write Protection Mode Register -------- */
114 #define EEFC_WPMR_WPEN (0x1u << 0)
115 #define EEFC_WPMR_WPKEY_Pos 8
116 #define EEFC_WPMR_WPKEY_Msk (0xffffffu << EEFC_WPMR_WPKEY_Pos)
117 #define EEFC_WPMR_WPKEY(value) ((EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos)))
118 #define EEFC_WPMR_WPKEY_PASSWD (0x454643u << 8)
121 
122 
123 #endif /* _SAME70_EFC_COMPONENT_ */
__O uint32_t EEFC_FCR
(Efc Offset: 0x04) EEFC Flash Command Register
#define __IO
Definition: core_cm7.h:266
#define __O
Definition: core_cm7.h:265
Efc hardware registers.
__I uint32_t EEFC_VERSION
(Efc Offset: 0x14) EEFC Version Register
__IO uint32_t EEFC_WPMR
(Efc Offset: 0xE4) Write Protection Mode Register
__I uint32_t EEFC_FRR
(Efc Offset: 0x0C) EEFC Flash Result Register
__I uint32_t EEFC_FSR
(Efc Offset: 0x08) EEFC Flash Status Register
__IO uint32_t EEFC_FMR
(Efc Offset: 0x00) EEFC Flash Mode Register
#define __I
Definition: core_cm7.h:263


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autogenerated on Sat Sep 19 2020 03:19:04