Classes | Macros
Power Management Controller

Classes

struct  Pmc
 Pmc hardware registers. More...
 

Macros

#define CKGR_MCFR_CCSS   (0x1u << 24)
 (CKGR_MCFR) Counter Clock Source Selection More...
 
#define CKGR_MCFR_MAINF(value)   ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)))
 
#define CKGR_MCFR_MAINF_Msk   (0xffffu << CKGR_MCFR_MAINF_Pos)
 (CKGR_MCFR) Main Clock Frequency More...
 
#define CKGR_MCFR_MAINF_Pos   0
 
#define CKGR_MCFR_MAINFRDY   (0x1u << 16)
 (CKGR_MCFR) Main Clock Frequency Measure Ready More...
 
#define CKGR_MCFR_RCMEAS   (0x1u << 20)
 (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) More...
 
#define CKGR_MOR_CFDEN   (0x1u << 25)
 (CKGR_MOR) Clock Failure Detector Enable More...
 
#define CKGR_MOR_KEY(value)   ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
 
#define CKGR_MOR_KEY_Msk   (0xffu << CKGR_MOR_KEY_Pos)
 (CKGR_MOR) Write Access Password More...
 
#define CKGR_MOR_KEY_PASSWD   (0x37u << 16)
 (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. More...
 
#define CKGR_MOR_KEY_Pos   16
 
#define CKGR_MOR_MOSCRCEN   (0x1u << 3)
 (CKGR_MOR) Main On-Chip RC Oscillator Enable More...
 
#define CKGR_MOR_MOSCRCF(value)   ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos)))
 
#define CKGR_MOR_MOSCRCF_12_MHz   (0x2u << 4)
 (CKGR_MOR) Fast RC oscillator frequency is at 12 MHz More...
 
#define CKGR_MOR_MOSCRCF_4_MHz   (0x0u << 4)
 (CKGR_MOR) Fast RC oscillator frequency is at 4 MHz (default) More...
 
#define CKGR_MOR_MOSCRCF_8_MHz   (0x1u << 4)
 (CKGR_MOR) Fast RC oscillator frequency is at 8 MHz More...
 
#define CKGR_MOR_MOSCRCF_Msk   (0x7u << CKGR_MOR_MOSCRCF_Pos)
 (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection More...
 
#define CKGR_MOR_MOSCRCF_Pos   4
 
#define CKGR_MOR_MOSCSEL   (0x1u << 24)
 (CKGR_MOR) Main Oscillator Selection More...
 
#define CKGR_MOR_MOSCXTBY   (0x1u << 1)
 (CKGR_MOR) Main Crystal Oscillator Bypass More...
 
#define CKGR_MOR_MOSCXTEN   (0x1u << 0)
 (CKGR_MOR) Main Crystal Oscillator Enable More...
 
#define CKGR_MOR_MOSCXTST(value)   ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
 
#define CKGR_MOR_MOSCXTST_Msk   (0xffu << CKGR_MOR_MOSCXTST_Pos)
 (CKGR_MOR) Main Crystal Oscillator Start-up Time More...
 
#define CKGR_MOR_MOSCXTST_Pos   8
 
#define CKGR_MOR_WAITMODE   (0x1u << 2)
 (CKGR_MOR) Wait Mode Command (Write-only) More...
 
#define CKGR_MOR_XT32KFME   (0x1u << 26)
 (CKGR_MOR) Slow Crystal Oscillator Frequency Monitoring Enable More...
 
#define CKGR_PLLAR_DIVA(value)   ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
 
#define CKGR_PLLAR_DIVA_0   (0x0u << 0)
 (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. More...
 
#define CKGR_PLLAR_DIVA_BYPASS   (0x1u << 0)
 (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. More...
 
#define CKGR_PLLAR_DIVA_Msk   (0xffu << CKGR_PLLAR_DIVA_Pos)
 (CKGR_PLLAR) PLLA Front End Divider More...
 
#define CKGR_PLLAR_DIVA_Pos   0
 
#define CKGR_PLLAR_MULA(value)   ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
 
#define CKGR_PLLAR_MULA_Msk   (0x7ffu << CKGR_PLLAR_MULA_Pos)
 (CKGR_PLLAR) PLLA Multiplier More...
 
#define CKGR_PLLAR_MULA_Pos   16
 
#define CKGR_PLLAR_ONE   (0x1u << 29)
 (CKGR_PLLAR) Must Be Set to 1 More...
 
#define CKGR_PLLAR_PLLACOUNT(value)   ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
 
#define CKGR_PLLAR_PLLACOUNT_Msk   (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos)
 (CKGR_PLLAR) PLLA Counter More...
 
#define CKGR_PLLAR_PLLACOUNT_Pos   8
 
#define CKGR_UCKR_UPLLCOUNT(value)   ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))
 
#define CKGR_UCKR_UPLLCOUNT_Msk   (0xfu << CKGR_UCKR_UPLLCOUNT_Pos)
 (CKGR_UCKR) UTMI PLL Start-up Time More...
 
#define CKGR_UCKR_UPLLCOUNT_Pos   20
 
#define CKGR_UCKR_UPLLEN   (0x1u << 16)
 (CKGR_UCKR) UTMI PLL Enable More...
 
#define PMC_APLLACR_BIAS(value)   ((PMC_APLLACR_BIAS_Msk & ((value) << PMC_APLLACR_BIAS_Pos)))
 
#define PMC_APLLACR_BIAS_Msk   (0x3u << PMC_APLLACR_BIAS_Pos)
 (PMC_APLLACR) Bias Voltage Selection More...
 
#define PMC_APLLACR_BIAS_Pos   8
 
#define PMC_APLLACR_DCOFLTSEL(value)   ((PMC_APLLACR_DCOFLTSEL_Msk & ((value) << PMC_APLLACR_DCOFLTSEL_Pos)))
 
#define PMC_APLLACR_DCOFLTSEL_Msk   (0xfu << PMC_APLLACR_DCOFLTSEL_Pos)
 (PMC_APLLACR) DCO Filter Selection More...
 
#define PMC_APLLACR_DCOFLTSEL_Pos   0
 
#define PMC_APLLACR_FLTSEL(value)   ((PMC_APLLACR_FLTSEL_Msk & ((value) << PMC_APLLACR_FLTSEL_Pos)))
 
#define PMC_APLLACR_FLTSEL_Msk   (0xfu << PMC_APLLACR_FLTSEL_Pos)
 (PMC_APLLACR) PLL Filter Selection More...
 
#define PMC_APLLACR_FLTSEL_Pos   4
 
#define PMC_FOCR_FOCLR   (0x1u << 0)
 (PMC_FOCR) Fault Output Clear More...
 
#define PMC_FSMR_FFLPM   (0x1u << 23)
 (PMC_FSMR) Force Flash Low-power Mode More...
 
#define PMC_FSMR_FLPM(value)   ((PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos)))
 
#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN   (0x1u << 21)
 (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode More...
 
#define PMC_FSMR_FLPM_FLASH_IDLE   (0x2u << 21)
 (PMC_FSMR) Idle mode More...
 
#define PMC_FSMR_FLPM_FLASH_STANDBY   (0x0u << 21)
 (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode More...
 
#define PMC_FSMR_FLPM_Msk   (0x3u << PMC_FSMR_FLPM_Pos)
 (PMC_FSMR) Flash Low-power Mode More...
 
#define PMC_FSMR_FLPM_Pos   21
 
#define PMC_FSMR_FSTT0   (0x1u << 0)
 (PMC_FSMR) Fast Startup Input Enable 0 More...
 
#define PMC_FSMR_FSTT1   (0x1u << 1)
 (PMC_FSMR) Fast Startup Input Enable 1 More...
 
#define PMC_FSMR_FSTT10   (0x1u << 10)
 (PMC_FSMR) Fast Startup Input Enable 10 More...
 
#define PMC_FSMR_FSTT11   (0x1u << 11)
 (PMC_FSMR) Fast Startup Input Enable 11 More...
 
#define PMC_FSMR_FSTT12   (0x1u << 12)
 (PMC_FSMR) Fast Startup Input Enable 12 More...
 
#define PMC_FSMR_FSTT13   (0x1u << 13)
 (PMC_FSMR) Fast Startup Input Enable 13 More...
 
#define PMC_FSMR_FSTT14   (0x1u << 14)
 (PMC_FSMR) Fast Startup Input Enable 14 More...
 
#define PMC_FSMR_FSTT15   (0x1u << 15)
 (PMC_FSMR) Fast Startup Input Enable 15 More...
 
#define PMC_FSMR_FSTT2   (0x1u << 2)
 (PMC_FSMR) Fast Startup Input Enable 2 More...
 
#define PMC_FSMR_FSTT3   (0x1u << 3)
 (PMC_FSMR) Fast Startup Input Enable 3 More...
 
#define PMC_FSMR_FSTT4   (0x1u << 4)
 (PMC_FSMR) Fast Startup Input Enable 4 More...
 
#define PMC_FSMR_FSTT5   (0x1u << 5)
 (PMC_FSMR) Fast Startup Input Enable 5 More...
 
#define PMC_FSMR_FSTT6   (0x1u << 6)
 (PMC_FSMR) Fast Startup Input Enable 6 More...
 
#define PMC_FSMR_FSTT7   (0x1u << 7)
 (PMC_FSMR) Fast Startup Input Enable 7 More...
 
#define PMC_FSMR_FSTT8   (0x1u << 8)
 (PMC_FSMR) Fast Startup Input Enable 8 More...
 
#define PMC_FSMR_FSTT9   (0x1u << 9)
 (PMC_FSMR) Fast Startup Input Enable 9 More...
 
#define PMC_FSMR_LPM   (0x1u << 20)
 (PMC_FSMR) Low-power Mode More...
 
#define PMC_FSMR_RTCAL   (0x1u << 17)
 (PMC_FSMR) RTC Alarm Enable More...
 
#define PMC_FSMR_RTTAL   (0x1u << 16)
 (PMC_FSMR) RTT Alarm Enable More...
 
#define PMC_FSMR_USBAL   (0x1u << 18)
 (PMC_FSMR) USB Alarm Enable More...
 
#define PMC_FSPR_FSTP0   (0x1u << 0)
 (PMC_FSPR) Fast Startup Input Polarity 0 More...
 
#define PMC_FSPR_FSTP1   (0x1u << 1)
 (PMC_FSPR) Fast Startup Input Polarity 1 More...
 
#define PMC_FSPR_FSTP10   (0x1u << 10)
 (PMC_FSPR) Fast Startup Input Polarity 10 More...
 
#define PMC_FSPR_FSTP11   (0x1u << 11)
 (PMC_FSPR) Fast Startup Input Polarity 11 More...
 
#define PMC_FSPR_FSTP12   (0x1u << 12)
 (PMC_FSPR) Fast Startup Input Polarity 12 More...
 
#define PMC_FSPR_FSTP13   (0x1u << 13)
 (PMC_FSPR) Fast Startup Input Polarity 13 More...
 
#define PMC_FSPR_FSTP14   (0x1u << 14)
 (PMC_FSPR) Fast Startup Input Polarity 14 More...
 
#define PMC_FSPR_FSTP15   (0x1u << 15)
 (PMC_FSPR) Fast Startup Input Polarity 15 More...
 
#define PMC_FSPR_FSTP2   (0x1u << 2)
 (PMC_FSPR) Fast Startup Input Polarity 2 More...
 
#define PMC_FSPR_FSTP3   (0x1u << 3)
 (PMC_FSPR) Fast Startup Input Polarity 3 More...
 
#define PMC_FSPR_FSTP4   (0x1u << 4)
 (PMC_FSPR) Fast Startup Input Polarity 4 More...
 
#define PMC_FSPR_FSTP5   (0x1u << 5)
 (PMC_FSPR) Fast Startup Input Polarity 5 More...
 
#define PMC_FSPR_FSTP6   (0x1u << 6)
 (PMC_FSPR) Fast Startup Input Polarity 6 More...
 
#define PMC_FSPR_FSTP7   (0x1u << 7)
 (PMC_FSPR) Fast Startup Input Polarity 7 More...
 
#define PMC_FSPR_FSTP8   (0x1u << 8)
 (PMC_FSPR) Fast Startup Input Polarity 8 More...
 
#define PMC_FSPR_FSTP9   (0x1u << 9)
 (PMC_FSPR) Fast Startup Input Polarity 9 More...
 
#define PMC_IDR_CFDEV   (0x1u << 18)
 (PMC_IDR) Clock Failure Detector Event Interrupt Disable More...
 
#define PMC_IDR_LOCKA   (0x1u << 1)
 (PMC_IDR) PLLA Lock Interrupt Disable More...
 
#define PMC_IDR_LOCKU   (0x1u << 6)
 (PMC_IDR) UTMI PLL Lock Interrupt Disable More...
 
#define PMC_IDR_MCKRDY   (0x1u << 3)
 (PMC_IDR) Master Clock Ready Interrupt Disable More...
 
#define PMC_IDR_MOSCRCS   (0x1u << 17)
 (PMC_IDR) Main On-Chip RC Status Interrupt Disable More...
 
#define PMC_IDR_MOSCSELS   (0x1u << 16)
 (PMC_IDR) Main Oscillator Selection Status Interrupt Disable More...
 
#define PMC_IDR_MOSCXTS   (0x1u << 0)
 (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable More...
 
#define PMC_IDR_PCKRDY0   (0x1u << 8)
 (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable More...
 
#define PMC_IDR_PCKRDY1   (0x1u << 9)
 (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable More...
 
#define PMC_IDR_PCKRDY2   (0x1u << 10)
 (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable More...
 
#define PMC_IDR_PCKRDY3   (0x1u << 11)
 (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable More...
 
#define PMC_IDR_PCKRDY4   (0x1u << 12)
 (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable More...
 
#define PMC_IDR_PCKRDY5   (0x1u << 13)
 (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable More...
 
#define PMC_IDR_PCKRDY6   (0x1u << 14)
 (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable More...
 
#define PMC_IDR_XT32KERR   (0x1u << 21)
 (PMC_IDR) Slow Crystal Oscillator Error Interrupt Disable More...
 
#define PMC_IER_CFDEV   (0x1u << 18)
 (PMC_IER) Clock Failure Detector Event Interrupt Enable More...
 
#define PMC_IER_LOCKA   (0x1u << 1)
 (PMC_IER) PLLA Lock Interrupt Enable More...
 
#define PMC_IER_LOCKU   (0x1u << 6)
 (PMC_IER) UTMI PLL Lock Interrupt Enable More...
 
#define PMC_IER_MCKRDY   (0x1u << 3)
 (PMC_IER) Master Clock Ready Interrupt Enable More...
 
#define PMC_IER_MOSCRCS   (0x1u << 17)
 (PMC_IER) Main On-Chip RC Status Interrupt Enable More...
 
#define PMC_IER_MOSCSELS   (0x1u << 16)
 (PMC_IER) Main Oscillator Selection Status Interrupt Enable More...
 
#define PMC_IER_MOSCXTS   (0x1u << 0)
 (PMC_IER) Main Crystal Oscillator Status Interrupt Enable More...
 
#define PMC_IER_PCKRDY0   (0x1u << 8)
 (PMC_IER) Programmable Clock Ready 0 Interrupt Enable More...
 
#define PMC_IER_PCKRDY1   (0x1u << 9)
 (PMC_IER) Programmable Clock Ready 1 Interrupt Enable More...
 
#define PMC_IER_PCKRDY2   (0x1u << 10)
 (PMC_IER) Programmable Clock Ready 2 Interrupt Enable More...
 
#define PMC_IER_PCKRDY3   (0x1u << 11)
 (PMC_IER) Programmable Clock Ready 3 Interrupt Enable More...
 
#define PMC_IER_PCKRDY4   (0x1u << 12)
 (PMC_IER) Programmable Clock Ready 4 Interrupt Enable More...
 
#define PMC_IER_PCKRDY5   (0x1u << 13)
 (PMC_IER) Programmable Clock Ready 5 Interrupt Enable More...
 
#define PMC_IER_PCKRDY6   (0x1u << 14)
 (PMC_IER) Programmable Clock Ready 6 Interrupt Enable More...
 
#define PMC_IER_XT32KERR   (0x1u << 21)
 (PMC_IER) Slow Crystal Oscillator Error Interrupt Enable More...
 
#define PMC_IMR_CFDEV   (0x1u << 18)
 (PMC_IMR) Clock Failure Detector Event Interrupt Mask More...
 
#define PMC_IMR_LOCKA   (0x1u << 1)
 (PMC_IMR) PLLA Lock Interrupt Mask More...
 
#define PMC_IMR_LOCKU   (0x1u << 6)
 (PMC_IMR) UTMI PLL Lock Interrupt Mask More...
 
#define PMC_IMR_MCKRDY   (0x1u << 3)
 (PMC_IMR) Master Clock Ready Interrupt Mask More...
 
#define PMC_IMR_MOSCRCS   (0x1u << 17)
 (PMC_IMR) Main On-Chip RC Status Interrupt Mask More...
 
#define PMC_IMR_MOSCSELS   (0x1u << 16)
 (PMC_IMR) Main Oscillator Selection Status Interrupt Mask More...
 
#define PMC_IMR_MOSCXTS   (0x1u << 0)
 (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask More...
 
#define PMC_IMR_PCKRDY0   (0x1u << 8)
 (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask More...
 
#define PMC_IMR_PCKRDY1   (0x1u << 9)
 (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask More...
 
#define PMC_IMR_PCKRDY2   (0x1u << 10)
 (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask More...
 
#define PMC_IMR_PCKRDY3   (0x1u << 11)
 (PMC_IMR) Programmable Clock Ready 3 Interrupt Mask More...
 
#define PMC_IMR_PCKRDY4   (0x1u << 12)
 (PMC_IMR) Programmable Clock Ready 4 Interrupt Mask More...
 
#define PMC_IMR_PCKRDY5   (0x1u << 13)
 (PMC_IMR) Programmable Clock Ready 5 Interrupt Mask More...
 
#define PMC_IMR_PCKRDY6   (0x1u << 14)
 (PMC_IMR) Programmable Clock Ready 6 Interrupt Mask More...
 
#define PMC_IMR_XT32KERR   (0x1u << 21)
 (PMC_IMR) Slow Crystal Oscillator Error Interrupt Mask More...
 
#define PMC_MCKR_CSS(value)   ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos)))
 
#define PMC_MCKR_CSS_MAIN_CLK   (0x1u << 0)
 (PMC_MCKR) Main Clock is selected More...
 
#define PMC_MCKR_CSS_Msk   (0x3u << PMC_MCKR_CSS_Pos)
 (PMC_MCKR) Master Clock Source Selection More...
 
#define PMC_MCKR_CSS_PLLA_CLK   (0x2u << 0)
 (PMC_MCKR) PLLA Clock is selected More...
 
#define PMC_MCKR_CSS_Pos   0
 
#define PMC_MCKR_CSS_SLOW_CLK   (0x0u << 0)
 (PMC_MCKR) Slow Clock is selected More...
 
#define PMC_MCKR_CSS_UPLL_CLK   (0x3u << 0)
 (PMC_MCKR) Divided UPLL Clock is selected More...
 
#define PMC_MCKR_MDIV(value)   ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos)))
 
#define PMC_MCKR_MDIV_EQ_PCK   (0x0u << 8)
 (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. More...
 
#define PMC_MCKR_MDIV_Msk   (0x3u << PMC_MCKR_MDIV_Pos)
 (PMC_MCKR) Master Clock Division More...
 
#define PMC_MCKR_MDIV_PCK_DIV2   (0x1u << 8)
 (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. More...
 
#define PMC_MCKR_MDIV_PCK_DIV3   (0x3u << 8)
 (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. More...
 
#define PMC_MCKR_MDIV_PCK_DIV4   (0x2u << 8)
 (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. More...
 
#define PMC_MCKR_MDIV_Pos   8
 
#define PMC_MCKR_PRES(value)   ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos)))
 
#define PMC_MCKR_PRES_CLK_1   (0x0u << 4)
 (PMC_MCKR) Selected clock More...
 
#define PMC_MCKR_PRES_CLK_16   (0x4u << 4)
 (PMC_MCKR) Selected clock divided by 16 More...
 
#define PMC_MCKR_PRES_CLK_2   (0x1u << 4)
 (PMC_MCKR) Selected clock divided by 2 More...
 
#define PMC_MCKR_PRES_CLK_3   (0x7u << 4)
 (PMC_MCKR) Selected clock divided by 3 More...
 
#define PMC_MCKR_PRES_CLK_32   (0x5u << 4)
 (PMC_MCKR) Selected clock divided by 32 More...
 
#define PMC_MCKR_PRES_CLK_4   (0x2u << 4)
 (PMC_MCKR) Selected clock divided by 4 More...
 
#define PMC_MCKR_PRES_CLK_64   (0x6u << 4)
 (PMC_MCKR) Selected clock divided by 64 More...
 
#define PMC_MCKR_PRES_CLK_8   (0x3u << 4)
 (PMC_MCKR) Selected clock divided by 8 More...
 
#define PMC_MCKR_PRES_Msk   (0x7u << PMC_MCKR_PRES_Pos)
 (PMC_MCKR) Processor Clock Prescaler More...
 
#define PMC_MCKR_PRES_Pos   4
 
#define PMC_MCKR_UPLLDIV2   (0x1u << 13)
 (PMC_MCKR) UPLL Divisor by 2 More...
 
#define PMC_OCR_CAL12(value)   ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))
 
#define PMC_OCR_CAL12_Msk   (0x7fu << PMC_OCR_CAL12_Pos)
 (PMC_OCR) RC Oscillator Calibration bits for 12 MHz More...
 
#define PMC_OCR_CAL12_Pos   16
 
#define PMC_OCR_CAL4(value)   ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))
 
#define PMC_OCR_CAL4_Msk   (0x7fu << PMC_OCR_CAL4_Pos)
 (PMC_OCR) RC Oscillator Calibration bits for 4 MHz More...
 
#define PMC_OCR_CAL4_Pos   0
 
#define PMC_OCR_CAL8(value)   ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))
 
#define PMC_OCR_CAL8_Msk   (0x7fu << PMC_OCR_CAL8_Pos)
 (PMC_OCR) RC Oscillator Calibration bits for 8 MHz More...
 
#define PMC_OCR_CAL8_Pos   8
 
#define PMC_OCR_SEL12   (0x1u << 23)
 (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz More...
 
#define PMC_OCR_SEL4   (0x1u << 7)
 (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz More...
 
#define PMC_OCR_SEL8   (0x1u << 15)
 (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz More...
 
#define PMC_PCDR0_PID10   (0x1u << 10)
 (PMC_PCDR0) Peripheral Clock 10 Disable More...
 
#define PMC_PCDR0_PID11   (0x1u << 11)
 (PMC_PCDR0) Peripheral Clock 11 Disable More...
 
#define PMC_PCDR0_PID12   (0x1u << 12)
 (PMC_PCDR0) Peripheral Clock 12 Disable More...
 
#define PMC_PCDR0_PID13   (0x1u << 13)
 (PMC_PCDR0) Peripheral Clock 13 Disable More...
 
#define PMC_PCDR0_PID14   (0x1u << 14)
 (PMC_PCDR0) Peripheral Clock 14 Disable More...
 
#define PMC_PCDR0_PID15   (0x1u << 15)
 (PMC_PCDR0) Peripheral Clock 15 Disable More...
 
#define PMC_PCDR0_PID16   (0x1u << 16)
 (PMC_PCDR0) Peripheral Clock 16 Disable More...
 
#define PMC_PCDR0_PID17   (0x1u << 17)
 (PMC_PCDR0) Peripheral Clock 17 Disable More...
 
#define PMC_PCDR0_PID18   (0x1u << 18)
 (PMC_PCDR0) Peripheral Clock 18 Disable More...
 
#define PMC_PCDR0_PID19   (0x1u << 19)
 (PMC_PCDR0) Peripheral Clock 19 Disable More...
 
#define PMC_PCDR0_PID20   (0x1u << 20)
 (PMC_PCDR0) Peripheral Clock 20 Disable More...
 
#define PMC_PCDR0_PID21   (0x1u << 21)
 (PMC_PCDR0) Peripheral Clock 21 Disable More...
 
#define PMC_PCDR0_PID22   (0x1u << 22)
 (PMC_PCDR0) Peripheral Clock 22 Disable More...
 
#define PMC_PCDR0_PID23   (0x1u << 23)
 (PMC_PCDR0) Peripheral Clock 23 Disable More...
 
#define PMC_PCDR0_PID24   (0x1u << 24)
 (PMC_PCDR0) Peripheral Clock 24 Disable More...
 
#define PMC_PCDR0_PID25   (0x1u << 25)
 (PMC_PCDR0) Peripheral Clock 25 Disable More...
 
#define PMC_PCDR0_PID26   (0x1u << 26)
 (PMC_PCDR0) Peripheral Clock 26 Disable More...
 
#define PMC_PCDR0_PID27   (0x1u << 27)
 (PMC_PCDR0) Peripheral Clock 27 Disable More...
 
#define PMC_PCDR0_PID28   (0x1u << 28)
 (PMC_PCDR0) Peripheral Clock 28 Disable More...
 
#define PMC_PCDR0_PID29   (0x1u << 29)
 (PMC_PCDR0) Peripheral Clock 29 Disable More...
 
#define PMC_PCDR0_PID30   (0x1u << 30)
 (PMC_PCDR0) Peripheral Clock 30 Disable More...
 
#define PMC_PCDR0_PID31   (0x1u << 31)
 (PMC_PCDR0) Peripheral Clock 31 Disable More...
 
#define PMC_PCDR0_PID7   (0x1u << 7)
 (PMC_PCDR0) Peripheral Clock 7 Disable More...
 
#define PMC_PCDR0_PID8   (0x1u << 8)
 (PMC_PCDR0) Peripheral Clock 8 Disable More...
 
#define PMC_PCDR0_PID9   (0x1u << 9)
 (PMC_PCDR0) Peripheral Clock 9 Disable More...
 
#define PMC_PCDR1_PID32   (0x1u << 0)
 (PMC_PCDR1) Peripheral Clock 32 Disable More...
 
#define PMC_PCDR1_PID33   (0x1u << 1)
 (PMC_PCDR1) Peripheral Clock 33 Disable More...
 
#define PMC_PCDR1_PID34   (0x1u << 2)
 (PMC_PCDR1) Peripheral Clock 34 Disable More...
 
#define PMC_PCDR1_PID35   (0x1u << 3)
 (PMC_PCDR1) Peripheral Clock 35 Disable More...
 
#define PMC_PCDR1_PID37   (0x1u << 5)
 (PMC_PCDR1) Peripheral Clock 37 Disable More...
 
#define PMC_PCDR1_PID39   (0x1u << 7)
 (PMC_PCDR1) Peripheral Clock 39 Disable More...
 
#define PMC_PCDR1_PID40   (0x1u << 8)
 (PMC_PCDR1) Peripheral Clock 40 Disable More...
 
#define PMC_PCDR1_PID41   (0x1u << 9)
 (PMC_PCDR1) Peripheral Clock 41 Disable More...
 
#define PMC_PCDR1_PID42   (0x1u << 10)
 (PMC_PCDR1) Peripheral Clock 42 Disable More...
 
#define PMC_PCDR1_PID43   (0x1u << 11)
 (PMC_PCDR1) Peripheral Clock 43 Disable More...
 
#define PMC_PCDR1_PID44   (0x1u << 12)
 (PMC_PCDR1) Peripheral Clock 44 Disable More...
 
#define PMC_PCDR1_PID45   (0x1u << 13)
 (PMC_PCDR1) Peripheral Clock 45 Disable More...
 
#define PMC_PCDR1_PID46   (0x1u << 14)
 (PMC_PCDR1) Peripheral Clock 46 Disable More...
 
#define PMC_PCDR1_PID47   (0x1u << 15)
 (PMC_PCDR1) Peripheral Clock 47 Disable More...
 
#define PMC_PCDR1_PID48   (0x1u << 16)
 (PMC_PCDR1) Peripheral Clock 48 Disable More...
 
#define PMC_PCDR1_PID49   (0x1u << 17)
 (PMC_PCDR1) Peripheral Clock 49 Disable More...
 
#define PMC_PCDR1_PID50   (0x1u << 18)
 (PMC_PCDR1) Peripheral Clock 50 Disable More...
 
#define PMC_PCDR1_PID51   (0x1u << 19)
 (PMC_PCDR1) Peripheral Clock 51 Disable More...
 
#define PMC_PCDR1_PID52   (0x1u << 20)
 (PMC_PCDR1) Peripheral Clock 52 Disable More...
 
#define PMC_PCDR1_PID53   (0x1u << 21)
 (PMC_PCDR1) Peripheral Clock 53 Disable More...
 
#define PMC_PCDR1_PID56   (0x1u << 24)
 (PMC_PCDR1) Peripheral Clock 56 Disable More...
 
#define PMC_PCDR1_PID57   (0x1u << 25)
 (PMC_PCDR1) Peripheral Clock 57 Disable More...
 
#define PMC_PCDR1_PID58   (0x1u << 26)
 (PMC_PCDR1) Peripheral Clock 58 Disable More...
 
#define PMC_PCDR1_PID59   (0x1u << 27)
 (PMC_PCDR1) Peripheral Clock 59 Disable More...
 
#define PMC_PCDR1_PID60   (0x1u << 28)
 (PMC_PCDR1) Peripheral Clock 60 Disable More...
 
#define PMC_PCER0_PID10   (0x1u << 10)
 (PMC_PCER0) Peripheral Clock 10 Enable More...
 
#define PMC_PCER0_PID11   (0x1u << 11)
 (PMC_PCER0) Peripheral Clock 11 Enable More...
 
#define PMC_PCER0_PID12   (0x1u << 12)
 (PMC_PCER0) Peripheral Clock 12 Enable More...
 
#define PMC_PCER0_PID13   (0x1u << 13)
 (PMC_PCER0) Peripheral Clock 13 Enable More...
 
#define PMC_PCER0_PID14   (0x1u << 14)
 (PMC_PCER0) Peripheral Clock 14 Enable More...
 
#define PMC_PCER0_PID15   (0x1u << 15)
 (PMC_PCER0) Peripheral Clock 15 Enable More...
 
#define PMC_PCER0_PID16   (0x1u << 16)
 (PMC_PCER0) Peripheral Clock 16 Enable More...
 
#define PMC_PCER0_PID17   (0x1u << 17)
 (PMC_PCER0) Peripheral Clock 17 Enable More...
 
#define PMC_PCER0_PID18   (0x1u << 18)
 (PMC_PCER0) Peripheral Clock 18 Enable More...
 
#define PMC_PCER0_PID19   (0x1u << 19)
 (PMC_PCER0) Peripheral Clock 19 Enable More...
 
#define PMC_PCER0_PID20   (0x1u << 20)
 (PMC_PCER0) Peripheral Clock 20 Enable More...
 
#define PMC_PCER0_PID21   (0x1u << 21)
 (PMC_PCER0) Peripheral Clock 21 Enable More...
 
#define PMC_PCER0_PID22   (0x1u << 22)
 (PMC_PCER0) Peripheral Clock 22 Enable More...
 
#define PMC_PCER0_PID23   (0x1u << 23)
 (PMC_PCER0) Peripheral Clock 23 Enable More...
 
#define PMC_PCER0_PID24   (0x1u << 24)
 (PMC_PCER0) Peripheral Clock 24 Enable More...
 
#define PMC_PCER0_PID25   (0x1u << 25)
 (PMC_PCER0) Peripheral Clock 25 Enable More...
 
#define PMC_PCER0_PID26   (0x1u << 26)
 (PMC_PCER0) Peripheral Clock 26 Enable More...
 
#define PMC_PCER0_PID27   (0x1u << 27)
 (PMC_PCER0) Peripheral Clock 27 Enable More...
 
#define PMC_PCER0_PID28   (0x1u << 28)
 (PMC_PCER0) Peripheral Clock 28 Enable More...
 
#define PMC_PCER0_PID29   (0x1u << 29)
 (PMC_PCER0) Peripheral Clock 29 Enable More...
 
#define PMC_PCER0_PID30   (0x1u << 30)
 (PMC_PCER0) Peripheral Clock 30 Enable More...
 
#define PMC_PCER0_PID31   (0x1u << 31)
 (PMC_PCER0) Peripheral Clock 31 Enable More...
 
#define PMC_PCER0_PID7   (0x1u << 7)
 (PMC_PCER0) Peripheral Clock 7 Enable More...
 
#define PMC_PCER0_PID8   (0x1u << 8)
 (PMC_PCER0) Peripheral Clock 8 Enable More...
 
#define PMC_PCER0_PID9   (0x1u << 9)
 (PMC_PCER0) Peripheral Clock 9 Enable More...
 
#define PMC_PCER1_PID32   (0x1u << 0)
 (PMC_PCER1) Peripheral Clock 32 Enable More...
 
#define PMC_PCER1_PID33   (0x1u << 1)
 (PMC_PCER1) Peripheral Clock 33 Enable More...
 
#define PMC_PCER1_PID34   (0x1u << 2)
 (PMC_PCER1) Peripheral Clock 34 Enable More...
 
#define PMC_PCER1_PID35   (0x1u << 3)
 (PMC_PCER1) Peripheral Clock 35 Enable More...
 
#define PMC_PCER1_PID37   (0x1u << 5)
 (PMC_PCER1) Peripheral Clock 37 Enable More...
 
#define PMC_PCER1_PID39   (0x1u << 7)
 (PMC_PCER1) Peripheral Clock 39 Enable More...
 
#define PMC_PCER1_PID40   (0x1u << 8)
 (PMC_PCER1) Peripheral Clock 40 Enable More...
 
#define PMC_PCER1_PID41   (0x1u << 9)
 (PMC_PCER1) Peripheral Clock 41 Enable More...
 
#define PMC_PCER1_PID42   (0x1u << 10)
 (PMC_PCER1) Peripheral Clock 42 Enable More...
 
#define PMC_PCER1_PID43   (0x1u << 11)
 (PMC_PCER1) Peripheral Clock 43 Enable More...
 
#define PMC_PCER1_PID44   (0x1u << 12)
 (PMC_PCER1) Peripheral Clock 44 Enable More...
 
#define PMC_PCER1_PID45   (0x1u << 13)
 (PMC_PCER1) Peripheral Clock 45 Enable More...
 
#define PMC_PCER1_PID46   (0x1u << 14)
 (PMC_PCER1) Peripheral Clock 46 Enable More...
 
#define PMC_PCER1_PID47   (0x1u << 15)
 (PMC_PCER1) Peripheral Clock 47 Enable More...
 
#define PMC_PCER1_PID48   (0x1u << 16)
 (PMC_PCER1) Peripheral Clock 48 Enable More...
 
#define PMC_PCER1_PID49   (0x1u << 17)
 (PMC_PCER1) Peripheral Clock 49 Enable More...
 
#define PMC_PCER1_PID50   (0x1u << 18)
 (PMC_PCER1) Peripheral Clock 50 Enable More...
 
#define PMC_PCER1_PID51   (0x1u << 19)
 (PMC_PCER1) Peripheral Clock 51 Enable More...
 
#define PMC_PCER1_PID52   (0x1u << 20)
 (PMC_PCER1) Peripheral Clock 52 Enable More...
 
#define PMC_PCER1_PID53   (0x1u << 21)
 (PMC_PCER1) Peripheral Clock 53 Enable More...
 
#define PMC_PCER1_PID56   (0x1u << 24)
 (PMC_PCER1) Peripheral Clock 56 Enable More...
 
#define PMC_PCER1_PID57   (0x1u << 25)
 (PMC_PCER1) Peripheral Clock 57 Enable More...
 
#define PMC_PCER1_PID58   (0x1u << 26)
 (PMC_PCER1) Peripheral Clock 58 Enable More...
 
#define PMC_PCER1_PID59   (0x1u << 27)
 (PMC_PCER1) Peripheral Clock 59 Enable More...
 
#define PMC_PCER1_PID60   (0x1u << 28)
 (PMC_PCER1) Peripheral Clock 60 Enable More...
 
#define PMC_PCK_CSS(value)   ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos)))
 
#define PMC_PCK_CSS_MAIN_CLK   (0x1u << 0)
 (PMC_PCK[8]) Main Clock is selected More...
 
#define PMC_PCK_CSS_MCK   (0x4u << 0)
 (PMC_PCK[8]) Master Clock is selected More...
 
#define PMC_PCK_CSS_Msk   (0x7u << PMC_PCK_CSS_Pos)
 (PMC_PCK[8]) Programmable Clock Source Selection More...
 
#define PMC_PCK_CSS_PLLA_CLK   (0x2u << 0)
 (PMC_PCK[8]) PLLA Clock is selected More...
 
#define PMC_PCK_CSS_Pos   0
 
#define PMC_PCK_CSS_SLOW_CLK   (0x0u << 0)
 (PMC_PCK[8]) Slow Clock is selected More...
 
#define PMC_PCK_CSS_UPLL_CLK   (0x3u << 0)
 (PMC_PCK[8]) Divided UPLL Clock is selected More...
 
#define PMC_PCK_PRES(value)   ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)))
 
#define PMC_PCK_PRES_Msk   (0xffu << PMC_PCK_PRES_Pos)
 (PMC_PCK[8]) Programmable Clock Prescaler More...
 
#define PMC_PCK_PRES_Pos   4
 
#define PMC_PCR_CMD   (0x1u << 12)
 (PMC_PCR) Command More...
 
#define PMC_PCR_DIV(value)   ((PMC_PCR_DIV_Msk & ((value) << PMC_PCR_DIV_Pos)))
 
#define PMC_PCR_DIV_Msk   (0x3u << PMC_PCR_DIV_Pos)
 (PMC_PCR) Divisor Value More...
 
#define PMC_PCR_DIV_PERIPH_DIV2_MCK   (0x1u << 16)
 (PMC_PCR) Peripheral clock is MCK/2 More...
 
#define PMC_PCR_DIV_PERIPH_DIV4_MCK   (0x2u << 16)
 (PMC_PCR) Peripheral clock is MCK/4 More...
 
#define PMC_PCR_DIV_PERIPH_DIV8_MCK   (0x3u << 16)
 (PMC_PCR) Peripheral clock is MCK/8 More...
 
#define PMC_PCR_DIV_PERIPH_DIV_MCK   (0x0u << 16)
 (PMC_PCR) Peripheral clock is MCK More...
 
#define PMC_PCR_DIV_Pos   16
 
#define PMC_PCR_EN   (0x1u << 28)
 (PMC_PCR) Enable More...
 
#define PMC_PCR_GCLKCSS(value)   ((PMC_PCR_GCLKCSS_Msk & ((value) << PMC_PCR_GCLKCSS_Pos)))
 
#define PMC_PCR_GCLKCSS_MAIN_CLK   (0x1u << 8)
 (PMC_PCR) Main clock is selected More...
 
#define PMC_PCR_GCLKCSS_MCK_CLK   (0x4u << 8)
 (PMC_PCR) Master Clock is selected More...
 
#define PMC_PCR_GCLKCSS_Msk   (0x7u << PMC_PCR_GCLKCSS_Pos)
 (PMC_PCR) Generic Clock Source Selection More...
 
#define PMC_PCR_GCLKCSS_PLLA_CLK   (0x2u << 8)
 (PMC_PCR) PLLACK is selected More...
 
#define PMC_PCR_GCLKCSS_Pos   8
 
#define PMC_PCR_GCLKCSS_SLOW_CLK   (0x0u << 8)
 (PMC_PCR) Slow clock is selected More...
 
#define PMC_PCR_GCLKCSS_UPLL_CLK   (0x3u << 8)
 (PMC_PCR) UPLL Clock is selected More...
 
#define PMC_PCR_GCLKDIV(value)   ((PMC_PCR_GCLKDIV_Msk & ((value) << PMC_PCR_GCLKDIV_Pos)))
 
#define PMC_PCR_GCLKDIV_Msk   (0xffu << PMC_PCR_GCLKDIV_Pos)
 (PMC_PCR) Generic Clock Division Ratio More...
 
#define PMC_PCR_GCLKDIV_Pos   20
 
#define PMC_PCR_GCLKEN   (0x1u << 29)
 (PMC_PCR) Generic Clock Enable More...
 
#define PMC_PCR_PID(value)   ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)))
 
#define PMC_PCR_PID_Msk   (0x7fu << PMC_PCR_PID_Pos)
 (PMC_PCR) Peripheral ID More...
 
#define PMC_PCR_PID_Pos   0
 
#define PMC_PCSR0_PID10   (0x1u << 10)
 (PMC_PCSR0) Peripheral Clock 10 Status More...
 
#define PMC_PCSR0_PID11   (0x1u << 11)
 (PMC_PCSR0) Peripheral Clock 11 Status More...
 
#define PMC_PCSR0_PID12   (0x1u << 12)
 (PMC_PCSR0) Peripheral Clock 12 Status More...
 
#define PMC_PCSR0_PID13   (0x1u << 13)
 (PMC_PCSR0) Peripheral Clock 13 Status More...
 
#define PMC_PCSR0_PID14   (0x1u << 14)
 (PMC_PCSR0) Peripheral Clock 14 Status More...
 
#define PMC_PCSR0_PID15   (0x1u << 15)
 (PMC_PCSR0) Peripheral Clock 15 Status More...
 
#define PMC_PCSR0_PID16   (0x1u << 16)
 (PMC_PCSR0) Peripheral Clock 16 Status More...
 
#define PMC_PCSR0_PID17   (0x1u << 17)
 (PMC_PCSR0) Peripheral Clock 17 Status More...
 
#define PMC_PCSR0_PID18   (0x1u << 18)
 (PMC_PCSR0) Peripheral Clock 18 Status More...
 
#define PMC_PCSR0_PID19   (0x1u << 19)
 (PMC_PCSR0) Peripheral Clock 19 Status More...
 
#define PMC_PCSR0_PID20   (0x1u << 20)
 (PMC_PCSR0) Peripheral Clock 20 Status More...
 
#define PMC_PCSR0_PID21   (0x1u << 21)
 (PMC_PCSR0) Peripheral Clock 21 Status More...
 
#define PMC_PCSR0_PID22   (0x1u << 22)
 (PMC_PCSR0) Peripheral Clock 22 Status More...
 
#define PMC_PCSR0_PID23   (0x1u << 23)
 (PMC_PCSR0) Peripheral Clock 23 Status More...
 
#define PMC_PCSR0_PID24   (0x1u << 24)
 (PMC_PCSR0) Peripheral Clock 24 Status More...
 
#define PMC_PCSR0_PID25   (0x1u << 25)
 (PMC_PCSR0) Peripheral Clock 25 Status More...
 
#define PMC_PCSR0_PID26   (0x1u << 26)
 (PMC_PCSR0) Peripheral Clock 26 Status More...
 
#define PMC_PCSR0_PID27   (0x1u << 27)
 (PMC_PCSR0) Peripheral Clock 27 Status More...
 
#define PMC_PCSR0_PID28   (0x1u << 28)
 (PMC_PCSR0) Peripheral Clock 28 Status More...
 
#define PMC_PCSR0_PID29   (0x1u << 29)
 (PMC_PCSR0) Peripheral Clock 29 Status More...
 
#define PMC_PCSR0_PID30   (0x1u << 30)
 (PMC_PCSR0) Peripheral Clock 30 Status More...
 
#define PMC_PCSR0_PID31   (0x1u << 31)
 (PMC_PCSR0) Peripheral Clock 31 Status More...
 
#define PMC_PCSR0_PID7   (0x1u << 7)
 (PMC_PCSR0) Peripheral Clock 7 Status More...
 
#define PMC_PCSR0_PID8   (0x1u << 8)
 (PMC_PCSR0) Peripheral Clock 8 Status More...
 
#define PMC_PCSR0_PID9   (0x1u << 9)
 (PMC_PCSR0) Peripheral Clock 9 Status More...
 
#define PMC_PCSR1_PID32   (0x1u << 0)
 (PMC_PCSR1) Peripheral Clock 32 Status More...
 
#define PMC_PCSR1_PID33   (0x1u << 1)
 (PMC_PCSR1) Peripheral Clock 33 Status More...
 
#define PMC_PCSR1_PID34   (0x1u << 2)
 (PMC_PCSR1) Peripheral Clock 34 Status More...
 
#define PMC_PCSR1_PID35   (0x1u << 3)
 (PMC_PCSR1) Peripheral Clock 35 Status More...
 
#define PMC_PCSR1_PID37   (0x1u << 5)
 (PMC_PCSR1) Peripheral Clock 37 Status More...
 
#define PMC_PCSR1_PID39   (0x1u << 7)
 (PMC_PCSR1) Peripheral Clock 39 Status More...
 
#define PMC_PCSR1_PID40   (0x1u << 8)
 (PMC_PCSR1) Peripheral Clock 40 Status More...
 
#define PMC_PCSR1_PID41   (0x1u << 9)
 (PMC_PCSR1) Peripheral Clock 41 Status More...
 
#define PMC_PCSR1_PID42   (0x1u << 10)
 (PMC_PCSR1) Peripheral Clock 42 Status More...
 
#define PMC_PCSR1_PID43   (0x1u << 11)
 (PMC_PCSR1) Peripheral Clock 43 Status More...
 
#define PMC_PCSR1_PID44   (0x1u << 12)
 (PMC_PCSR1) Peripheral Clock 44 Status More...
 
#define PMC_PCSR1_PID45   (0x1u << 13)
 (PMC_PCSR1) Peripheral Clock 45 Status More...
 
#define PMC_PCSR1_PID46   (0x1u << 14)
 (PMC_PCSR1) Peripheral Clock 46 Status More...
 
#define PMC_PCSR1_PID47   (0x1u << 15)
 (PMC_PCSR1) Peripheral Clock 47 Status More...
 
#define PMC_PCSR1_PID48   (0x1u << 16)
 (PMC_PCSR1) Peripheral Clock 48 Status More...
 
#define PMC_PCSR1_PID49   (0x1u << 17)
 (PMC_PCSR1) Peripheral Clock 49 Status More...
 
#define PMC_PCSR1_PID50   (0x1u << 18)
 (PMC_PCSR1) Peripheral Clock 50 Status More...
 
#define PMC_PCSR1_PID51   (0x1u << 19)
 (PMC_PCSR1) Peripheral Clock 51 Status More...
 
#define PMC_PCSR1_PID52   (0x1u << 20)
 (PMC_PCSR1) Peripheral Clock 52 Status More...
 
#define PMC_PCSR1_PID53   (0x1u << 21)
 (PMC_PCSR1) Peripheral Clock 53 Status More...
 
#define PMC_PCSR1_PID56   (0x1u << 24)
 (PMC_PCSR1) Peripheral Clock 56 Status More...
 
#define PMC_PCSR1_PID57   (0x1u << 25)
 (PMC_PCSR1) Peripheral Clock 57 Status More...
 
#define PMC_PCSR1_PID58   (0x1u << 26)
 (PMC_PCSR1) Peripheral Clock 58 Status More...
 
#define PMC_PCSR1_PID59   (0x1u << 27)
 (PMC_PCSR1) Peripheral Clock 59 Status More...
 
#define PMC_PCSR1_PID60   (0x1u << 28)
 (PMC_PCSR1) Peripheral Clock 60 Status More...
 
#define PMC_PMMR_PLLA_MMAX(value)   ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos)))
 
#define PMC_PMMR_PLLA_MMAX_Msk   (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos)
 (PMC_PMMR) PLLA Maximum Allowed Multiplier Value More...
 
#define PMC_PMMR_PLLA_MMAX_Pos   0
 
#define PMC_SCDR_PCK0   (0x1u << 8)
 (PMC_SCDR) Programmable Clock 0 Output Disable More...
 
#define PMC_SCDR_PCK1   (0x1u << 9)
 (PMC_SCDR) Programmable Clock 1 Output Disable More...
 
#define PMC_SCDR_PCK2   (0x1u << 10)
 (PMC_SCDR) Programmable Clock 2 Output Disable More...
 
#define PMC_SCDR_PCK3   (0x1u << 11)
 (PMC_SCDR) Programmable Clock 3 Output Disable More...
 
#define PMC_SCDR_PCK4   (0x1u << 12)
 (PMC_SCDR) Programmable Clock 4 Output Disable More...
 
#define PMC_SCDR_PCK5   (0x1u << 13)
 (PMC_SCDR) Programmable Clock 5 Output Disable More...
 
#define PMC_SCDR_PCK6   (0x1u << 14)
 (PMC_SCDR) Programmable Clock 6 Output Disable More...
 
#define PMC_SCDR_USBCLK   (0x1u << 5)
 (PMC_SCDR) Disable USB FS Clock More...
 
#define PMC_SCER_PCK0   (0x1u << 8)
 (PMC_SCER) Programmable Clock 0 Output Enable More...
 
#define PMC_SCER_PCK1   (0x1u << 9)
 (PMC_SCER) Programmable Clock 1 Output Enable More...
 
#define PMC_SCER_PCK2   (0x1u << 10)
 (PMC_SCER) Programmable Clock 2 Output Enable More...
 
#define PMC_SCER_PCK3   (0x1u << 11)
 (PMC_SCER) Programmable Clock 3 Output Enable More...
 
#define PMC_SCER_PCK4   (0x1u << 12)
 (PMC_SCER) Programmable Clock 4 Output Enable More...
 
#define PMC_SCER_PCK5   (0x1u << 13)
 (PMC_SCER) Programmable Clock 5 Output Enable More...
 
#define PMC_SCER_PCK6   (0x1u << 14)
 (PMC_SCER) Programmable Clock 6 Output Enable More...
 
#define PMC_SCER_USBCLK   (0x1u << 5)
 (PMC_SCER) Enable USB FS Clock More...
 
#define PMC_SCSR_HCLKS   (0x1u << 0)
 (PMC_SCSR) Processor Clock Status More...
 
#define PMC_SCSR_PCK0   (0x1u << 8)
 (PMC_SCSR) Programmable Clock 0 Output Status More...
 
#define PMC_SCSR_PCK1   (0x1u << 9)
 (PMC_SCSR) Programmable Clock 1 Output Status More...
 
#define PMC_SCSR_PCK2   (0x1u << 10)
 (PMC_SCSR) Programmable Clock 2 Output Status More...
 
#define PMC_SCSR_PCK3   (0x1u << 11)
 (PMC_SCSR) Programmable Clock 3 Output Status More...
 
#define PMC_SCSR_PCK4   (0x1u << 12)
 (PMC_SCSR) Programmable Clock 4 Output Status More...
 
#define PMC_SCSR_PCK5   (0x1u << 13)
 (PMC_SCSR) Programmable Clock 5 Output Status More...
 
#define PMC_SCSR_PCK6   (0x1u << 14)
 (PMC_SCSR) Programmable Clock 6 Output Status More...
 
#define PMC_SCSR_USBCLK   (0x1u << 5)
 (PMC_SCSR) USB FS Clock Status More...
 
#define PMC_SLPWK_AIPR_AIP   (0x1u << 0)
 (PMC_SLPWK_AIPR) Activity In Progress More...
 
#define PMC_SLPWK_ASR0_PID10   (0x1u << 10)
 (PMC_SLPWK_ASR0) Peripheral 10 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID11   (0x1u << 11)
 (PMC_SLPWK_ASR0) Peripheral 11 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID12   (0x1u << 12)
 (PMC_SLPWK_ASR0) Peripheral 12 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID13   (0x1u << 13)
 (PMC_SLPWK_ASR0) Peripheral 13 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID14   (0x1u << 14)
 (PMC_SLPWK_ASR0) Peripheral 14 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID15   (0x1u << 15)
 (PMC_SLPWK_ASR0) Peripheral 15 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID16   (0x1u << 16)
 (PMC_SLPWK_ASR0) Peripheral 16 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID17   (0x1u << 17)
 (PMC_SLPWK_ASR0) Peripheral 17 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID18   (0x1u << 18)
 (PMC_SLPWK_ASR0) Peripheral 18 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID19   (0x1u << 19)
 (PMC_SLPWK_ASR0) Peripheral 19 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID20   (0x1u << 20)
 (PMC_SLPWK_ASR0) Peripheral 20 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID21   (0x1u << 21)
 (PMC_SLPWK_ASR0) Peripheral 21 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID22   (0x1u << 22)
 (PMC_SLPWK_ASR0) Peripheral 22 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID23   (0x1u << 23)
 (PMC_SLPWK_ASR0) Peripheral 23 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID24   (0x1u << 24)
 (PMC_SLPWK_ASR0) Peripheral 24 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID25   (0x1u << 25)
 (PMC_SLPWK_ASR0) Peripheral 25 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID26   (0x1u << 26)
 (PMC_SLPWK_ASR0) Peripheral 26 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID27   (0x1u << 27)
 (PMC_SLPWK_ASR0) Peripheral 27 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID28   (0x1u << 28)
 (PMC_SLPWK_ASR0) Peripheral 28 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID29   (0x1u << 29)
 (PMC_SLPWK_ASR0) Peripheral 29 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID30   (0x1u << 30)
 (PMC_SLPWK_ASR0) Peripheral 30 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID31   (0x1u << 31)
 (PMC_SLPWK_ASR0) Peripheral 31 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID7   (0x1u << 7)
 (PMC_SLPWK_ASR0) Peripheral 7 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID8   (0x1u << 8)
 (PMC_SLPWK_ASR0) Peripheral 8 Activity Status More...
 
#define PMC_SLPWK_ASR0_PID9   (0x1u << 9)
 (PMC_SLPWK_ASR0) Peripheral 9 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID32   (0x1u << 0)
 (PMC_SLPWK_ASR1) Peripheral 32 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID33   (0x1u << 1)
 (PMC_SLPWK_ASR1) Peripheral 33 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID34   (0x1u << 2)
 (PMC_SLPWK_ASR1) Peripheral 34 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID35   (0x1u << 3)
 (PMC_SLPWK_ASR1) Peripheral 35 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID37   (0x1u << 5)
 (PMC_SLPWK_ASR1) Peripheral 37 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID39   (0x1u << 7)
 (PMC_SLPWK_ASR1) Peripheral 39 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID40   (0x1u << 8)
 (PMC_SLPWK_ASR1) Peripheral 40 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID41   (0x1u << 9)
 (PMC_SLPWK_ASR1) Peripheral 41 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID42   (0x1u << 10)
 (PMC_SLPWK_ASR1) Peripheral 42 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID43   (0x1u << 11)
 (PMC_SLPWK_ASR1) Peripheral 43 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID44   (0x1u << 12)
 (PMC_SLPWK_ASR1) Peripheral 44 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID45   (0x1u << 13)
 (PMC_SLPWK_ASR1) Peripheral 45 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID46   (0x1u << 14)
 (PMC_SLPWK_ASR1) Peripheral 46 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID47   (0x1u << 15)
 (PMC_SLPWK_ASR1) Peripheral 47 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID48   (0x1u << 16)
 (PMC_SLPWK_ASR1) Peripheral 48 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID49   (0x1u << 17)
 (PMC_SLPWK_ASR1) Peripheral 49 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID50   (0x1u << 18)
 (PMC_SLPWK_ASR1) Peripheral 50 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID51   (0x1u << 19)
 (PMC_SLPWK_ASR1) Peripheral 51 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID52   (0x1u << 20)
 (PMC_SLPWK_ASR1) Peripheral 52 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID53   (0x1u << 21)
 (PMC_SLPWK_ASR1) Peripheral 53 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID56   (0x1u << 24)
 (PMC_SLPWK_ASR1) Peripheral 56 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID57   (0x1u << 25)
 (PMC_SLPWK_ASR1) Peripheral 57 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID58   (0x1u << 26)
 (PMC_SLPWK_ASR1) Peripheral 58 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID59   (0x1u << 27)
 (PMC_SLPWK_ASR1) Peripheral 59 Activity Status More...
 
#define PMC_SLPWK_ASR1_PID60   (0x1u << 28)
 (PMC_SLPWK_ASR1) Peripheral 60 Activity Status More...
 
#define PMC_SLPWK_DR0_PID10   (0x1u << 10)
 (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID11   (0x1u << 11)
 (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID12   (0x1u << 12)
 (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID13   (0x1u << 13)
 (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID14   (0x1u << 14)
 (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID15   (0x1u << 15)
 (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID16   (0x1u << 16)
 (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID17   (0x1u << 17)
 (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID18   (0x1u << 18)
 (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID19   (0x1u << 19)
 (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID20   (0x1u << 20)
 (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID21   (0x1u << 21)
 (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID22   (0x1u << 22)
 (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID23   (0x1u << 23)
 (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID24   (0x1u << 24)
 (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID25   (0x1u << 25)
 (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID26   (0x1u << 26)
 (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID27   (0x1u << 27)
 (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID28   (0x1u << 28)
 (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID29   (0x1u << 29)
 (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID30   (0x1u << 30)
 (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID31   (0x1u << 31)
 (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID7   (0x1u << 7)
 (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID8   (0x1u << 8)
 (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable More...
 
#define PMC_SLPWK_DR0_PID9   (0x1u << 9)
 (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID32   (0x1u << 0)
 (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID33   (0x1u << 1)
 (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID34   (0x1u << 2)
 (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID35   (0x1u << 3)
 (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID37   (0x1u << 5)
 (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID39   (0x1u << 7)
 (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID40   (0x1u << 8)
 (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID41   (0x1u << 9)
 (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID42   (0x1u << 10)
 (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID43   (0x1u << 11)
 (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID44   (0x1u << 12)
 (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID45   (0x1u << 13)
 (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID46   (0x1u << 14)
 (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID47   (0x1u << 15)
 (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID48   (0x1u << 16)
 (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID49   (0x1u << 17)
 (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID50   (0x1u << 18)
 (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID51   (0x1u << 19)
 (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID52   (0x1u << 20)
 (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID53   (0x1u << 21)
 (PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID56   (0x1u << 24)
 (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID57   (0x1u << 25)
 (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID58   (0x1u << 26)
 (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID59   (0x1u << 27)
 (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable More...
 
#define PMC_SLPWK_DR1_PID60   (0x1u << 28)
 (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable More...
 
#define PMC_SLPWK_ER0_PID10   (0x1u << 10)
 (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID11   (0x1u << 11)
 (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID12   (0x1u << 12)
 (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID13   (0x1u << 13)
 (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID14   (0x1u << 14)
 (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID15   (0x1u << 15)
 (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID16   (0x1u << 16)
 (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID17   (0x1u << 17)
 (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID18   (0x1u << 18)
 (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID19   (0x1u << 19)
 (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID20   (0x1u << 20)
 (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID21   (0x1u << 21)
 (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID22   (0x1u << 22)
 (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID23   (0x1u << 23)
 (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID24   (0x1u << 24)
 (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID25   (0x1u << 25)
 (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID26   (0x1u << 26)
 (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID27   (0x1u << 27)
 (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID28   (0x1u << 28)
 (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID29   (0x1u << 29)
 (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID30   (0x1u << 30)
 (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID31   (0x1u << 31)
 (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID7   (0x1u << 7)
 (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID8   (0x1u << 8)
 (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable More...
 
#define PMC_SLPWK_ER0_PID9   (0x1u << 9)
 (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID32   (0x1u << 0)
 (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID33   (0x1u << 1)
 (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID34   (0x1u << 2)
 (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID35   (0x1u << 3)
 (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID37   (0x1u << 5)
 (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID39   (0x1u << 7)
 (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID40   (0x1u << 8)
 (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID41   (0x1u << 9)
 (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID42   (0x1u << 10)
 (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID43   (0x1u << 11)
 (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID44   (0x1u << 12)
 (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID45   (0x1u << 13)
 (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID46   (0x1u << 14)
 (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID47   (0x1u << 15)
 (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID48   (0x1u << 16)
 (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID49   (0x1u << 17)
 (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID50   (0x1u << 18)
 (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID51   (0x1u << 19)
 (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID52   (0x1u << 20)
 (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID53   (0x1u << 21)
 (PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID56   (0x1u << 24)
 (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID57   (0x1u << 25)
 (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID58   (0x1u << 26)
 (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID59   (0x1u << 27)
 (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable More...
 
#define PMC_SLPWK_ER1_PID60   (0x1u << 28)
 (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable More...
 
#define PMC_SLPWK_SR0_PID10   (0x1u << 10)
 (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID11   (0x1u << 11)
 (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID12   (0x1u << 12)
 (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID13   (0x1u << 13)
 (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID14   (0x1u << 14)
 (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID15   (0x1u << 15)
 (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID16   (0x1u << 16)
 (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID17   (0x1u << 17)
 (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID18   (0x1u << 18)
 (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID19   (0x1u << 19)
 (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID20   (0x1u << 20)
 (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID21   (0x1u << 21)
 (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID22   (0x1u << 22)
 (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID23   (0x1u << 23)
 (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID24   (0x1u << 24)
 (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID25   (0x1u << 25)
 (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID26   (0x1u << 26)
 (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID27   (0x1u << 27)
 (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID28   (0x1u << 28)
 (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID29   (0x1u << 29)
 (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID30   (0x1u << 30)
 (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID31   (0x1u << 31)
 (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID7   (0x1u << 7)
 (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID8   (0x1u << 8)
 (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status More...
 
#define PMC_SLPWK_SR0_PID9   (0x1u << 9)
 (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID32   (0x1u << 0)
 (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID33   (0x1u << 1)
 (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID34   (0x1u << 2)
 (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID35   (0x1u << 3)
 (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID37   (0x1u << 5)
 (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID39   (0x1u << 7)
 (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID40   (0x1u << 8)
 (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID41   (0x1u << 9)
 (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID42   (0x1u << 10)
 (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID43   (0x1u << 11)
 (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID44   (0x1u << 12)
 (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID45   (0x1u << 13)
 (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID46   (0x1u << 14)
 (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID47   (0x1u << 15)
 (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID48   (0x1u << 16)
 (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID49   (0x1u << 17)
 (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID50   (0x1u << 18)
 (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID51   (0x1u << 19)
 (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID52   (0x1u << 20)
 (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID53   (0x1u << 21)
 (PMC_SLPWK_SR1) Peripheral 53 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID56   (0x1u << 24)
 (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID57   (0x1u << 25)
 (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID58   (0x1u << 26)
 (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID59   (0x1u << 27)
 (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status More...
 
#define PMC_SLPWK_SR1_PID60   (0x1u << 28)
 (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status More...
 
#define PMC_SR_CFDEV   (0x1u << 18)
 (PMC_SR) Clock Failure Detector Event More...
 
#define PMC_SR_CFDS   (0x1u << 19)
 (PMC_SR) Clock Failure Detector Status More...
 
#define PMC_SR_FOS   (0x1u << 20)
 (PMC_SR) Clock Failure Detector Fault Output Status More...
 
#define PMC_SR_LOCKA   (0x1u << 1)
 (PMC_SR) PLLA Lock Status More...
 
#define PMC_SR_LOCKU   (0x1u << 6)
 (PMC_SR) UTMI PLL Lock Status More...
 
#define PMC_SR_MCKRDY   (0x1u << 3)
 (PMC_SR) Master Clock Status More...
 
#define PMC_SR_MOSCRCS   (0x1u << 17)
 (PMC_SR) Main On-Chip RC Oscillator Status More...
 
#define PMC_SR_MOSCSELS   (0x1u << 16)
 (PMC_SR) Main Oscillator Selection Status More...
 
#define PMC_SR_MOSCXTS   (0x1u << 0)
 (PMC_SR) Main Crystal Oscillator Status More...
 
#define PMC_SR_OSCSELS   (0x1u << 7)
 (PMC_SR) Slow Clock Oscillator Selection More...
 
#define PMC_SR_PCKRDY0   (0x1u << 8)
 (PMC_SR) Programmable Clock Ready Status More...
 
#define PMC_SR_PCKRDY1   (0x1u << 9)
 (PMC_SR) Programmable Clock Ready Status More...
 
#define PMC_SR_PCKRDY2   (0x1u << 10)
 (PMC_SR) Programmable Clock Ready Status More...
 
#define PMC_SR_PCKRDY3   (0x1u << 11)
 (PMC_SR) Programmable Clock Ready Status More...
 
#define PMC_SR_PCKRDY4   (0x1u << 12)
 (PMC_SR) Programmable Clock Ready Status More...
 
#define PMC_SR_PCKRDY5   (0x1u << 13)
 (PMC_SR) Programmable Clock Ready Status More...
 
#define PMC_SR_PCKRDY6   (0x1u << 14)
 (PMC_SR) Programmable Clock Ready Status More...
 
#define PMC_SR_XT32KERR   (0x1u << 21)
 (PMC_SR) Slow Crystal Oscillator Error More...
 
#define PMC_USB_USBDIV(value)   ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
 
#define PMC_USB_USBDIV_Msk   (0xfu << PMC_USB_USBDIV_Pos)
 (PMC_USB) Divider for USB Clock More...
 
#define PMC_USB_USBDIV_Pos   8
 
#define PMC_USB_USBS   (0x1u << 0)
 (PMC_USB) USB Input Clock Selection More...
 
#define PMC_VERSION_MFN_Msk   (0x7u << PMC_VERSION_MFN_Pos)
 (PMC_VERSION) Metal Fix Number More...
 
#define PMC_VERSION_MFN_Pos   16
 
#define PMC_VERSION_VERSION_Msk   (0xfffu << PMC_VERSION_VERSION_Pos)
 (PMC_VERSION) Version of the Hardware Module More...
 
#define PMC_VERSION_VERSION_Pos   0
 
#define PMC_WMST_KEY(value)   ((PMC_WMST_KEY_Msk & ((value) << PMC_WMST_KEY_Pos)))
 
#define PMC_WMST_KEY_Msk   (0xffu << PMC_WMST_KEY_Pos)
 (PMC_WMST) Write Access Password More...
 
#define PMC_WMST_KEY_PASSWD   (0x5Au << 24)
 (PMC_WMST) Writing any other value in this field aborts the write operation.Always reads as 0. More...
 
#define PMC_WMST_KEY_Pos   24
 
#define PMC_WMST_WMST(value)   ((PMC_WMST_WMST_Msk & ((value) << PMC_WMST_WMST_Pos)))
 
#define PMC_WMST_WMST_Msk   (0xffu << PMC_WMST_WMST_Pos)
 (PMC_WMST) Wait Mode Startup Time More...
 
#define PMC_WMST_WMST_Pos   0
 
#define PMC_WPMR_WPEN   (0x1u << 0)
 (PMC_WPMR) Write Protection Enable More...
 
#define PMC_WPMR_WPKEY(value)   ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
 
#define PMC_WPMR_WPKEY_Msk   (0xffffffu << PMC_WPMR_WPKEY_Pos)
 (PMC_WPMR) Write Protection Key More...
 
#define PMC_WPMR_WPKEY_PASSWD   (0x504D43u << 8)
 (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. More...
 
#define PMC_WPMR_WPKEY_Pos   8
 
#define PMC_WPSR_WPVS   (0x1u << 0)
 (PMC_WPSR) Write Protection Violation Status More...
 
#define PMC_WPSR_WPVSRC_Msk   (0xffffu << PMC_WPSR_WPVSRC_Pos)
 (PMC_WPSR) Write Protection Violation Source More...
 
#define PMC_WPSR_WPVSRC_Pos   8
 

Detailed Description

SOFTWARE API DEFINITION FOR Power Management Controller

Macro Definition Documentation

◆ CKGR_MCFR_CCSS

#define CKGR_MCFR_CCSS   (0x1u << 24)

(CKGR_MCFR) Counter Clock Source Selection

Definition at line 235 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MCFR_MAINF

#define CKGR_MCFR_MAINF (   value)    ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)))

Definition at line 232 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MCFR_MAINF_Msk

#define CKGR_MCFR_MAINF_Msk   (0xffffu << CKGR_MCFR_MAINF_Pos)

(CKGR_MCFR) Main Clock Frequency

Definition at line 231 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MCFR_MAINF_Pos

#define CKGR_MCFR_MAINF_Pos   0

Definition at line 230 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MCFR_MAINFRDY

#define CKGR_MCFR_MAINFRDY   (0x1u << 16)

(CKGR_MCFR) Main Clock Frequency Measure Ready

Definition at line 233 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MCFR_RCMEAS

#define CKGR_MCFR_RCMEAS   (0x1u << 20)

(CKGR_MCFR) RC Oscillator Frequency Measure (write-only)

Definition at line 234 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_CFDEN

#define CKGR_MOR_CFDEN   (0x1u << 25)

(CKGR_MOR) Clock Failure Detector Enable

Definition at line 227 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_KEY

#define CKGR_MOR_KEY (   value)    ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))

Definition at line 224 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_KEY_Msk

#define CKGR_MOR_KEY_Msk   (0xffu << CKGR_MOR_KEY_Pos)

(CKGR_MOR) Write Access Password

Definition at line 223 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_KEY_PASSWD

#define CKGR_MOR_KEY_PASSWD   (0x37u << 16)

(CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0.

Definition at line 225 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_KEY_Pos

#define CKGR_MOR_KEY_Pos   16

Definition at line 222 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_MOSCRCEN

#define CKGR_MOR_MOSCRCEN   (0x1u << 3)

(CKGR_MOR) Main On-Chip RC Oscillator Enable

Definition at line 212 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_MOSCRCF

#define CKGR_MOR_MOSCRCF (   value)    ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos)))

Definition at line 215 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_MOSCRCF_12_MHz

#define CKGR_MOR_MOSCRCF_12_MHz   (0x2u << 4)

(CKGR_MOR) Fast RC oscillator frequency is at 12 MHz

Definition at line 218 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_MOSCRCF_4_MHz

#define CKGR_MOR_MOSCRCF_4_MHz   (0x0u << 4)

(CKGR_MOR) Fast RC oscillator frequency is at 4 MHz (default)

Definition at line 216 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_MOSCRCF_8_MHz

#define CKGR_MOR_MOSCRCF_8_MHz   (0x1u << 4)

(CKGR_MOR) Fast RC oscillator frequency is at 8 MHz

Definition at line 217 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_MOSCRCF_Msk

#define CKGR_MOR_MOSCRCF_Msk   (0x7u << CKGR_MOR_MOSCRCF_Pos)

(CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection

Definition at line 214 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_MOSCRCF_Pos

#define CKGR_MOR_MOSCRCF_Pos   4

Definition at line 213 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_MOSCSEL

#define CKGR_MOR_MOSCSEL   (0x1u << 24)

(CKGR_MOR) Main Oscillator Selection

Definition at line 226 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_MOSCXTBY

#define CKGR_MOR_MOSCXTBY   (0x1u << 1)

(CKGR_MOR) Main Crystal Oscillator Bypass

Definition at line 210 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_MOSCXTEN

#define CKGR_MOR_MOSCXTEN   (0x1u << 0)

(CKGR_MOR) Main Crystal Oscillator Enable

Definition at line 209 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_MOSCXTST

#define CKGR_MOR_MOSCXTST (   value)    ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))

Definition at line 221 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_MOSCXTST_Msk

#define CKGR_MOR_MOSCXTST_Msk   (0xffu << CKGR_MOR_MOSCXTST_Pos)

(CKGR_MOR) Main Crystal Oscillator Start-up Time

Definition at line 220 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_MOSCXTST_Pos

#define CKGR_MOR_MOSCXTST_Pos   8

Definition at line 219 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_WAITMODE

#define CKGR_MOR_WAITMODE   (0x1u << 2)

(CKGR_MOR) Wait Mode Command (Write-only)

Definition at line 211 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_MOR_XT32KFME

#define CKGR_MOR_XT32KFME   (0x1u << 26)

(CKGR_MOR) Slow Crystal Oscillator Frequency Monitoring Enable

Definition at line 228 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_PLLAR_DIVA

#define CKGR_PLLAR_DIVA (   value)    ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))

Definition at line 239 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_PLLAR_DIVA_0

#define CKGR_PLLAR_DIVA_0   (0x0u << 0)

(CKGR_PLLAR) Divider output is 0 and PLLA is disabled.

Definition at line 240 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_PLLAR_DIVA_BYPASS

#define CKGR_PLLAR_DIVA_BYPASS   (0x1u << 0)

(CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled.

Definition at line 241 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_PLLAR_DIVA_Msk

#define CKGR_PLLAR_DIVA_Msk   (0xffu << CKGR_PLLAR_DIVA_Pos)

(CKGR_PLLAR) PLLA Front End Divider

Definition at line 238 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_PLLAR_DIVA_Pos

#define CKGR_PLLAR_DIVA_Pos   0

Definition at line 237 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_PLLAR_MULA

#define CKGR_PLLAR_MULA (   value)    ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))

Definition at line 247 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_PLLAR_MULA_Msk

#define CKGR_PLLAR_MULA_Msk   (0x7ffu << CKGR_PLLAR_MULA_Pos)

(CKGR_PLLAR) PLLA Multiplier

Definition at line 246 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_PLLAR_MULA_Pos

#define CKGR_PLLAR_MULA_Pos   16

Definition at line 245 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_PLLAR_ONE

#define CKGR_PLLAR_ONE   (0x1u << 29)

(CKGR_PLLAR) Must Be Set to 1

Definition at line 248 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_PLLAR_PLLACOUNT

#define CKGR_PLLAR_PLLACOUNT (   value)    ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))

Definition at line 244 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_PLLAR_PLLACOUNT_Msk

#define CKGR_PLLAR_PLLACOUNT_Msk   (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos)

(CKGR_PLLAR) PLLA Counter

Definition at line 243 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_PLLAR_PLLACOUNT_Pos

#define CKGR_PLLAR_PLLACOUNT_Pos   8

Definition at line 242 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_UCKR_UPLLCOUNT

#define CKGR_UCKR_UPLLCOUNT (   value)    ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))

Definition at line 207 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_UCKR_UPLLCOUNT_Msk

#define CKGR_UCKR_UPLLCOUNT_Msk   (0xfu << CKGR_UCKR_UPLLCOUNT_Pos)

(CKGR_UCKR) UTMI PLL Start-up Time

Definition at line 206 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_UCKR_UPLLCOUNT_Pos

#define CKGR_UCKR_UPLLCOUNT_Pos   20

Definition at line 205 of file utils/cmsis/same70/include/component/pmc.h.

◆ CKGR_UCKR_UPLLEN

#define CKGR_UCKR_UPLLEN   (0x1u << 16)

(CKGR_UCKR) UTMI PLL Enable

Definition at line 204 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_APLLACR_BIAS

#define PMC_APLLACR_BIAS (   value)    ((PMC_APLLACR_BIAS_Msk & ((value) << PMC_APLLACR_BIAS_Pos)))

Definition at line 761 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_APLLACR_BIAS_Msk

#define PMC_APLLACR_BIAS_Msk   (0x3u << PMC_APLLACR_BIAS_Pos)

(PMC_APLLACR) Bias Voltage Selection

Definition at line 760 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_APLLACR_BIAS_Pos

#define PMC_APLLACR_BIAS_Pos   8

Definition at line 759 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_APLLACR_DCOFLTSEL

#define PMC_APLLACR_DCOFLTSEL (   value)    ((PMC_APLLACR_DCOFLTSEL_Msk & ((value) << PMC_APLLACR_DCOFLTSEL_Pos)))

Definition at line 755 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_APLLACR_DCOFLTSEL_Msk

#define PMC_APLLACR_DCOFLTSEL_Msk   (0xfu << PMC_APLLACR_DCOFLTSEL_Pos)

(PMC_APLLACR) DCO Filter Selection

Definition at line 754 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_APLLACR_DCOFLTSEL_Pos

#define PMC_APLLACR_DCOFLTSEL_Pos   0

Definition at line 753 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_APLLACR_FLTSEL

#define PMC_APLLACR_FLTSEL (   value)    ((PMC_APLLACR_FLTSEL_Msk & ((value) << PMC_APLLACR_FLTSEL_Pos)))

Definition at line 758 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_APLLACR_FLTSEL_Msk

#define PMC_APLLACR_FLTSEL_Msk   (0xfu << PMC_APLLACR_FLTSEL_Pos)

(PMC_APLLACR) PLL Filter Selection

Definition at line 757 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_APLLACR_FLTSEL_Pos

#define PMC_APLLACR_FLTSEL_Pos   4

Definition at line 756 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FOCR_FOCLR

#define PMC_FOCR_FOCLR   (0x1u << 0)

(PMC_FOCR) Fault Output Clear

Definition at line 406 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FFLPM

#define PMC_FSMR_FFLPM   (0x1u << 23)

(PMC_FSMR) Force Flash Low-power Mode

Definition at line 387 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FLPM

#define PMC_FSMR_FLPM (   value)    ((PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos)))

Definition at line 383 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN

#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN   (0x1u << 21)

(PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode

Definition at line 385 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FLPM_FLASH_IDLE

#define PMC_FSMR_FLPM_FLASH_IDLE   (0x2u << 21)

(PMC_FSMR) Idle mode

Definition at line 386 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FLPM_FLASH_STANDBY

#define PMC_FSMR_FLPM_FLASH_STANDBY   (0x0u << 21)

(PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode

Definition at line 384 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FLPM_Msk

#define PMC_FSMR_FLPM_Msk   (0x3u << PMC_FSMR_FLPM_Pos)

(PMC_FSMR) Flash Low-power Mode

Definition at line 382 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FLPM_Pos

#define PMC_FSMR_FLPM_Pos   21

Definition at line 381 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FSTT0

#define PMC_FSMR_FSTT0   (0x1u << 0)

(PMC_FSMR) Fast Startup Input Enable 0

Definition at line 361 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FSTT1

#define PMC_FSMR_FSTT1   (0x1u << 1)

(PMC_FSMR) Fast Startup Input Enable 1

Definition at line 362 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FSTT10

#define PMC_FSMR_FSTT10   (0x1u << 10)

(PMC_FSMR) Fast Startup Input Enable 10

Definition at line 371 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FSTT11

#define PMC_FSMR_FSTT11   (0x1u << 11)

(PMC_FSMR) Fast Startup Input Enable 11

Definition at line 372 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FSTT12

#define PMC_FSMR_FSTT12   (0x1u << 12)

(PMC_FSMR) Fast Startup Input Enable 12

Definition at line 373 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FSTT13

#define PMC_FSMR_FSTT13   (0x1u << 13)

(PMC_FSMR) Fast Startup Input Enable 13

Definition at line 374 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FSTT14

#define PMC_FSMR_FSTT14   (0x1u << 14)

(PMC_FSMR) Fast Startup Input Enable 14

Definition at line 375 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FSTT15

#define PMC_FSMR_FSTT15   (0x1u << 15)

(PMC_FSMR) Fast Startup Input Enable 15

Definition at line 376 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FSTT2

#define PMC_FSMR_FSTT2   (0x1u << 2)

(PMC_FSMR) Fast Startup Input Enable 2

Definition at line 363 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FSTT3

#define PMC_FSMR_FSTT3   (0x1u << 3)

(PMC_FSMR) Fast Startup Input Enable 3

Definition at line 364 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FSTT4

#define PMC_FSMR_FSTT4   (0x1u << 4)

(PMC_FSMR) Fast Startup Input Enable 4

Definition at line 365 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FSTT5

#define PMC_FSMR_FSTT5   (0x1u << 5)

(PMC_FSMR) Fast Startup Input Enable 5

Definition at line 366 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FSTT6

#define PMC_FSMR_FSTT6   (0x1u << 6)

(PMC_FSMR) Fast Startup Input Enable 6

Definition at line 367 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FSTT7

#define PMC_FSMR_FSTT7   (0x1u << 7)

(PMC_FSMR) Fast Startup Input Enable 7

Definition at line 368 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FSTT8

#define PMC_FSMR_FSTT8   (0x1u << 8)

(PMC_FSMR) Fast Startup Input Enable 8

Definition at line 369 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_FSTT9

#define PMC_FSMR_FSTT9   (0x1u << 9)

(PMC_FSMR) Fast Startup Input Enable 9

Definition at line 370 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_LPM

#define PMC_FSMR_LPM   (0x1u << 20)

(PMC_FSMR) Low-power Mode

Definition at line 380 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_RTCAL

#define PMC_FSMR_RTCAL   (0x1u << 17)

(PMC_FSMR) RTC Alarm Enable

Definition at line 378 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_RTTAL

#define PMC_FSMR_RTTAL   (0x1u << 16)

(PMC_FSMR) RTT Alarm Enable

Definition at line 377 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSMR_USBAL

#define PMC_FSMR_USBAL   (0x1u << 18)

(PMC_FSMR) USB Alarm Enable

Definition at line 379 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSPR_FSTP0

#define PMC_FSPR_FSTP0   (0x1u << 0)

(PMC_FSPR) Fast Startup Input Polarity 0

Definition at line 389 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSPR_FSTP1

#define PMC_FSPR_FSTP1   (0x1u << 1)

(PMC_FSPR) Fast Startup Input Polarity 1

Definition at line 390 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSPR_FSTP10

#define PMC_FSPR_FSTP10   (0x1u << 10)

(PMC_FSPR) Fast Startup Input Polarity 10

Definition at line 399 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSPR_FSTP11

#define PMC_FSPR_FSTP11   (0x1u << 11)

(PMC_FSPR) Fast Startup Input Polarity 11

Definition at line 400 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSPR_FSTP12

#define PMC_FSPR_FSTP12   (0x1u << 12)

(PMC_FSPR) Fast Startup Input Polarity 12

Definition at line 401 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSPR_FSTP13

#define PMC_FSPR_FSTP13   (0x1u << 13)

(PMC_FSPR) Fast Startup Input Polarity 13

Definition at line 402 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSPR_FSTP14

#define PMC_FSPR_FSTP14   (0x1u << 14)

(PMC_FSPR) Fast Startup Input Polarity 14

Definition at line 403 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSPR_FSTP15

#define PMC_FSPR_FSTP15   (0x1u << 15)

(PMC_FSPR) Fast Startup Input Polarity 15

Definition at line 404 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSPR_FSTP2

#define PMC_FSPR_FSTP2   (0x1u << 2)

(PMC_FSPR) Fast Startup Input Polarity 2

Definition at line 391 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSPR_FSTP3

#define PMC_FSPR_FSTP3   (0x1u << 3)

(PMC_FSPR) Fast Startup Input Polarity 3

Definition at line 392 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSPR_FSTP4

#define PMC_FSPR_FSTP4   (0x1u << 4)

(PMC_FSPR) Fast Startup Input Polarity 4

Definition at line 393 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSPR_FSTP5

#define PMC_FSPR_FSTP5   (0x1u << 5)

(PMC_FSPR) Fast Startup Input Polarity 5

Definition at line 394 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSPR_FSTP6

#define PMC_FSPR_FSTP6   (0x1u << 6)

(PMC_FSPR) Fast Startup Input Polarity 6

Definition at line 395 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSPR_FSTP7

#define PMC_FSPR_FSTP7   (0x1u << 7)

(PMC_FSPR) Fast Startup Input Polarity 7

Definition at line 396 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSPR_FSTP8

#define PMC_FSPR_FSTP8   (0x1u << 8)

(PMC_FSPR) Fast Startup Input Polarity 8

Definition at line 397 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_FSPR_FSTP9

#define PMC_FSPR_FSTP9   (0x1u << 9)

(PMC_FSPR) Fast Startup Input Polarity 9

Definition at line 398 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IDR_CFDEV

#define PMC_IDR_CFDEV   (0x1u << 18)

(PMC_IDR) Clock Failure Detector Event Interrupt Disable

Definition at line 323 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IDR_LOCKA

#define PMC_IDR_LOCKA   (0x1u << 1)

(PMC_IDR) PLLA Lock Interrupt Disable

Definition at line 311 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IDR_LOCKU

#define PMC_IDR_LOCKU   (0x1u << 6)

(PMC_IDR) UTMI PLL Lock Interrupt Disable

Definition at line 313 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IDR_MCKRDY

#define PMC_IDR_MCKRDY   (0x1u << 3)

(PMC_IDR) Master Clock Ready Interrupt Disable

Definition at line 312 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IDR_MOSCRCS

#define PMC_IDR_MOSCRCS   (0x1u << 17)

(PMC_IDR) Main On-Chip RC Status Interrupt Disable

Definition at line 322 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IDR_MOSCSELS

#define PMC_IDR_MOSCSELS   (0x1u << 16)

(PMC_IDR) Main Oscillator Selection Status Interrupt Disable

Definition at line 321 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IDR_MOSCXTS

#define PMC_IDR_MOSCXTS   (0x1u << 0)

(PMC_IDR) Main Crystal Oscillator Status Interrupt Disable

Definition at line 310 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IDR_PCKRDY0

#define PMC_IDR_PCKRDY0   (0x1u << 8)

(PMC_IDR) Programmable Clock Ready 0 Interrupt Disable

Definition at line 314 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IDR_PCKRDY1

#define PMC_IDR_PCKRDY1   (0x1u << 9)

(PMC_IDR) Programmable Clock Ready 1 Interrupt Disable

Definition at line 315 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IDR_PCKRDY2

#define PMC_IDR_PCKRDY2   (0x1u << 10)

(PMC_IDR) Programmable Clock Ready 2 Interrupt Disable

Definition at line 316 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IDR_PCKRDY3

#define PMC_IDR_PCKRDY3   (0x1u << 11)

(PMC_IDR) Programmable Clock Ready 3 Interrupt Disable

Definition at line 317 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IDR_PCKRDY4

#define PMC_IDR_PCKRDY4   (0x1u << 12)

(PMC_IDR) Programmable Clock Ready 4 Interrupt Disable

Definition at line 318 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IDR_PCKRDY5

#define PMC_IDR_PCKRDY5   (0x1u << 13)

(PMC_IDR) Programmable Clock Ready 5 Interrupt Disable

Definition at line 319 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IDR_PCKRDY6

#define PMC_IDR_PCKRDY6   (0x1u << 14)

(PMC_IDR) Programmable Clock Ready 6 Interrupt Disable

Definition at line 320 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IDR_XT32KERR

#define PMC_IDR_XT32KERR   (0x1u << 21)

(PMC_IDR) Slow Crystal Oscillator Error Interrupt Disable

Definition at line 324 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IER_CFDEV

#define PMC_IER_CFDEV   (0x1u << 18)

(PMC_IER) Clock Failure Detector Event Interrupt Enable

Definition at line 307 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IER_LOCKA

#define PMC_IER_LOCKA   (0x1u << 1)

(PMC_IER) PLLA Lock Interrupt Enable

Definition at line 295 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IER_LOCKU

#define PMC_IER_LOCKU   (0x1u << 6)

(PMC_IER) UTMI PLL Lock Interrupt Enable

Definition at line 297 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IER_MCKRDY

#define PMC_IER_MCKRDY   (0x1u << 3)

(PMC_IER) Master Clock Ready Interrupt Enable

Definition at line 296 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IER_MOSCRCS

#define PMC_IER_MOSCRCS   (0x1u << 17)

(PMC_IER) Main On-Chip RC Status Interrupt Enable

Definition at line 306 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IER_MOSCSELS

#define PMC_IER_MOSCSELS   (0x1u << 16)

(PMC_IER) Main Oscillator Selection Status Interrupt Enable

Definition at line 305 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IER_MOSCXTS

#define PMC_IER_MOSCXTS   (0x1u << 0)

(PMC_IER) Main Crystal Oscillator Status Interrupt Enable

Definition at line 294 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IER_PCKRDY0

#define PMC_IER_PCKRDY0   (0x1u << 8)

(PMC_IER) Programmable Clock Ready 0 Interrupt Enable

Definition at line 298 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IER_PCKRDY1

#define PMC_IER_PCKRDY1   (0x1u << 9)

(PMC_IER) Programmable Clock Ready 1 Interrupt Enable

Definition at line 299 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IER_PCKRDY2

#define PMC_IER_PCKRDY2   (0x1u << 10)

(PMC_IER) Programmable Clock Ready 2 Interrupt Enable

Definition at line 300 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IER_PCKRDY3

#define PMC_IER_PCKRDY3   (0x1u << 11)

(PMC_IER) Programmable Clock Ready 3 Interrupt Enable

Definition at line 301 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IER_PCKRDY4

#define PMC_IER_PCKRDY4   (0x1u << 12)

(PMC_IER) Programmable Clock Ready 4 Interrupt Enable

Definition at line 302 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IER_PCKRDY5

#define PMC_IER_PCKRDY5   (0x1u << 13)

(PMC_IER) Programmable Clock Ready 5 Interrupt Enable

Definition at line 303 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IER_PCKRDY6

#define PMC_IER_PCKRDY6   (0x1u << 14)

(PMC_IER) Programmable Clock Ready 6 Interrupt Enable

Definition at line 304 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IER_XT32KERR

#define PMC_IER_XT32KERR   (0x1u << 21)

(PMC_IER) Slow Crystal Oscillator Error Interrupt Enable

Definition at line 308 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IMR_CFDEV

#define PMC_IMR_CFDEV   (0x1u << 18)

(PMC_IMR) Clock Failure Detector Event Interrupt Mask

Definition at line 358 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IMR_LOCKA

#define PMC_IMR_LOCKA   (0x1u << 1)

(PMC_IMR) PLLA Lock Interrupt Mask

Definition at line 346 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IMR_LOCKU

#define PMC_IMR_LOCKU   (0x1u << 6)

(PMC_IMR) UTMI PLL Lock Interrupt Mask

Definition at line 348 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IMR_MCKRDY

#define PMC_IMR_MCKRDY   (0x1u << 3)

(PMC_IMR) Master Clock Ready Interrupt Mask

Definition at line 347 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IMR_MOSCRCS

#define PMC_IMR_MOSCRCS   (0x1u << 17)

(PMC_IMR) Main On-Chip RC Status Interrupt Mask

Definition at line 357 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IMR_MOSCSELS

#define PMC_IMR_MOSCSELS   (0x1u << 16)

(PMC_IMR) Main Oscillator Selection Status Interrupt Mask

Definition at line 356 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IMR_MOSCXTS

#define PMC_IMR_MOSCXTS   (0x1u << 0)

(PMC_IMR) Main Crystal Oscillator Status Interrupt Mask

Definition at line 345 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IMR_PCKRDY0

#define PMC_IMR_PCKRDY0   (0x1u << 8)

(PMC_IMR) Programmable Clock Ready 0 Interrupt Mask

Definition at line 349 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IMR_PCKRDY1

#define PMC_IMR_PCKRDY1   (0x1u << 9)

(PMC_IMR) Programmable Clock Ready 1 Interrupt Mask

Definition at line 350 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IMR_PCKRDY2

#define PMC_IMR_PCKRDY2   (0x1u << 10)

(PMC_IMR) Programmable Clock Ready 2 Interrupt Mask

Definition at line 351 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IMR_PCKRDY3

#define PMC_IMR_PCKRDY3   (0x1u << 11)

(PMC_IMR) Programmable Clock Ready 3 Interrupt Mask

Definition at line 352 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IMR_PCKRDY4

#define PMC_IMR_PCKRDY4   (0x1u << 12)

(PMC_IMR) Programmable Clock Ready 4 Interrupt Mask

Definition at line 353 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IMR_PCKRDY5

#define PMC_IMR_PCKRDY5   (0x1u << 13)

(PMC_IMR) Programmable Clock Ready 5 Interrupt Mask

Definition at line 354 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IMR_PCKRDY6

#define PMC_IMR_PCKRDY6   (0x1u << 14)

(PMC_IMR) Programmable Clock Ready 6 Interrupt Mask

Definition at line 355 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_IMR_XT32KERR

#define PMC_IMR_XT32KERR   (0x1u << 21)

(PMC_IMR) Slow Crystal Oscillator Error Interrupt Mask

Definition at line 359 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_CSS

#define PMC_MCKR_CSS (   value)    ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos)))

Definition at line 252 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_CSS_MAIN_CLK

#define PMC_MCKR_CSS_MAIN_CLK   (0x1u << 0)

(PMC_MCKR) Main Clock is selected

Definition at line 254 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_CSS_Msk

#define PMC_MCKR_CSS_Msk   (0x3u << PMC_MCKR_CSS_Pos)

(PMC_MCKR) Master Clock Source Selection

Definition at line 251 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_CSS_PLLA_CLK

#define PMC_MCKR_CSS_PLLA_CLK   (0x2u << 0)

(PMC_MCKR) PLLA Clock is selected

Definition at line 255 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_CSS_Pos

#define PMC_MCKR_CSS_Pos   0

Definition at line 250 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_CSS_SLOW_CLK

#define PMC_MCKR_CSS_SLOW_CLK   (0x0u << 0)

(PMC_MCKR) Slow Clock is selected

Definition at line 253 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_CSS_UPLL_CLK

#define PMC_MCKR_CSS_UPLL_CLK   (0x3u << 0)

(PMC_MCKR) Divided UPLL Clock is selected

Definition at line 256 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_MDIV

#define PMC_MCKR_MDIV (   value)    ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos)))

Definition at line 270 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_MDIV_EQ_PCK

#define PMC_MCKR_MDIV_EQ_PCK   (0x0u << 8)

(PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1.

Definition at line 271 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_MDIV_Msk

#define PMC_MCKR_MDIV_Msk   (0x3u << PMC_MCKR_MDIV_Pos)

(PMC_MCKR) Master Clock Division

Definition at line 269 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_MDIV_PCK_DIV2

#define PMC_MCKR_MDIV_PCK_DIV2   (0x1u << 8)

(PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2.

Definition at line 272 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_MDIV_PCK_DIV3

#define PMC_MCKR_MDIV_PCK_DIV3   (0x3u << 8)

(PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3.

Definition at line 274 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_MDIV_PCK_DIV4

#define PMC_MCKR_MDIV_PCK_DIV4   (0x2u << 8)

(PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4.

Definition at line 273 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_MDIV_Pos

#define PMC_MCKR_MDIV_Pos   8

Definition at line 268 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_PRES

#define PMC_MCKR_PRES (   value)    ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos)))

Definition at line 259 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_PRES_CLK_1

#define PMC_MCKR_PRES_CLK_1   (0x0u << 4)

(PMC_MCKR) Selected clock

Definition at line 260 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_PRES_CLK_16

#define PMC_MCKR_PRES_CLK_16   (0x4u << 4)

(PMC_MCKR) Selected clock divided by 16

Definition at line 264 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_PRES_CLK_2

#define PMC_MCKR_PRES_CLK_2   (0x1u << 4)

(PMC_MCKR) Selected clock divided by 2

Definition at line 261 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_PRES_CLK_3

#define PMC_MCKR_PRES_CLK_3   (0x7u << 4)

(PMC_MCKR) Selected clock divided by 3

Definition at line 267 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_PRES_CLK_32

#define PMC_MCKR_PRES_CLK_32   (0x5u << 4)

(PMC_MCKR) Selected clock divided by 32

Definition at line 265 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_PRES_CLK_4

#define PMC_MCKR_PRES_CLK_4   (0x2u << 4)

(PMC_MCKR) Selected clock divided by 4

Definition at line 262 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_PRES_CLK_64

#define PMC_MCKR_PRES_CLK_64   (0x6u << 4)

(PMC_MCKR) Selected clock divided by 64

Definition at line 266 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_PRES_CLK_8

#define PMC_MCKR_PRES_CLK_8   (0x3u << 4)

(PMC_MCKR) Selected clock divided by 8

Definition at line 263 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_PRES_Msk

#define PMC_MCKR_PRES_Msk   (0x7u << PMC_MCKR_PRES_Pos)

(PMC_MCKR) Processor Clock Prescaler

Definition at line 258 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_PRES_Pos

#define PMC_MCKR_PRES_Pos   4

Definition at line 257 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_MCKR_UPLLDIV2

#define PMC_MCKR_UPLLDIV2   (0x1u << 13)

(PMC_MCKR) UPLL Divisor by 2

Definition at line 275 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_OCR_CAL12

#define PMC_OCR_CAL12 (   value)    ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))

Definition at line 536 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_OCR_CAL12_Msk

#define PMC_OCR_CAL12_Msk   (0x7fu << PMC_OCR_CAL12_Pos)

(PMC_OCR) RC Oscillator Calibration bits for 12 MHz

Definition at line 535 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_OCR_CAL12_Pos

#define PMC_OCR_CAL12_Pos   16

Definition at line 534 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_OCR_CAL4

#define PMC_OCR_CAL4 (   value)    ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))

Definition at line 528 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_OCR_CAL4_Msk

#define PMC_OCR_CAL4_Msk   (0x7fu << PMC_OCR_CAL4_Pos)

(PMC_OCR) RC Oscillator Calibration bits for 4 MHz

Definition at line 527 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_OCR_CAL4_Pos

#define PMC_OCR_CAL4_Pos   0

Definition at line 526 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_OCR_CAL8

#define PMC_OCR_CAL8 (   value)    ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))

Definition at line 532 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_OCR_CAL8_Msk

#define PMC_OCR_CAL8_Msk   (0x7fu << PMC_OCR_CAL8_Pos)

(PMC_OCR) RC Oscillator Calibration bits for 8 MHz

Definition at line 531 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_OCR_CAL8_Pos

#define PMC_OCR_CAL8_Pos   8

Definition at line 530 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_OCR_SEL12

#define PMC_OCR_SEL12   (0x1u << 23)

(PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz

Definition at line 537 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_OCR_SEL4

#define PMC_OCR_SEL4   (0x1u << 7)

(PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz

Definition at line 529 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_OCR_SEL8

#define PMC_OCR_SEL8   (0x1u << 15)

(PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz

Definition at line 533 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID10

#define PMC_PCDR0_PID10   (0x1u << 10)

(PMC_PCDR0) Peripheral Clock 10 Disable

Definition at line 155 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID11

#define PMC_PCDR0_PID11   (0x1u << 11)

(PMC_PCDR0) Peripheral Clock 11 Disable

Definition at line 156 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID12

#define PMC_PCDR0_PID12   (0x1u << 12)

(PMC_PCDR0) Peripheral Clock 12 Disable

Definition at line 157 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID13

#define PMC_PCDR0_PID13   (0x1u << 13)

(PMC_PCDR0) Peripheral Clock 13 Disable

Definition at line 158 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID14

#define PMC_PCDR0_PID14   (0x1u << 14)

(PMC_PCDR0) Peripheral Clock 14 Disable

Definition at line 159 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID15

#define PMC_PCDR0_PID15   (0x1u << 15)

(PMC_PCDR0) Peripheral Clock 15 Disable

Definition at line 160 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID16

#define PMC_PCDR0_PID16   (0x1u << 16)

(PMC_PCDR0) Peripheral Clock 16 Disable

Definition at line 161 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID17

#define PMC_PCDR0_PID17   (0x1u << 17)

(PMC_PCDR0) Peripheral Clock 17 Disable

Definition at line 162 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID18

#define PMC_PCDR0_PID18   (0x1u << 18)

(PMC_PCDR0) Peripheral Clock 18 Disable

Definition at line 163 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID19

#define PMC_PCDR0_PID19   (0x1u << 19)

(PMC_PCDR0) Peripheral Clock 19 Disable

Definition at line 164 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID20

#define PMC_PCDR0_PID20   (0x1u << 20)

(PMC_PCDR0) Peripheral Clock 20 Disable

Definition at line 165 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID21

#define PMC_PCDR0_PID21   (0x1u << 21)

(PMC_PCDR0) Peripheral Clock 21 Disable

Definition at line 166 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID22

#define PMC_PCDR0_PID22   (0x1u << 22)

(PMC_PCDR0) Peripheral Clock 22 Disable

Definition at line 167 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID23

#define PMC_PCDR0_PID23   (0x1u << 23)

(PMC_PCDR0) Peripheral Clock 23 Disable

Definition at line 168 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID24

#define PMC_PCDR0_PID24   (0x1u << 24)

(PMC_PCDR0) Peripheral Clock 24 Disable

Definition at line 169 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID25

#define PMC_PCDR0_PID25   (0x1u << 25)

(PMC_PCDR0) Peripheral Clock 25 Disable

Definition at line 170 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID26

#define PMC_PCDR0_PID26   (0x1u << 26)

(PMC_PCDR0) Peripheral Clock 26 Disable

Definition at line 171 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID27

#define PMC_PCDR0_PID27   (0x1u << 27)

(PMC_PCDR0) Peripheral Clock 27 Disable

Definition at line 172 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID28

#define PMC_PCDR0_PID28   (0x1u << 28)

(PMC_PCDR0) Peripheral Clock 28 Disable

Definition at line 173 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID29

#define PMC_PCDR0_PID29   (0x1u << 29)

(PMC_PCDR0) Peripheral Clock 29 Disable

Definition at line 174 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID30

#define PMC_PCDR0_PID30   (0x1u << 30)

(PMC_PCDR0) Peripheral Clock 30 Disable

Definition at line 175 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID31

#define PMC_PCDR0_PID31   (0x1u << 31)

(PMC_PCDR0) Peripheral Clock 31 Disable

Definition at line 176 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID7

#define PMC_PCDR0_PID7   (0x1u << 7)

(PMC_PCDR0) Peripheral Clock 7 Disable

Definition at line 152 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID8

#define PMC_PCDR0_PID8   (0x1u << 8)

(PMC_PCDR0) Peripheral Clock 8 Disable

Definition at line 153 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR0_PID9

#define PMC_PCDR0_PID9   (0x1u << 9)

(PMC_PCDR0) Peripheral Clock 9 Disable

Definition at line 154 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID32

#define PMC_PCDR1_PID32   (0x1u << 0)

(PMC_PCDR1) Peripheral Clock 32 Disable

Definition at line 449 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID33

#define PMC_PCDR1_PID33   (0x1u << 1)

(PMC_PCDR1) Peripheral Clock 33 Disable

Definition at line 450 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID34

#define PMC_PCDR1_PID34   (0x1u << 2)

(PMC_PCDR1) Peripheral Clock 34 Disable

Definition at line 451 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID35

#define PMC_PCDR1_PID35   (0x1u << 3)

(PMC_PCDR1) Peripheral Clock 35 Disable

Definition at line 452 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID37

#define PMC_PCDR1_PID37   (0x1u << 5)

(PMC_PCDR1) Peripheral Clock 37 Disable

Definition at line 453 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID39

#define PMC_PCDR1_PID39   (0x1u << 7)

(PMC_PCDR1) Peripheral Clock 39 Disable

Definition at line 454 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID40

#define PMC_PCDR1_PID40   (0x1u << 8)

(PMC_PCDR1) Peripheral Clock 40 Disable

Definition at line 455 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID41

#define PMC_PCDR1_PID41   (0x1u << 9)

(PMC_PCDR1) Peripheral Clock 41 Disable

Definition at line 456 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID42

#define PMC_PCDR1_PID42   (0x1u << 10)

(PMC_PCDR1) Peripheral Clock 42 Disable

Definition at line 457 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID43

#define PMC_PCDR1_PID43   (0x1u << 11)

(PMC_PCDR1) Peripheral Clock 43 Disable

Definition at line 458 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID44

#define PMC_PCDR1_PID44   (0x1u << 12)

(PMC_PCDR1) Peripheral Clock 44 Disable

Definition at line 459 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID45

#define PMC_PCDR1_PID45   (0x1u << 13)

(PMC_PCDR1) Peripheral Clock 45 Disable

Definition at line 460 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID46

#define PMC_PCDR1_PID46   (0x1u << 14)

(PMC_PCDR1) Peripheral Clock 46 Disable

Definition at line 461 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID47

#define PMC_PCDR1_PID47   (0x1u << 15)

(PMC_PCDR1) Peripheral Clock 47 Disable

Definition at line 462 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID48

#define PMC_PCDR1_PID48   (0x1u << 16)

(PMC_PCDR1) Peripheral Clock 48 Disable

Definition at line 463 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID49

#define PMC_PCDR1_PID49   (0x1u << 17)

(PMC_PCDR1) Peripheral Clock 49 Disable

Definition at line 464 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID50

#define PMC_PCDR1_PID50   (0x1u << 18)

(PMC_PCDR1) Peripheral Clock 50 Disable

Definition at line 465 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID51

#define PMC_PCDR1_PID51   (0x1u << 19)

(PMC_PCDR1) Peripheral Clock 51 Disable

Definition at line 466 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID52

#define PMC_PCDR1_PID52   (0x1u << 20)

(PMC_PCDR1) Peripheral Clock 52 Disable

Definition at line 467 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID53

#define PMC_PCDR1_PID53   (0x1u << 21)

(PMC_PCDR1) Peripheral Clock 53 Disable

Definition at line 468 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID56

#define PMC_PCDR1_PID56   (0x1u << 24)

(PMC_PCDR1) Peripheral Clock 56 Disable

Definition at line 469 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID57

#define PMC_PCDR1_PID57   (0x1u << 25)

(PMC_PCDR1) Peripheral Clock 57 Disable

Definition at line 470 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID58

#define PMC_PCDR1_PID58   (0x1u << 26)

(PMC_PCDR1) Peripheral Clock 58 Disable

Definition at line 471 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID59

#define PMC_PCDR1_PID59   (0x1u << 27)

(PMC_PCDR1) Peripheral Clock 59 Disable

Definition at line 472 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCDR1_PID60

#define PMC_PCDR1_PID60   (0x1u << 28)

(PMC_PCDR1) Peripheral Clock 60 Disable

Definition at line 473 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID10

#define PMC_PCER0_PID10   (0x1u << 10)

(PMC_PCER0) Peripheral Clock 10 Enable

Definition at line 129 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID11

#define PMC_PCER0_PID11   (0x1u << 11)

(PMC_PCER0) Peripheral Clock 11 Enable

Definition at line 130 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID12

#define PMC_PCER0_PID12   (0x1u << 12)

(PMC_PCER0) Peripheral Clock 12 Enable

Definition at line 131 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID13

#define PMC_PCER0_PID13   (0x1u << 13)

(PMC_PCER0) Peripheral Clock 13 Enable

Definition at line 132 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID14

#define PMC_PCER0_PID14   (0x1u << 14)

(PMC_PCER0) Peripheral Clock 14 Enable

Definition at line 133 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID15

#define PMC_PCER0_PID15   (0x1u << 15)

(PMC_PCER0) Peripheral Clock 15 Enable

Definition at line 134 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID16

#define PMC_PCER0_PID16   (0x1u << 16)

(PMC_PCER0) Peripheral Clock 16 Enable

Definition at line 135 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID17

#define PMC_PCER0_PID17   (0x1u << 17)

(PMC_PCER0) Peripheral Clock 17 Enable

Definition at line 136 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID18

#define PMC_PCER0_PID18   (0x1u << 18)

(PMC_PCER0) Peripheral Clock 18 Enable

Definition at line 137 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID19

#define PMC_PCER0_PID19   (0x1u << 19)

(PMC_PCER0) Peripheral Clock 19 Enable

Definition at line 138 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID20

#define PMC_PCER0_PID20   (0x1u << 20)

(PMC_PCER0) Peripheral Clock 20 Enable

Definition at line 139 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID21

#define PMC_PCER0_PID21   (0x1u << 21)

(PMC_PCER0) Peripheral Clock 21 Enable

Definition at line 140 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID22

#define PMC_PCER0_PID22   (0x1u << 22)

(PMC_PCER0) Peripheral Clock 22 Enable

Definition at line 141 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID23

#define PMC_PCER0_PID23   (0x1u << 23)

(PMC_PCER0) Peripheral Clock 23 Enable

Definition at line 142 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID24

#define PMC_PCER0_PID24   (0x1u << 24)

(PMC_PCER0) Peripheral Clock 24 Enable

Definition at line 143 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID25

#define PMC_PCER0_PID25   (0x1u << 25)

(PMC_PCER0) Peripheral Clock 25 Enable

Definition at line 144 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID26

#define PMC_PCER0_PID26   (0x1u << 26)

(PMC_PCER0) Peripheral Clock 26 Enable

Definition at line 145 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID27

#define PMC_PCER0_PID27   (0x1u << 27)

(PMC_PCER0) Peripheral Clock 27 Enable

Definition at line 146 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID28

#define PMC_PCER0_PID28   (0x1u << 28)

(PMC_PCER0) Peripheral Clock 28 Enable

Definition at line 147 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID29

#define PMC_PCER0_PID29   (0x1u << 29)

(PMC_PCER0) Peripheral Clock 29 Enable

Definition at line 148 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID30

#define PMC_PCER0_PID30   (0x1u << 30)

(PMC_PCER0) Peripheral Clock 30 Enable

Definition at line 149 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID31

#define PMC_PCER0_PID31   (0x1u << 31)

(PMC_PCER0) Peripheral Clock 31 Enable

Definition at line 150 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID7

#define PMC_PCER0_PID7   (0x1u << 7)

(PMC_PCER0) Peripheral Clock 7 Enable

Definition at line 126 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID8

#define PMC_PCER0_PID8   (0x1u << 8)

(PMC_PCER0) Peripheral Clock 8 Enable

Definition at line 127 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER0_PID9

#define PMC_PCER0_PID9   (0x1u << 9)

(PMC_PCER0) Peripheral Clock 9 Enable

Definition at line 128 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID32

#define PMC_PCER1_PID32   (0x1u << 0)

(PMC_PCER1) Peripheral Clock 32 Enable

Definition at line 423 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID33

#define PMC_PCER1_PID33   (0x1u << 1)

(PMC_PCER1) Peripheral Clock 33 Enable

Definition at line 424 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID34

#define PMC_PCER1_PID34   (0x1u << 2)

(PMC_PCER1) Peripheral Clock 34 Enable

Definition at line 425 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID35

#define PMC_PCER1_PID35   (0x1u << 3)

(PMC_PCER1) Peripheral Clock 35 Enable

Definition at line 426 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID37

#define PMC_PCER1_PID37   (0x1u << 5)

(PMC_PCER1) Peripheral Clock 37 Enable

Definition at line 427 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID39

#define PMC_PCER1_PID39   (0x1u << 7)

(PMC_PCER1) Peripheral Clock 39 Enable

Definition at line 428 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID40

#define PMC_PCER1_PID40   (0x1u << 8)

(PMC_PCER1) Peripheral Clock 40 Enable

Definition at line 429 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID41

#define PMC_PCER1_PID41   (0x1u << 9)

(PMC_PCER1) Peripheral Clock 41 Enable

Definition at line 430 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID42

#define PMC_PCER1_PID42   (0x1u << 10)

(PMC_PCER1) Peripheral Clock 42 Enable

Definition at line 431 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID43

#define PMC_PCER1_PID43   (0x1u << 11)

(PMC_PCER1) Peripheral Clock 43 Enable

Definition at line 432 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID44

#define PMC_PCER1_PID44   (0x1u << 12)

(PMC_PCER1) Peripheral Clock 44 Enable

Definition at line 433 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID45

#define PMC_PCER1_PID45   (0x1u << 13)

(PMC_PCER1) Peripheral Clock 45 Enable

Definition at line 434 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID46

#define PMC_PCER1_PID46   (0x1u << 14)

(PMC_PCER1) Peripheral Clock 46 Enable

Definition at line 435 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID47

#define PMC_PCER1_PID47   (0x1u << 15)

(PMC_PCER1) Peripheral Clock 47 Enable

Definition at line 436 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID48

#define PMC_PCER1_PID48   (0x1u << 16)

(PMC_PCER1) Peripheral Clock 48 Enable

Definition at line 437 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID49

#define PMC_PCER1_PID49   (0x1u << 17)

(PMC_PCER1) Peripheral Clock 49 Enable

Definition at line 438 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID50

#define PMC_PCER1_PID50   (0x1u << 18)

(PMC_PCER1) Peripheral Clock 50 Enable

Definition at line 439 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID51

#define PMC_PCER1_PID51   (0x1u << 19)

(PMC_PCER1) Peripheral Clock 51 Enable

Definition at line 440 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID52

#define PMC_PCER1_PID52   (0x1u << 20)

(PMC_PCER1) Peripheral Clock 52 Enable

Definition at line 441 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID53

#define PMC_PCER1_PID53   (0x1u << 21)

(PMC_PCER1) Peripheral Clock 53 Enable

Definition at line 442 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID56

#define PMC_PCER1_PID56   (0x1u << 24)

(PMC_PCER1) Peripheral Clock 56 Enable

Definition at line 443 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID57

#define PMC_PCER1_PID57   (0x1u << 25)

(PMC_PCER1) Peripheral Clock 57 Enable

Definition at line 444 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID58

#define PMC_PCER1_PID58   (0x1u << 26)

(PMC_PCER1) Peripheral Clock 58 Enable

Definition at line 445 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID59

#define PMC_PCER1_PID59   (0x1u << 27)

(PMC_PCER1) Peripheral Clock 59 Enable

Definition at line 446 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCER1_PID60

#define PMC_PCER1_PID60   (0x1u << 28)

(PMC_PCER1) Peripheral Clock 60 Enable

Definition at line 447 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCK_CSS

#define PMC_PCK_CSS (   value)    ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos)))

Definition at line 284 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCK_CSS_MAIN_CLK

#define PMC_PCK_CSS_MAIN_CLK   (0x1u << 0)

(PMC_PCK[8]) Main Clock is selected

Definition at line 286 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCK_CSS_MCK

#define PMC_PCK_CSS_MCK   (0x4u << 0)

(PMC_PCK[8]) Master Clock is selected

Definition at line 289 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCK_CSS_Msk

#define PMC_PCK_CSS_Msk   (0x7u << PMC_PCK_CSS_Pos)

(PMC_PCK[8]) Programmable Clock Source Selection

Definition at line 283 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCK_CSS_PLLA_CLK

#define PMC_PCK_CSS_PLLA_CLK   (0x2u << 0)

(PMC_PCK[8]) PLLA Clock is selected

Definition at line 287 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCK_CSS_Pos

#define PMC_PCK_CSS_Pos   0

Definition at line 282 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCK_CSS_SLOW_CLK

#define PMC_PCK_CSS_SLOW_CLK   (0x0u << 0)

(PMC_PCK[8]) Slow Clock is selected

Definition at line 285 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCK_CSS_UPLL_CLK

#define PMC_PCK_CSS_UPLL_CLK   (0x3u << 0)

(PMC_PCK[8]) Divided UPLL Clock is selected

Definition at line 288 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCK_PRES

#define PMC_PCK_PRES (   value)    ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)))

Definition at line 292 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCK_PRES_Msk

#define PMC_PCK_PRES_Msk   (0xffu << PMC_PCK_PRES_Pos)

(PMC_PCK[8]) Programmable Clock Prescaler

Definition at line 291 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCK_PRES_Pos

#define PMC_PCK_PRES_Pos   4

Definition at line 290 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_CMD

#define PMC_PCR_CMD   (0x1u << 12)

(PMC_PCR) Command

Definition at line 512 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_DIV

#define PMC_PCR_DIV (   value)    ((PMC_PCR_DIV_Msk & ((value) << PMC_PCR_DIV_Pos)))

Definition at line 515 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_DIV_Msk

#define PMC_PCR_DIV_Msk   (0x3u << PMC_PCR_DIV_Pos)

(PMC_PCR) Divisor Value

Definition at line 514 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_DIV_PERIPH_DIV2_MCK

#define PMC_PCR_DIV_PERIPH_DIV2_MCK   (0x1u << 16)

(PMC_PCR) Peripheral clock is MCK/2

Definition at line 517 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_DIV_PERIPH_DIV4_MCK

#define PMC_PCR_DIV_PERIPH_DIV4_MCK   (0x2u << 16)

(PMC_PCR) Peripheral clock is MCK/4

Definition at line 518 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_DIV_PERIPH_DIV8_MCK

#define PMC_PCR_DIV_PERIPH_DIV8_MCK   (0x3u << 16)

(PMC_PCR) Peripheral clock is MCK/8

Definition at line 519 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_DIV_PERIPH_DIV_MCK

#define PMC_PCR_DIV_PERIPH_DIV_MCK   (0x0u << 16)

(PMC_PCR) Peripheral clock is MCK

Definition at line 516 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_DIV_Pos

#define PMC_PCR_DIV_Pos   16

Definition at line 513 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_EN

#define PMC_PCR_EN   (0x1u << 28)

(PMC_PCR) Enable

Definition at line 523 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_GCLKCSS

#define PMC_PCR_GCLKCSS (   value)    ((PMC_PCR_GCLKCSS_Msk & ((value) << PMC_PCR_GCLKCSS_Pos)))

Definition at line 506 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_GCLKCSS_MAIN_CLK

#define PMC_PCR_GCLKCSS_MAIN_CLK   (0x1u << 8)

(PMC_PCR) Main clock is selected

Definition at line 508 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_GCLKCSS_MCK_CLK

#define PMC_PCR_GCLKCSS_MCK_CLK   (0x4u << 8)

(PMC_PCR) Master Clock is selected

Definition at line 511 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_GCLKCSS_Msk

#define PMC_PCR_GCLKCSS_Msk   (0x7u << PMC_PCR_GCLKCSS_Pos)

(PMC_PCR) Generic Clock Source Selection

Definition at line 505 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_GCLKCSS_PLLA_CLK

#define PMC_PCR_GCLKCSS_PLLA_CLK   (0x2u << 8)

(PMC_PCR) PLLACK is selected

Definition at line 509 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_GCLKCSS_Pos

#define PMC_PCR_GCLKCSS_Pos   8

Definition at line 504 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_GCLKCSS_SLOW_CLK

#define PMC_PCR_GCLKCSS_SLOW_CLK   (0x0u << 8)

(PMC_PCR) Slow clock is selected

Definition at line 507 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_GCLKCSS_UPLL_CLK

#define PMC_PCR_GCLKCSS_UPLL_CLK   (0x3u << 8)

(PMC_PCR) UPLL Clock is selected

Definition at line 510 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_GCLKDIV

#define PMC_PCR_GCLKDIV (   value)    ((PMC_PCR_GCLKDIV_Msk & ((value) << PMC_PCR_GCLKDIV_Pos)))

Definition at line 522 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_GCLKDIV_Msk

#define PMC_PCR_GCLKDIV_Msk   (0xffu << PMC_PCR_GCLKDIV_Pos)

(PMC_PCR) Generic Clock Division Ratio

Definition at line 521 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_GCLKDIV_Pos

#define PMC_PCR_GCLKDIV_Pos   20

Definition at line 520 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_GCLKEN

#define PMC_PCR_GCLKEN   (0x1u << 29)

(PMC_PCR) Generic Clock Enable

Definition at line 524 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_PID

#define PMC_PCR_PID (   value)    ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)))

Definition at line 503 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_PID_Msk

#define PMC_PCR_PID_Msk   (0x7fu << PMC_PCR_PID_Pos)

(PMC_PCR) Peripheral ID

Definition at line 502 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCR_PID_Pos

#define PMC_PCR_PID_Pos   0

Definition at line 501 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID10

#define PMC_PCSR0_PID10   (0x1u << 10)

(PMC_PCSR0) Peripheral Clock 10 Status

Definition at line 181 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID11

#define PMC_PCSR0_PID11   (0x1u << 11)

(PMC_PCSR0) Peripheral Clock 11 Status

Definition at line 182 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID12

#define PMC_PCSR0_PID12   (0x1u << 12)

(PMC_PCSR0) Peripheral Clock 12 Status

Definition at line 183 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID13

#define PMC_PCSR0_PID13   (0x1u << 13)

(PMC_PCSR0) Peripheral Clock 13 Status

Definition at line 184 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID14

#define PMC_PCSR0_PID14   (0x1u << 14)

(PMC_PCSR0) Peripheral Clock 14 Status

Definition at line 185 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID15

#define PMC_PCSR0_PID15   (0x1u << 15)

(PMC_PCSR0) Peripheral Clock 15 Status

Definition at line 186 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID16

#define PMC_PCSR0_PID16   (0x1u << 16)

(PMC_PCSR0) Peripheral Clock 16 Status

Definition at line 187 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID17

#define PMC_PCSR0_PID17   (0x1u << 17)

(PMC_PCSR0) Peripheral Clock 17 Status

Definition at line 188 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID18

#define PMC_PCSR0_PID18   (0x1u << 18)

(PMC_PCSR0) Peripheral Clock 18 Status

Definition at line 189 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID19

#define PMC_PCSR0_PID19   (0x1u << 19)

(PMC_PCSR0) Peripheral Clock 19 Status

Definition at line 190 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID20

#define PMC_PCSR0_PID20   (0x1u << 20)

(PMC_PCSR0) Peripheral Clock 20 Status

Definition at line 191 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID21

#define PMC_PCSR0_PID21   (0x1u << 21)

(PMC_PCSR0) Peripheral Clock 21 Status

Definition at line 192 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID22

#define PMC_PCSR0_PID22   (0x1u << 22)

(PMC_PCSR0) Peripheral Clock 22 Status

Definition at line 193 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID23

#define PMC_PCSR0_PID23   (0x1u << 23)

(PMC_PCSR0) Peripheral Clock 23 Status

Definition at line 194 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID24

#define PMC_PCSR0_PID24   (0x1u << 24)

(PMC_PCSR0) Peripheral Clock 24 Status

Definition at line 195 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID25

#define PMC_PCSR0_PID25   (0x1u << 25)

(PMC_PCSR0) Peripheral Clock 25 Status

Definition at line 196 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID26

#define PMC_PCSR0_PID26   (0x1u << 26)

(PMC_PCSR0) Peripheral Clock 26 Status

Definition at line 197 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID27

#define PMC_PCSR0_PID27   (0x1u << 27)

(PMC_PCSR0) Peripheral Clock 27 Status

Definition at line 198 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID28

#define PMC_PCSR0_PID28   (0x1u << 28)

(PMC_PCSR0) Peripheral Clock 28 Status

Definition at line 199 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID29

#define PMC_PCSR0_PID29   (0x1u << 29)

(PMC_PCSR0) Peripheral Clock 29 Status

Definition at line 200 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID30

#define PMC_PCSR0_PID30   (0x1u << 30)

(PMC_PCSR0) Peripheral Clock 30 Status

Definition at line 201 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID31

#define PMC_PCSR0_PID31   (0x1u << 31)

(PMC_PCSR0) Peripheral Clock 31 Status

Definition at line 202 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID7

#define PMC_PCSR0_PID7   (0x1u << 7)

(PMC_PCSR0) Peripheral Clock 7 Status

Definition at line 178 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID8

#define PMC_PCSR0_PID8   (0x1u << 8)

(PMC_PCSR0) Peripheral Clock 8 Status

Definition at line 179 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR0_PID9

#define PMC_PCSR0_PID9   (0x1u << 9)

(PMC_PCSR0) Peripheral Clock 9 Status

Definition at line 180 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID32

#define PMC_PCSR1_PID32   (0x1u << 0)

(PMC_PCSR1) Peripheral Clock 32 Status

Definition at line 475 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID33

#define PMC_PCSR1_PID33   (0x1u << 1)

(PMC_PCSR1) Peripheral Clock 33 Status

Definition at line 476 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID34

#define PMC_PCSR1_PID34   (0x1u << 2)

(PMC_PCSR1) Peripheral Clock 34 Status

Definition at line 477 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID35

#define PMC_PCSR1_PID35   (0x1u << 3)

(PMC_PCSR1) Peripheral Clock 35 Status

Definition at line 478 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID37

#define PMC_PCSR1_PID37   (0x1u << 5)

(PMC_PCSR1) Peripheral Clock 37 Status

Definition at line 479 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID39

#define PMC_PCSR1_PID39   (0x1u << 7)

(PMC_PCSR1) Peripheral Clock 39 Status

Definition at line 480 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID40

#define PMC_PCSR1_PID40   (0x1u << 8)

(PMC_PCSR1) Peripheral Clock 40 Status

Definition at line 481 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID41

#define PMC_PCSR1_PID41   (0x1u << 9)

(PMC_PCSR1) Peripheral Clock 41 Status

Definition at line 482 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID42

#define PMC_PCSR1_PID42   (0x1u << 10)

(PMC_PCSR1) Peripheral Clock 42 Status

Definition at line 483 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID43

#define PMC_PCSR1_PID43   (0x1u << 11)

(PMC_PCSR1) Peripheral Clock 43 Status

Definition at line 484 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID44

#define PMC_PCSR1_PID44   (0x1u << 12)

(PMC_PCSR1) Peripheral Clock 44 Status

Definition at line 485 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID45

#define PMC_PCSR1_PID45   (0x1u << 13)

(PMC_PCSR1) Peripheral Clock 45 Status

Definition at line 486 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID46

#define PMC_PCSR1_PID46   (0x1u << 14)

(PMC_PCSR1) Peripheral Clock 46 Status

Definition at line 487 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID47

#define PMC_PCSR1_PID47   (0x1u << 15)

(PMC_PCSR1) Peripheral Clock 47 Status

Definition at line 488 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID48

#define PMC_PCSR1_PID48   (0x1u << 16)

(PMC_PCSR1) Peripheral Clock 48 Status

Definition at line 489 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID49

#define PMC_PCSR1_PID49   (0x1u << 17)

(PMC_PCSR1) Peripheral Clock 49 Status

Definition at line 490 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID50

#define PMC_PCSR1_PID50   (0x1u << 18)

(PMC_PCSR1) Peripheral Clock 50 Status

Definition at line 491 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID51

#define PMC_PCSR1_PID51   (0x1u << 19)

(PMC_PCSR1) Peripheral Clock 51 Status

Definition at line 492 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID52

#define PMC_PCSR1_PID52   (0x1u << 20)

(PMC_PCSR1) Peripheral Clock 52 Status

Definition at line 493 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID53

#define PMC_PCSR1_PID53   (0x1u << 21)

(PMC_PCSR1) Peripheral Clock 53 Status

Definition at line 494 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID56

#define PMC_PCSR1_PID56   (0x1u << 24)

(PMC_PCSR1) Peripheral Clock 56 Status

Definition at line 495 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID57

#define PMC_PCSR1_PID57   (0x1u << 25)

(PMC_PCSR1) Peripheral Clock 57 Status

Definition at line 496 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID58

#define PMC_PCSR1_PID58   (0x1u << 26)

(PMC_PCSR1) Peripheral Clock 58 Status

Definition at line 497 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID59

#define PMC_PCSR1_PID59   (0x1u << 27)

(PMC_PCSR1) Peripheral Clock 59 Status

Definition at line 498 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PCSR1_PID60

#define PMC_PCSR1_PID60   (0x1u << 28)

(PMC_PCSR1) Peripheral Clock 60 Status

Definition at line 499 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PMMR_PLLA_MMAX

#define PMC_PMMR_PLLA_MMAX (   value)    ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos)))

Definition at line 645 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PMMR_PLLA_MMAX_Msk

#define PMC_PMMR_PLLA_MMAX_Msk   (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos)

(PMC_PMMR) PLLA Maximum Allowed Multiplier Value

Definition at line 644 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_PMMR_PLLA_MMAX_Pos

#define PMC_PMMR_PLLA_MMAX_Pos   0

Definition at line 643 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCDR_PCK0

#define PMC_SCDR_PCK0   (0x1u << 8)

(PMC_SCDR) Programmable Clock 0 Output Disable

Definition at line 108 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCDR_PCK1

#define PMC_SCDR_PCK1   (0x1u << 9)

(PMC_SCDR) Programmable Clock 1 Output Disable

Definition at line 109 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCDR_PCK2

#define PMC_SCDR_PCK2   (0x1u << 10)

(PMC_SCDR) Programmable Clock 2 Output Disable

Definition at line 110 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCDR_PCK3

#define PMC_SCDR_PCK3   (0x1u << 11)

(PMC_SCDR) Programmable Clock 3 Output Disable

Definition at line 111 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCDR_PCK4

#define PMC_SCDR_PCK4   (0x1u << 12)

(PMC_SCDR) Programmable Clock 4 Output Disable

Definition at line 112 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCDR_PCK5

#define PMC_SCDR_PCK5   (0x1u << 13)

(PMC_SCDR) Programmable Clock 5 Output Disable

Definition at line 113 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCDR_PCK6

#define PMC_SCDR_PCK6   (0x1u << 14)

(PMC_SCDR) Programmable Clock 6 Output Disable

Definition at line 114 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCDR_USBCLK

#define PMC_SCDR_USBCLK   (0x1u << 5)

(PMC_SCDR) Disable USB FS Clock

Definition at line 107 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCER_PCK0

#define PMC_SCER_PCK0   (0x1u << 8)

(PMC_SCER) Programmable Clock 0 Output Enable

Definition at line 99 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCER_PCK1

#define PMC_SCER_PCK1   (0x1u << 9)

(PMC_SCER) Programmable Clock 1 Output Enable

Definition at line 100 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCER_PCK2

#define PMC_SCER_PCK2   (0x1u << 10)

(PMC_SCER) Programmable Clock 2 Output Enable

Definition at line 101 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCER_PCK3

#define PMC_SCER_PCK3   (0x1u << 11)

(PMC_SCER) Programmable Clock 3 Output Enable

Definition at line 102 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCER_PCK4

#define PMC_SCER_PCK4   (0x1u << 12)

(PMC_SCER) Programmable Clock 4 Output Enable

Definition at line 103 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCER_PCK5

#define PMC_SCER_PCK5   (0x1u << 13)

(PMC_SCER) Programmable Clock 5 Output Enable

Definition at line 104 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCER_PCK6

#define PMC_SCER_PCK6   (0x1u << 14)

(PMC_SCER) Programmable Clock 6 Output Enable

Definition at line 105 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCER_USBCLK

#define PMC_SCER_USBCLK   (0x1u << 5)

(PMC_SCER) Enable USB FS Clock

Definition at line 98 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCSR_HCLKS

#define PMC_SCSR_HCLKS   (0x1u << 0)

(PMC_SCSR) Processor Clock Status

Definition at line 116 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCSR_PCK0

#define PMC_SCSR_PCK0   (0x1u << 8)

(PMC_SCSR) Programmable Clock 0 Output Status

Definition at line 118 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCSR_PCK1

#define PMC_SCSR_PCK1   (0x1u << 9)

(PMC_SCSR) Programmable Clock 1 Output Status

Definition at line 119 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCSR_PCK2

#define PMC_SCSR_PCK2   (0x1u << 10)

(PMC_SCSR) Programmable Clock 2 Output Status

Definition at line 120 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCSR_PCK3

#define PMC_SCSR_PCK3   (0x1u << 11)

(PMC_SCSR) Programmable Clock 3 Output Status

Definition at line 121 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCSR_PCK4

#define PMC_SCSR_PCK4   (0x1u << 12)

(PMC_SCSR) Programmable Clock 4 Output Status

Definition at line 122 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCSR_PCK5

#define PMC_SCSR_PCK5   (0x1u << 13)

(PMC_SCSR) Programmable Clock 5 Output Status

Definition at line 123 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCSR_PCK6

#define PMC_SCSR_PCK6   (0x1u << 14)

(PMC_SCSR) Programmable Clock 6 Output Status

Definition at line 124 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SCSR_USBCLK

#define PMC_SCSR_USBCLK   (0x1u << 5)

(PMC_SCSR) USB FS Clock Status

Definition at line 117 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_AIPR_AIP

#define PMC_SLPWK_AIPR_AIP   (0x1u << 0)

(PMC_SLPWK_AIPR) Activity In Progress

Definition at line 751 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID10

#define PMC_SLPWK_ASR0_PID10   (0x1u << 10)

(PMC_SLPWK_ASR0) Peripheral 10 Activity Status

Definition at line 620 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID11

#define PMC_SLPWK_ASR0_PID11   (0x1u << 11)

(PMC_SLPWK_ASR0) Peripheral 11 Activity Status

Definition at line 621 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID12

#define PMC_SLPWK_ASR0_PID12   (0x1u << 12)

(PMC_SLPWK_ASR0) Peripheral 12 Activity Status

Definition at line 622 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID13

#define PMC_SLPWK_ASR0_PID13   (0x1u << 13)

(PMC_SLPWK_ASR0) Peripheral 13 Activity Status

Definition at line 623 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID14

#define PMC_SLPWK_ASR0_PID14   (0x1u << 14)

(PMC_SLPWK_ASR0) Peripheral 14 Activity Status

Definition at line 624 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID15

#define PMC_SLPWK_ASR0_PID15   (0x1u << 15)

(PMC_SLPWK_ASR0) Peripheral 15 Activity Status

Definition at line 625 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID16

#define PMC_SLPWK_ASR0_PID16   (0x1u << 16)

(PMC_SLPWK_ASR0) Peripheral 16 Activity Status

Definition at line 626 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID17

#define PMC_SLPWK_ASR0_PID17   (0x1u << 17)

(PMC_SLPWK_ASR0) Peripheral 17 Activity Status

Definition at line 627 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID18

#define PMC_SLPWK_ASR0_PID18   (0x1u << 18)

(PMC_SLPWK_ASR0) Peripheral 18 Activity Status

Definition at line 628 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID19

#define PMC_SLPWK_ASR0_PID19   (0x1u << 19)

(PMC_SLPWK_ASR0) Peripheral 19 Activity Status

Definition at line 629 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID20

#define PMC_SLPWK_ASR0_PID20   (0x1u << 20)

(PMC_SLPWK_ASR0) Peripheral 20 Activity Status

Definition at line 630 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID21

#define PMC_SLPWK_ASR0_PID21   (0x1u << 21)

(PMC_SLPWK_ASR0) Peripheral 21 Activity Status

Definition at line 631 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID22

#define PMC_SLPWK_ASR0_PID22   (0x1u << 22)

(PMC_SLPWK_ASR0) Peripheral 22 Activity Status

Definition at line 632 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID23

#define PMC_SLPWK_ASR0_PID23   (0x1u << 23)

(PMC_SLPWK_ASR0) Peripheral 23 Activity Status

Definition at line 633 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID24

#define PMC_SLPWK_ASR0_PID24   (0x1u << 24)

(PMC_SLPWK_ASR0) Peripheral 24 Activity Status

Definition at line 634 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID25

#define PMC_SLPWK_ASR0_PID25   (0x1u << 25)

(PMC_SLPWK_ASR0) Peripheral 25 Activity Status

Definition at line 635 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID26

#define PMC_SLPWK_ASR0_PID26   (0x1u << 26)

(PMC_SLPWK_ASR0) Peripheral 26 Activity Status

Definition at line 636 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID27

#define PMC_SLPWK_ASR0_PID27   (0x1u << 27)

(PMC_SLPWK_ASR0) Peripheral 27 Activity Status

Definition at line 637 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID28

#define PMC_SLPWK_ASR0_PID28   (0x1u << 28)

(PMC_SLPWK_ASR0) Peripheral 28 Activity Status

Definition at line 638 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID29

#define PMC_SLPWK_ASR0_PID29   (0x1u << 29)

(PMC_SLPWK_ASR0) Peripheral 29 Activity Status

Definition at line 639 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID30

#define PMC_SLPWK_ASR0_PID30   (0x1u << 30)

(PMC_SLPWK_ASR0) Peripheral 30 Activity Status

Definition at line 640 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID31

#define PMC_SLPWK_ASR0_PID31   (0x1u << 31)

(PMC_SLPWK_ASR0) Peripheral 31 Activity Status

Definition at line 641 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID7

#define PMC_SLPWK_ASR0_PID7   (0x1u << 7)

(PMC_SLPWK_ASR0) Peripheral 7 Activity Status

Definition at line 617 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID8

#define PMC_SLPWK_ASR0_PID8   (0x1u << 8)

(PMC_SLPWK_ASR0) Peripheral 8 Activity Status

Definition at line 618 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR0_PID9

#define PMC_SLPWK_ASR0_PID9   (0x1u << 9)

(PMC_SLPWK_ASR0) Peripheral 9 Activity Status

Definition at line 619 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID32

#define PMC_SLPWK_ASR1_PID32   (0x1u << 0)

(PMC_SLPWK_ASR1) Peripheral 32 Activity Status

Definition at line 725 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID33

#define PMC_SLPWK_ASR1_PID33   (0x1u << 1)

(PMC_SLPWK_ASR1) Peripheral 33 Activity Status

Definition at line 726 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID34

#define PMC_SLPWK_ASR1_PID34   (0x1u << 2)

(PMC_SLPWK_ASR1) Peripheral 34 Activity Status

Definition at line 727 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID35

#define PMC_SLPWK_ASR1_PID35   (0x1u << 3)

(PMC_SLPWK_ASR1) Peripheral 35 Activity Status

Definition at line 728 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID37

#define PMC_SLPWK_ASR1_PID37   (0x1u << 5)

(PMC_SLPWK_ASR1) Peripheral 37 Activity Status

Definition at line 729 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID39

#define PMC_SLPWK_ASR1_PID39   (0x1u << 7)

(PMC_SLPWK_ASR1) Peripheral 39 Activity Status

Definition at line 730 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID40

#define PMC_SLPWK_ASR1_PID40   (0x1u << 8)

(PMC_SLPWK_ASR1) Peripheral 40 Activity Status

Definition at line 731 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID41

#define PMC_SLPWK_ASR1_PID41   (0x1u << 9)

(PMC_SLPWK_ASR1) Peripheral 41 Activity Status

Definition at line 732 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID42

#define PMC_SLPWK_ASR1_PID42   (0x1u << 10)

(PMC_SLPWK_ASR1) Peripheral 42 Activity Status

Definition at line 733 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID43

#define PMC_SLPWK_ASR1_PID43   (0x1u << 11)

(PMC_SLPWK_ASR1) Peripheral 43 Activity Status

Definition at line 734 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID44

#define PMC_SLPWK_ASR1_PID44   (0x1u << 12)

(PMC_SLPWK_ASR1) Peripheral 44 Activity Status

Definition at line 735 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID45

#define PMC_SLPWK_ASR1_PID45   (0x1u << 13)

(PMC_SLPWK_ASR1) Peripheral 45 Activity Status

Definition at line 736 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID46

#define PMC_SLPWK_ASR1_PID46   (0x1u << 14)

(PMC_SLPWK_ASR1) Peripheral 46 Activity Status

Definition at line 737 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID47

#define PMC_SLPWK_ASR1_PID47   (0x1u << 15)

(PMC_SLPWK_ASR1) Peripheral 47 Activity Status

Definition at line 738 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID48

#define PMC_SLPWK_ASR1_PID48   (0x1u << 16)

(PMC_SLPWK_ASR1) Peripheral 48 Activity Status

Definition at line 739 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID49

#define PMC_SLPWK_ASR1_PID49   (0x1u << 17)

(PMC_SLPWK_ASR1) Peripheral 49 Activity Status

Definition at line 740 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID50

#define PMC_SLPWK_ASR1_PID50   (0x1u << 18)

(PMC_SLPWK_ASR1) Peripheral 50 Activity Status

Definition at line 741 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID51

#define PMC_SLPWK_ASR1_PID51   (0x1u << 19)

(PMC_SLPWK_ASR1) Peripheral 51 Activity Status

Definition at line 742 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID52

#define PMC_SLPWK_ASR1_PID52   (0x1u << 20)

(PMC_SLPWK_ASR1) Peripheral 52 Activity Status

Definition at line 743 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID53

#define PMC_SLPWK_ASR1_PID53   (0x1u << 21)

(PMC_SLPWK_ASR1) Peripheral 53 Activity Status

Definition at line 744 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID56

#define PMC_SLPWK_ASR1_PID56   (0x1u << 24)

(PMC_SLPWK_ASR1) Peripheral 56 Activity Status

Definition at line 745 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID57

#define PMC_SLPWK_ASR1_PID57   (0x1u << 25)

(PMC_SLPWK_ASR1) Peripheral 57 Activity Status

Definition at line 746 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID58

#define PMC_SLPWK_ASR1_PID58   (0x1u << 26)

(PMC_SLPWK_ASR1) Peripheral 58 Activity Status

Definition at line 747 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID59

#define PMC_SLPWK_ASR1_PID59   (0x1u << 27)

(PMC_SLPWK_ASR1) Peripheral 59 Activity Status

Definition at line 748 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ASR1_PID60

#define PMC_SLPWK_ASR1_PID60   (0x1u << 28)

(PMC_SLPWK_ASR1) Peripheral 60 Activity Status

Definition at line 749 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID10

#define PMC_SLPWK_DR0_PID10   (0x1u << 10)

(PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable

Definition at line 568 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID11

#define PMC_SLPWK_DR0_PID11   (0x1u << 11)

(PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable

Definition at line 569 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID12

#define PMC_SLPWK_DR0_PID12   (0x1u << 12)

(PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable

Definition at line 570 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID13

#define PMC_SLPWK_DR0_PID13   (0x1u << 13)

(PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable

Definition at line 571 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID14

#define PMC_SLPWK_DR0_PID14   (0x1u << 14)

(PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable

Definition at line 572 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID15

#define PMC_SLPWK_DR0_PID15   (0x1u << 15)

(PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable

Definition at line 573 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID16

#define PMC_SLPWK_DR0_PID16   (0x1u << 16)

(PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable

Definition at line 574 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID17

#define PMC_SLPWK_DR0_PID17   (0x1u << 17)

(PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable

Definition at line 575 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID18

#define PMC_SLPWK_DR0_PID18   (0x1u << 18)

(PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable

Definition at line 576 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID19

#define PMC_SLPWK_DR0_PID19   (0x1u << 19)

(PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable

Definition at line 577 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID20

#define PMC_SLPWK_DR0_PID20   (0x1u << 20)

(PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable

Definition at line 578 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID21

#define PMC_SLPWK_DR0_PID21   (0x1u << 21)

(PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable

Definition at line 579 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID22

#define PMC_SLPWK_DR0_PID22   (0x1u << 22)

(PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable

Definition at line 580 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID23

#define PMC_SLPWK_DR0_PID23   (0x1u << 23)

(PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable

Definition at line 581 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID24

#define PMC_SLPWK_DR0_PID24   (0x1u << 24)

(PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable

Definition at line 582 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID25

#define PMC_SLPWK_DR0_PID25   (0x1u << 25)

(PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable

Definition at line 583 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID26

#define PMC_SLPWK_DR0_PID26   (0x1u << 26)

(PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable

Definition at line 584 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID27

#define PMC_SLPWK_DR0_PID27   (0x1u << 27)

(PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable

Definition at line 585 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID28

#define PMC_SLPWK_DR0_PID28   (0x1u << 28)

(PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable

Definition at line 586 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID29

#define PMC_SLPWK_DR0_PID29   (0x1u << 29)

(PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable

Definition at line 587 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID30

#define PMC_SLPWK_DR0_PID30   (0x1u << 30)

(PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable

Definition at line 588 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID31

#define PMC_SLPWK_DR0_PID31   (0x1u << 31)

(PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable

Definition at line 589 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID7

#define PMC_SLPWK_DR0_PID7   (0x1u << 7)

(PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable

Definition at line 565 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID8

#define PMC_SLPWK_DR0_PID8   (0x1u << 8)

(PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable

Definition at line 566 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR0_PID9

#define PMC_SLPWK_DR0_PID9   (0x1u << 9)

(PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable

Definition at line 567 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID32

#define PMC_SLPWK_DR1_PID32   (0x1u << 0)

(PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable

Definition at line 673 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID33

#define PMC_SLPWK_DR1_PID33   (0x1u << 1)

(PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable

Definition at line 674 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID34

#define PMC_SLPWK_DR1_PID34   (0x1u << 2)

(PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable

Definition at line 675 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID35

#define PMC_SLPWK_DR1_PID35   (0x1u << 3)

(PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable

Definition at line 676 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID37

#define PMC_SLPWK_DR1_PID37   (0x1u << 5)

(PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable

Definition at line 677 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID39

#define PMC_SLPWK_DR1_PID39   (0x1u << 7)

(PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable

Definition at line 678 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID40

#define PMC_SLPWK_DR1_PID40   (0x1u << 8)

(PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable

Definition at line 679 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID41

#define PMC_SLPWK_DR1_PID41   (0x1u << 9)

(PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable

Definition at line 680 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID42

#define PMC_SLPWK_DR1_PID42   (0x1u << 10)

(PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable

Definition at line 681 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID43

#define PMC_SLPWK_DR1_PID43   (0x1u << 11)

(PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable

Definition at line 682 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID44

#define PMC_SLPWK_DR1_PID44   (0x1u << 12)

(PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable

Definition at line 683 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID45

#define PMC_SLPWK_DR1_PID45   (0x1u << 13)

(PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable

Definition at line 684 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID46

#define PMC_SLPWK_DR1_PID46   (0x1u << 14)

(PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable

Definition at line 685 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID47

#define PMC_SLPWK_DR1_PID47   (0x1u << 15)

(PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable

Definition at line 686 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID48

#define PMC_SLPWK_DR1_PID48   (0x1u << 16)

(PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable

Definition at line 687 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID49

#define PMC_SLPWK_DR1_PID49   (0x1u << 17)

(PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable

Definition at line 688 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID50

#define PMC_SLPWK_DR1_PID50   (0x1u << 18)

(PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable

Definition at line 689 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID51

#define PMC_SLPWK_DR1_PID51   (0x1u << 19)

(PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable

Definition at line 690 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID52

#define PMC_SLPWK_DR1_PID52   (0x1u << 20)

(PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable

Definition at line 691 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID53

#define PMC_SLPWK_DR1_PID53   (0x1u << 21)

(PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable

Definition at line 692 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID56

#define PMC_SLPWK_DR1_PID56   (0x1u << 24)

(PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable

Definition at line 693 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID57

#define PMC_SLPWK_DR1_PID57   (0x1u << 25)

(PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable

Definition at line 694 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID58

#define PMC_SLPWK_DR1_PID58   (0x1u << 26)

(PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable

Definition at line 695 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID59

#define PMC_SLPWK_DR1_PID59   (0x1u << 27)

(PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable

Definition at line 696 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_DR1_PID60

#define PMC_SLPWK_DR1_PID60   (0x1u << 28)

(PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable

Definition at line 697 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID10

#define PMC_SLPWK_ER0_PID10   (0x1u << 10)

(PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable

Definition at line 542 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID11

#define PMC_SLPWK_ER0_PID11   (0x1u << 11)

(PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable

Definition at line 543 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID12

#define PMC_SLPWK_ER0_PID12   (0x1u << 12)

(PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable

Definition at line 544 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID13

#define PMC_SLPWK_ER0_PID13   (0x1u << 13)

(PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable

Definition at line 545 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID14

#define PMC_SLPWK_ER0_PID14   (0x1u << 14)

(PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable

Definition at line 546 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID15

#define PMC_SLPWK_ER0_PID15   (0x1u << 15)

(PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable

Definition at line 547 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID16

#define PMC_SLPWK_ER0_PID16   (0x1u << 16)

(PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable

Definition at line 548 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID17

#define PMC_SLPWK_ER0_PID17   (0x1u << 17)

(PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable

Definition at line 549 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID18

#define PMC_SLPWK_ER0_PID18   (0x1u << 18)

(PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable

Definition at line 550 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID19

#define PMC_SLPWK_ER0_PID19   (0x1u << 19)

(PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable

Definition at line 551 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID20

#define PMC_SLPWK_ER0_PID20   (0x1u << 20)

(PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable

Definition at line 552 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID21

#define PMC_SLPWK_ER0_PID21   (0x1u << 21)

(PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable

Definition at line 553 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID22

#define PMC_SLPWK_ER0_PID22   (0x1u << 22)

(PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable

Definition at line 554 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID23

#define PMC_SLPWK_ER0_PID23   (0x1u << 23)

(PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable

Definition at line 555 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID24

#define PMC_SLPWK_ER0_PID24   (0x1u << 24)

(PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable

Definition at line 556 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID25

#define PMC_SLPWK_ER0_PID25   (0x1u << 25)

(PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable

Definition at line 557 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID26

#define PMC_SLPWK_ER0_PID26   (0x1u << 26)

(PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable

Definition at line 558 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID27

#define PMC_SLPWK_ER0_PID27   (0x1u << 27)

(PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable

Definition at line 559 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID28

#define PMC_SLPWK_ER0_PID28   (0x1u << 28)

(PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable

Definition at line 560 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID29

#define PMC_SLPWK_ER0_PID29   (0x1u << 29)

(PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable

Definition at line 561 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID30

#define PMC_SLPWK_ER0_PID30   (0x1u << 30)

(PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable

Definition at line 562 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID31

#define PMC_SLPWK_ER0_PID31   (0x1u << 31)

(PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable

Definition at line 563 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID7

#define PMC_SLPWK_ER0_PID7   (0x1u << 7)

(PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable

Definition at line 539 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID8

#define PMC_SLPWK_ER0_PID8   (0x1u << 8)

(PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable

Definition at line 540 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER0_PID9

#define PMC_SLPWK_ER0_PID9   (0x1u << 9)

(PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable

Definition at line 541 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID32

#define PMC_SLPWK_ER1_PID32   (0x1u << 0)

(PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable

Definition at line 647 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID33

#define PMC_SLPWK_ER1_PID33   (0x1u << 1)

(PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable

Definition at line 648 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID34

#define PMC_SLPWK_ER1_PID34   (0x1u << 2)

(PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable

Definition at line 649 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID35

#define PMC_SLPWK_ER1_PID35   (0x1u << 3)

(PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable

Definition at line 650 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID37

#define PMC_SLPWK_ER1_PID37   (0x1u << 5)

(PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable

Definition at line 651 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID39

#define PMC_SLPWK_ER1_PID39   (0x1u << 7)

(PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable

Definition at line 652 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID40

#define PMC_SLPWK_ER1_PID40   (0x1u << 8)

(PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable

Definition at line 653 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID41

#define PMC_SLPWK_ER1_PID41   (0x1u << 9)

(PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable

Definition at line 654 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID42

#define PMC_SLPWK_ER1_PID42   (0x1u << 10)

(PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable

Definition at line 655 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID43

#define PMC_SLPWK_ER1_PID43   (0x1u << 11)

(PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable

Definition at line 656 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID44

#define PMC_SLPWK_ER1_PID44   (0x1u << 12)

(PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable

Definition at line 657 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID45

#define PMC_SLPWK_ER1_PID45   (0x1u << 13)

(PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable

Definition at line 658 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID46

#define PMC_SLPWK_ER1_PID46   (0x1u << 14)

(PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable

Definition at line 659 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID47

#define PMC_SLPWK_ER1_PID47   (0x1u << 15)

(PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable

Definition at line 660 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID48

#define PMC_SLPWK_ER1_PID48   (0x1u << 16)

(PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable

Definition at line 661 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID49

#define PMC_SLPWK_ER1_PID49   (0x1u << 17)

(PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable

Definition at line 662 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID50

#define PMC_SLPWK_ER1_PID50   (0x1u << 18)

(PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable

Definition at line 663 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID51

#define PMC_SLPWK_ER1_PID51   (0x1u << 19)

(PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable

Definition at line 664 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID52

#define PMC_SLPWK_ER1_PID52   (0x1u << 20)

(PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable

Definition at line 665 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID53

#define PMC_SLPWK_ER1_PID53   (0x1u << 21)

(PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable

Definition at line 666 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID56

#define PMC_SLPWK_ER1_PID56   (0x1u << 24)

(PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable

Definition at line 667 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID57

#define PMC_SLPWK_ER1_PID57   (0x1u << 25)

(PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable

Definition at line 668 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID58

#define PMC_SLPWK_ER1_PID58   (0x1u << 26)

(PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable

Definition at line 669 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID59

#define PMC_SLPWK_ER1_PID59   (0x1u << 27)

(PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable

Definition at line 670 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_ER1_PID60

#define PMC_SLPWK_ER1_PID60   (0x1u << 28)

(PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable

Definition at line 671 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID10

#define PMC_SLPWK_SR0_PID10   (0x1u << 10)

(PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status

Definition at line 594 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID11

#define PMC_SLPWK_SR0_PID11   (0x1u << 11)

(PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status

Definition at line 595 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID12

#define PMC_SLPWK_SR0_PID12   (0x1u << 12)

(PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status

Definition at line 596 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID13

#define PMC_SLPWK_SR0_PID13   (0x1u << 13)

(PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status

Definition at line 597 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID14

#define PMC_SLPWK_SR0_PID14   (0x1u << 14)

(PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status

Definition at line 598 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID15

#define PMC_SLPWK_SR0_PID15   (0x1u << 15)

(PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status

Definition at line 599 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID16

#define PMC_SLPWK_SR0_PID16   (0x1u << 16)

(PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status

Definition at line 600 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID17

#define PMC_SLPWK_SR0_PID17   (0x1u << 17)

(PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status

Definition at line 601 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID18

#define PMC_SLPWK_SR0_PID18   (0x1u << 18)

(PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status

Definition at line 602 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID19

#define PMC_SLPWK_SR0_PID19   (0x1u << 19)

(PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status

Definition at line 603 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID20

#define PMC_SLPWK_SR0_PID20   (0x1u << 20)

(PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status

Definition at line 604 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID21

#define PMC_SLPWK_SR0_PID21   (0x1u << 21)

(PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status

Definition at line 605 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID22

#define PMC_SLPWK_SR0_PID22   (0x1u << 22)

(PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status

Definition at line 606 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID23

#define PMC_SLPWK_SR0_PID23   (0x1u << 23)

(PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status

Definition at line 607 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID24

#define PMC_SLPWK_SR0_PID24   (0x1u << 24)

(PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status

Definition at line 608 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID25

#define PMC_SLPWK_SR0_PID25   (0x1u << 25)

(PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status

Definition at line 609 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID26

#define PMC_SLPWK_SR0_PID26   (0x1u << 26)

(PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status

Definition at line 610 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID27

#define PMC_SLPWK_SR0_PID27   (0x1u << 27)

(PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status

Definition at line 611 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID28

#define PMC_SLPWK_SR0_PID28   (0x1u << 28)

(PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status

Definition at line 612 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID29

#define PMC_SLPWK_SR0_PID29   (0x1u << 29)

(PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status

Definition at line 613 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID30

#define PMC_SLPWK_SR0_PID30   (0x1u << 30)

(PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status

Definition at line 614 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID31

#define PMC_SLPWK_SR0_PID31   (0x1u << 31)

(PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status

Definition at line 615 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID7

#define PMC_SLPWK_SR0_PID7   (0x1u << 7)

(PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status

Definition at line 591 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID8

#define PMC_SLPWK_SR0_PID8   (0x1u << 8)

(PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status

Definition at line 592 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR0_PID9

#define PMC_SLPWK_SR0_PID9   (0x1u << 9)

(PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status

Definition at line 593 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID32

#define PMC_SLPWK_SR1_PID32   (0x1u << 0)

(PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status

Definition at line 699 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID33

#define PMC_SLPWK_SR1_PID33   (0x1u << 1)

(PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status

Definition at line 700 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID34

#define PMC_SLPWK_SR1_PID34   (0x1u << 2)

(PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status

Definition at line 701 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID35

#define PMC_SLPWK_SR1_PID35   (0x1u << 3)

(PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status

Definition at line 702 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID37

#define PMC_SLPWK_SR1_PID37   (0x1u << 5)

(PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status

Definition at line 703 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID39

#define PMC_SLPWK_SR1_PID39   (0x1u << 7)

(PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status

Definition at line 704 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID40

#define PMC_SLPWK_SR1_PID40   (0x1u << 8)

(PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status

Definition at line 705 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID41

#define PMC_SLPWK_SR1_PID41   (0x1u << 9)

(PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status

Definition at line 706 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID42

#define PMC_SLPWK_SR1_PID42   (0x1u << 10)

(PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status

Definition at line 707 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID43

#define PMC_SLPWK_SR1_PID43   (0x1u << 11)

(PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status

Definition at line 708 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID44

#define PMC_SLPWK_SR1_PID44   (0x1u << 12)

(PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status

Definition at line 709 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID45

#define PMC_SLPWK_SR1_PID45   (0x1u << 13)

(PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status

Definition at line 710 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID46

#define PMC_SLPWK_SR1_PID46   (0x1u << 14)

(PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status

Definition at line 711 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID47

#define PMC_SLPWK_SR1_PID47   (0x1u << 15)

(PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status

Definition at line 712 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID48

#define PMC_SLPWK_SR1_PID48   (0x1u << 16)

(PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status

Definition at line 713 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID49

#define PMC_SLPWK_SR1_PID49   (0x1u << 17)

(PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status

Definition at line 714 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID50

#define PMC_SLPWK_SR1_PID50   (0x1u << 18)

(PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status

Definition at line 715 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID51

#define PMC_SLPWK_SR1_PID51   (0x1u << 19)

(PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status

Definition at line 716 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID52

#define PMC_SLPWK_SR1_PID52   (0x1u << 20)

(PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status

Definition at line 717 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID53

#define PMC_SLPWK_SR1_PID53   (0x1u << 21)

(PMC_SLPWK_SR1) Peripheral 53 SleepWalking Status

Definition at line 718 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID56

#define PMC_SLPWK_SR1_PID56   (0x1u << 24)

(PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status

Definition at line 719 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID57

#define PMC_SLPWK_SR1_PID57   (0x1u << 25)

(PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status

Definition at line 720 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID58

#define PMC_SLPWK_SR1_PID58   (0x1u << 26)

(PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status

Definition at line 721 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID59

#define PMC_SLPWK_SR1_PID59   (0x1u << 27)

(PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status

Definition at line 722 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SLPWK_SR1_PID60

#define PMC_SLPWK_SR1_PID60   (0x1u << 28)

(PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status

Definition at line 723 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SR_CFDEV

#define PMC_SR_CFDEV   (0x1u << 18)

(PMC_SR) Clock Failure Detector Event

Definition at line 340 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SR_CFDS

#define PMC_SR_CFDS   (0x1u << 19)

(PMC_SR) Clock Failure Detector Status

Definition at line 341 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SR_FOS

#define PMC_SR_FOS   (0x1u << 20)

(PMC_SR) Clock Failure Detector Fault Output Status

Definition at line 342 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SR_LOCKA

#define PMC_SR_LOCKA   (0x1u << 1)

(PMC_SR) PLLA Lock Status

Definition at line 327 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SR_LOCKU

#define PMC_SR_LOCKU   (0x1u << 6)

(PMC_SR) UTMI PLL Lock Status

Definition at line 329 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SR_MCKRDY

#define PMC_SR_MCKRDY   (0x1u << 3)

(PMC_SR) Master Clock Status

Definition at line 328 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SR_MOSCRCS

#define PMC_SR_MOSCRCS   (0x1u << 17)

(PMC_SR) Main On-Chip RC Oscillator Status

Definition at line 339 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SR_MOSCSELS

#define PMC_SR_MOSCSELS   (0x1u << 16)

(PMC_SR) Main Oscillator Selection Status

Definition at line 338 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SR_MOSCXTS

#define PMC_SR_MOSCXTS   (0x1u << 0)

(PMC_SR) Main Crystal Oscillator Status

Definition at line 326 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SR_OSCSELS

#define PMC_SR_OSCSELS   (0x1u << 7)

(PMC_SR) Slow Clock Oscillator Selection

Definition at line 330 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SR_PCKRDY0

#define PMC_SR_PCKRDY0   (0x1u << 8)

(PMC_SR) Programmable Clock Ready Status

Definition at line 331 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SR_PCKRDY1

#define PMC_SR_PCKRDY1   (0x1u << 9)

(PMC_SR) Programmable Clock Ready Status

Definition at line 332 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SR_PCKRDY2

#define PMC_SR_PCKRDY2   (0x1u << 10)

(PMC_SR) Programmable Clock Ready Status

Definition at line 333 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SR_PCKRDY3

#define PMC_SR_PCKRDY3   (0x1u << 11)

(PMC_SR) Programmable Clock Ready Status

Definition at line 334 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SR_PCKRDY4

#define PMC_SR_PCKRDY4   (0x1u << 12)

(PMC_SR) Programmable Clock Ready Status

Definition at line 335 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SR_PCKRDY5

#define PMC_SR_PCKRDY5   (0x1u << 13)

(PMC_SR) Programmable Clock Ready Status

Definition at line 336 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SR_PCKRDY6

#define PMC_SR_PCKRDY6   (0x1u << 14)

(PMC_SR) Programmable Clock Ready Status

Definition at line 337 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_SR_XT32KERR

#define PMC_SR_XT32KERR   (0x1u << 21)

(PMC_SR) Slow Crystal Oscillator Error

Definition at line 343 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_USB_USBDIV

#define PMC_USB_USBDIV (   value)    ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))

Definition at line 280 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_USB_USBDIV_Msk

#define PMC_USB_USBDIV_Msk   (0xfu << PMC_USB_USBDIV_Pos)

(PMC_USB) Divider for USB Clock

Definition at line 279 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_USB_USBDIV_Pos

#define PMC_USB_USBDIV_Pos   8

Definition at line 278 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_USB_USBS

#define PMC_USB_USBS   (0x1u << 0)

(PMC_USB) USB Input Clock Selection

Definition at line 277 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_VERSION_MFN_Msk

#define PMC_VERSION_MFN_Msk   (0x7u << PMC_VERSION_MFN_Pos)

(PMC_VERSION) Metal Fix Number

Definition at line 421 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_VERSION_MFN_Pos

#define PMC_VERSION_MFN_Pos   16

Definition at line 420 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_VERSION_VERSION_Msk

#define PMC_VERSION_VERSION_Msk   (0xfffu << PMC_VERSION_VERSION_Pos)

(PMC_VERSION) Version of the Hardware Module

Definition at line 419 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_VERSION_VERSION_Pos

#define PMC_VERSION_VERSION_Pos   0

Definition at line 418 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_WMST_KEY

#define PMC_WMST_KEY (   value)    ((PMC_WMST_KEY_Msk & ((value) << PMC_WMST_KEY_Pos)))

Definition at line 768 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_WMST_KEY_Msk

#define PMC_WMST_KEY_Msk   (0xffu << PMC_WMST_KEY_Pos)

(PMC_WMST) Write Access Password

Definition at line 767 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_WMST_KEY_PASSWD

#define PMC_WMST_KEY_PASSWD   (0x5Au << 24)

(PMC_WMST) Writing any other value in this field aborts the write operation.Always reads as 0.

Definition at line 769 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_WMST_KEY_Pos

#define PMC_WMST_KEY_Pos   24

Definition at line 766 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_WMST_WMST

#define PMC_WMST_WMST (   value)    ((PMC_WMST_WMST_Msk & ((value) << PMC_WMST_WMST_Pos)))

Definition at line 765 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_WMST_WMST_Msk

#define PMC_WMST_WMST_Msk   (0xffu << PMC_WMST_WMST_Pos)

(PMC_WMST) Wait Mode Startup Time

Definition at line 764 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_WMST_WMST_Pos

#define PMC_WMST_WMST_Pos   0

Definition at line 763 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_WPMR_WPEN

#define PMC_WPMR_WPEN   (0x1u << 0)

(PMC_WPMR) Write Protection Enable

Definition at line 408 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_WPMR_WPKEY

#define PMC_WPMR_WPKEY (   value)    ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))

Definition at line 411 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_WPMR_WPKEY_Msk

#define PMC_WPMR_WPKEY_Msk   (0xffffffu << PMC_WPMR_WPKEY_Pos)

(PMC_WPMR) Write Protection Key

Definition at line 410 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_WPMR_WPKEY_PASSWD

#define PMC_WPMR_WPKEY_PASSWD   (0x504D43u << 8)

(PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

Definition at line 412 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_WPMR_WPKEY_Pos

#define PMC_WPMR_WPKEY_Pos   8

Definition at line 409 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_WPSR_WPVS

#define PMC_WPSR_WPVS   (0x1u << 0)

(PMC_WPSR) Write Protection Violation Status

Definition at line 414 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_WPSR_WPVSRC_Msk

#define PMC_WPSR_WPVSRC_Msk   (0xffffu << PMC_WPSR_WPVSRC_Pos)

(PMC_WPSR) Write Protection Violation Source

Definition at line 416 of file utils/cmsis/same70/include/component/pmc.h.

◆ PMC_WPSR_WPVSRC_Pos

#define PMC_WPSR_WPVSRC_Pos   8

Definition at line 415 of file utils/cmsis/same70/include/component/pmc.h.



inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:08