mcan.c
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1 
33 /*
34  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
35  */
36 
37 #include "mcan.h"
38 #include "pmc.h"
39 #include <string.h>
40 #include <sysclk.h>
41 
44 #ifdef __cplusplus
45 extern "C" {
46 #endif
47 
50 /* PCK5 ID,assigned to MCAN module */
51 #define PMC_PCK_5 5
52 /* Get a value of 2 to 15 bit. */
53 #define BIT_2_TO_15_MASK 0x0000fffc
54 
55 /* Message ram definition. */
70 
85 
93 {
94  if (hw == MCAN0) {
95  hw->MCAN_SIDFC = ((uint32_t)mcan0_rx_standard_filter & BIT_2_TO_15_MASK) |
96  MCAN_SIDFC_LSS(CONF_MCAN0_RX_STANDARD_ID_FILTER_NUM);
97  hw->MCAN_XIDFC = ((uint32_t)mcan0_rx_extended_filter & BIT_2_TO_15_MASK) |
98  MCAN_XIDFC_LSE(CONF_MCAN0_RX_EXTENDED_ID_FILTER_NUM);
99  hw->MCAN_RXF0C = ((uint32_t)mcan0_rx_fifo_0 & BIT_2_TO_15_MASK) |
100  MCAN_RXF0C_F0S(CONF_MCAN0_RX_FIFO_0_NUM);
101  hw->MCAN_RXF1C = ((uint32_t)mcan0_rx_fifo_1 & BIT_2_TO_15_MASK) |
102  MCAN_RXF1C_F1S(CONF_MCAN0_RX_FIFO_1_NUM);
103  hw->MCAN_RXBC = ((uint32_t)mcan0_rx_buffer & BIT_2_TO_15_MASK);
104  hw->MCAN_TXBC = ((uint32_t)mcan0_tx_buffer & BIT_2_TO_15_MASK) |
106  MCAN_TXBC_TFQS(CONF_MCAN0_TX_FIFO_QUEUE_NUM);
107  hw->MCAN_TXEFC = ((uint32_t)mcan0_tx_event_fifo & BIT_2_TO_15_MASK) |
108  MCAN_TXEFC_EFS(CONF_MCAN0_TX_EVENT_FIFO);
109  } else if (hw == MCAN1) {
110  if((uint32_t)&mcan1_rx_standard_filter > 0x2040ffff ||
111  (uint32_t)&mcan1_rx_extended_filter > 0x2040ffff ||
112  (uint32_t)&mcan1_rx_fifo_0 > 0x2040ffff ||
113  (uint32_t)&mcan1_rx_fifo_1 > 0x2040ffff ||
114  (uint32_t)&mcan1_rx_buffer > 0x2040ffff ||
115  (uint32_t)&mcan1_tx_buffer > 0x2040ffff ||
116  (uint32_t)mcan1_tx_event_fifo > 0x2040ffff)
117  {
118  //Error, memory needs to be at beginning of RAM to function with CAN module
119  while(1);
120  }
121 
122  hw->MCAN_SIDFC = ((uint32_t)mcan1_rx_standard_filter & BIT_2_TO_15_MASK) |
123  MCAN_SIDFC_LSS(CONF_MCAN1_RX_STANDARD_ID_FILTER_NUM);
124  hw->MCAN_XIDFC = ((uint32_t)mcan1_rx_extended_filter & BIT_2_TO_15_MASK) |
125  MCAN_XIDFC_LSE(CONF_MCAN1_RX_EXTENDED_ID_FILTER_NUM);
126  hw->MCAN_RXF0C = ((uint32_t)mcan1_rx_fifo_0 & BIT_2_TO_15_MASK) |
127  MCAN_RXF0C_F0S(CONF_MCAN1_RX_FIFO_0_NUM);
128  hw->MCAN_RXF1C = ((uint32_t)mcan1_rx_fifo_1 & BIT_2_TO_15_MASK) |
129  MCAN_RXF1C_F1S(CONF_MCAN1_RX_FIFO_1_NUM);
130  hw->MCAN_RXBC = ((uint32_t)mcan1_rx_buffer & BIT_2_TO_15_MASK);
131  hw->MCAN_TXBC = ((uint32_t)mcan1_tx_buffer & BIT_2_TO_15_MASK) |
133  MCAN_TXBC_TFQS(CONF_MCAN1_TX_FIFO_QUEUE_NUM);
134  hw->MCAN_TXEFC = ((uint32_t)mcan1_tx_event_fifo & BIT_2_TO_15_MASK) |
135  MCAN_TXEFC_EFS(CONF_MCAN1_TX_EVENT_FIFO);
136  }
137 
144  if (CONF_MCAN_ELEMENT_DATA_SIZE <= 24) {
145  hw->MCAN_RXESC = MCAN_RXESC_RBDS((CONF_MCAN_ELEMENT_DATA_SIZE - 8) / 4) |
148  hw->MCAN_TXESC = MCAN_TXESC_TBDS((CONF_MCAN_ELEMENT_DATA_SIZE - 8) / 4);
149  } else {
150  hw->MCAN_RXESC = MCAN_RXESC_RBDS((CONF_MCAN_ELEMENT_DATA_SIZE - 32) / 16 + 5) |
153  hw->MCAN_TXESC = MCAN_TXESC_TBDS((CONF_MCAN_ELEMENT_DATA_SIZE - 32) / 16 + 5);
154  }
155 }
156 
164 {
165 #if (SAMV71B || SAME70B || SAMV70B)
166  /* Timing setting for Rev B */
167  hw->MCAN_NBTP = MCAN_NBTP_NBRP(CONF_MCAN_NBTP_NBRP_VALUE) |
171  hw->MCAN_DBTP = MCAN_DBTP_DBRP(CONF_MCAN_FBTP_FBRP_VALUE) |
175 
176  hw->MCAN_TDCR = MCAN_TDCR_TDCO(config->delay_compensation_offset) |
177  MCAN_TDCR_TDCF(config->delay_compensation_filter_window_length);
178 
179  if (config->tdc_enable) {
180  hw->MCAN_DBTP |= MCAN_DBTP_TDC_ENABLED;
181  }
182 #else
183  /* Timing setting. */
193 
194  if (config->tdc_enable) {
196  }
197 #endif
199 
200  if (config->transmit_pause) {
201  hw->MCAN_CCCR |= MCAN_CCCR_TXP;
202  }
203 
204  if (!config->automatic_retransmission) {
205  hw->MCAN_CCCR |= MCAN_CCCR_DAR;
206  }
207 
208  if (config->clock_stop_request) {
209  hw->MCAN_CCCR |= MCAN_CCCR_CSR;
210  }
211 
214 
215  hw->MCAN_TOCC = MCAN_TOCC_TOP(config->timeout_period) |
216  config->timeout_mode | config->timeout_enable;
217 
220  if (config->remote_frames_standard_reject) {
221  hw->MCAN_GFC |= MCAN_GFC_RRFS;
222  }
223  if (config->remote_frames_extended_reject) {
224  hw->MCAN_GFC|= MCAN_GFC_RRFE;
225  }
226 
227  hw->MCAN_XIDAM = config->extended_id_mask;
228 
229  if (config->rx_fifo_0_overwrite) {
231  }
233 
234  if (config->rx_fifo_1_overwrite) {
236  }
238 
239  if (config->tx_queue_mode) {
240  hw->MCAN_TXBC |= MCAN_TXBC_TFQM;
241  }
242 
244 }
245 
252 static void _mcan_enable_peripheral_clock(struct mcan_module *const module_inst)
253 {
254  if (module_inst->hw == MCAN0) {
255  /* Turn on the digital interface clock. */
257  } else if (module_inst->hw == MCAN1) {
258  /* Turn on the digital interface clock. */
260  }
261 }
262 
270 void mcan_init(struct mcan_module *const module_inst, Mcan *hw,
271  struct mcan_config *config)
272 {
273  /* Sanity check arguments */
274  Assert(module_inst);
275  Assert(hw);
276  Assert(config);
277 
278  /* Associate the software module instance with the hardware module */
279  module_inst->hw = hw;
280 
282  pmc_enable_upll_clock();
283  pmc_switch_pck_to_upllck(PMC_PCK_5, PMC_PCK_PRES(23)); //PCK5 (CAN Core Clock) at 20 MHz ("Selected clock is divided by PRES+1" - datasheet)
285 
286  /* Enable peripheral clock */
287  _mcan_enable_peripheral_clock(module_inst);
288 
289 
290  /* Configuration Change Enable. */
291  hw->MCAN_CCCR |= MCAN_CCCR_CCE;
292 
293  /* Initialize the message memory address. */
295 
296  /* Set the configuration. */
297  _mcan_set_configuration(hw, config);
298 
299  /* Enable the interrupt setting which no need change. */
301  hw->MCAN_TXBTIE = 0xFFFFFFFFul;
302  hw->MCAN_TXBCIE = 0xFFFFFFFFul;
303 }
304 
311 void mcan_set_baudrate(Mcan *hw, uint32_t baudrate)
312 {
313  uint32_t gclk_mcan_value;
314  uint32_t mcan_nbtp_nbrp_value;
315  uint32_t mcan_nbtp_nsgw_value = 3, mcan_nbtp_ntseg1_value = 10, mcan_nbtp_ntseg2_value = 7;
316 
317  gclk_mcan_value = 20000000; //See PCK5 setup above on line 271 - CAN Core clock speed
318 
319  //bit time is [NTSEG1 + NTSEG2 + 3] and does not factor in mcan_nbtp_nsgw_value
320  mcan_nbtp_nbrp_value = gclk_mcan_value / baudrate / (3 + mcan_nbtp_ntseg1_value + mcan_nbtp_ntseg2_value)-1;
321 #if (SAMV71B || SAME70B || SAMV70B)
322  hw->MCAN_NBTP = MCAN_NBTP_NBRP(mcan_nbtp_nbrp_value) |
323  MCAN_NBTP_NSJW(mcan_nbtp_nsgw_value) |
324  MCAN_NBTP_NTSEG1(mcan_nbtp_ntseg1_value) |
325  MCAN_NBTP_NTSEG2(mcan_nbtp_ntseg2_value);
326 #else
327  hw->MCAN_BTP = MCAN_BTP_BRP(mcan_nbtp_nbrp_value) |
328  MCAN_BTP_SJW(mcan_nbtp_nsgw_value) |
329  MCAN_BTP_TSEG1(mcan_nbtp_ntseg1_value) |
330  MCAN_BTP_TSEG2(mcan_nbtp_ntseg2_value);
331 #endif
332 }
333 
340 void mcan_fd_set_baudrate(Mcan *hw, uint32_t baudrate)
341 {
342  uint32_t gclk_mcan_fd_value;
343  uint32_t mcan_fd_dbtp_dbrp_value;
344  uint32_t mcan_fd_dbtp_dsgw_value = 3, mcan_fd_dbtp_dtseg1_value = 9, mcan_fd_dbtp_dtseg2_value = 3;
345 
346  gclk_mcan_fd_value = sysclk_get_peripheral_hz();
347 
348  mcan_fd_dbtp_dbrp_value = gclk_mcan_fd_value / baudrate / (3 + mcan_fd_dbtp_dtseg1_value + mcan_fd_dbtp_dtseg2_value);
349 #if (SAMV71B || SAME70B || SAMV70B)
350  hw->MCAN_DBTP = MCAN_DBTP_DBRP(mcan_fd_dbtp_dbrp_value) |
351  MCAN_DBTP_DSJW(mcan_fd_dbtp_dsgw_value) |
352  MCAN_DBTP_DTSEG1(mcan_fd_dbtp_dtseg1_value) |
353  MCAN_DBTP_DTSEG2(mcan_fd_dbtp_dtseg2_value);
354 #else
355  hw->MCAN_FBTP = MCAN_FBTP_FBRP(mcan_fd_dbtp_dbrp_value) |
356  MCAN_FBTP_FSJW(mcan_fd_dbtp_dsgw_value) |
357  MCAN_FBTP_FTSEG1(mcan_fd_dbtp_dtseg1_value) |
358  MCAN_FBTP_FTSEG2(mcan_fd_dbtp_dtseg2_value);
359 #endif
360 }
361 
368 void mcan_start(struct mcan_module *const module_inst)
369 {
370  module_inst->hw->MCAN_CCCR &= ~MCAN_CCCR_INIT;
371  /* Wait for the sync. */
372  while (module_inst->hw->MCAN_CCCR & MCAN_CCCR_INIT);
373 }
374 
381 void mcan_stop(struct mcan_module *const module_inst)
382 {
383  module_inst->hw->MCAN_CCCR |= MCAN_CCCR_INIT;
384  /* Wait for the sync. */
385  while (!(module_inst->hw->MCAN_CCCR & MCAN_CCCR_INIT));
386 }
387 
394 void mcan_enable_fd_mode(struct mcan_module *const module_inst)
395 {
396  module_inst->hw->MCAN_CCCR |= MCAN_CCCR_INIT;
397  /* Wait for the sync. */
398  while (!(module_inst->hw->MCAN_CCCR & MCAN_CCCR_INIT));
399  module_inst->hw->MCAN_CCCR |= MCAN_CCCR_CCE;
400 #if (SAMV71B || SAME70B || SAMV70B)
401  module_inst->hw->MCAN_CCCR |= (MCAN_CCCR_FDOE | MCAN_CCCR_BRSE);
402 #else
403  module_inst->hw->MCAN_CCCR |= MCAN_CCCR_CME(2);
404  module_inst->hw->MCAN_CCCR |= MCAN_CCCR_CMR(2);
405 #endif
406 
407 }
408 
415 void mcan_disable_fd_mode(struct mcan_module *const module_inst)
416 {
417  module_inst->hw->MCAN_CCCR |= MCAN_CCCR_INIT;
418  /* Wait for the sync. */
419  while (!(module_inst->hw->MCAN_CCCR & MCAN_CCCR_INIT));
420  module_inst->hw->MCAN_CCCR |= MCAN_CCCR_CCE;
421 #if (SAMV71B || SAME70B || SAMV70B)
422  module_inst->hw->MCAN_CCCR &= MCAN_CCCR_FDOE;
423 #else
425 #endif
426 }
427 
435  struct mcan_module *const module_inst)
436 {
437  module_inst->hw->MCAN_CCCR |= MCAN_CCCR_INIT;
438  /* Wait for the sync. */
439  while (!(module_inst->hw->MCAN_CCCR & MCAN_CCCR_INIT));
440  module_inst->hw->MCAN_CCCR |= MCAN_CCCR_CCE;
441 
442  module_inst->hw->MCAN_CCCR |= MCAN_CCCR_ASM;
443 }
444 
452  struct mcan_module *const module_inst)
453 {
454  module_inst->hw->MCAN_CCCR &= ~MCAN_CCCR_ASM;
455 }
456 
463 void mcan_enable_bus_monitor_mode(struct mcan_module *const module_inst)
464 {
465  module_inst->hw->MCAN_CCCR |= MCAN_CCCR_INIT;
466  /* Wait for the sync. */
467  while (!(module_inst->hw->MCAN_CCCR & MCAN_CCCR_INIT));
468  module_inst->hw->MCAN_CCCR |= MCAN_CCCR_CCE;
469 
470  module_inst->hw->MCAN_CCCR |= MCAN_CCCR_MON;
471 }
472 
479 void mcan_disable_bus_monitor_mode(struct mcan_module *const module_inst)
480 {
481  module_inst->hw->MCAN_CCCR &= ~MCAN_CCCR_MON;
482 }
483 
490 void mcan_enable_sleep_mode(struct mcan_module *const module_inst)
491 {
492  module_inst->hw->MCAN_CCCR |= MCAN_CCCR_CSR;
493  /* Wait for the sync. */
494  while (!(module_inst->hw->MCAN_CCCR & MCAN_CCCR_INIT));
495 
496  while (!(module_inst->hw->MCAN_CCCR & MCAN_CCCR_CSA));
497 }
498 
505 void mcan_disable_sleep_mode(struct mcan_module *const module_inst)
506 {
507  /* Enable peripheral clock */
508  _mcan_enable_peripheral_clock(module_inst);
509 
510  module_inst->hw->MCAN_CCCR &= ~MCAN_CCCR_CSR;
511  while ((module_inst->hw->MCAN_CCCR & MCAN_CCCR_CSA));
512 }
513 
520 void mcan_enable_test_mode(struct mcan_module *const module_inst)
521 {
522  module_inst->hw->MCAN_CCCR |= MCAN_CCCR_INIT;
523  /* Wait for the sync. */
524  while (!(module_inst->hw->MCAN_CCCR & MCAN_CCCR_INIT));
525  module_inst->hw->MCAN_CCCR |= MCAN_CCCR_CCE;
526 
527  module_inst->hw->MCAN_CCCR |= MCAN_CCCR_TEST;
528  module_inst->hw->MCAN_TEST |= MCAN_TEST_LBCK;
529 }
530 
537 void mcan_disable_test_mode(struct mcan_module *const module_inst)
538 {
539  module_inst->hw->MCAN_CCCR &= ~MCAN_CCCR_TEST;
540 }
541 
552  struct mcan_module *const module_inst,
553  struct mcan_standard_message_filter_element *sd_filter, uint32_t index)
554 {
555  if (module_inst->hw == MCAN0) {
556  mcan0_rx_standard_filter[index].S0.reg = sd_filter->S0.reg;
557  return STATUS_OK;
558  } else if (module_inst->hw == MCAN1) {
559  mcan1_rx_standard_filter[index].S0.reg = sd_filter->S0.reg;
560  return STATUS_OK;
561  }
562  return ERR_INVALID_ARG;
563 }
564 
575  struct mcan_module *const module_inst,
576  struct mcan_extended_message_filter_element *et_filter, uint32_t index)
577 {
578  if (module_inst->hw == MCAN0) {
579  mcan0_rx_extended_filter[index].F0.reg = et_filter->F0.reg;
580  mcan0_rx_extended_filter[index].F1.reg = et_filter->F1.reg;
581  return STATUS_OK;
582  } else if (module_inst->hw == MCAN1) {
583  mcan1_rx_extended_filter[index].F0.reg = et_filter->F0.reg;
584  mcan1_rx_extended_filter[index].F1.reg = et_filter->F1.reg;
585  return STATUS_OK;
586  }
587  return ERR_INVALID_ARG;
588 }
589 
600  struct mcan_module *const module_inst,
601  struct mcan_rx_element_buffer *rx_element, uint32_t index)
602 {
603  if (module_inst->hw == MCAN0) {
604  memcpy(rx_element, &mcan0_rx_buffer[index], sizeof(struct mcan_rx_element_buffer));
605  return STATUS_OK;
606  } else if (module_inst->hw == MCAN1) {
607  memcpy(rx_element, &mcan1_rx_buffer[index], sizeof(struct mcan_rx_element_buffer));
608  return STATUS_OK;
609  }
610  return ERR_INVALID_ARG;
611 }
612 
623  struct mcan_module *const module_inst,
624  struct mcan_rx_element_fifo_0 *rx_element, uint32_t index)
625 {
626  if (module_inst->hw == MCAN0) {
627  memcpy(rx_element, &mcan0_rx_fifo_0[index], sizeof(struct mcan_rx_element_buffer));
628  return STATUS_OK;
629  } else if (module_inst->hw == MCAN1) {
630  memcpy(rx_element, &mcan1_rx_fifo_0[index], sizeof(struct mcan_rx_element_buffer));
631  return STATUS_OK;
632  }
633  return ERR_INVALID_ARG;
634 }
635 
646  struct mcan_module *const module_inst,
647  struct mcan_rx_element_fifo_1 *rx_element, uint32_t index)
648 {
649  if (module_inst->hw == MCAN0) {
650  memcpy(rx_element, &mcan0_rx_fifo_1[index], sizeof(struct mcan_rx_element_buffer));
651  return STATUS_OK;
652  } else if (module_inst->hw == MCAN1) {
653  memcpy(rx_element, &mcan1_rx_fifo_1[index], sizeof(struct mcan_rx_element_buffer));
654  return STATUS_OK;
655  }
656  return ERR_INVALID_ARG;
657 }
658 
669  struct mcan_module *const module_inst,
670  struct mcan_tx_element *tx_element, uint32_t index)
671 {
672  uint32_t i;
673  if (module_inst->hw == MCAN0) {
674  mcan0_tx_buffer[index].T0.reg = tx_element->T0.reg;
675  mcan0_tx_buffer[index].T1.reg = tx_element->T1.reg;
676  for (i = 0; i < CONF_MCAN_ELEMENT_DATA_SIZE; i++) {
677  mcan0_tx_buffer[index].data[i] = tx_element->data[i];
678  }
679  return STATUS_OK;
680  } else if (module_inst->hw == MCAN1) {
681  mcan1_tx_buffer[index].T0.reg = tx_element->T0.reg;
682  mcan1_tx_buffer[index].T1.reg = tx_element->T1.reg;
683  for (i = 0; i < CONF_MCAN_ELEMENT_DATA_SIZE; i++) {
684  mcan1_tx_buffer[index].data[i] = tx_element->data[i];
685  }
686  return STATUS_OK;
687  }
688  return ERR_INVALID_ARG;
689 }
690 
701  struct mcan_module *const module_inst,
702  struct mcan_tx_event_element *tx_event_element, uint32_t index)
703 {
704  if (module_inst->hw == MCAN0) {
705  tx_event_element->E0.reg = mcan0_tx_event_fifo[index].E0.reg;
706  tx_event_element->E1.reg = mcan0_tx_event_fifo[index].E1.reg;
707  return STATUS_OK;
708  } else if (module_inst->hw == MCAN1) {
709  tx_event_element->E0.reg = mcan1_tx_event_fifo[index].E0.reg;
710  tx_event_element->E1.reg = mcan1_tx_event_fifo[index].E1.reg;
711  return STATUS_OK;
712  }
713  return ERR_INVALID_ARG;
714 }
715 
718 #ifdef __cplusplus
719 }
720 #endif
721 
#define CONF_MCAN1_RX_FIFO_1_NUM
Definition: conf_mcan.h:62
#define MCAN_CCCR_DAR
(MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection)
enum mcan_nonmatching_frames_action nonmatching_frames_action_standard
static void _mcan_enable_peripheral_clock(struct mcan_module *const module_inst)
enable can module clock.
Definition: mcan.c:252
__IO uint32_t MCAN_XIDAM
(Mcan Offset: 0x90) Extended ID AND Mask Register
#define MCAN_FBTP_FSJW(value)
MCAN transfer event FIFO element structure.
#define MCAN_TDCR_TDCO(value)
MCAN receive element structure for FIFO 0.
#define MCAN_CCCR_CME_ISO11898_1
(MCAN_CCCR) CAN operation according to ISO11898-1 enabled
static struct mcan_tx_event_element mcan0_tx_event_fifo[CONF_MCAN0_TX_EVENT_FIFO]
Definition: mcan.c:65
MCAN receive element structure for buffer.
#define CONF_MCAN_NBTP_NBRP_VALUE
Definition: conf_mcan.h:86
bool automatic_retransmission
static struct mcan_rx_element_fifo_0 mcan0_rx_fifo_0[CONF_MCAN0_RX_FIFO_0_NUM]
Definition: mcan.c:59
#define MCAN_BTP_TSEG1(value)
#define CONF_MCAN0_RX_FIFO_1_NUM
Definition: conf_mcan.h:46
#define CONF_MCAN0_TX_BUFFER_NUM
Definition: conf_mcan.h:50
#define MCAN_NBTP_NTSEG2(value)
MCAN transfer element structure.
#define CONF_MCAN0_RX_BUFFER_NUM
Definition: conf_mcan.h:48
#define MCAN_RXF0C_F0WM(value)
static struct mcan_rx_element_fifo_0 mcan1_rx_fifo_0[CONF_MCAN1_RX_FIFO_0_NUM]
Definition: mcan.c:74
void pmc_enable_pck(uint32_t ul_id)
Enable the specified programmable clock.
Definition: pmc.c:1020
#define MCAN_TXBC_TFQM
(MCAN_TXBC) Tx FIFO/Queue Mode
Success.
Definition: status_codes.h:66
__IO uint32_t MCAN_TXBCIE
(Mcan Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register ...
#define CONF_MCAN0_RX_EXTENDED_ID_FILTER_NUM
Definition: conf_mcan.h:58
#define CONF_MCAN1_RX_EXTENDED_ID_FILTER_NUM
Definition: conf_mcan.h:74
MCAN extended message ID filter element structure.
__IO MCAN_TX_EVENT_ELEMENT_E0_Type E0
#define MCAN_DBTP_DTSEG2(value)
#define MCAN1
(MCAN1 ) Base Address
Definition: same70j20.h:509
__IO MCAN_TX_EVENT_ELEMENT_E1_Type E1
#define MCAN_DBTP_DSJW(value)
#define MCAN_RXESC_RBDS(value)
__IO MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_Type F0
#define CONF_MCAN_NBTP_NTSEG2_VALUE
Definition: conf_mcan.h:92
#define MCAN_RXESC_F0DS(value)
#define MCAN_CCCR_CCE
(MCAN_CCCR) Configuration Change Enable (read/write, write protection)
Mcan hardware registers.
#define MCAN_TSCC_TSS_TCP_INC
(MCAN_TSCC) Timestamp counter value incremented according to TCP
static struct mcan_tx_event_element mcan1_tx_event_fifo[CONF_MCAN1_TX_EVENT_FIFO]
Definition: mcan.c:80
#define MCAN_CCCR_CMR(value)
enum status_code mcan_get_tx_event_fifo_element(struct mcan_module *const module_inst, struct mcan_tx_event_element *tx_event_element, uint32_t index)
set FIFO transmit buffer element .
Definition: mcan.c:700
uint8_t delay_compensation_offset
#define MCAN_GFC_ANFS(value)
MCAN receive element structure for FIFO 1.
#define MCAN_TXBC_TFQS(value)
#define CONF_MCAN_FBTP_FTSEG1_VALUE
Definition: conf_mcan.h:105
void mcan_disable_bus_monitor_mode(struct mcan_module *const module_inst)
disable bus monitor mode of mcan module.
Definition: mcan.c:479
uint32_t pmc_enable_periph_clk(uint32_t ul_id)
Enable the specified peripheral clock.
Definition: pmc.c:682
#define MCAN_CCCR_CSA
(MCAN_CCCR) Clock Stop Acknowledge (read-only)
#define MCAN_RXF1C_F1OM
(MCAN_RXF1C) FIFO 1 Operation Mode
SAM Control Area Network (MCAN) Low Level Driver.
__IO uint32_t MCAN_TEST
(Mcan Offset: 0x10) Test Register
#define MCAN_CCCR_FDOE
(MCAN_CCCR) CAN FD Operation Enable (read/write, write protection)
#define MCAN_TOCC_TOP(value)
#define MCAN_CCCR_CME(value)
#define MCAN_CCCR_CSR
(MCAN_CCCR) Clock Stop Request (read/write)
#define PMC_PCK_5
Definition: mcan.c:51
#define MCAN_FBTP_FBRP(value)
#define MCAN_TXEFC_EFWM(value)
void mcan_stop(struct mcan_module *const module_inst)
stop mcan module when bus off occurs
Definition: mcan.c:381
__IO uint32_t MCAN_RXF0C
(Mcan Offset: 0xA0) Receive FIFO 0 Configuration Register
#define CONF_MCAN_NBTP_NTSEG1_VALUE
Definition: conf_mcan.h:90
static struct mcan_extended_message_filter_element mcan0_rx_extended_filter[CONF_MCAN0_RX_EXTENDED_ID_FILTER_NUM]
Definition: mcan.c:69
#define MCAN_FBTP_TDC_ENABLED
(MCAN_FBTP) Transceiver Delay Compensation enabled.
#define MCAN_TDCR_TDCF(value)
#define MCAN_NBTP_NBRP(value)
void mcan_enable_test_mode(struct mcan_module *const module_inst)
enable test mode of mcan module.
Definition: mcan.c:520
void pmc_disable_pck(uint32_t ul_id)
Disable the specified programmable clock.
Definition: pmc.c:1030
bool remote_frames_standard_reject
void mcan_enable_restricted_operation_mode(struct mcan_module *const module_inst)
enable restricted mode of mcan module.
Definition: mcan.c:434
void mcan_start(struct mcan_module *const module_inst)
start can module after initialization.
Definition: mcan.c:368
#define MCAN_CCCR_MON
(MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against &#39;1&#39;)
__IO uint32_t MCAN_FBTP
(Mcan Offset: 0x0C) Fast Bit Timing and Prescaler Register
#define CONF_MCAN_ELEMENT_DATA_SIZE
Definition: conf_mcan.h:77
#define MCAN_TEST_LBCK
(MCAN_TEST) Loop Back Mode (read/write)
#define CONF_MCAN1_RX_STANDARD_ID_FILTER_NUM
Definition: conf_mcan.h:72
MCAN configuration structure.
status_code
Definition: status_codes.h:65
#define MCAN_FBTP_FTSEG2(value)
#define CONF_MCAN_FBTP_FSJW_VALUE
Definition: conf_mcan.h:103
void mcan_disable_sleep_mode(struct mcan_module *const module_inst)
disable sleep mode of mcan module.
Definition: mcan.c:505
__IO MCAN_TX_ELEMENT_T0_Type T0
#define MCAN_CCCR_TXP
(MCAN_CCCR) Transmit Pause (read/write, write protection)
__IO uint32_t MCAN_TXBC
(Mcan Offset: 0xC0) Transmit Buffer Configuration Register
static struct mcan_extended_message_filter_element mcan1_rx_extended_filter[CONF_MCAN1_RX_EXTENDED_ID_FILTER_NUM]
Definition: mcan.c:84
static void _mcan_message_memory_init(Mcan *hw)
initialize MCAN memory .
Definition: mcan.c:92
static uint32_t sysclk_get_peripheral_hz(void)
Retrieves the current rate in Hz of the peripheral clocks.
#define MCAN_TSCC_TCP(value)
__IO uint32_t MCAN_ILE
(Mcan Offset: 0x5C) Interrupt Line Enable Register
#define MCAN_CCCR_ASM
(MCAN_CCCR) Restricted Operation Mode (read/write, write protection against &#39;1&#39;)
COMPILER_ALIGNED(32)
Buffer to receive data.
Definition: udi_cdc.c:233
static struct mcan_rx_element_buffer mcan0_rx_buffer[CONF_MCAN0_RX_BUFFER_NUM]
Definition: mcan.c:57
#define CONF_MCAN1_TX_EVENT_FIFO
Definition: conf_mcan.h:70
__IO uint32_t MCAN_TSCC
(Mcan Offset: 0x20) Timestamp Counter Configuration Register
#define MCAN_ILE_EINT0
(MCAN_ILE) Enable Interrupt Line 0
__IO uint32_t MCAN_CCCR
(Mcan Offset: 0x18) CC Control Register
#define CONF_MCAN_NBTP_NSJW_VALUE
Definition: conf_mcan.h:88
#define MCAN_GFC_RRFE
(MCAN_GFC) Reject Remote Frames Extended
#define CONF_MCAN_FBTP_FTSEG2_VALUE
Definition: conf_mcan.h:107
#define CONF_MCAN1_TX_FIFO_QUEUE_NUM
Definition: conf_mcan.h:68
enum status_code mcan_set_rx_extended_filter(struct mcan_module *const module_inst, struct mcan_extended_message_filter_element *et_filter, uint32_t index)
set extended receive CAN ID.
Definition: mcan.c:574
enum status_code mcan_get_rx_buffer_element(struct mcan_module *const module_inst, struct mcan_rx_element_buffer *rx_element, uint32_t index)
get dedicated rx buffer element .
Definition: mcan.c:599
#define MCAN_RXF0C_F0OM
(MCAN_RXF0C) FIFO 0 Operation Mode
#define MCAN_NBTP_NTSEG1(value)
#define MCAN_FBTP_TDCO(value)
#define CONF_MCAN0_RX_FIFO_0_NUM
Definition: conf_mcan.h:44
void mcan_disable_test_mode(struct mcan_module *const module_inst)
disable test mode of mcan module.
Definition: mcan.c:537
#define MCAN_TXBC_NDTB(value)
#define MCAN_DBTP_DBRP(value)
void mcan_fd_set_baudrate(Mcan *hw, uint32_t baudrate)
Set MCAN_FD baudrate.
Definition: mcan.c:340
#define CONF_MCAN0_RX_STANDARD_ID_FILTER_NUM
Definition: conf_mcan.h:56
#define MCAN_BTP_TSEG2(value)
#define MCAN_TXEFC_EFS(value)
#define MCAN_GFC_RRFS
(MCAN_GFC) Reject Remote Frames Standard
#define MCAN_SIDFC_LSS(value)
#define MCAN_RXF1C_F1S(value)
#define PMC_PCK_PRES(value)
#define MCAN_CCCR_TEST
(MCAN_CCCR) Test Mode Enable (read/write, write protection against &#39;1&#39;)
__IO uint32_t MCAN_TOCC
(Mcan Offset: 0x28) Timeout Counter Configuration Register
#define MCAN_ILE_EINT1
(MCAN_ILE) Enable Interrupt Line 1
#define CONF_MCAN0_TX_FIFO_QUEUE_NUM
Definition: conf_mcan.h:52
static struct mcan_rx_element_fifo_1 mcan0_rx_fifo_1[CONF_MCAN0_RX_FIFO_1_NUM]
Definition: mcan.c:61
__IO MCAN_TX_ELEMENT_T1_Type T1
uint8_t timestamp_prescaler
#define MCAN_RXF1C_F1WM(value)
enum mcan_nonmatching_frames_action nonmatching_frames_action_extended
#define MCAN_DBTP_TDC_ENABLED
(MCAN_DBTP) Transmitter Delay Compensation enabled.
bool remote_frames_extended_reject
__IO uint32_t MCAN_BTP
(Mcan Offset: 0x1C) Bit Timing and Prescaler Register
static struct mcan_rx_element_buffer mcan1_rx_buffer[CONF_MCAN1_RX_BUFFER_NUM]
Definition: mcan.c:72
#define MCAN0
(MCAN0 ) Base Address
Definition: same70j19.h:507
uint8_t watchdog_configuration
#define MCAN_CCCR_INIT
(MCAN_CCCR) Initialization (read/write)
static struct mcan_standard_message_filter_element mcan0_rx_standard_filter[CONF_MCAN0_RX_STANDARD_ID_FILTER_NUM]
Definition: mcan.c:67
uint8_t rx_fifo_1_watermark
enum status_code mcan_get_rx_fifo_0_element(struct mcan_module *const module_inst, struct mcan_rx_element_fifo_0 *rx_element, uint32_t index)
get FIFO rx buffer element .
Definition: mcan.c:622
void mcan_enable_sleep_mode(struct mcan_module *const module_inst)
enable sleep mode of mcan module.
Definition: mcan.c:490
void mcan_enable_fd_mode(struct mcan_module *const module_inst)
switch mcan module into fd mode.
Definition: mcan.c:394
#define MCAN_CCCR_BRSE
(MCAN_CCCR) Bit Rate Switching Enable (read/write, write protection)
#define ID_MCAN1
MCAN Controller 1 (MCAN1)
Definition: same70j20.h:433
enum mcan_timeout_mode timeout_mode
void mcan_enable_bus_monitor_mode(struct mcan_module *const module_inst)
enable bus monitor mode of mcan module.
Definition: mcan.c:463
static struct mcan_standard_message_filter_element mcan1_rx_standard_filter[CONF_MCAN1_RX_STANDARD_ID_FILTER_NUM]
Definition: mcan.c:82
#define CONF_MCAN1_TX_BUFFER_NUM
Definition: conf_mcan.h:66
static struct mcan_tx_element mcan1_tx_buffer[CONF_MCAN1_TX_BUFFER_NUM+CONF_MCAN1_TX_FIFO_QUEUE_NUM]
Definition: mcan.c:78
uint32_t extended_id_mask
enum status_code mcan_get_rx_fifo_1_element(struct mcan_module *const module_inst, struct mcan_rx_element_fifo_1 *rx_element, uint32_t index)
get FIFO rx buffer element .
Definition: mcan.c:645
#define MCAN_NBTP_NSJW(value)
void mcan_disable_fd_mode(struct mcan_module *const module_inst)
disable fd mode of mcan module.
Definition: mcan.c:415
static void _mcan_set_configuration(Mcan *hw, struct mcan_config *config)
set default configuration when initialization.
Definition: mcan.c:163
void mcan_set_baudrate(Mcan *hw, uint32_t baudrate)
Set MCAN baudrate.
Definition: mcan.c:311
__IO uint32_t MCAN_TXBTIE
(Mcan Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register
#define MCAN_RXF0C_F0S(value)
uint8_t rx_fifo_0_watermark
#define MCAN_XIDFC_LSE(value)
uint8_t tx_event_fifo_watermark
#define CONF_MCAN1_RX_FIFO_0_NUM
Definition: conf_mcan.h:60
uint16_t timeout_period
#define BIT_2_TO_15_MASK
Definition: mcan.c:53
__IO uint32_t MCAN_RXF1C
(Mcan Offset: 0xB0) Receive FIFO 1 Configuration Register
#define MCAN_GFC_ANFE(value)
__IO uint32_t MCAN_GFC
(Mcan Offset: 0x80) Global Filter Configuration Register
#define MCAN_DBTP_DTSEG1(value)
MCAN standard message ID filter element structure.
#define ID_MCAN0
MCAN Controller 0 (MCAN0)
Definition: same70j19.h:433
#define CONF_MCAN1_RX_BUFFER_NUM
Definition: conf_mcan.h:64
__IO MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_Type S0
#define MCAN_FBTP_FTSEG1(value)
__IO MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_Type F1
enum status_code mcan_set_tx_buffer_element(struct mcan_module *const module_inst, struct mcan_tx_element *tx_element, uint32_t index)
set dedicated transmit buffer element .
Definition: mcan.c:668
void mcan_disable_restricted_operation_mode(struct mcan_module *const module_inst)
disable restricted mode of mcan module.
Definition: mcan.c:451
static struct mcan_rx_element_fifo_1 mcan1_rx_fifo_1[CONF_MCAN1_RX_FIFO_1_NUM]
Definition: mcan.c:76
__IO uint32_t MCAN_RWD
(Mcan Offset: 0x14) RAM Watchdog Register
#define Assert(expr)
This macro is used to test fatal errors.
Definition: compiler.h:196
void mcan_init(struct mcan_module *const module_inst, Mcan *hw, struct mcan_config *config)
initialize can module.
Definition: mcan.c:270
MCAN software device instance structure.
__IO uint32_t MCAN_TXEFC
(Mcan Offset: 0xF0) Transmit Event FIFO Configuration Register
#define CONF_MCAN_FBTP_FBRP_VALUE
Definition: conf_mcan.h:101
#define MCAN_TXESC_TBDS(value)
enum status_code mcan_set_rx_standard_filter(struct mcan_module *const module_inst, struct mcan_standard_message_filter_element *sd_filter, uint32_t index)
set standard receive CAN ID.
Definition: mcan.c:551
uint8_t data[CONF_MCAN_ELEMENT_DATA_SIZE]
static struct mcan_tx_element mcan0_tx_buffer[CONF_MCAN0_TX_BUFFER_NUM+CONF_MCAN0_TX_FIFO_QUEUE_NUM]
Definition: mcan.c:63
#define CONF_MCAN0_TX_EVENT_FIFO
Definition: conf_mcan.h:54
#define MCAN_RXESC_F1DS(value)
Invalid argument.
Definition: status_codes.h:77


inertial_sense_ros
Author(s):
autogenerated on Sat Sep 19 2020 03:19:04