pmc.c
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1 
33 /*
34  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
35  */
36 
37 #include "pmc.h"
38 
39 #if (SAM3N)
40 # define MAX_PERIPH_ID 31
41 #elif (SAM3XA)
42 # define MAX_PERIPH_ID 44
43 #elif (SAM3U)
44 # define MAX_PERIPH_ID 29
45 #elif (SAM3S || SAM4S)
46 # define MAX_PERIPH_ID 34
47 #elif (SAM4E)
48 # define MAX_PERIPH_ID 47
49 #elif (SAMV71)
50 # define MAX_PERIPH_ID 63
51 #elif (SAMV70)
52 # define MAX_PERIPH_ID 63
53 #elif (SAME70)
54 # define MAX_PERIPH_ID 63
55 #elif (SAMS70)
56 # define MAX_PERIPH_ID 63
57 #elif (SAM4N)
58 # define MAX_PERIPH_ID 31
59 #elif (SAM4C || SAM4CM || SAM4CP)
60 # define MAX_PERIPH_ID 43
61 #elif (SAMG51)
62 # define MAX_PERIPH_ID 47
63 #elif (SAMG53)
64 # define MAX_PERIPH_ID 47
65 #elif (SAMG54)
66 # define MAX_PERIPH_ID 47
67 #elif (SAMG55)
68 # define MAX_PERIPH_ID 50
69 #endif
70 
72 
73 #ifdef __cplusplus
74 extern "C" {
75 #endif
76 
77 
96 void pmc_mck_set_prescaler(uint32_t ul_pres)
97 {
98  PMC->PMC_MCKR =
99  (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
100  while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
101 }
102 
103 #if SAMV71 || SAMV70 || SAME70 || SAMS70
104 
109 void pmc_mck_set_division(uint32_t ul_div)
110 {
111  switch (ul_div) {
112  case 1:
113  ul_div = PMC_MCKR_MDIV_EQ_PCK;
114  break;
115  case 2:
116  ul_div = PMC_MCKR_MDIV_PCK_DIV2;
117  break;
118  case 3:
119  ul_div = PMC_MCKR_MDIV_PCK_DIV3;
120  break;
121  case 4:
122  ul_div = PMC_MCKR_MDIV_PCK_DIV4;
123  break;
124  default:
125  ul_div = PMC_MCKR_MDIV_EQ_PCK;
126  break;
127  }
128  PMC->PMC_MCKR =
129  (PMC->PMC_MCKR & (~PMC_MCKR_MDIV_Msk)) | ul_div;
130  while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
131 }
132 #endif
133 
139 void pmc_mck_set_source(uint32_t ul_source)
140 {
141  PMC->PMC_MCKR =
142  (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | ul_source;
143  while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
144 }
145 
154 uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres)
155 {
156  uint32_t ul_timeout;
157 
158  PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
160  for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
161  --ul_timeout) {
162  if (ul_timeout == 0) {
163  return 1;
164  }
165  }
166 
167  PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
168  for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
169  --ul_timeout) {
170  if (ul_timeout == 0) {
171  return 1;
172  }
173  }
174 
175  return 0;
176 }
177 
186 uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres)
187 {
188  uint32_t ul_timeout;
189 
190  PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
192  for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
193  --ul_timeout) {
194  if (ul_timeout == 0) {
195  return 1;
196  }
197  }
198 
199  PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
200  for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
201  --ul_timeout) {
202  if (ul_timeout == 0) {
203  return 1;
204  }
205  }
206 
207  return 0;
208 }
209 
218 uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres)
219 {
220  uint32_t ul_timeout;
221 
222  PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
223  for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
224  --ul_timeout) {
225  if (ul_timeout == 0) {
226  return 1;
227  }
228  }
229 
230  PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
232 
233  for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
234  --ul_timeout) {
235  if (ul_timeout == 0) {
236  return 1;
237  }
238  }
239 
240  return 0;
241 }
242 
243 #if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
244 
252 uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres)
253 {
254  uint32_t ul_timeout;
255 
256  PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
257  for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
258  --ul_timeout) {
259  if (ul_timeout == 0) {
260  return 1;
261  }
262  }
263 
264  PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
265  PMC_MCKR_CSS_PLLB_CLK;
266  for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
267  --ul_timeout) {
268  if (ul_timeout == 0) {
269  return 1;
270  }
271  }
272 
273  return 0;
274 }
275 #endif
276 
277 #if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
278 
286 uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres)
287 {
288  uint32_t ul_timeout;
289 
290  PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
291  for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
292  --ul_timeout) {
293  if (ul_timeout == 0) {
294  return 1;
295  }
296  }
297 
298  PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
300  for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
301  --ul_timeout) {
302  if (ul_timeout == 0) {
303  return 1;
304  }
305  }
306 
307  return 0;
308 }
309 #endif
310 
319 void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass)
320 {
321  /* Set Bypass mode if required */
322  if (ul_bypass == 1) {
323  SUPC->SUPC_MR |= SUPC_MR_KEY_PASSWD |
325  }
326 
328 }
329 
337 {
338  return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL)
339  && (PMC->PMC_SR & PMC_SR_OSCSELS));
340 }
341 
351 void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf)
352 {
353  /* Enable Fast RC oscillator but DO NOT switch to RC now */
354  PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN);
355 
356  /* Wait the Fast RC to stabilize */
357  while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
358 
359  /* Change Fast RC oscillator frequency */
360  PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |
361  CKGR_MOR_KEY_PASSWD | ul_moscrcf;
362 
363  /* Wait the Fast RC to stabilize */
364  while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
365 
366  /* Switch to Fast RC */
367  PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) |
369 }
370 
376 void pmc_osc_enable_fastrc(uint32_t ul_rc)
377 {
378  /* Enable Fast RC oscillator but DO NOT switch to RC */
379  PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN);
380  /* Wait the Fast RC to stabilize */
381  while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
382 
383  /* Change Fast RC oscillator frequency */
384  PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |
385  CKGR_MOR_KEY_PASSWD | ul_rc;
386  /* Wait the Fast RC to stabilize */
387  while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
388 }
389 
394 {
395  /* Disable Fast RC oscillator */
396  PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN &
399 }
400 
407 {
408  return (PMC->PMC_SR & PMC_SR_MOSCRCS);
409 }
410 
416 void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time)
417 {
418  uint32_t mor = PMC->CKGR_MOR;
421  CKGR_MOR_MOSCXTST(ul_xtal_startup_time);
422  PMC->CKGR_MOR = mor;
423  /* Wait the main Xtal to stabilize */
424  while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
425 }
426 
431 {
432  uint32_t mor = PMC->CKGR_MOR;
435  /* Enable Crystal oscillator but DO NOT switch now. Keep MOSCSEL to 0 */
436  PMC->CKGR_MOR = mor;
437  /* The MOSCXTS in PMC_SR is automatically set */
438 }
439 
444 {
445  uint32_t mor = PMC->CKGR_MOR;
447  PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;
448 }
449 
456 {
457  return (PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY);
458 }
459 
468 {
469  return (PMC->PMC_SR & PMC_SR_MOSCXTS);
470 }
471 
485 void pmc_switch_mainck_to_xtal(uint32_t ul_bypass,
486  uint32_t ul_xtal_startup_time)
487 {
488  /* Enable Main Xtal oscillator */
489  if (ul_bypass) {
490  PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
493  } else {
494  PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
496  CKGR_MOR_MOSCXTST(ul_xtal_startup_time);
497  /* Wait the Xtal to stabilize */
498  while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
499 
501  }
502 }
503 
509 void pmc_osc_disable_xtal(uint32_t ul_bypass)
510 {
511  /* Disable xtal oscillator */
512  if (ul_bypass) {
513  PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
515  } else {
516  PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
518  }
519 }
520 
529 {
530  return PMC->PMC_SR & PMC_SR_MOSCSELS;
531 }
532 
540 void pmc_mainck_osc_select(uint32_t ul_xtal_rc)
541 {
542  uint32_t mor = PMC->CKGR_MOR;
543  if (ul_xtal_rc) {
544  mor |= CKGR_MOR_MOSCSEL;
545  } else {
546  mor &= ~CKGR_MOR_MOSCSEL;
547  }
548  PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;
549 }
550 
558 void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva)
559 {
560  /* first disable the PLL to unlock the lock */
562 
563 #if (SAM4C || SAM4CM || SAM4CP || SAMG)
564  PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(diva) |
565  CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula);
566 #else
567  PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(diva) |
568  CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula);
569 #endif
570  while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0);
571 }
572 
577 {
578 #if (SAM4C || SAM4CM || SAM4CP || SAMG)
579  PMC->CKGR_PLLAR = CKGR_PLLAR_MULA(0);
580 #else
581  PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0);
582 #endif
583 }
584 
591 uint32_t pmc_is_locked_pllack(void)
592 {
593  return (PMC->PMC_SR & PMC_SR_LOCKA);
594 }
595 
596 #if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
597 
604 void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb)
605 {
606  /* first disable the PLL to unlock the lock */
607  pmc_disable_pllbck();
608 
609 #if SAMG55
610  PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(divb) |
611  CKGR_PLLAR_PLLACOUNT(pllbcount) | CKGR_PLLAR_MULA(mulb);
612 #else
613  PMC->CKGR_PLLBR =
614  CKGR_PLLBR_DIVB(divb) | CKGR_PLLBR_PLLBCOUNT(pllbcount)
615  | CKGR_PLLBR_MULB(mulb);
616 #endif
617  while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0);
618 }
619 
623 void pmc_disable_pllbck(void)
624 {
625  PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0);
626 }
627 
634 uint32_t pmc_is_locked_pllbck(void)
635 {
636  return (PMC->PMC_SR & PMC_SR_LOCKB);
637 }
638 #endif
639 
640 #if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
641 
644 void pmc_enable_upll_clock(void)
645 {
646  PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN;
647 
648  /* Wait UTMI PLL Lock Status */
649  while (!(PMC->PMC_SR & PMC_SR_LOCKU));
650 }
651 
655 void pmc_disable_upll_clock(void)
656 {
657  PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;
658 }
659 
666 uint32_t pmc_is_locked_upll(void)
667 {
668  return (PMC->PMC_SR & PMC_SR_LOCKU);
669 }
670 #endif
671 
682 uint32_t pmc_enable_periph_clk(uint32_t ul_id)
683 {
684 #if defined(REG_PMC_PCR) && !SAMG55
685  uint32_t pcr;
686  PMC->PMC_PCR = ul_id & 0x7F;
687  pcr = PMC->PMC_PCR | PMC_PCR_EN | PMC_PCR_CMD;
688  PMC->PMC_PCR = pcr;
689  return 0;
690 #else
691  if (ul_id > MAX_PERIPH_ID) {
692  return 1;
693  }
694 
695  if (ul_id < 32) {
696  if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) {
697  PMC->PMC_PCER0 = 1 << ul_id;
698  }
699 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
700  } else {
701  ul_id -= 32;
702  if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) {
703  PMC->PMC_PCER1 = 1 << ul_id;
704  }
705 #endif
706  }
707 
708  return 0;
709 #endif /* defined(REG_PMC_PCR) && !SAMG55 */
710 }
711 
722 uint32_t pmc_disable_periph_clk(uint32_t ul_id)
723 {
724 #if defined(REG_PMC_PCR) && !SAMG55
725  uint32_t pcr;
726  PMC->PMC_PCR = ul_id & 0x7F;
727  pcr = PMC->PMC_PCR | PMC_PCR_CMD;
728  PMC->PMC_PCR = pcr;
729  return 0;
730 #else
731  if (ul_id > MAX_PERIPH_ID) {
732  return 1;
733  }
734 
735  if (ul_id < 32) {
736  if ((PMC->PMC_PCSR0 & (1u << ul_id)) == (1u << ul_id)) {
737  PMC->PMC_PCDR0 = 1 << ul_id;
738  }
739 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 \
740  || SAMV70 || SAME70 || SAMS70)
741  } else {
742  ul_id -= 32;
743  if ((PMC->PMC_PCSR1 & (1u << ul_id)) == (1u << ul_id)) {
744  PMC->PMC_PCDR1 = 1 << ul_id;
745  }
746 #endif
747  }
748  return 0;
749 #endif /* defined(REG_PMC_PCR) && !SAMG55 */
750 }
751 
756 {
757  PMC->PMC_PCER0 = PMC_MASK_STATUS0;
758  while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != PMC_MASK_STATUS0);
759 
760 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
761  || SAMV70 || SAME70 || SAMS70)
762  PMC->PMC_PCER1 = PMC_MASK_STATUS1;
763  while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != PMC_MASK_STATUS1);
764 #endif
765 
766 #if defined(REG_PMC_PCR) && !SAMG55
767  for (uint32_t id = 64; id <= 0x7F; id ++) {
769  }
770 #endif
771 }
772 
777 {
778  PMC->PMC_PCDR0 = PMC_MASK_STATUS0;
779  while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != 0);
780 
781 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
782  || SAMV70 || SAME70 || SAMS70)
783  PMC->PMC_PCDR1 = PMC_MASK_STATUS1;
784  while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != 0);
785 #endif
786 
787 #if defined(REG_PMC_PCR) && !SAMG55
788  for (uint32_t id = 64; id <= 0x7F; id ++) {
790  }
791 #endif
792 }
793 
804 uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id)
805 {
806 #if defined(REG_PMC_PCR) && !SAMG55
807  PMC->PMC_PCR = ul_id & 0x7F;
808  return (PMC->PMC_PCR & PMC_PCR_EN) ? 1 : 0;
809 #else
810  if (ul_id > MAX_PERIPH_ID) {
811  return 0;
812  }
813 
814 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
815  || SAMV70 || SAME70 || SAMS70)
816  if (ul_id < 32) {
817 #endif
818  if ((PMC->PMC_PCSR0 & (1u << ul_id))) {
819  return 1;
820  } else {
821  return 0;
822  }
823 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
824  || SAMV70 || SAME70 || SAMS70)
825  } else {
826  ul_id -= 32;
827  if ((PMC->PMC_PCSR1 & (1u << ul_id))) {
828  return 1;
829  } else {
830  return 0;
831  }
832  }
833 #endif
834 #endif /* defined(REG_PMC_PCR) && !SAMG55 */
835 }
836 
843 void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres)
844 {
845  PMC->PMC_PCK[ul_id] =
846  (PMC->PMC_PCK[ul_id] & ~PMC_PCK_PRES_Msk) | ul_pres;
847  while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))
848  && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));
849 }
850 
857 void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source)
858 {
859  PMC->PMC_PCK[ul_id] =
860  (PMC->PMC_PCK[ul_id] & ~PMC_PCK_CSS_Msk) | ul_source;
861  while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))
862  && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));
863 }
864 
874 uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres)
875 {
876  uint32_t ul_timeout;
877 
878  PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_SLOW_CLK | ul_pres;
879  for (ul_timeout = PMC_TIMEOUT;
880  !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
881  if (ul_timeout == 0) {
882  return 1;
883  }
884  }
885 
886  return 0;
887 }
888 
898 uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres)
899 {
900  uint32_t ul_timeout;
901 
902  PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MAIN_CLK | ul_pres;
903  for (ul_timeout = PMC_TIMEOUT;
904  !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
905  if (ul_timeout == 0) {
906  return 1;
907  }
908  }
909 
910  return 0;
911 }
912 
922 uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres)
923 {
924  uint32_t ul_timeout;
925 
926  PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLA_CLK | ul_pres;
927  for (ul_timeout = PMC_TIMEOUT;
928  !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
929  if (ul_timeout == 0) {
930  return 1;
931  }
932  }
933 
934  return 0;
935 }
936 
937 #if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
938 
947 uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres)
948 {
949  uint32_t ul_timeout;
950 
951  PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLB_CLK | ul_pres;
952  for (ul_timeout = PMC_TIMEOUT;
953  !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));
954  --ul_timeout) {
955  if (ul_timeout == 0) {
956  return 1;
957  }
958  }
959 
960  return 0;
961 }
962 #endif
963 
964 #if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
965 
974 uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres)
975 {
976  uint32_t ul_timeout;
977 
978  PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_UPLL_CLK | ul_pres;
979  for (ul_timeout = PMC_TIMEOUT;
980  !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));
981  --ul_timeout) {
982  if (ul_timeout == 0) {
983  return 1;
984  }
985  }
986 
987  return 0;
988 }
989 #endif
990 
1000 uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres)
1001 {
1002  uint32_t ul_timeout;
1003 
1004  PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MCK | ul_pres;
1005  for (ul_timeout = PMC_TIMEOUT;
1006  !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
1007  if (ul_timeout == 0) {
1008  return 1;
1009  }
1010  }
1011 
1012  return 0;
1013 }
1014 
1020 void pmc_enable_pck(uint32_t ul_id)
1021 {
1022  PMC->PMC_SCER = PMC_SCER_PCK0 << ul_id;
1023 }
1024 
1030 void pmc_disable_pck(uint32_t ul_id)
1031 {
1032  PMC->PMC_SCDR = PMC_SCER_PCK0 << ul_id;
1033 }
1034 
1039 {
1040  PMC->PMC_SCER = PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2;
1041 }
1042 
1047 {
1048  PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2;
1049 }
1050 
1059 uint32_t pmc_is_pck_enabled(uint32_t ul_id)
1060 {
1061  if (ul_id > 2) {
1062  return 0;
1063  }
1064 
1065  return (PMC->PMC_SCSR & (PMC_SCSR_PCK0 << ul_id));
1066 }
1067 
1068 #if (SAM4C || SAM4CM || SAM4CP)
1069 
1072 void pmc_enable_cpck(void)
1073 {
1074  PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD;
1075 }
1076 
1080 void pmc_disable_cpck(void)
1081 {
1082  PMC->PMC_SCDR = PMC_SCDR_CPCK | PMC_SCDR_CPKEY_PASSWD;
1083 }
1084 
1091 bool pmc_is_cpck_enabled(void)
1092 {
1093  if(PMC->PMC_SCSR & PMC_SCSR_CPCK) {
1094  return 1;
1095  } else {
1096  return 0;
1097  }
1098 }
1099 
1103 void pmc_enable_cpbmck(void)
1104 {
1105  PMC->PMC_SCER = PMC_SCER_CPBMCK | PMC_SCER_CPKEY_PASSWD;
1106 }
1107 
1111 void pmc_disable_cpbmck(void)
1112 {
1113  PMC->PMC_SCDR = PMC_SCDR_CPBMCK | PMC_SCDR_CPKEY_PASSWD;
1114 }
1115 
1122 bool pmc_is_cpbmck_enabled(void)
1123 {
1124  if(PMC->PMC_SCSR & PMC_SCSR_CPBMCK) {
1125  return 1;
1126  } else {
1127  return 0;
1128  }
1129 }
1130 
1136 void pmc_cpck_set_prescaler(uint32_t ul_pres)
1137 {
1138  PMC->PMC_MCKR =
1139  (PMC->PMC_MCKR & (~PMC_MCKR_CPPRES_Msk)) | PMC_MCKR_CPPRES(ul_pres);
1140 }
1141 
1147 void pmc_cpck_set_source(uint32_t ul_source)
1148 {
1149  PMC->PMC_MCKR =
1150  (PMC->PMC_MCKR & (~PMC_MCKR_CPCSS_Msk)) | ul_source;
1151 }
1152 #endif
1153 
1154 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
1155 
1160 void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv)
1161 {
1162  PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv);
1163 }
1164 #endif
1165 
1166 #if (SAM3S || SAM4S || SAMG55)
1167 
1172 void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv)
1173 {
1174  PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS;
1175 }
1176 #endif
1177 
1178 #if (SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70)
1179 
1184 void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv)
1185 {
1186  PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(ul_usbdiv);
1187 }
1188 #endif
1189 
1190 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
1191 
1194 void pmc_enable_udpck(void)
1195 {
1196 #if (SAM3S || SAM4S || SAM4E || SAMG55)
1197  PMC->PMC_SCER = PMC_SCER_UDP;
1198 #elif (SAMV71 || SAMV70 || SAME70 || SAMS70)
1199  PMC->PMC_SCER = PMC_SCER_USBCLK;
1200 #else
1201  PMC->PMC_SCER = PMC_SCER_UOTGCLK;
1202 # endif
1203 }
1204 
1208 void pmc_disable_udpck(void)
1209 {
1210 #if (SAM3S || SAM4S || SAM4E || SAMG55)
1211  PMC->PMC_SCDR = PMC_SCDR_UDP;
1212 #elif (SAMV71 || SAMV70 || SAME70 || SAMS70)
1213  PMC->PMC_SCDR = PMC_SCDR_USBCLK;
1214 #else
1215  PMC->PMC_SCDR = PMC_SCDR_UOTGCLK;
1216 # endif
1217 }
1218 #endif
1219 
1220 #if SAMG55
1221 
1226 void pmc_switch_uhpck_to_pllack(uint32_t ul_usbdiv)
1227 {
1228  PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv);
1229 }
1230 
1236 void pmc_switch_uhpck_to_pllbck(uint32_t ul_usbdiv)
1237 {
1238  PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS;
1239 }
1240 
1244 void pmc_enable_uhpck(void)
1245 {
1246  PMC->PMC_SCER = PMC_SCER_UHP;
1247 }
1248 #endif
1249 
1255 void pmc_enable_interrupt(uint32_t ul_sources)
1256 {
1257  PMC->PMC_IER = ul_sources;
1258 }
1259 
1265 void pmc_disable_interrupt(uint32_t ul_sources)
1266 {
1267  PMC->PMC_IDR = ul_sources;
1268 }
1269 
1276 {
1277  return PMC->PMC_IMR;
1278 }
1279 
1285 uint32_t pmc_get_status(void)
1286 {
1287  return PMC->PMC_SR;
1288 }
1289 
1296 void pmc_set_fast_startup_input(uint32_t ul_inputs)
1297 {
1298  ul_inputs &= PMC_FAST_STARTUP_Msk;
1299  PMC->PMC_FSMR |= ul_inputs;
1300 }
1301 
1308 void pmc_clr_fast_startup_input(uint32_t ul_inputs)
1309 {
1310  ul_inputs &= PMC_FAST_STARTUP_Msk;
1311  PMC->PMC_FSMR &= ~ul_inputs;
1312 }
1313 
1314 #if (SAM4C || SAM4CM || SAM4CP)
1315 
1321 void pmc_cp_set_fast_startup_input(uint32_t ul_inputs)
1322 {
1323  ul_inputs &= PMC_FAST_STARTUP_Msk;
1324  PMC->PMC_CPFSMR |= ul_inputs;
1325 }
1326 
1333 void pmc_cp_clr_fast_startup_input(uint32_t ul_inputs)
1334 {
1335  ul_inputs &= PMC_FAST_STARTUP_Msk;
1336  PMC->PMC_CPFSMR &= ~ul_inputs;
1337 }
1338 #endif
1339 
1348 void pmc_enable_sleepmode(uint8_t uc_type)
1349 {
1350 #if !(SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
1351  PMC->PMC_FSMR &= (uint32_t) ~ PMC_FSMR_LPM; // Enter Sleep mode
1352 #endif
1353  SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep
1354 
1355 #if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
1356  UNUSED(uc_type);
1357  __DSB();
1358  __WFI();
1359 #else
1360  if (uc_type == 0) {
1361  __DSB();
1362  __WFI();
1363  } else {
1364  __DSB();
1365  __WFE();
1366  }
1367 #endif
1368 }
1369 
1370 #if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
1371 static uint32_t ul_flash_in_wait_mode = PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN;
1378 void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state)
1379 {
1380  ul_flash_in_wait_mode = ul_flash_state;
1381 }
1382 
1391 void pmc_enable_waitmode(void)
1392 {
1393  uint32_t i;
1394 
1395  /* Flash in wait mode */
1396  i = PMC->PMC_FSMR;
1397  i &= ~PMC_FSMR_FLPM_Msk;
1398 #if !(SAMV71 || SAMV70 || SAME70 || SAMS70)
1399  i |= ul_flash_in_wait_mode;
1400 #else
1401  (void)ul_flash_in_wait_mode;
1402  i |= PMC_WAIT_MODE_FLASH_IDLE;
1403 #endif
1404  PMC->PMC_FSMR = i;
1405 
1406  /* Set the WAITMODE bit = 1 */
1407  PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_WAITMODE;
1408 
1409  /* Waiting for Master Clock Ready MCKRDY = 1 */
1410  while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
1411 
1412  /* Waiting for MOSCRCEN bit cleared is strongly recommended
1413  * to ensure that the core will not execute undesired instructions
1414  */
1415  for (i = 0; i < 500; i++) {
1416  __NOP();
1417  }
1418  while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));
1419 
1420 #if (!SAMG)
1421  /* Restore Flash in idle mode */
1422  i = PMC->PMC_FSMR;
1423  i &= ~PMC_FSMR_FLPM_Msk;
1424  i |= PMC_WAIT_MODE_FLASH_IDLE;
1425  PMC->PMC_FSMR = i;
1426 #endif
1427 }
1428 #else
1429 
1434 {
1435  uint32_t i;
1436 
1437  PMC->PMC_FSMR |= PMC_FSMR_LPM; /* Enter Wait mode */
1438  SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; /* Deep sleep */
1439 
1440  __DSB();
1441  __WFE();
1442 
1443  /* Waiting for MOSCRCEN bit cleared is strongly recommended
1444  * to ensure that the core will not execute undesired instructions
1445  */
1446  for (i = 0; i < 500; i++) {
1447  __NOP();
1448  }
1449  while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));
1450 
1451 }
1452 #endif
1453 
1454 #if (!(SAMG51 || SAMG53 || SAMG54))
1455 
1460 {
1461 #if (SAM4C || SAM4CM || SAM4CP)
1462  uint32_t tmp = SUPC->SUPC_MR & ~(SUPC_MR_BUPPOREN | SUPC_MR_KEY_Msk);
1463  SUPC->SUPC_MR = tmp | SUPC_MR_KEY_PASSWD;
1464  while (SUPC->SUPC_SR & SUPC_SR_BUPPORS);
1465 #endif
1466  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
1467 #if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
1469  uint32_t ul_dummy = SUPC->SUPC_MR;
1470  UNUSED(ul_dummy);
1471  __DSB();
1472  __WFE();
1473  __WFI();
1474 #else
1475  __DSB();
1476  __WFE();
1477 #endif
1478 }
1479 #endif
1480 
1485 {
1486  uint32_t ul_reg = PMC->CKGR_MOR;
1487 
1488  PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_CFDEN | ul_reg;
1489 }
1490 
1495 {
1496  uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN);
1497 
1498  PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg;
1499 }
1500 
1501 #if (SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
1502 
1505 void pmc_enable_sclk_osc_freq_monitor(void)
1506 {
1507  uint32_t ul_reg = PMC->CKGR_MOR;
1508 
1509  PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_XT32KFME | ul_reg;
1510 }
1511 
1515 void pmc_disable_sclk_osc_freq_monitor(void)
1516 {
1517  uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_XT32KFME);
1518 
1519  PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg;
1520 }
1521 #endif
1522 
1528 void pmc_set_writeprotect(uint32_t ul_enable)
1529 {
1530  if (ul_enable) {
1531  PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD | PMC_WPMR_WPEN;
1532  } else {
1533  PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD;
1534  }
1535 }
1536 
1543 {
1544  return PMC->PMC_WPSR;
1545 }
1546 
1547 #if (SAMG53 || SAMG54 || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
1548 
1558 uint32_t pmc_enable_sleepwalking(uint32_t ul_id)
1559 {
1560  uint32_t temp;
1561 #if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
1562  if ((7 <= ul_id) && (ul_id<= 29)) {
1563 #else
1564  if ((8 <= ul_id) && (ul_id<= 29)) {
1565 #endif
1566  temp = pmc_get_active_status0();
1567  if (temp & (1 << ul_id)) {
1568  return 1;
1569  }
1570  PMC->PMC_SLPWK_ER0 = 1 << ul_id;
1571  temp = pmc_get_active_status0();
1572  if (temp & (1 << ul_id)) {
1573  pmc_disable_sleepwalking(ul_id);
1574  return 1;
1575  }
1576  return 0;
1577  }
1578 #if (SAMV71 || SAMV70 || SAME70 || SAMS70)
1579  else if ((32 <= ul_id) && (ul_id<= 60)) {
1580  ul_id -= 32;
1581  temp = pmc_get_active_status1();
1582  if (temp & (1 << ul_id)) {
1583  return 1;
1584  }
1585  PMC->PMC_SLPWK_ER1 = 1 << ul_id;
1586  temp = pmc_get_active_status1();
1587  if (temp & (1 << ul_id)) {
1588  pmc_disable_sleepwalking(ul_id);
1589  return 1;
1590  }
1591  return 0;
1592  }
1593 #endif
1594  else {
1595  return 1;
1596  }
1597 }
1598 
1609 uint32_t pmc_disable_sleepwalking(uint32_t ul_id)
1610 {
1611 #if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
1612  if ((7 <= ul_id) && (ul_id<= 29)) {
1613 #else
1614  if ((8 <= ul_id) && (ul_id<= 29)) {
1615 #endif
1616  PMC->PMC_SLPWK_DR0 = 1 << ul_id;
1617  return 0;
1618  }
1619 #if (SAMV71 || SAMV70 || SAME70 || SAMS70)
1620  else if ((32 <= ul_id) && (ul_id<= 60)) {
1621  ul_id -= 32;
1622  PMC->PMC_SLPWK_DR1 = 1 << ul_id;
1623  return 0;
1624  }
1625 #endif
1626  else {
1627  return 1;
1628  }
1629 }
1630 
1636 uint32_t pmc_get_sleepwalking_status0(void)
1637 {
1638  return PMC->PMC_SLPWK_SR0;
1639 }
1640 
1646 uint32_t pmc_get_active_status0(void)
1647 {
1648  return PMC->PMC_SLPWK_ASR0;
1649 }
1650 
1651 #endif
1652 
1653 #if (SAMV71 || SAMV70 || SAME70 || SAMS70)
1654 
1659 uint32_t pmc_get_sleepwalking_status1(void)
1660 {
1661  return PMC->PMC_SLPWK_SR1;
1662 }
1663 
1669 uint32_t pmc_get_active_status1(void)
1670 {
1671  return PMC->PMC_SLPWK_ASR1;
1672 }
1673 #endif
1674 
1676 
1677 #ifdef __cplusplus
1678 }
1679 #endif
1680 
1681 
void pmc_disable_all_periph_clk(void)
Disable all peripheral clocks.
Definition: pmc.c:776
#define CKGR_MOR_MOSCSEL
(CKGR_MOR) Main Oscillator Selection
void pmc_disable_clock_failure_detector(void)
Disable Clock Failure Detector.
Definition: pmc.c:1494
uint32_t pmc_get_writeprotect_status(void)
Return write protect status.
Definition: pmc.c:1542
#define PMC_FSMR_FLPM_Msk
(PMC_FSMR) Flash Low-power Mode
#define CKGR_MOR_WAITMODE
(CKGR_MOR) Wait Mode Command (Write-only)
#define CKGR_MOR_MOSCXTBY
(CKGR_MOR) Main Crystal Oscillator Bypass
void pmc_switch_mainck_to_xtal(uint32_t ul_bypass, uint32_t ul_xtal_startup_time)
Switch main clock source selection to external Xtal/Bypass.
Definition: pmc.c:485
#define PMC
(PMC ) Base Address
Definition: same70j19.h:524
uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres)
Switch programmable clock source selection to slow clock.
Definition: pmc.c:874
uint32_t pmc_osc_is_ready_32kxtal(void)
Check if the external 32k Xtal is ready.
Definition: pmc.c:336
#define CKGR_MOR_MOSCRCF_Msk
(CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection
void pmc_disable_all_pck(void)
Disable all programmable clocks.
Definition: pmc.c:1046
#define UNUSED(v)
Marking v as a unused parameter or value.
Definition: compiler.h:86
#define SUPC_MR_OSCBYPASS
(SUPC_MR) Oscillator Bypass
#define CKGR_UCKR_UPLLCOUNT(value)
void pmc_enable_sleepmode(uint8_t uc_type)
Enable Sleep Mode. Enter condition: (WFE or WFI) + (SLEEPDEEP bit = 0) + (LPM bit = 0) ...
Definition: pmc.c:1348
#define PMC_PCK_PRES_Msk
(PMC_PCK[8]) Programmable Clock Prescaler
void pmc_enable_pck(uint32_t ul_id)
Enable the specified programmable clock.
Definition: pmc.c:1020
#define PMC_MCKR_CSS_SLOW_CLK
(PMC_MCKR) Slow Clock is selected
#define SCB_SCR_SLEEPDEEP_Msk
Definition: core_cm7.h:544
#define CKGR_MOR_MOSCRCEN
(CKGR_MOR) Main On-Chip RC Oscillator Enable
#define PMC_MCKR_MDIV_PCK_DIV4
(PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4.
void pmc_osc_bypass_main_xtal(void)
Bypass main XTAL.
Definition: pmc.c:430
uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres)
Switch master clock source selection to PLLA clock.
Definition: pmc.c:218
#define CKGR_PLLAR_MULA(value)
void pmc_enable_waitmode(void)
Enable Wait Mode. Enter condition: WFE + (SLEEPDEEP bit = 0) + (LPM bit = 1)
Definition: pmc.c:1433
#define CKGR_MOR_XT32KFME
(CKGR_MOR) Slow Crystal Oscillator Frequency Monitoring Enable
#define CKGR_UCKR_UPLLEN
(CKGR_UCKR) UTMI PLL Enable
#define PMC_SR_MOSCXTS
(PMC_SR) Main Crystal Oscillator Status
void pmc_disable_interrupt(uint32_t ul_sources)
Disable PMC interrupts.
Definition: pmc.c:1265
#define PMC_PCK_CSS_UPLL_CLK
(PMC_PCK[8]) Divided UPLL Clock is selected
uint32_t pmc_is_pck_enabled(uint32_t ul_id)
Check if the specified programmable clock is enabled.
Definition: pmc.c:1059
#define PMC_MCKR_MDIV_PCK_DIV3
(PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3.
#define SUPC_CR_XTALSEL
(SUPC_CR) Crystal Oscillator Select
void pmc_osc_disable_main_xtal(void)
Disable the main Xtal.
Definition: pmc.c:443
void pmc_mck_set_prescaler(uint32_t ul_pres)
Set the prescaler of the MCK.
Definition: pmc.c:96
#define PMC_USB_USBDIV(value)
#define PMC_MASK_STATUS1
uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres)
Switch master clock source selection to slow clock.
Definition: pmc.c:154
void pmc_enable_clock_failure_detector(void)
Enable Clock Failure Detector.
Definition: pmc.c:1484
uint32_t pmc_disable_periph_clk(uint32_t ul_id)
Disable the specified peripheral clock.
Definition: pmc.c:722
uint32_t pmc_enable_periph_clk(uint32_t ul_id)
Enable the specified peripheral clock.
Definition: pmc.c:682
void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass)
Switch slow clock source selection to external 32k (Xtal or Bypass).
Definition: pmc.c:319
uint32_t pmc_osc_is_ready_main_xtal(void)
Check if the main crystal is ready.
Definition: pmc.c:467
void pmc_enable_all_periph_clk(void)
Enable all peripheral clocks.
Definition: pmc.c:755
#define PMC_SCDR_USBCLK
(PMC_SCDR) Disable USB FS Clock
#define PMC_SR_MOSCRCS
(PMC_SR) Main On-Chip RC Oscillator Status
#define PMC_SCDR_PCK0
(PMC_SCDR) Programmable Clock 0 Output Disable
#define PMC_WPMR_WPEN
(PMC_WPMR) Write Protection Enable
#define PMC_FAST_STARTUP_Msk
#define PMC_PCK_CSS_SLOW_CLK
(PMC_PCK[8]) Slow Clock is selected
uint32_t pmc_osc_is_ready_mainck(void)
Check if the MAINCK is ready. Depending on MOSCEL, MAINCK can be one of Xtal, bypass or internal RC...
Definition: pmc.c:528
void pmc_set_writeprotect(uint32_t ul_enable)
Enable or disable write protect of PMC registers.
Definition: pmc.c:1528
void pmc_disable_pck(uint32_t ul_id)
Disable the specified programmable clock.
Definition: pmc.c:1030
void pmc_enable_all_pck(void)
Enable all programmable clocks.
Definition: pmc.c:1038
void pmc_enable_interrupt(uint32_t ul_sources)
Enable PMC interrupts.
Definition: pmc.c:1255
#define PMC_FSMR_LPM
(PMC_FSMR) Low-power Mode
#define PMC_SCER_PCK1
(PMC_SCER) Programmable Clock 1 Output Enable
#define SCB
Definition: core_cm7.h:1599
void pmc_set_fast_startup_input(uint32_t ul_inputs)
Set the wake-up inputs for fast startup mode registers (event generation).
Definition: pmc.c:1296
#define PMC_MASK_STATUS0
void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva)
Enable PLLA clock.
Definition: pmc.c:558
#define PMC_SR_PCKRDY0
(PMC_SR) Programmable Clock Ready Status
#define PMC_MCKR_MDIV_PCK_DIV2
(PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2.
#define PMC_PCK_CSS_PLLA_CLK
(PMC_PCK[8]) PLLA Clock is selected
void pmc_clr_fast_startup_input(uint32_t ul_inputs)
Clear the wake-up inputs for fast startup mode registers (remove event generation).
Definition: pmc.c:1308
#define PMC_MCKR_CSS_MAIN_CLK
(PMC_MCKR) Main Clock is selected
uint32_t pmc_is_locked_pllack(void)
Is PLLA locked?
Definition: pmc.c:591
void pmc_mainck_osc_select(uint32_t ul_xtal_rc)
Select Main Crystal or internal RC as main clock source.
Definition: pmc.c:540
#define PMC_SCER_PCK0
(PMC_SCER) Programmable Clock 0 Output Enable
#define CKGR_PLLAR_ONE
(CKGR_PLLAR) Must Be Set to 1
#define CKGR_MOR_MOSCXTEN
(CKGR_MOR) Main Crystal Oscillator Enable
uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres)
Switch programmable clock source selection to PLLA clock.
Definition: pmc.c:922
uint32_t pmc_get_status(void)
Get current status.
Definition: pmc.c:1285
#define PMC_PCK_CSS_MAIN_CLK
(PMC_PCK[8]) Main Clock is selected
#define CKGR_PLLAR_DIVA(value)
void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source)
Set the source oscillator for the specified programmable clock.
Definition: pmc.c:857
#define PMC_SCDR_PCK2
(PMC_SCDR) Programmable Clock 2 Output Disable
#define PMC_SR_LOCKA
(PMC_SR) PLLA Lock Status
#define PMC_PCK_CSS_Msk
(PMC_PCK[8]) Programmable Clock Source Selection
void pmc_enable_backupmode(void)
Enable Backup Mode. Enter condition: WFE/(VROFF bit = 1) + (SLEEPDEEP bit = 1)
Definition: pmc.c:1459
#define PMC_SR_MOSCSELS
(PMC_SR) Main Oscillator Selection Status
void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf)
Switch main clock source selection to internal fast RC.
Definition: pmc.c:351
void pmc_osc_disable_xtal(uint32_t ul_bypass)
Disable the external Xtal.
Definition: pmc.c:509
#define PMC_SR_MCKRDY
(PMC_SR) Master Clock Status
#define PMC_PCR_EN
(PMC_PCR) Enable
uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres)
Switch programmable clock source selection to mck.
Definition: pmc.c:1000
#define CKGR_PLLAR_PLLACOUNT(value)
#define PMC_PCK_CSS_MCK
(PMC_PCK[8]) Master Clock is selected
#define PMC_TIMEOUT
void pmc_mck_set_source(uint32_t ul_source)
Set the source of the MCK.
Definition: pmc.c:139
#define PMC_MCKR_CSS_PLLA_CLK
(PMC_MCKR) PLLA Clock is selected
#define PMC_SCDR_PCK1
(PMC_SCDR) Programmable Clock 1 Output Disable
#define SUPC_MR_KEY_PASSWD
#define SUPC
(SUPC ) Base Address
Definition: same70j19.h:533
#define SUPC_MR_KEY_Msk
(SUPC_MR) Password Key
#define CKGR_MOR_MOSCXTST(value)
void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time)
Enable main XTAL oscillator.
Definition: pmc.c:416
uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres)
Switch master clock source selection to main clock.
Definition: pmc.c:186
#define PMC_SR_LOCKU
(PMC_SR) UTMI PLL Lock Status
#define PMC_USB_USBS
(PMC_USB) USB Input Clock Selection
uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres)
Switch programmable clock source selection to main clock.
Definition: pmc.c:898
#define PMC_MCKR_PRES_Msk
(PMC_MCKR) Processor Clock Prescaler
#define PMC_MCKR_MDIV_EQ_PCK
(PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1.
void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres)
Set the prescaler for the specified programmable clock.
Definition: pmc.c:843
#define PMC_MCKR_CSS_UPLL_CLK
(PMC_MCKR) Divided UPLL Clock is selected
uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id)
Check if the specified peripheral clock is enabled.
Definition: pmc.c:804
#define SUPC_CR_KEY_PASSWD
Power Management Controller (PMC) driver for SAM.
void pmc_osc_disable_fastrc(void)
Disable the internal fast RC.
Definition: pmc.c:393
#define CKGR_MOR_CFDEN
(CKGR_MOR) Clock Failure Detector Enable
#define SUPC_CR_VROFF_STOP_VREG
(SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator...
#define PMC_SCER_USBCLK
(PMC_SCER) Enable USB FS Clock
#define PMC_PCR_CMD
(PMC_PCR) Command
#define PMC_WPMR_WPKEY_PASSWD
void pmc_osc_enable_fastrc(uint32_t ul_rc)
Enable fast RC oscillator.
Definition: pmc.c:376
uint32_t pmc_osc_is_bypassed_main_xtal(void)
Check if the main crystal is bypassed.
Definition: pmc.c:455
uint32_t pmc_get_interrupt_mask(void)
Get PMC interrupt mask.
Definition: pmc.c:1275
#define PMC_MCKR_CSS_Msk
(PMC_MCKR) Master Clock Source Selection
#define PMC_SR_OSCSELS
(PMC_SR) Slow Clock Oscillator Selection
uint32_t pmc_osc_is_ready_fastrc(void)
Check if the main fastrc is ready.
Definition: pmc.c:406
#define PMC_SCER_PCK2
(PMC_SCER) Programmable Clock 2 Output Enable
void pmc_disable_pllack(void)
Disable PLLA clock.
Definition: pmc.c:576
#define SUPC_SR_OSCSEL
(SUPC_SR) 32-kHz Oscillator Selection Status
#define PMC_SCSR_PCK0
(PMC_SCSR) Programmable Clock 0 Output Status
#define PMC_MCKR_MDIV_Msk
(PMC_MCKR) Master Clock Division
#define CKGR_MOR_KEY_PASSWD


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:04