drivers/mcan/mcan.h
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1 
33 /*
34  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
35  */
36 
37 #ifndef MCAN_H_INCLUDED
38 #define MCAN_H_INCLUDED
39 
40 #include <compiler.h>
41 #include <conf_mcan.h>
42 #include "status_codes.h"
48 /* -------- MCAN_RX_ELEMENT_R0 : (MCAN RX element: 0x00) (R/W 32) Rx Element R0 Configuration -------- */
49 typedef union {
50  struct {
51  /* bit: 0..28 Identifier */
52  uint32_t ID:29;
53  /* bit: 29 Remote Transmission Request */
54  uint32_t RTR:1;
55  /* bit: 30 Extended Identifier */
56  uint32_t XTD:1;
57  /* bit: 31 Error State Indicator */
58  uint32_t ESI:1;
59  } bit;
60  /* Type used for register access */
61  uint32_t reg;
63 
64 #define MCAN_RX_ELEMENT_R0_ID_Pos 0
65 #define MCAN_RX_ELEMENT_R0_ID_Msk (0x1FFFFFFFul << MCAN_RX_ELEMENT_R0_ID_Pos)
66 #define MCAN_RX_ELEMENT_R0_ID(value) ((MCAN_RX_ELEMENT_R0_ID_Msk & ((value) << MCAN_RX_ELEMENT_R0_ID_Pos)))
67 #define MCAN_RX_ELEMENT_R0_RTR_Pos 29
68 #define MCAN_RX_ELEMENT_R0_RTR (0x1ul << MCAN_RX_ELEMENT_R0_RTR_Pos)
69 #define MCAN_RX_ELEMENT_R0_XTD_Pos 30
70 #define MCAN_RX_ELEMENT_R0_XTD (0x1ul << MCAN_RX_ELEMENT_R0_XTD_Pos)
71 #define MCAN_RX_ELEMENT_R0_ESI_Pos 31
72 #define MCAN_RX_ELEMENT_R0_ESI (0x1ul << MCAN_RX_ELEMENT_R0_ESI_Pos)
73 
74 /* -------- MCAN_RX_ELEMENT_R1 : (MCAN RX element: 0x01) (R/W 32) Rx Element R1 Configuration -------- */
75 typedef union {
76  struct {
77  /* bit: 0..15 Rx Timestamp */
78  uint32_t RXTS:16;
79  /* bit: 16..19 Data Length Code */
80  uint32_t DLC:4;
81  /* bit: 20 Bit Rate Switch */
82  uint32_t BRS:1;
83  /* bit: 21 FD Format */
84  uint32_t EDL:1;
85  /* bit: 22..23 Reserved */
86  uint32_t :2;
87  /* bit: 24..30 Filter Index */
88  uint32_t FIDX:7;
89  /* bit: 31 Accepted Non-matching Frame */
90  uint32_t ANMF:1;
91  } bit;
92  /* Type used for register access */
93  uint32_t reg;
95 
96 #define MCAN_RX_ELEMENT_R1_RXTS_Pos 0
97 #define MCAN_RX_ELEMENT_R1_RXTS_Msk (0xFFFFul << MCAN_RX_ELEMENT_R1_RXTS_Pos)
98 #define MCAN_RX_ELEMENT_R1_RXTS(value) ((MCAN_RX_ELEMENT_R1_RXTS_Msk & ((value) << MCAN_RX_ELEMENT_R1_RXTS_Pos)))
99 #define MCAN_RX_ELEMENT_R1_DLC_Pos 16
100 #define MCAN_RX_ELEMENT_R1_DLC_Msk (0xFul << MCAN_RX_ELEMENT_R1_DLC_Pos)
101 #define MCAN_RX_ELEMENT_R1_DLC(value) ((MCAN_RX_ELEMENT_R1_DLC_Msk & ((value) << MCAN_RX_ELEMENT_R1_DLC_Pos)))
102 #define MCAN_RX_ELEMENT_R1_BRS_Pos 20
103 #define MCAN_RX_ELEMENT_R1_BRS (0x1ul << MCAN_RX_ELEMENT_R1_BRS_Pos)
104 #define MCAN_RX_ELEMENT_R1_FDF_Pos 21
105 #define MCAN_RX_ELEMENT_R1_FDF (0x1ul << MCAN_RX_ELEMENT_R1_FDF_Pos)
106 #define MCAN_RX_ELEMENT_R1_FIDX_Pos 24
107 #define MCAN_RX_ELEMENT_R1_FIDX_Msk (0x7Ful << MCAN_RX_ELEMENT_R1_FIDX_Pos)
108 #define MCAN_RX_ELEMENT_R1_FIDX(value) ((MCAN_RX_ELEMENT_R1_FIDX_Msk & ((value) << MCAN_RX_ELEMENT_R1_FIDX_Pos)))
109 #define MCAN_RX_ELEMENT_R1_ANMF_Pos 31
110 #define MCAN_RX_ELEMENT_R1_ANMF (0x1ul << MCAN_RX_ELEMENT_R1_ANMF_Pos)
111 
119 };
120 
128 };
129 
137 };
138 
139 /* -------- MCAN_TX_ELEMENT_T0 : (MCAN TX element: 0x00) (R/W 32) Tx Element T0 Configuration -------- */
140 typedef union {
141  struct {
142  /* bit: 0..28 Identifier */
143  uint32_t ID:29;
144  /* bit: 29 Remote Transmission Request */
145  uint32_t RTR:1;
146  /* bit: 30 Extended Identifier */
147  uint32_t XTD:1;
148 #if (SAMV71B || SAME70B || SAMV70B)
149  /* bit: 31 Error State Indicator */
150  uint32_t ESI:1;
151 #else
152  /* bit: 31 Reserved */
153  uint32_t :1;
154 #endif
155  } bit;
156  /* Type used for register access */
157  uint32_t reg;
159 
160 #define MCAN_TX_ELEMENT_T0_EXTENDED_ID_Pos 0
161 #define MCAN_TX_ELEMENT_T0_EXTENDED_ID_Msk (0x1FFFFFFFul << MCAN_TX_ELEMENT_T0_EXTENDED_ID_Pos)
162 #define MCAN_TX_ELEMENT_T0_EXTENDED_ID(value) ((MCAN_TX_ELEMENT_T0_EXTENDED_ID_Msk & ((value) << MCAN_TX_ELEMENT_T0_EXTENDED_ID_Pos)))
163 #define MCAN_TX_ELEMENT_T0_STANDARD_ID_Pos 18
164 #define MCAN_TX_ELEMENT_T0_STANDARD_ID_Msk (0x7FFul << MCAN_TX_ELEMENT_T0_STANDARD_ID_Pos)
165 #define MCAN_TX_ELEMENT_T0_STANDARD_ID(value) ((MCAN_TX_ELEMENT_T0_STANDARD_ID_Msk & ((value) << MCAN_TX_ELEMENT_T0_STANDARD_ID_Pos)))
166 #define MCAN_TX_ELEMENT_T0_RTR_Pos 29
167 #define MCAN_TX_ELEMENT_T0_RTR (0x1ul << MCAN_TX_ELEMENT_T0_RTR_Pos)
168 #define MCAN_TX_ELEMENT_T0_XTD_Pos 30
169 #define MCAN_TX_ELEMENT_T0_XTD (0x1ul << MCAN_TX_ELEMENT_T0_XTD_Pos)
170 #if (SAMV71B || SAME70B || SAMV70B)
171 #define MCAN_TX_ELEMENT_T0_ESI_Pos 31
172 #define MCAN_TX_ELEMENT_T0_ESI (0x1ul << MCAN_TX_ELEMENT_T0_ESI_Pos)
173 #endif
174 
175 /* -------- MCAN_TX_ELEMENT_T1 : (MCAN TX element: 0x01) (R/W 32) Tx Element T1 Configuration -------- */
176 typedef union {
177  struct {
178  /* bit: 0..15 Reserved */
179  uint32_t :16;
180  /* bit: 16..19 Data Length Code */
181  uint32_t DLC:4;
182 #if (SAMV71B || SAME70B || SAMV70B)
183  /* bit: 20 Bit Rate Switch */
184  uint32_t BRS:1;
185  /* bit: 21 FD Format */
186  uint32_t FDF:1;
187  /* bit: 22 Reserved */
188  uint32_t :1;
189 #else
190  /* bit: 20..22 Reserved */
191  uint32_t :3;
192 #endif
193  /* bit: 23 Event FIFO Control */
194  uint32_t EFCC:1;
195  /* bit: 24..31 Message Marker */
196  uint32_t MM:8;
197  } bit;
198  /* Type used for register access */
199  uint32_t reg;
201 
202 #define MCAN_TX_ELEMENT_T1_DLC_Pos 16
203 #define MCAN_TX_ELEMENT_T1_DLC_Msk (0xFul << MCAN_TX_ELEMENT_T1_DLC_Pos)
204 #define MCAN_TX_ELEMENT_T1_DLC(value) ((MCAN_TX_ELEMENT_T1_DLC_Msk & ((value) << MCAN_TX_ELEMENT_T1_DLC_Pos)))
205 
206 #define MCAN_TX_ELEMENT_T1_DLC_DATA8_Val 0x8ul
208 #define MCAN_TX_ELEMENT_T1_DLC_DATA12_Val 0x9ul
210 #define MCAN_TX_ELEMENT_T1_DLC_DATA16_Val 0xAul
212 #define MCAN_TX_ELEMENT_T1_DLC_DATA20_Val 0xBul
214 #define MCAN_TX_ELEMENT_T1_DLC_DATA24_Val 0xCul
216 #define MCAN_TX_ELEMENT_T1_DLC_DATA32_Val 0xDul
218 #define MCAN_TX_ELEMENT_T1_DLC_DATA48_Val 0xEul
220 #define MCAN_TX_ELEMENT_T1_DLC_DATA64_Val 0xFul
221 #if (SAMV71B || SAME70B || SAMV70B)
222 #define MCAN_TX_ELEMENT_T1_BRS_Pos 20
223 #define MCAN_TX_ELEMENT_T1_BRS (0x1ul << MCAN_TX_ELEMENT_T1_BRS_Pos)
224 #define MCAN_TX_ELEMENT_T1_FDF_Pos 21
225 #define MCAN_TX_ELEMENT_T1_FDF (0x1ul << MCAN_TX_ELEMENT_T1_FDF_Pos)
226 #endif
227 #define MCAN_TX_ELEMENT_T1_EFC_Pos 23
228 #define MCAN_TX_ELEMENT_T1_EFC (0x1ul << MCAN_TX_ELEMENT_T1_EFC_Pos)
229 #define MCAN_TX_ELEMENT_T1_MM_Pos 24
230 #define MCAN_TX_ELEMENT_T1_MM_Msk (0xFFul << MCAN_TX_ELEMENT_T1_MM_Pos)
231 #define MCAN_TX_ELEMENT_T1_MM(value) ((MCAN_TX_ELEMENT_T1_MM_Msk & ((value) << MCAN_TX_ELEMENT_T1_MM_Pos)))
238 struct mcan_tx_element {
242 };
243 
244 /* -------- MCAN_TX_EVENT_ELEMENT_E0 : (MCAN TX event element: 0x00) (R/W 32) Tx Event Element E0 Configuration -------- */
245 typedef union {
246  struct {
247  /* bit: 0..28 Identifier */
248  uint32_t ID:29;
249  /* bit: 29 Remote Transmission Request */
250  uint32_t RTR:1;
251  /* bit: 30 Extended Identifier */
252  uint32_t XTD:1;
253  /* bit: 31 Error State Indicator */
254  uint32_t ESI:1;
255  } bit;
256  /* Type used for register access */
257  uint32_t reg;
259 
260 #define MCAN_TX_EVENT_ELEMENT_E0_ID_Pos 0
261 #define MCAN_TX_EVENT_ELEMENT_E0_ID_Msk (0x1FFFFFFFul << MCAN_TX_EVENT_ELEMENT_E0_ID_Pos)
262 #define MCAN_TX_EVENT_ELEMENT_E0_ID(value) ((MCAN_TX_EVENT_ELEMENT_E0_ID_Msk & ((value) << MCAN_TX_EVENT_ELEMENT_E0_ID_Pos)))
263 #define MCAN_TX_EVENT_ELEMENT_E0_RTR_Pos 29
264 #define MCAN_TX_EVENT_ELEMENT_E0_RTR (0x1ul << MCAN_TX_EVENT_ELEMENT_E0_RTR_Pos)
265 #define MCAN_TX_EVENT_ELEMENT_E0_XTD_Pos 30
266 #define MCAN_TX_EVENT_ELEMENT_E0_XTD (0x1ul << MCAN_TX_EVENT_ELEMENT_E0_XTD_Pos)
267 #define MCAN_TX_EVENT_ELEMENT_E0_ESI_Pos 31
268 #define MCAN_TX_EVENT_ELEMENT_E0_ESI (0x1ul << MCAN_TX_EVENT_ELEMENT_E0_ESI_Pos)
270 /* -------- MCAN_TX_EVENT_ELEMENT_E1 : (MCAN TX event element: 0x01) (R/W 32) Tx Event Element E1 Configuration -------- */
271 typedef union {
272  struct {
273  /* bit: 0..15 Tx Timestamp */
274  uint32_t TXTS:16;
275  /* bit: 16..19 Data Length Code */
276  uint32_t DLC:4;
277  /* bit: 20 Bit Rate Switch */
278  uint32_t BRS:1;
279  /* bit: 21 FD Format */
280  uint32_t EDL:1;
281  /* bit: 22..23 Event Type */
282  uint32_t ET:2;
283  /* bit: 24..31 Message Marker */
284  uint32_t MM:8;
285  } bit;
286  /* Type used for register access */
287  uint32_t reg;
289 
290 #define MCAN_TX_EVENT_ELEMENT_E1_TXTS_Pos 0
291 #define MCAN_TX_EVENT_ELEMENT_E1_TXTS_Msk (0xFFFFul << MCAN_TX_EVENT_ELEMENT_E1_TXTS_Pos)
292 #define MCAN_TX_EVENT_ELEMENT_E1_TXTS(value) ((MCAN_TX_EVENT_ELEMENT_E1_TXTS_Msk & ((value) << MCAN_TX_EVENT_ELEMENT_E1_TXTS_Pos)))
293 #define MCAN_TX_EVENT_ELEMENT_E1_DLC_Pos 16
294 #define MCAN_TX_EVENT_ELEMENT_E1_DLC_Msk (0xFul << MCAN_TX_EVENT_ELEMENT_E1_DLC_Pos)
295 #define MCAN_TX_EVENT_ELEMENT_E1_DLC(value) ((MCAN_TX_EVENT_ELEMENT_E1_DLC_Msk & ((value) << MCAN_TX_EVENT_ELEMENT_E1_DLC_Pos)))
296 #define MCAN_TX_EVENT_ELEMENT_E1_BRS_Pos 20
297 #define MCAN_TX_EVENT_ELEMENT_E1_BRS (0x1ul << MCAN_TX_EVENT_ELEMENT_E1_BRS_Pos)
298 #define MCAN_TX_EVENT_ELEMENT_E1_FDF_Pos 21
299 #define MCAN_TX_EVENT_ELEMENT_E1_FDF (0x1ul << MCAN_TX_EVENT_ELEMENT_E1_FDF_Pos)
300 #define MCAN_TX_EVENT_ELEMENT_E1_ET_Pos 22
301 #define MCAN_TX_EVENT_ELEMENT_E1_ET_Msk (0x3ul << MCAN_TX_EVENT_ELEMENT_E1_ET_Pos)
302 #define MCAN_TX_EVENT_ELEMENT_E1_ET(value) ((MCAN_TX_EVENT_ELEMENT_E1_ET_Msk & ((value) << MCAN_TX_EVENT_ELEMENT_E1_ET_Pos)))
303 #define MCAN_TX_EVENT_ELEMENT_E1_MM_Pos 24
304 #define MCAN_TX_EVENT_ELEMENT_E1_MM_Msk (0xFFul << MCAN_TX_EVENT_ELEMENT_E1_MM_Pos)
305 #define MCAN_TX_EVENT_ELEMENT_E1_MM(value) ((MCAN_TX_EVENT_ELEMENT_E1_MM_Msk & ((value) << MCAN_TX_EVENT_ELEMENT_E1_MM_Pos)))
312 struct mcan_tx_event_element {
315 };
316 
317 /* -------- MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0 : (MCAN standard message ID filter element: 0x00) (R/W 32) Standard Message ID Filter Element S0 Configuration -------- */
318 typedef union {
319  struct {
320  /* bit: 0..10 Standard Filter ID 2 */
321  uint32_t SFID2:11;
322  /* bit: 11..15 Reserved */
323  uint32_t :5;
324  /* bit: 16..26 Standard Filter ID 1 */
325  uint32_t SFID1:11;
326  /* bit: 27..29 Standard Filter Element Configuration */
327  uint32_t SFEC:3;
328  /* bit: 30..31 Standard Filter Type */
329  uint32_t SFT:2;
330  } bit;
331  /* Type used for register access */
332  uint32_t reg;
334 
335 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Pos 0
336 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Msk (0x7FFul << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Pos)
337 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2(value) ((MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Msk & ((value) << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Pos)))
338 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Pos 16
339 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Msk (0x7FFul << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Pos)
340 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1(value) ((MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Msk & ((value) << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Pos)))
341 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Pos 27
342 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Msk (0x7ul << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Pos)
343 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC(value) ((MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Msk & ((value) << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Pos)))
344 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_DISABLE_Val 0
345 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_STF0M_Val 1
346 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_STF1M_Val 2
347 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_REJECT_Val 3
348 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_PRIORITY_Val 4
349 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_PRIF0M_Val 5
350 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_PRIF1M_Val 6
351 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_STRXBUF_Val 7
352 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Pos 30
353 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Msk (0x3ul << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Pos)
354 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT(value) ((MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Msk & ((value) << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Pos)))
355 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_RANGE MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT(0)
356 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_DUAL MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT(1)
357 #define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_CLASSIC MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT(2)
366 };
367 
368 /* -------- MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0 : (MCAN extended message ID filter element: 0x00) (R/W 32) Extended Message ID Filter Element F0 Configuration -------- */
369 typedef union {
370  struct {
371  /* bit: 0..28 Extended Filter ID 1 */
372  uint32_t EFID1:29;
373  /* bit: 29..31 Extended Filter Element Configuration */
374  uint32_t EFEC:3;
375  } bit;
376  /* Type used for register access */
377  uint32_t reg;
379 
380 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Pos 0
381 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Msk (0x1FFFFFFFul << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Pos)
382 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1(value) ((MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Msk & ((value) << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Pos)))
383 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Pos 29
384 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Msk (0x7ul << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Pos)
385 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC(value) ((MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Msk & ((value) << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Pos)))
386 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_DISABLE_Val 0
387 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_STF0M_Val 1
388 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_STF1M_Val 2
389 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_REJECT_Val 3
390 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_PRIORITY_Val 4
391 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_PRIF0M_Val 5
392 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_PRIF1M_Val 6
393 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_STRXBUF_Val 7
395 /* -------- MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1 : (MCAN extended message ID filter element: 0x01) (R/W 32) Extended Message ID Filter Element F1 Configuration -------- */
396 typedef union {
397  struct {
398  /* bit: 0..28 Extended Filter ID 2 */
399  uint32_t EFID2:29;
400  /* bit: 29 Reserved */
401  uint32_t :1;
402  /* bit: 30..31 Extended Filter Type */
403  uint32_t EFT:2;
404  } bit;
405  /* Type used for register access */
406  uint32_t reg;
408 
409 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Pos 0
410 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Msk (0x1FFFFFFFul << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Pos)
411 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2(value) ((MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Msk & ((value) << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Pos)))
412 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Pos 30
413 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Msk (0x3ul << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Pos)
414 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(value) ((MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Msk & ((value) << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Pos)))
415 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_RANGEM MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(0)
416 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_DUAL MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(1)
417 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_CLASSIC MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(2)
418 #define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_RANGE MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(3)
428 };
498 #ifdef __cplusplus
499 extern "C" {
500 #endif
501 
510 enum mcan_timeout_mode {
519 };
520 
521 
532 };
533 
543 struct mcan_module {
544 #if !defined(__DOXYGEN__)
545 
546  Mcan *hw;
547 #endif
548 };
549 
557 struct mcan_config {
559  bool run_in_standby;
561  uint8_t watchdog_configuration;
563  bool transmit_pause;
565  bool edge_filtering;
567  bool protocol_exception_handling;
569  bool automatic_retransmission;
571  bool clock_stop_request;
573  bool clock_stop_acknowledge;
575  uint8_t timestamp_prescaler;
577  uint16_t timeout_period;
579  enum mcan_timeout_mode timeout_mode;
581  bool timeout_enable;
583  bool tdc_enable;
585  uint8_t delay_compensation_offset;
586 #if (SAMV71B || SAME70B || SAMV70B)
587 
588  uint8_t delay_compensation_filter_window_length;
589 #endif
590 
591  enum mcan_nonmatching_frames_action nonmatching_frames_action_standard;
593  enum mcan_nonmatching_frames_action nonmatching_frames_action_extended;
595  bool remote_frames_standard_reject;
597  bool remote_frames_extended_reject;
599  uint32_t extended_id_mask;
601  bool rx_fifo_0_overwrite;
603  uint8_t rx_fifo_0_watermark;
605  bool rx_fifo_1_overwrite;
607  uint8_t rx_fifo_1_watermark;
609  bool tx_queue_mode;
611  uint8_t tx_event_fifo_watermark;
612 };
613 
651 static inline void mcan_get_config_defaults(
652  struct mcan_config *const config)
653 {
654  /* Sanity check arguments */
655  Assert(config);
656 
657  /* Default configuration values */
658  config->run_in_standby = false;
659  config->watchdog_configuration = 0x00;
660  config->transmit_pause = true;
661  config->edge_filtering = true;
662  config->protocol_exception_handling = true;
663  config->automatic_retransmission = true;
664  config->clock_stop_request = false;
665  config->clock_stop_acknowledge = false;
666  config->timestamp_prescaler = 0;
667  config->timeout_period = 0xFFFF;
669  config->timeout_enable = false;
670  config->tdc_enable = false;
671  config->delay_compensation_offset = 0;
672 #if (SAMV71B || SAME70B || SAMV70B)
673  config->delay_compensation_filter_window_length = 0;
674 #endif
677  config->remote_frames_standard_reject = true;
678  config->remote_frames_extended_reject = true;
679  config->extended_id_mask = 0x1FFFFFFF;
680  config->rx_fifo_0_overwrite = true;
681  config->rx_fifo_0_watermark = 0;
682  config->rx_fifo_1_overwrite = true;
683  config->rx_fifo_1_watermark = 0;
684  config->tx_queue_mode = false;
685  config->tx_event_fifo_watermark = 0;
686 }
687 
688 void mcan_init(struct mcan_module *const module_inst, Mcan *hw,
689  struct mcan_config *config);
690 void mcan_set_baudrate(Mcan *hw, uint32_t baudrate);
691 void mcan_fd_set_baudrate(Mcan *hw, uint32_t baudrate);
692 void mcan_start(struct mcan_module *const module_inst);
693 void mcan_stop(struct mcan_module *const module_inst);
694 void mcan_enable_fd_mode(struct mcan_module *const module_inst);
695 void mcan_disable_fd_mode(struct mcan_module *const module_inst);
697  struct mcan_module *const module_inst);
699  struct mcan_module *const module_inst);
700 
701 void mcan_enable_bus_monitor_mode(struct mcan_module *const module_inst);
702 void mcan_disable_bus_monitor_mode(struct mcan_module *const module_inst);
703 void mcan_enable_sleep_mode(struct mcan_module *const module_inst);
704 void mcan_disable_sleep_mode(struct mcan_module *const module_inst);
705 void mcan_enable_test_mode(struct mcan_module *const module_inst);
706 void mcan_disable_test_mode(struct mcan_module *const module_inst);
707 
715 static inline uint16_t mcan_read_timestamp_count_value(
716  struct mcan_module *const module_inst)
717 {
718  return module_inst->hw->MCAN_TSCV;
719 }
720 
728 static inline uint16_t mcan_read_timeout_count_value(
729  struct mcan_module *const module_inst)
730 {
731  return module_inst->hw->MCAN_TOCV;
732 }
733 
741 static inline uint32_t mcan_read_error_count(
742  struct mcan_module *const module_inst)
743 {
744  return module_inst->hw->MCAN_ECR;
745 }
746 
754 static inline uint32_t mcan_read_protocal_status(
755  struct mcan_module *const module_inst)
756 {
757  return module_inst->hw->MCAN_PSR;
758 }
759 
774 static inline uint32_t mcan_read_high_priority_message_status(
775  struct mcan_module *const module_inst)
776 {
777  return module_inst->hw->MCAN_HPMS;
778 }
779 
791 static inline bool mcan_rx_get_buffer_status(
792  struct mcan_module *const module_inst, uint32_t index)
793 {
794  if (index < 32) {
795  if (module_inst->hw->MCAN_NDAT1 & (1 << index)) {
796  return true;
797  } else {
798  return false;
799  }
800  } else {
801  index -= 32;
802  if (module_inst->hw->MCAN_NDAT2 & (1 << index)) {
803  return true;
804  } else {
805  return false;
806  }
807  }
808 }
809 
817 static inline void mcan_rx_clear_buffer_status(
818  struct mcan_module *const module_inst, uint32_t index)
819 {
820  if (index < 32) {
821  module_inst->hw->MCAN_NDAT1 = (1 << index);
822  } else {
823  index -= 32;
824  module_inst->hw->MCAN_NDAT2 = (1 << index);
825  }
826 }
827 
836 static inline uint32_t mcan_rx_get_fifo_status(
837  struct mcan_module *const module_inst, bool fifo_number)
838 {
839  if (!fifo_number) {
840  return module_inst->hw->MCAN_RXF0S;
841  } else {
842  return module_inst->hw->MCAN_RXF1S;
843  }
844 }
845 
853 static inline void mcan_rx_fifo_acknowledge(
854  struct mcan_module *const module_inst, bool fifo_number, uint32_t index)
855 {
856  if (!fifo_number) {
857  module_inst->hw->MCAN_RXF0A = MCAN_RXF0A_F0AI(index);
858  } else {
859  module_inst->hw->MCAN_RXF1A = MCAN_RXF1A_F1AI(index);
860  }
861 }
862 
876 {
882 }
883 
885  struct mcan_module *const module_inst,
886  struct mcan_standard_message_filter_element *sd_filter, uint32_t index);
887 
901 {
907 }
908 
910  struct mcan_module *const module_inst,
911  struct mcan_extended_message_filter_element *et_filter, uint32_t index);
912 
914  struct mcan_module *const module_inst,
915  struct mcan_rx_element_buffer *rx_element, uint32_t index);
916 
918  struct mcan_module *const module_inst,
919  struct mcan_rx_element_fifo_0 *rx_element, uint32_t index);
920 
922  struct mcan_module *const module_inst,
923  struct mcan_rx_element_fifo_1 *rx_element, uint32_t index);
924 
932 static inline uint32_t mcan_tx_get_fifo_queue_status(
933  struct mcan_module *const module_inst)
934 {
935  return module_inst->hw->MCAN_TXFQS;
936 }
937 
945 static inline uint32_t mcan_tx_get_pending_status(
946  struct mcan_module *const module_inst)
947 {
948  return module_inst->hw->MCAN_TXBRP;
949 }
950 
962 static inline enum status_code mcan_tx_transfer_request(
963  struct mcan_module *const module_inst, uint32_t trig_mask)
964 {
965  if (module_inst->hw->MCAN_CCCR & MCAN_CCCR_CCE) {
966  return ERR_BUSY;
967  }
968  module_inst->hw->MCAN_TXBAR = trig_mask;
969  return STATUS_OK;
970 }
971 
983 static inline enum status_code mcan_tx_cancel_request(
984  struct mcan_module *const module_inst, uint32_t trig_mask)
985 {
986  if (module_inst->hw->MCAN_CCCR & MCAN_CCCR_CCE) {
987  return STATUS_ERR_BUSY;
988  }
989  module_inst->hw->MCAN_TXBCR = trig_mask;
990  return STATUS_OK;
991 }
992 
1000 static inline uint32_t mcan_tx_get_transmission_status(
1001  struct mcan_module *const module_inst)
1002 {
1003  return module_inst->hw->MCAN_TXBTO;
1004 }
1005 
1013 static inline uint32_t mcan_tx_get_cancellation_status(
1014  struct mcan_module *const module_inst)
1015 {
1016  return module_inst->hw->MCAN_TXBCF;
1017 }
1018 
1026 static inline uint32_t mcan_tx_get_event_fifo_status(
1027  struct mcan_module *const module_inst)
1028 {
1029  return module_inst->hw->MCAN_TXEFS;
1030 }
1031 
1038 static inline void mcan_tx_event_fifo_acknowledge(
1039  struct mcan_module *const module_inst, uint32_t index)
1040 {
1041  module_inst->hw->MCAN_TXEFA = MCAN_TXEFA_EFAI(index);
1042 }
1043 
1057 static inline void mcan_get_tx_buffer_element_defaults(
1058  struct mcan_tx_element *tx_element)
1059 {
1060  tx_element->T0.reg = 0;
1061  tx_element->T1.reg = MCAN_TX_ELEMENT_T1_EFC |
1063 }
1064 
1066  struct mcan_module *const module_inst,
1067  struct mcan_tx_element *tx_element, uint32_t index);
1068 
1070  struct mcan_module *const module_inst,
1071  struct mcan_tx_event_element *tx_event_element, uint32_t index);
1072 
1078 enum mcan_interrupt_source {
1139 };
1140 
1147 static inline void mcan_enable_interrupt(struct mcan_module *const module_inst,
1148  const enum mcan_interrupt_source source)
1149 {
1150  module_inst->hw->MCAN_IE |= source;
1151 }
1152 
1159 static inline void mcan_disable_interrupt(struct mcan_module *const module_inst,
1160  const enum mcan_interrupt_source source)
1161 {
1162  module_inst->hw->MCAN_IE &= ~source;
1163 }
1164 
1170 static inline uint32_t mcan_read_interrupt_status(
1171  struct mcan_module *const module_inst)
1172 {
1173  return module_inst->hw->MCAN_IR;
1174 }
1175 
1184 static inline void mcan_clear_interrupt_status(
1185  struct mcan_module *const module_inst,
1186  const enum mcan_interrupt_source source)
1187 {
1188  module_inst->hw->MCAN_IR = source;
1189 }
1190 
1195 #ifdef __cplusplus
1196 }
1197 #endif
1198 
1214 #endif /* CAN_H_INCLUDED */
1215 
#define MCAN_IE_TOOE
(MCAN_IE) Timeout Occurred Interrupt Enable
__I uint32_t MCAN_HPMS
(Mcan Offset: 0x94) High Priority Message Status Register
enum mcan_nonmatching_frames_action nonmatching_frames_action_standard
mcan_nonmatching_frames_action
Can nonmatching frames action.
MCAN transfer event FIFO element structure.
MCAN receive element structure for FIFO 0.
MCAN receive element structure for buffer.
bool automatic_retransmission
__I uint32_t MCAN_RXF0S
(Mcan Offset: 0xA4) Receive FIFO 0 Status Register
static uint16_t mcan_read_timestamp_count_value(struct mcan_module *const module_inst)
Can read timestamp count value.
#define MCAN_IE_RF0LE
(MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable
static void mcan_enable_interrupt(struct mcan_module *const module_inst, const enum mcan_interrupt_source source)
Enable MCAN interrupt.
__I uint32_t MCAN_TXBTO
(Mcan Offset: 0xD8) Transmit Buffer Transmission Occurred Register
MCAN transfer element structure.
#define MCAN_TOCC_TOS_RX1_EV_TIMEOUT
(MCAN_TOCC) Timeout controlled by Receive FIFO 1
#define MCAN_TX_ELEMENT_T1_DLC(value)
(MCAN_RXESC) 8 byte data field
#define MCAN_IE_HPME
(MCAN_IE) High Priority Message Interrupt Enable
#define MCAN_IE_WDIE
(MCAN_IE) Watchdog Interrupt Enable
static uint32_t mcan_tx_get_cancellation_status(struct mcan_module *const module_inst)
Get Tx cancellation status.
Success.
Definition: status_codes.h:66
__IO uint32_t MCAN_TXBCR
(Mcan Offset: 0xD4) Transmit Buffer Cancellation Request Register
__IO uint32_t MCAN_TXBAR
(Mcan Offset: 0xD0) Transmit Buffer Add Request Register
Status code definitions.
__I uint32_t MCAN_TXBRP
(Mcan Offset: 0xCC) Transmit Buffer Request Pending Register
static void mcan_rx_clear_buffer_status(struct mcan_module *const module_inst, uint32_t index)
Clear Rx buffer status.
#define MCAN_RXF1A_F1AI(value)
__IO uint32_t MCAN_IE
(Mcan Offset: 0x54) Interrupt Enable Register
MCAN extended message ID filter element structure.
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_CLASSIC
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC(value)
__IO MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_Type F0
static uint32_t mcan_read_high_priority_message_status(struct mcan_module *const module_inst)
Read high priority message status.
#define __IO
Definition: core_cm7.h:266
static uint16_t mcan_read_timeout_count_value(struct mcan_module *const module_inst)
Can read timeout count value.
#define MCAN_IE_TFEE
(MCAN_IE) Tx FIFO Empty Interrupt Enable
#define MCAN_CCCR_CCE
(MCAN_CCCR) Configuration Change Enable (read/write, write protection)
Mcan hardware registers.
enum status_code mcan_get_tx_event_fifo_element(struct mcan_module *const module_inst, struct mcan_tx_event_element *tx_event_element, uint32_t index)
set FIFO transmit buffer element .
Definition: mcan.c:700
uint8_t delay_compensation_offset
MCAN receive element structure for FIFO 1.
static void mcan_rx_fifo_acknowledge(struct mcan_module *const module_inst, bool fifo_number, uint32_t index)
Set Rx acknowledge.
void mcan_disable_bus_monitor_mode(struct mcan_module *const module_inst)
disable bus monitor mode of mcan module.
Definition: mcan.c:479
#define MCAN_IE_TCE
(MCAN_IE) Transmission Completed Interrupt Enable
SAM Control Area Network Driver Configuration Header.
__IO uint32_t MCAN_TOCV
(Mcan Offset: 0x2C) Timeout Counter Value Register
#define MCAN_IE_RF0NE
(MCAN_IE) Receive FIFO 0 New Message Interrupt Enable
mcan_timeout_mode
Can time out modes.
__I uint32_t MCAN_TXFQS
(Mcan Offset: 0xC4) Transmit FIFO/Queue Status Register
__IO MCAN_RX_ELEMENT_R1_Type R1
#define MCAN_IE_RF0WE
(MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable
void mcan_stop(struct mcan_module *const module_inst)
stop mcan module when bus off occurs
Definition: mcan.c:381
#define MCAN_TXEFA_EFAI(value)
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1(value)
#define MCAN_IE_BOE
(MCAN_IE) Bus_Off Status Interrupt Enable
static void mcan_clear_interrupt_status(struct mcan_module *const module_inst, const enum mcan_interrupt_source source)
Clear MCAN interrupt status.
static void mcan_get_config_defaults(struct mcan_config *const config)
Initializes an MCAN configuration structure to defaults.
void mcan_enable_test_mode(struct mcan_module *const module_inst)
enable test mode of mcan module.
Definition: mcan.c:520
bool remote_frames_standard_reject
void mcan_enable_restricted_operation_mode(struct mcan_module *const module_inst)
enable restricted mode of mcan module.
Definition: mcan.c:434
void mcan_start(struct mcan_module *const module_inst)
start can module after initialization.
Definition: mcan.c:368
static uint32_t mcan_tx_get_event_fifo_status(struct mcan_module *const module_inst)
Get Tx event FIFO status.
#define CONF_MCAN_ELEMENT_DATA_SIZE
Definition: conf_mcan.h:77
__IO uint32_t MCAN_NDAT2
(Mcan Offset: 0x9C) New Data 2 Register
Commonly used includes, types and macros.
mcan_interrupt_source
Can module interrupt source.
static void mcan_get_extended_message_filter_element_default(struct mcan_extended_message_filter_element *et_filter)
Get the extended message filter default value.
static uint32_t mcan_tx_get_pending_status(struct mcan_module *const module_inst)
Get Tx buffer request pending status.
#define MCAN_IE_STEE
(MCAN_IE) Stuff Error Interrupt Enable
MCAN configuration structure.
status_code
Definition: status_codes.h:65
void mcan_disable_sleep_mode(struct mcan_module *const module_inst)
disable sleep mode of mcan module.
Definition: mcan.c:505
__IO MCAN_TX_ELEMENT_T0_Type T0
#define MCAN_TOCC_TOS_RX0_EV_TIMEOUT
(MCAN_TOCC) Timeout controlled by Receive FIFO 0
#define MCAN_IE_RF1NE
(MCAN_IE) Receive FIFO 1 New Message Interrupt Enable
#define MCAN_IE_TEFFE
(MCAN_IE) Tx Event FIFO Full Interrupt Enable
__IO uint32_t MCAN_CCCR
(Mcan Offset: 0x18) CC Control Register
#define MCAN_TOCC_TOS_CONTINUOUS
(MCAN_TOCC) Continuous operation
static uint32_t mcan_read_error_count(struct mcan_module *const module_inst)
Can read error count.
static void mcan_get_standard_message_filter_element_default(struct mcan_standard_message_filter_element *sd_filter)
Get the standard message filter default value.
enum status_code mcan_set_rx_extended_filter(struct mcan_module *const module_inst, struct mcan_extended_message_filter_element *et_filter, uint32_t index)
set extended receive CAN ID.
Definition: mcan.c:574
#define MCAN_RXF0A_F0AI(value)
enum status_code mcan_get_rx_buffer_element(struct mcan_module *const module_inst, struct mcan_rx_element_buffer *rx_element, uint32_t index)
get dedicated rx buffer element .
Definition: mcan.c:599
__IO MCAN_RX_ELEMENT_R1_Type R1
#define MCAN_IE_BEE
(MCAN_IE) Bit Error Interrupt Enable
Resource is busy.
Definition: status_codes.h:79
#define MCAN_TX_ELEMENT_T1_EFC
#define MCAN_IE_EPE
(MCAN_IE) Error Passive Interrupt Enable
bool protocol_exception_handling
void mcan_disable_test_mode(struct mcan_module *const module_inst)
disable test mode of mcan module.
Definition: mcan.c:537
static uint32_t mcan_tx_get_fifo_queue_status(struct mcan_module *const module_inst)
Get Tx FIFO/Queue status.
__I uint32_t MCAN_ECR
(Mcan Offset: 0x40) Error Counter Register
#define MCAN_IE_TEFNE
(MCAN_IE) Tx Event FIFO New Entry Interrupt Enable
__I uint32_t MCAN_TXBCF
(Mcan Offset: 0xDC) Transmit Buffer Cancellation Finished Register
static bool mcan_rx_get_buffer_status(struct mcan_module *const module_inst, uint32_t index)
Get Rx buffer status.
void mcan_fd_set_baudrate(Mcan *hw, uint32_t baudrate)
Set MCAN_FD baudrate.
Definition: mcan.c:340
__IO MCAN_RX_ELEMENT_R0_Type R0
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_STF0M_Val
#define MCAN_IE_TEFLE
(MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable
__IO uint32_t MCAN_RXF1A
(Mcan Offset: 0xB8) Receive FIFO 1 Acknowledge Register
__IO uint32_t MCAN_RXF0A
(Mcan Offset: 0xA8) Receive FIFO 0 Acknowledge Register
static void mcan_get_tx_buffer_element_defaults(struct mcan_tx_element *tx_element)
Get the default transfer buffer element.
__IO MCAN_TX_ELEMENT_T1_Type T1
uint8_t timestamp_prescaler
enum mcan_nonmatching_frames_action nonmatching_frames_action_extended
bool remote_frames_extended_reject
__IO uint32_t MCAN_IR
(Mcan Offset: 0x50) Interrupt Register
__IO uint32_t MCAN_TSCV
(Mcan Offset: 0x24) Timestamp Counter Value Register
static uint32_t mcan_rx_get_fifo_status(struct mcan_module *const module_inst, bool fifo_number)
Get Rx FIFO status.
#define MCAN_IE_RF1LE
(MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable
#define MCAN_IE_RF0FE
(MCAN_IE) Receive FIFO 0 Full Interrupt Enable
uint8_t watchdog_configuration
uint8_t rx_fifo_1_watermark
#define MCAN_IE_FOEE
(MCAN_IE) Format Error Interrupt Enable
enum status_code mcan_get_rx_fifo_0_element(struct mcan_module *const module_inst, struct mcan_rx_element_fifo_0 *rx_element, uint32_t index)
get FIFO rx buffer element .
Definition: mcan.c:622
static uint32_t mcan_read_protocal_status(struct mcan_module *const module_inst)
Can read protocol status.
void mcan_enable_sleep_mode(struct mcan_module *const module_inst)
enable sleep mode of mcan module.
Definition: mcan.c:490
void mcan_enable_fd_mode(struct mcan_module *const module_inst)
switch mcan module into fd mode.
Definition: mcan.c:394
#define MCAN_IE_TSWE
(MCAN_IE) Timestamp Wraparound Interrupt Enable
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Msk
#define MCAN_IE_CRCEE
(MCAN_IE) CRC Error Interrupt Enable
static void mcan_disable_interrupt(struct mcan_module *const module_inst, const enum mcan_interrupt_source source)
Disable MCAN interrupt.
enum mcan_timeout_mode timeout_mode
void mcan_enable_bus_monitor_mode(struct mcan_module *const module_inst)
enable bus monitor mode of mcan module.
Definition: mcan.c:463
static enum status_code mcan_tx_transfer_request(struct mcan_module *const module_inst, uint32_t trig_mask)
Tx buffer add transfer request.
#define MCAN_IE_DRXE
(MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable
__I uint32_t MCAN_RXF1S
(Mcan Offset: 0xB4) Receive FIFO 1 Status Register
uint32_t extended_id_mask
enum status_code mcan_get_rx_fifo_1_element(struct mcan_module *const module_inst, struct mcan_rx_element_fifo_1 *rx_element, uint32_t index)
get FIFO rx buffer element .
Definition: mcan.c:645
void mcan_disable_fd_mode(struct mcan_module *const module_inst)
disable fd mode of mcan module.
Definition: mcan.c:415
void mcan_set_baudrate(Mcan *hw, uint32_t baudrate)
Set MCAN baudrate.
Definition: mcan.c:311
#define MCAN_IE_ACKEE
(MCAN_IE) Acknowledge Error Interrupt Enable
static enum status_code mcan_tx_cancel_request(struct mcan_module *const module_inst, uint32_t trig_mask)
Set Tx Queue operation.
static void mcan_tx_event_fifo_acknowledge(struct mcan_module *const module_inst, uint32_t index)
Set Tx Queue operation.
uint8_t rx_fifo_0_watermark
#define MCAN_TX_ELEMENT_T1_DLC_DATA8_Val
(MCAN_RXESC) 12 byte data field
uint8_t tx_event_fifo_watermark
__IO uint32_t MCAN_NDAT1
(Mcan Offset: 0x98) New Data 1 Register
__IO uint32_t MCAN_TXEFA
(Mcan Offset: 0xF8) Transmit Event FIFO Acknowledge Register
__IO MCAN_RX_ELEMENT_R1_Type R1
__I uint32_t MCAN_PSR
(Mcan Offset: 0x44) Protocol Status Register
#define MCAN_IE_ELOE
(MCAN_IE) Error Logging Overflow Interrupt Enable
uint16_t timeout_period
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_CLASSIC
static uint32_t mcan_read_interrupt_status(struct mcan_module *const module_inst)
Get MCAN interrupt status.
__IO MCAN_RX_ELEMENT_R0_Type R0
#define MCAN_IE_TEFWE
(MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable
MCAN standard message ID filter element structure.
#define MCAN_IE_MRAFE
(MCAN_IE) Message RAM Access Failure Interrupt Enable
#define MCAN_TOCC_TOS_TX_EV_TIMEOUT
(MCAN_TOCC) Timeout controlled by Tx Event FIFO
#define MCAN_IE_EWE
(MCAN_IE) Warning Status Interrupt Enable
#define MCAN_IE_TCFE
(MCAN_IE) Transmission Cancellation Finished Interrupt Enable
__IO MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_Type S0
#define MCAN_IE_RF1FE
(MCAN_IE) Receive FIFO 1 Full Interrupt Enable
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Msk
__I uint32_t MCAN_TXEFS
(Mcan Offset: 0xF4) Transmit Event FIFO Status Register
__IO MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_Type F1
enum status_code mcan_set_tx_buffer_element(struct mcan_module *const module_inst, struct mcan_tx_element *tx_element, uint32_t index)
set dedicated transmit buffer element .
Definition: mcan.c:668
void mcan_disable_restricted_operation_mode(struct mcan_module *const module_inst)
disable restricted mode of mcan module.
Definition: mcan.c:451
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC(value)
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1(value)
__IO MCAN_RX_ELEMENT_R0_Type R0
#define Assert(expr)
This macro is used to test fatal errors.
Definition: compiler.h:196
void mcan_init(struct mcan_module *const module_inst, Mcan *hw, struct mcan_config *config)
initialize can module.
Definition: mcan.c:270
static uint32_t mcan_tx_get_transmission_status(struct mcan_module *const module_inst)
Get Tx transmission status.
#define MCAN_IE_RF1WE
(MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable
bool clock_stop_acknowledge
MCAN software device instance structure.
uint8_t data[CONF_MCAN_ELEMENT_DATA_SIZE]
enum status_code mcan_set_rx_standard_filter(struct mcan_module *const module_inst, struct mcan_standard_message_filter_element *sd_filter, uint32_t index)
set standard receive CAN ID.
Definition: mcan.c:551
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_STF1M_Val


inertial_sense_ros
Author(s):
autogenerated on Sat Sep 19 2020 03:19:04