utils/cmsis/same70/include/component/mcan.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_MCAN_COMPONENT_
36 #define _SAME70_MCAN_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __I uint32_t MCAN_CREL;
48  __I uint32_t MCAN_ENDN;
49  __IO uint32_t MCAN_CUST;
50 #if (__SAM_M7_REVB == 1)
51  __IO uint32_t MCAN_DBTP;
52 #else
53  __IO uint32_t MCAN_FBTP;
54 #endif
55  __IO uint32_t MCAN_TEST;
56  __IO uint32_t MCAN_RWD;
57  __IO uint32_t MCAN_CCCR;
58 #if (__SAM_M7_REVB == 1)
59  __IO uint32_t MCAN_NBTP;
60 #else
61  __IO uint32_t MCAN_BTP;
62 #endif
63  __IO uint32_t MCAN_TSCC;
64  __IO uint32_t MCAN_TSCV;
65  __IO uint32_t MCAN_TOCC;
66  __IO uint32_t MCAN_TOCV;
67  __I uint32_t Reserved1[4];
68  __I uint32_t MCAN_ECR;
69  __I uint32_t MCAN_PSR;
70 #if (__SAM_M7_REVB == 1)
71  __IO uint32_t MCAN_TDCR;
72  __I uint32_t Reserved2[1];
73 #else
74  __I uint32_t Reserved2[2];
75 #endif
76  __IO uint32_t MCAN_IR;
77  __IO uint32_t MCAN_IE;
78  __IO uint32_t MCAN_ILS;
79  __IO uint32_t MCAN_ILE;
80  __I uint32_t Reserved3[8];
81  __IO uint32_t MCAN_GFC;
82  __IO uint32_t MCAN_SIDFC;
83  __IO uint32_t MCAN_XIDFC;
84  __I uint32_t Reserved4[1];
85  __IO uint32_t MCAN_XIDAM;
86  __I uint32_t MCAN_HPMS;
87  __IO uint32_t MCAN_NDAT1;
88  __IO uint32_t MCAN_NDAT2;
89  __IO uint32_t MCAN_RXF0C;
90  __I uint32_t MCAN_RXF0S;
91  __IO uint32_t MCAN_RXF0A;
92  __IO uint32_t MCAN_RXBC;
93  __IO uint32_t MCAN_RXF1C;
94  __I uint32_t MCAN_RXF1S;
95  __IO uint32_t MCAN_RXF1A;
96  __IO uint32_t MCAN_RXESC;
97  __IO uint32_t MCAN_TXBC;
98  __I uint32_t MCAN_TXFQS;
99  __IO uint32_t MCAN_TXESC;
100  __I uint32_t MCAN_TXBRP;
101  __IO uint32_t MCAN_TXBAR;
102  __IO uint32_t MCAN_TXBCR;
103  __I uint32_t MCAN_TXBTO;
104  __I uint32_t MCAN_TXBCF;
105  __IO uint32_t MCAN_TXBTIE;
106  __IO uint32_t MCAN_TXBCIE;
107  __I uint32_t Reserved5[2];
108  __IO uint32_t MCAN_TXEFC;
109  __I uint32_t MCAN_TXEFS;
110  __IO uint32_t MCAN_TXEFA;
111 } Mcan;
112 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
113 /* -------- MCAN_CREL : (MCAN Offset: 0x00) Core Release Register -------- */
114 #define MCAN_CREL_DAY_Pos 0
115 #define MCAN_CREL_DAY_Msk (0xffu << MCAN_CREL_DAY_Pos)
116 #define MCAN_CREL_MON_Pos 8
117 #define MCAN_CREL_MON_Msk (0xffu << MCAN_CREL_MON_Pos)
118 #define MCAN_CREL_YEAR_Pos 16
119 #define MCAN_CREL_YEAR_Msk (0xfu << MCAN_CREL_YEAR_Pos)
120 #define MCAN_CREL_SUBSTEP_Pos 20
121 #define MCAN_CREL_SUBSTEP_Msk (0xfu << MCAN_CREL_SUBSTEP_Pos)
122 #define MCAN_CREL_STEP_Pos 24
123 #define MCAN_CREL_STEP_Msk (0xfu << MCAN_CREL_STEP_Pos)
124 #define MCAN_CREL_REL_Pos 28
125 #define MCAN_CREL_REL_Msk (0xfu << MCAN_CREL_REL_Pos)
126 /* -------- MCAN_ENDN : (MCAN Offset: 0x04) Endian Register -------- */
127 #define MCAN_ENDN_ETV_Pos 0
128 #define MCAN_ENDN_ETV_Msk (0xffffffffu << MCAN_ENDN_ETV_Pos)
129 /* -------- MCAN_CUST : (MCAN Offset: 0x08) Customer Register -------- */
130 #define MCAN_CUST_CSV_Pos 0
131 #define MCAN_CUST_CSV_Msk (0xffffffffu << MCAN_CUST_CSV_Pos)
132 #define MCAN_CUST_CSV(value) ((MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos)))
133 /* -------- MCAN_FBTP : (MCAN Offset: 0x0C) Fast Bit Timing and Prescaler Register -------- */
134 #define MCAN_FBTP_FSJW_Pos 0
135 #define MCAN_FBTP_FSJW_Msk (0x3u << MCAN_FBTP_FSJW_Pos)
136 #define MCAN_FBTP_FSJW(value) ((MCAN_FBTP_FSJW_Msk & ((value) << MCAN_FBTP_FSJW_Pos)))
137 #define MCAN_FBTP_FTSEG2_Pos 4
138 #define MCAN_FBTP_FTSEG2_Msk (0x7u << MCAN_FBTP_FTSEG2_Pos)
139 #define MCAN_FBTP_FTSEG2(value) ((MCAN_FBTP_FTSEG2_Msk & ((value) << MCAN_FBTP_FTSEG2_Pos)))
140 #define MCAN_FBTP_FTSEG1_Pos 8
141 #define MCAN_FBTP_FTSEG1_Msk (0xfu << MCAN_FBTP_FTSEG1_Pos)
142 #define MCAN_FBTP_FTSEG1(value) ((MCAN_FBTP_FTSEG1_Msk & ((value) << MCAN_FBTP_FTSEG1_Pos)))
143 #define MCAN_FBTP_FBRP_Pos 16
144 #define MCAN_FBTP_FBRP_Msk (0x1fu << MCAN_FBTP_FBRP_Pos)
145 #define MCAN_FBTP_FBRP(value) ((MCAN_FBTP_FBRP_Msk & ((value) << MCAN_FBTP_FBRP_Pos)))
146 #define MCAN_FBTP_TDC (0x1u << 23)
147 #define MCAN_FBTP_TDC_DISABLED (0x0u << 23)
148 #define MCAN_FBTP_TDC_ENABLED (0x1u << 23)
149 #define MCAN_FBTP_TDCO_Pos 24
150 #define MCAN_FBTP_TDCO_Msk (0x1fu << MCAN_FBTP_TDCO_Pos)
151 #define MCAN_FBTP_TDCO(value) ((MCAN_FBTP_TDCO_Msk & ((value) << MCAN_FBTP_TDCO_Pos)))
152 /* -------- MCAN_DBTP : (MCAN Offset: 0x0C) Data Bit Timing and Prescaler Register -------- */
153 #define MCAN_DBTP_DSJW_Pos 0
154 #define MCAN_DBTP_DSJW_Msk (0x7u << MCAN_DBTP_DSJW_Pos)
155 #define MCAN_DBTP_DSJW(value) ((MCAN_DBTP_DSJW_Msk & ((value) << MCAN_DBTP_DSJW_Pos)))
156 #define MCAN_DBTP_DTSEG2_Pos 4
157 #define MCAN_DBTP_DTSEG2_Msk (0xfu << MCAN_DBTP_DTSEG2_Pos)
158 #define MCAN_DBTP_DTSEG2(value) ((MCAN_DBTP_DTSEG2_Msk & ((value) << MCAN_DBTP_DTSEG2_Pos)))
159 #define MCAN_DBTP_DTSEG1_Pos 8
160 #define MCAN_DBTP_DTSEG1_Msk (0x1fu << MCAN_DBTP_DTSEG1_Pos)
161 #define MCAN_DBTP_DTSEG1(value) ((MCAN_DBTP_DTSEG1_Msk & ((value) << MCAN_DBTP_DTSEG1_Pos)))
162 #define MCAN_DBTP_DBRP_Pos 16
163 #define MCAN_DBTP_DBRP_Msk (0x1fu << MCAN_DBTP_DBRP_Pos)
164 #define MCAN_DBTP_DBRP(value) ((MCAN_DBTP_DBRP_Msk & ((value) << MCAN_DBTP_DBRP_Pos)))
165 #define MCAN_DBTP_TDC (0x1u << 23)
166 #define MCAN_DBTP_TDC_DISABLED (0x0u << 23)
167 #define MCAN_DBTP_TDC_ENABLED (0x1u << 23)
168 /* -------- MCAN_TEST : (MCAN Offset: 0x10) Test Register -------- */
169 #define MCAN_TEST_LBCK (0x1u << 4)
170 #define MCAN_TEST_LBCK_DISABLED (0x0u << 4)
171 #define MCAN_TEST_LBCK_ENABLED (0x1u << 4)
172 #define MCAN_TEST_TX_Pos 5
173 #define MCAN_TEST_TX_Msk (0x3u << MCAN_TEST_TX_Pos)
174 #define MCAN_TEST_TX(value) ((MCAN_TEST_TX_Msk & ((value) << MCAN_TEST_TX_Pos)))
175 #define MCAN_TEST_TX_RESET (0x0u << 5)
176 #define MCAN_TEST_TX_SAMPLE_POINT_MONITORING (0x1u << 5)
177 #define MCAN_TEST_TX_DOMINANT (0x2u << 5)
178 #define MCAN_TEST_TX_RECESSIVE (0x3u << 5)
179 #define MCAN_TEST_RX (0x1u << 7)
180 #define MCAN_TEST_TDCV_Pos 8
181 #define MCAN_TEST_TDCV_Msk (0x3fu << MCAN_TEST_TDCV_Pos)
182 #define MCAN_TEST_TDCV(value) ((MCAN_TEST_TDCV_Msk & ((value) << MCAN_TEST_TDCV_Pos)))
183 /* -------- MCAN_RWD : (MCAN Offset: 0x14) RAM Watchdog Register -------- */
184 #define MCAN_RWD_WDC_Pos 0
185 #define MCAN_RWD_WDC_Msk (0xffu << MCAN_RWD_WDC_Pos)
186 #define MCAN_RWD_WDC(value) ((MCAN_RWD_WDC_Msk & ((value) << MCAN_RWD_WDC_Pos)))
187 #define MCAN_RWD_WDV_Pos 8
188 #define MCAN_RWD_WDV_Msk (0xffu << MCAN_RWD_WDV_Pos)
189 #define MCAN_RWD_WDV(value) ((MCAN_RWD_WDV_Msk & ((value) << MCAN_RWD_WDV_Pos)))
190 /* -------- MCAN_CCCR : (MCAN Offset: 0x18) CC Control Register -------- */
191 #define MCAN_CCCR_INIT (0x1u << 0)
192 #define MCAN_CCCR_INIT_DISABLED (0x0u << 0)
193 #define MCAN_CCCR_INIT_ENABLED (0x1u << 0)
194 #define MCAN_CCCR_CCE (0x1u << 1)
195 #define MCAN_CCCR_CCE_PROTECTED (0x0u << 1)
196 #define MCAN_CCCR_CCE_CONFIGURABLE (0x1u << 1)
197 #define MCAN_CCCR_ASM (0x1u << 2)
198 #define MCAN_CCCR_ASM_NORMAL (0x0u << 2)
199 #define MCAN_CCCR_ASM_RESTRICTED (0x1u << 2)
200 #define MCAN_CCCR_CSA (0x1u << 3)
201 #define MCAN_CCCR_CSR (0x1u << 4)
202 #define MCAN_CCCR_CSR_NO_CLOCK_STOP (0x0u << 4)
203 #define MCAN_CCCR_CSR_CLOCK_STOP (0x1u << 4)
204 #define MCAN_CCCR_MON (0x1u << 5)
205 #define MCAN_CCCR_MON_DISABLED (0x0u << 5)
206 #define MCAN_CCCR_MON_ENABLED (0x1u << 5)
207 #define MCAN_CCCR_DAR (0x1u << 6)
208 #define MCAN_CCCR_DAR_AUTO_RETX (0x0u << 6)
209 #define MCAN_CCCR_DAR_NO_AUTO_RETX (0x1u << 6)
210 #define MCAN_CCCR_TEST (0x1u << 7)
211 #define MCAN_CCCR_TEST_DISABLED (0x0u << 7)
212 #define MCAN_CCCR_TEST_ENABLED (0x1u << 7)
213 #define MCAN_CCCR_CME_Pos 8
214 #define MCAN_CCCR_CME_Msk (0x3u << MCAN_CCCR_CME_Pos)
215 #define MCAN_CCCR_CME(value) ((MCAN_CCCR_CME_Msk & ((value) << MCAN_CCCR_CME_Pos)))
216 #define MCAN_CCCR_CME_ISO11898_1 (0x0u << 8)
217 #define MCAN_CCCR_CME_FD (0x1u << 8)
218 #define MCAN_CCCR_CMR_Pos 10
219 #define MCAN_CCCR_CMR_Msk (0x3u << MCAN_CCCR_CMR_Pos)
220 #define MCAN_CCCR_CMR(value) ((MCAN_CCCR_CMR_Msk & ((value) << MCAN_CCCR_CMR_Pos)))
221 #define MCAN_CCCR_CMR_NO_CHANGE (0x0u << 10)
222 #define MCAN_CCCR_CMR_FD (0x1u << 10)
223 #define MCAN_CCCR_CMR_FD_BITRATE_SWITCH (0x2u << 10)
224 #define MCAN_CCCR_CMR_ISO11898_1 (0x3u << 10)
225 #define MCAN_CCCR_FDO (0x1u << 12)
226 #define MCAN_CCCR_FDBS (0x1u << 13)
227 #define MCAN_CCCR_FDOE (0x1u << 8)
228 #define MCAN_CCCR_FDOE_DISABLED (0x0u << 8)
229 #define MCAN_CCCR_FDOE_ENABLED (0x1u << 8)
230 #define MCAN_CCCR_BRSE (0x1u << 9)
231 #define MCAN_CCCR_BRSE_DISABLED (0x0u << 9)
232 #define MCAN_CCCR_BRSE_ENABLED (0x1u << 9)
233 #define MCAN_CCCR_PXHD (0x1u << 12)
234 #define MCAN_CCCR_EFBI (0x1u << 13)
235 #define MCAN_CCCR_TXP (0x1u << 14)
236 #define MCAN_CCCR_NISO (0x1u << 15)
237 /* -------- MCAN_BTP : (MCAN Offset: 0x1C) Bit Timing and Prescaler Register -------- */
238 #define MCAN_BTP_SJW_Pos 0
239 #define MCAN_BTP_SJW_Msk (0xfu << MCAN_BTP_SJW_Pos)
240 #define MCAN_BTP_SJW(value) ((MCAN_BTP_SJW_Msk & ((value) << MCAN_BTP_SJW_Pos)))
241 #define MCAN_BTP_TSEG2_Pos 4
242 #define MCAN_BTP_TSEG2_Msk (0xfu << MCAN_BTP_TSEG2_Pos)
243 #define MCAN_BTP_TSEG2(value) ((MCAN_BTP_TSEG2_Msk & ((value) << MCAN_BTP_TSEG2_Pos)))
244 #define MCAN_BTP_TSEG1_Pos 8
245 #define MCAN_BTP_TSEG1_Msk (0x3fu << MCAN_BTP_TSEG1_Pos)
246 #define MCAN_BTP_TSEG1(value) ((MCAN_BTP_TSEG1_Msk & ((value) << MCAN_BTP_TSEG1_Pos)))
247 #define MCAN_BTP_BRP_Pos 16
248 #define MCAN_BTP_BRP_Msk (0x3ffu << MCAN_BTP_BRP_Pos)
249 #define MCAN_BTP_BRP(value) ((MCAN_BTP_BRP_Msk & ((value) << MCAN_BTP_BRP_Pos)))
250 /* -------- MCAN_NBTP : (MCAN Offset: 0x1C) Nominal Bit Timing and Prescaler Register -------- */
251 #define MCAN_NBTP_NTSEG2_Pos 0
252 #define MCAN_NBTP_NTSEG2_Msk (0x7fu << MCAN_NBTP_NTSEG2_Pos)
253 #define MCAN_NBTP_NTSEG2(value) ((MCAN_NBTP_NTSEG2_Msk & ((value) << MCAN_NBTP_NTSEG2_Pos)))
254 #define MCAN_NBTP_NTSEG1_Pos 8
255 #define MCAN_NBTP_NTSEG1_Msk (0xffu << MCAN_NBTP_NTSEG1_Pos)
256 #define MCAN_NBTP_NTSEG1(value) ((MCAN_NBTP_NTSEG1_Msk & ((value) << MCAN_NBTP_NTSEG1_Pos)))
257 #define MCAN_NBTP_NBRP_Pos 16
258 #define MCAN_NBTP_NBRP_Msk (0x1ffu << MCAN_NBTP_NBRP_Pos)
259 #define MCAN_NBTP_NBRP(value) ((MCAN_NBTP_NBRP_Msk & ((value) << MCAN_NBTP_NBRP_Pos)))
260 #define MCAN_NBTP_NSJW_Pos 25
261 #define MCAN_NBTP_NSJW_Msk (0x7fu << MCAN_NBTP_NSJW_Pos)
262 #define MCAN_NBTP_NSJW(value) ((MCAN_NBTP_NSJW_Msk & ((value) << MCAN_NBTP_NSJW_Pos)))
263 /* -------- MCAN_TSCC : (MCAN Offset: 0x20) Timestamp Counter Configuration Register -------- */
264 #define MCAN_TSCC_TSS_Pos 0
265 #define MCAN_TSCC_TSS_Msk (0x3u << MCAN_TSCC_TSS_Pos)
266 #define MCAN_TSCC_TSS(value) ((MCAN_TSCC_TSS_Msk & ((value) << MCAN_TSCC_TSS_Pos)))
267 #define MCAN_TSCC_TSS_ALWAYS_0 (0x0u << 0)
268 #define MCAN_TSCC_TSS_TCP_INC (0x1u << 0)
269 #define MCAN_TSCC_TSS_EXT_TIMESTAMP (0x2u << 0)
270 #define MCAN_TSCC_TCP_Pos 16
271 #define MCAN_TSCC_TCP_Msk (0xfu << MCAN_TSCC_TCP_Pos)
272 #define MCAN_TSCC_TCP(value) ((MCAN_TSCC_TCP_Msk & ((value) << MCAN_TSCC_TCP_Pos)))
273 /* -------- MCAN_TSCV : (MCAN Offset: 0x24) Timestamp Counter Value Register -------- */
274 #define MCAN_TSCV_TSC_Pos 0
275 #define MCAN_TSCV_TSC_Msk (0xffffu << MCAN_TSCV_TSC_Pos)
276 #define MCAN_TSCV_TSC(value) ((MCAN_TSCV_TSC_Msk & ((value) << MCAN_TSCV_TSC_Pos)))
277 /* -------- MCAN_TOCC : (MCAN Offset: 0x28) Timeout Counter Configuration Register -------- */
278 #define MCAN_TOCC_ETOC (0x1u << 0)
279 #define MCAN_TOCC_ETOC_NO_TIMEOUT (0x0u << 0)
280 #define MCAN_TOCC_ETOC_TOS_CONTROLLED (0x1u << 0)
281 #define MCAN_TOCC_TOS_Pos 1
282 #define MCAN_TOCC_TOS_Msk (0x3u << MCAN_TOCC_TOS_Pos)
283 #define MCAN_TOCC_TOS(value) ((MCAN_TOCC_TOS_Msk & ((value) << MCAN_TOCC_TOS_Pos)))
284 #define MCAN_TOCC_TOS_CONTINUOUS (0x0u << 1)
285 #define MCAN_TOCC_TOS_TX_EV_TIMEOUT (0x1u << 1)
286 #define MCAN_TOCC_TOS_RX0_EV_TIMEOUT (0x2u << 1)
287 #define MCAN_TOCC_TOS_RX1_EV_TIMEOUT (0x3u << 1)
288 #define MCAN_TOCC_TOP_Pos 16
289 #define MCAN_TOCC_TOP_Msk (0xffffu << MCAN_TOCC_TOP_Pos)
290 #define MCAN_TOCC_TOP(value) ((MCAN_TOCC_TOP_Msk & ((value) << MCAN_TOCC_TOP_Pos)))
291 /* -------- MCAN_TOCV : (MCAN Offset: 0x2C) Timeout Counter Value Register -------- */
292 #define MCAN_TOCV_TOC_Pos 0
293 #define MCAN_TOCV_TOC_Msk (0xffffu << MCAN_TOCV_TOC_Pos)
294 #define MCAN_TOCV_TOC(value) ((MCAN_TOCV_TOC_Msk & ((value) << MCAN_TOCV_TOC_Pos)))
295 /* -------- MCAN_ECR : (MCAN Offset: 0x40) Error Counter Register -------- */
296 #define MCAN_ECR_TEC_Pos 0
297 #define MCAN_ECR_TEC_Msk (0xffu << MCAN_ECR_TEC_Pos)
298 #define MCAN_ECR_REC_Pos 8
299 #define MCAN_ECR_REC_Msk (0x7fu << MCAN_ECR_REC_Pos)
300 #define MCAN_ECR_RP (0x1u << 15)
301 #define MCAN_ECR_CEL_Pos 16
302 #define MCAN_ECR_CEL_Msk (0xffu << MCAN_ECR_CEL_Pos)
303 /* -------- MCAN_PSR : (MCAN Offset: 0x44) Protocol Status Register -------- */
304 #define MCAN_PSR_LEC_Pos 0
305 #define MCAN_PSR_LEC_Msk (0x7u << MCAN_PSR_LEC_Pos)
306 #define MCAN_PSR_LEC_NO_ERROR (0x0u << 0)
307 #define MCAN_PSR_LEC_STUFF_ERROR (0x1u << 0)
308 #define MCAN_PSR_LEC_FORM_ERROR (0x2u << 0)
309 #define MCAN_PSR_LEC_ACK_ERROR (0x3u << 0)
310 #define MCAN_PSR_LEC_BIT1_ERROR (0x4u << 0)
311 #define MCAN_PSR_LEC_BIT0_ERROR (0x5u << 0)
312 #define MCAN_PSR_LEC_CRC_ERROR (0x6u << 0)
313 #define MCAN_PSR_LEC_NO_CHANGE (0x7u << 0)
314 #define MCAN_PSR_ACT_Pos 3
315 #define MCAN_PSR_ACT_Msk (0x3u << MCAN_PSR_ACT_Pos)
316 #define MCAN_PSR_ACT_SYNCHRONIZING (0x0u << 3)
317 #define MCAN_PSR_ACT_IDLE (0x1u << 3)
318 #define MCAN_PSR_ACT_RECEIVER (0x2u << 3)
319 #define MCAN_PSR_ACT_TRANSMITTER (0x3u << 3)
320 #define MCAN_PSR_EP (0x1u << 5)
321 #define MCAN_PSR_EW (0x1u << 6)
322 #define MCAN_PSR_BO (0x1u << 7)
323 #define MCAN_PSR_FLEC_Pos 8
324 #define MCAN_PSR_FLEC_Msk (0x7u << MCAN_PSR_FLEC_Pos)
325 #define MCAN_PSR_DLEC_Pos 8
326 #define MCAN_PSR_DLEC_Msk (0x7u << MCAN_PSR_DLEC_Pos)
327 #define MCAN_PSR_RESI (0x1u << 11)
328 #define MCAN_PSR_RBRS (0x1u << 12)
329 #define MCAN_PSR_REDL (0x1u << 13)
330 #define MCAN_PSR_RFDF (0x1u << 13)
331 #define MCAN_PSR_PXE (0x1u << 14)
332 #define MCAN_PSR_TDCV_Pos 16
333 #define MCAN_PSR_TDCV_Msk (0x7fu << MCAN_PSR_TDCV_Pos)
334 /* -------- MCAN_TDCR : (MCAN Offset: 0x48) Transmit Delay Compensation Register -------- */
335 #define MCAN_TDCR_TDCF_Pos 0
336 #define MCAN_TDCR_TDCF_Msk (0x7fu << MCAN_TDCR_TDCF_Pos)
337 #define MCAN_TDCR_TDCF(value) ((MCAN_TDCR_TDCF_Msk & ((value) << MCAN_TDCR_TDCF_Pos)))
338 #define MCAN_TDCR_TDCO_Pos 8
339 #define MCAN_TDCR_TDCO_Msk (0x7fu << MCAN_TDCR_TDCO_Pos)
340 #define MCAN_TDCR_TDCO(value) ((MCAN_TDCR_TDCO_Msk & ((value) << MCAN_TDCR_TDCO_Pos)))
341 /* -------- MCAN_IR : (MCAN Offset: 0x50) Interrupt Register -------- */
342 #define MCAN_IR_RF0N (0x1u << 0)
343 #define MCAN_IR_RF0W (0x1u << 1)
344 #define MCAN_IR_RF0F (0x1u << 2)
345 #define MCAN_IR_RF0L (0x1u << 3)
346 #define MCAN_IR_RF1N (0x1u << 4)
347 #define MCAN_IR_RF1W (0x1u << 5)
348 #define MCAN_IR_RF1F (0x1u << 6)
349 #define MCAN_IR_RF1L (0x1u << 7)
350 #define MCAN_IR_HPM (0x1u << 8)
351 #define MCAN_IR_TC (0x1u << 9)
352 #define MCAN_IR_TCF (0x1u << 10)
353 #define MCAN_IR_TFE (0x1u << 11)
354 #define MCAN_IR_TEFN (0x1u << 12)
355 #define MCAN_IR_TEFW (0x1u << 13)
356 #define MCAN_IR_TEFF (0x1u << 14)
357 #define MCAN_IR_TEFL (0x1u << 15)
358 #define MCAN_IR_TSW (0x1u << 16)
359 #define MCAN_IR_MRAF (0x1u << 17)
360 #define MCAN_IR_TOO (0x1u << 18)
361 #define MCAN_IR_DRX (0x1u << 19)
362 #define MCAN_IR_ELO (0x1u << 22)
363 #define MCAN_IR_EP (0x1u << 23)
364 #define MCAN_IR_EW (0x1u << 24)
365 #define MCAN_IR_BO (0x1u << 25)
366 #define MCAN_IR_WDI (0x1u << 26)
367 #define MCAN_IR_CRCE (0x1u << 27)
368 #define MCAN_IR_BE (0x1u << 28)
369 #define MCAN_IR_ACKE (0x1u << 29)
370 #define MCAN_IR_FOE (0x1u << 30)
371 #define MCAN_IR_STE (0x1u << 31)
372 #define MCAN_IR_PEA (0x1u << 27)
373 #define MCAN_IR_PED (0x1u << 28)
374 #define MCAN_IR_ARA (0x1u << 29)
375 /* -------- MCAN_IE : (MCAN Offset: 0x54) Interrupt Enable Register -------- */
376 #define MCAN_IE_RF0NE (0x1u << 0)
377 #define MCAN_IE_RF0WE (0x1u << 1)
378 #define MCAN_IE_RF0FE (0x1u << 2)
379 #define MCAN_IE_RF0LE (0x1u << 3)
380 #define MCAN_IE_RF1NE (0x1u << 4)
381 #define MCAN_IE_RF1WE (0x1u << 5)
382 #define MCAN_IE_RF1FE (0x1u << 6)
383 #define MCAN_IE_RF1LE (0x1u << 7)
384 #define MCAN_IE_HPME (0x1u << 8)
385 #define MCAN_IE_TCE (0x1u << 9)
386 #define MCAN_IE_TCFE (0x1u << 10)
387 #define MCAN_IE_TFEE (0x1u << 11)
388 #define MCAN_IE_TEFNE (0x1u << 12)
389 #define MCAN_IE_TEFWE (0x1u << 13)
390 #define MCAN_IE_TEFFE (0x1u << 14)
391 #define MCAN_IE_TEFLE (0x1u << 15)
392 #define MCAN_IE_TSWE (0x1u << 16)
393 #define MCAN_IE_MRAFE (0x1u << 17)
394 #define MCAN_IE_TOOE (0x1u << 18)
395 #define MCAN_IE_DRXE (0x1u << 19)
396 #define MCAN_IE_ELOE (0x1u << 22)
397 #define MCAN_IE_EPE (0x1u << 23)
398 #define MCAN_IE_EWE (0x1u << 24)
399 #define MCAN_IE_BOE (0x1u << 25)
400 #define MCAN_IE_WDIE (0x1u << 26)
401 #define MCAN_IE_CRCEE (0x1u << 27)
402 #define MCAN_IE_BEE (0x1u << 28)
403 #define MCAN_IE_ACKEE (0x1u << 29)
404 #define MCAN_IE_FOEE (0x1u << 30)
405 #define MCAN_IE_STEE (0x1u << 31)
406 #define MCAN_IE_PEAE (0x1u << 27)
407 #define MCAN_IE_PEDE (0x1u << 28)
408 #define MCAN_IE_ARAE (0x1u << 29)
409 /* -------- MCAN_ILS : (MCAN Offset: 0x58) Interrupt Line Select Register -------- */
410 #define MCAN_ILS_RF0NL (0x1u << 0)
411 #define MCAN_ILS_RF0WL (0x1u << 1)
412 #define MCAN_ILS_RF0FL (0x1u << 2)
413 #define MCAN_ILS_RF0LL (0x1u << 3)
414 #define MCAN_ILS_RF1NL (0x1u << 4)
415 #define MCAN_ILS_RF1WL (0x1u << 5)
416 #define MCAN_ILS_RF1FL (0x1u << 6)
417 #define MCAN_ILS_RF1LL (0x1u << 7)
418 #define MCAN_ILS_HPML (0x1u << 8)
419 #define MCAN_ILS_TCL (0x1u << 9)
420 #define MCAN_ILS_TCFL (0x1u << 10)
421 #define MCAN_ILS_TFEL (0x1u << 11)
422 #define MCAN_ILS_TEFNL (0x1u << 12)
423 #define MCAN_ILS_TEFWL (0x1u << 13)
424 #define MCAN_ILS_TEFFL (0x1u << 14)
425 #define MCAN_ILS_TEFLL (0x1u << 15)
426 #define MCAN_ILS_TSWL (0x1u << 16)
427 #define MCAN_ILS_MRAFL (0x1u << 17)
428 #define MCAN_ILS_TOOL (0x1u << 18)
429 #define MCAN_ILS_DRXL (0x1u << 19)
430 #define MCAN_ILS_ELOL (0x1u << 22)
431 #define MCAN_ILS_EPL (0x1u << 23)
432 #define MCAN_ILS_EWL (0x1u << 24)
433 #define MCAN_ILS_BOL (0x1u << 25)
434 #define MCAN_ILS_WDIL (0x1u << 26)
435 #define MCAN_ILS_CRCEL (0x1u << 27)
436 #define MCAN_ILS_BEL (0x1u << 28)
437 #define MCAN_ILS_ACKEL (0x1u << 29)
438 #define MCAN_ILS_FOEL (0x1u << 30)
439 #define MCAN_ILS_STEL (0x1u << 31)
440 #define MCAN_ILS_PEAL (0x1u << 27)
441 #define MCAN_ILS_PEDL (0x1u << 28)
442 #define MCAN_ILS_ARAL (0x1u << 29)
443 /* -------- MCAN_ILE : (MCAN Offset: 0x5C) Interrupt Line Enable Register -------- */
444 #define MCAN_ILE_EINT0 (0x1u << 0)
445 #define MCAN_ILE_EINT1 (0x1u << 1)
446 /* -------- MCAN_GFC : (MCAN Offset: 0x80) Global Filter Configuration Register -------- */
447 #define MCAN_GFC_RRFE (0x1u << 0)
448 #define MCAN_GFC_RRFE_FILTER (0x0u << 0)
449 #define MCAN_GFC_RRFE_REJECT (0x1u << 0)
450 #define MCAN_GFC_RRFS (0x1u << 1)
451 #define MCAN_GFC_RRFS_FILTER (0x0u << 1)
452 #define MCAN_GFC_RRFS_REJECT (0x1u << 1)
453 #define MCAN_GFC_ANFE_Pos 2
454 #define MCAN_GFC_ANFE_Msk (0x3u << MCAN_GFC_ANFE_Pos)
455 #define MCAN_GFC_ANFE(value) ((MCAN_GFC_ANFE_Msk & ((value) << MCAN_GFC_ANFE_Pos)))
456 #define MCAN_GFC_ANFE_RX_FIFO_0 (0x0u << 2)
457 #define MCAN_GFC_ANFE_RX_FIFO_1 (0x1u << 2)
458 #define MCAN_GFC_ANFS_Pos 4
459 #define MCAN_GFC_ANFS_Msk (0x3u << MCAN_GFC_ANFS_Pos)
460 #define MCAN_GFC_ANFS(value) ((MCAN_GFC_ANFS_Msk & ((value) << MCAN_GFC_ANFS_Pos)))
461 #define MCAN_GFC_ANFS_RX_FIFO_0 (0x0u << 4)
462 #define MCAN_GFC_ANFS_RX_FIFO_1 (0x1u << 4)
463 /* -------- MCAN_SIDFC : (MCAN Offset: 0x84) Standard ID Filter Configuration Register -------- */
464 #define MCAN_SIDFC_FLSSA_Pos 2
465 #define MCAN_SIDFC_FLSSA_Msk (0x3fffu << MCAN_SIDFC_FLSSA_Pos)
466 #define MCAN_SIDFC_FLSSA(value) ((MCAN_SIDFC_FLSSA_Msk & ((value) << MCAN_SIDFC_FLSSA_Pos)))
467 #define MCAN_SIDFC_LSS_Pos 16
468 #define MCAN_SIDFC_LSS_Msk (0xffu << MCAN_SIDFC_LSS_Pos)
469 #define MCAN_SIDFC_LSS(value) ((MCAN_SIDFC_LSS_Msk & ((value) << MCAN_SIDFC_LSS_Pos)))
470 /* -------- MCAN_XIDFC : (MCAN Offset: 0x88) Extended ID Filter Configuration Register -------- */
471 #define MCAN_XIDFC_FLESA_Pos 2
472 #define MCAN_XIDFC_FLESA_Msk (0x3fffu << MCAN_XIDFC_FLESA_Pos)
473 #define MCAN_XIDFC_FLESA(value) ((MCAN_XIDFC_FLESA_Msk & ((value) << MCAN_XIDFC_FLESA_Pos)))
474 #define MCAN_XIDFC_LSE_Pos 16
475 #define MCAN_XIDFC_LSE_Msk (0x7fu << MCAN_XIDFC_LSE_Pos)
476 #define MCAN_XIDFC_LSE(value) ((MCAN_XIDFC_LSE_Msk & ((value) << MCAN_XIDFC_LSE_Pos)))
477 /* -------- MCAN_XIDAM : (MCAN Offset: 0x90) Extended ID AND Mask Register -------- */
478 #define MCAN_XIDAM_EIDM_Pos 0
479 #define MCAN_XIDAM_EIDM_Msk (0x1fffffffu << MCAN_XIDAM_EIDM_Pos)
480 #define MCAN_XIDAM_EIDM(value) ((MCAN_XIDAM_EIDM_Msk & ((value) << MCAN_XIDAM_EIDM_Pos)))
481 /* -------- MCAN_HPMS : (MCAN Offset: 0x94) High Priority Message Status Register -------- */
482 #define MCAN_HPMS_BIDX_Pos 0
483 #define MCAN_HPMS_BIDX_Msk (0x3fu << MCAN_HPMS_BIDX_Pos)
484 #define MCAN_HPMS_MSI_Pos 6
485 #define MCAN_HPMS_MSI_Msk (0x3u << MCAN_HPMS_MSI_Pos)
486 #define MCAN_HPMS_MSI_NO_FIFO_SEL (0x0u << 6)
487 #define MCAN_HPMS_MSI_LOST (0x1u << 6)
488 #define MCAN_HPMS_MSI_FIFO_0 (0x2u << 6)
489 #define MCAN_HPMS_MSI_FIFO_1 (0x3u << 6)
490 #define MCAN_HPMS_FIDX_Pos 8
491 #define MCAN_HPMS_FIDX_Msk (0x7fu << MCAN_HPMS_FIDX_Pos)
492 #define MCAN_HPMS_FLST (0x1u << 15)
493 /* -------- MCAN_NDAT1 : (MCAN Offset: 0x98) New Data 1 Register -------- */
494 #define MCAN_NDAT1_ND0 (0x1u << 0)
495 #define MCAN_NDAT1_ND1 (0x1u << 1)
496 #define MCAN_NDAT1_ND2 (0x1u << 2)
497 #define MCAN_NDAT1_ND3 (0x1u << 3)
498 #define MCAN_NDAT1_ND4 (0x1u << 4)
499 #define MCAN_NDAT1_ND5 (0x1u << 5)
500 #define MCAN_NDAT1_ND6 (0x1u << 6)
501 #define MCAN_NDAT1_ND7 (0x1u << 7)
502 #define MCAN_NDAT1_ND8 (0x1u << 8)
503 #define MCAN_NDAT1_ND9 (0x1u << 9)
504 #define MCAN_NDAT1_ND10 (0x1u << 10)
505 #define MCAN_NDAT1_ND11 (0x1u << 11)
506 #define MCAN_NDAT1_ND12 (0x1u << 12)
507 #define MCAN_NDAT1_ND13 (0x1u << 13)
508 #define MCAN_NDAT1_ND14 (0x1u << 14)
509 #define MCAN_NDAT1_ND15 (0x1u << 15)
510 #define MCAN_NDAT1_ND16 (0x1u << 16)
511 #define MCAN_NDAT1_ND17 (0x1u << 17)
512 #define MCAN_NDAT1_ND18 (0x1u << 18)
513 #define MCAN_NDAT1_ND19 (0x1u << 19)
514 #define MCAN_NDAT1_ND20 (0x1u << 20)
515 #define MCAN_NDAT1_ND21 (0x1u << 21)
516 #define MCAN_NDAT1_ND22 (0x1u << 22)
517 #define MCAN_NDAT1_ND23 (0x1u << 23)
518 #define MCAN_NDAT1_ND24 (0x1u << 24)
519 #define MCAN_NDAT1_ND25 (0x1u << 25)
520 #define MCAN_NDAT1_ND26 (0x1u << 26)
521 #define MCAN_NDAT1_ND27 (0x1u << 27)
522 #define MCAN_NDAT1_ND28 (0x1u << 28)
523 #define MCAN_NDAT1_ND29 (0x1u << 29)
524 #define MCAN_NDAT1_ND30 (0x1u << 30)
525 #define MCAN_NDAT1_ND31 (0x1u << 31)
526 /* -------- MCAN_NDAT2 : (MCAN Offset: 0x9C) New Data 2 Register -------- */
527 #define MCAN_NDAT2_ND32 (0x1u << 0)
528 #define MCAN_NDAT2_ND33 (0x1u << 1)
529 #define MCAN_NDAT2_ND34 (0x1u << 2)
530 #define MCAN_NDAT2_ND35 (0x1u << 3)
531 #define MCAN_NDAT2_ND36 (0x1u << 4)
532 #define MCAN_NDAT2_ND37 (0x1u << 5)
533 #define MCAN_NDAT2_ND38 (0x1u << 6)
534 #define MCAN_NDAT2_ND39 (0x1u << 7)
535 #define MCAN_NDAT2_ND40 (0x1u << 8)
536 #define MCAN_NDAT2_ND41 (0x1u << 9)
537 #define MCAN_NDAT2_ND42 (0x1u << 10)
538 #define MCAN_NDAT2_ND43 (0x1u << 11)
539 #define MCAN_NDAT2_ND44 (0x1u << 12)
540 #define MCAN_NDAT2_ND45 (0x1u << 13)
541 #define MCAN_NDAT2_ND46 (0x1u << 14)
542 #define MCAN_NDAT2_ND47 (0x1u << 15)
543 #define MCAN_NDAT2_ND48 (0x1u << 16)
544 #define MCAN_NDAT2_ND49 (0x1u << 17)
545 #define MCAN_NDAT2_ND50 (0x1u << 18)
546 #define MCAN_NDAT2_ND51 (0x1u << 19)
547 #define MCAN_NDAT2_ND52 (0x1u << 20)
548 #define MCAN_NDAT2_ND53 (0x1u << 21)
549 #define MCAN_NDAT2_ND54 (0x1u << 22)
550 #define MCAN_NDAT2_ND55 (0x1u << 23)
551 #define MCAN_NDAT2_ND56 (0x1u << 24)
552 #define MCAN_NDAT2_ND57 (0x1u << 25)
553 #define MCAN_NDAT2_ND58 (0x1u << 26)
554 #define MCAN_NDAT2_ND59 (0x1u << 27)
555 #define MCAN_NDAT2_ND60 (0x1u << 28)
556 #define MCAN_NDAT2_ND61 (0x1u << 29)
557 #define MCAN_NDAT2_ND62 (0x1u << 30)
558 #define MCAN_NDAT2_ND63 (0x1u << 31)
559 /* -------- MCAN_RXF0C : (MCAN Offset: 0xA0) Receive FIFO 0 Configuration Register -------- */
560 #define MCAN_RXF0C_F0SA_Pos 2
561 #define MCAN_RXF0C_F0SA_Msk (0x3fffu << MCAN_RXF0C_F0SA_Pos)
562 #define MCAN_RXF0C_F0SA(value) ((MCAN_RXF0C_F0SA_Msk & ((value) << MCAN_RXF0C_F0SA_Pos)))
563 #define MCAN_RXF0C_F0S_Pos 16
564 #define MCAN_RXF0C_F0S_Msk (0x7fu << MCAN_RXF0C_F0S_Pos)
565 #define MCAN_RXF0C_F0S(value) ((MCAN_RXF0C_F0S_Msk & ((value) << MCAN_RXF0C_F0S_Pos)))
566 #define MCAN_RXF0C_F0WM_Pos 24
567 #define MCAN_RXF0C_F0WM_Msk (0x7fu << MCAN_RXF0C_F0WM_Pos)
568 #define MCAN_RXF0C_F0WM(value) ((MCAN_RXF0C_F0WM_Msk & ((value) << MCAN_RXF0C_F0WM_Pos)))
569 #define MCAN_RXF0C_F0OM (0x1u << 31)
570 /* -------- MCAN_RXF0S : (MCAN Offset: 0xA4) Receive FIFO 0 Status Register -------- */
571 #define MCAN_RXF0S_F0FL_Pos 0
572 #define MCAN_RXF0S_F0FL_Msk (0x7fu << MCAN_RXF0S_F0FL_Pos)
573 #define MCAN_RXF0S_F0GI_Pos 8
574 #define MCAN_RXF0S_F0GI_Msk (0x3fu << MCAN_RXF0S_F0GI_Pos)
575 #define MCAN_RXF0S_F0PI_Pos 16
576 #define MCAN_RXF0S_F0PI_Msk (0x3fu << MCAN_RXF0S_F0PI_Pos)
577 #define MCAN_RXF0S_F0F (0x1u << 24)
578 #define MCAN_RXF0S_RF0L (0x1u << 25)
579 /* -------- MCAN_RXF0A : (MCAN Offset: 0xA8) Receive FIFO 0 Acknowledge Register -------- */
580 #define MCAN_RXF0A_F0AI_Pos 0
581 #define MCAN_RXF0A_F0AI_Msk (0x3fu << MCAN_RXF0A_F0AI_Pos)
582 #define MCAN_RXF0A_F0AI(value) ((MCAN_RXF0A_F0AI_Msk & ((value) << MCAN_RXF0A_F0AI_Pos)))
583 /* -------- MCAN_RXBC : (MCAN Offset: 0xAC) Receive Rx Buffer Configuration Register -------- */
584 #define MCAN_RXBC_RBSA_Pos 2
585 #define MCAN_RXBC_RBSA_Msk (0x3fffu << MCAN_RXBC_RBSA_Pos)
586 #define MCAN_RXBC_RBSA(value) ((MCAN_RXBC_RBSA_Msk & ((value) << MCAN_RXBC_RBSA_Pos)))
587 /* -------- MCAN_RXF1C : (MCAN Offset: 0xB0) Receive FIFO 1 Configuration Register -------- */
588 #define MCAN_RXF1C_F1SA_Pos 2
589 #define MCAN_RXF1C_F1SA_Msk (0x3fffu << MCAN_RXF1C_F1SA_Pos)
590 #define MCAN_RXF1C_F1SA(value) ((MCAN_RXF1C_F1SA_Msk & ((value) << MCAN_RXF1C_F1SA_Pos)))
591 #define MCAN_RXF1C_F1S_Pos 16
592 #define MCAN_RXF1C_F1S_Msk (0x7fu << MCAN_RXF1C_F1S_Pos)
593 #define MCAN_RXF1C_F1S(value) ((MCAN_RXF1C_F1S_Msk & ((value) << MCAN_RXF1C_F1S_Pos)))
594 #define MCAN_RXF1C_F1WM_Pos 24
595 #define MCAN_RXF1C_F1WM_Msk (0x7fu << MCAN_RXF1C_F1WM_Pos)
596 #define MCAN_RXF1C_F1WM(value) ((MCAN_RXF1C_F1WM_Msk & ((value) << MCAN_RXF1C_F1WM_Pos)))
597 #define MCAN_RXF1C_F1OM (0x1u << 31)
598 /* -------- MCAN_RXF1S : (MCAN Offset: 0xB4) Receive FIFO 1 Status Register -------- */
599 #define MCAN_RXF1S_F1FL_Pos 0
600 #define MCAN_RXF1S_F1FL_Msk (0x7fu << MCAN_RXF1S_F1FL_Pos)
601 #define MCAN_RXF1S_F1GI_Pos 8
602 #define MCAN_RXF1S_F1GI_Msk (0x3fu << MCAN_RXF1S_F1GI_Pos)
603 #define MCAN_RXF1S_F1PI_Pos 16
604 #define MCAN_RXF1S_F1PI_Msk (0x3fu << MCAN_RXF1S_F1PI_Pos)
605 #define MCAN_RXF1S_F1F (0x1u << 24)
606 #define MCAN_RXF1S_RF1L (0x1u << 25)
607 #define MCAN_RXF1S_DMS_Pos 30
608 #define MCAN_RXF1S_DMS_Msk (0x3u << MCAN_RXF1S_DMS_Pos)
609 #define MCAN_RXF1S_DMS_IDLE (0x0u << 30)
610 #define MCAN_RXF1S_DMS_MSG_A (0x1u << 30)
611 #define MCAN_RXF1S_DMS_MSG_AB (0x2u << 30)
612 #define MCAN_RXF1S_DMS_MSG_ABC (0x3u << 30)
613 /* -------- MCAN_RXF1A : (MCAN Offset: 0xB8) Receive FIFO 1 Acknowledge Register -------- */
614 #define MCAN_RXF1A_F1AI_Pos 0
615 #define MCAN_RXF1A_F1AI_Msk (0x3fu << MCAN_RXF1A_F1AI_Pos)
616 #define MCAN_RXF1A_F1AI(value) ((MCAN_RXF1A_F1AI_Msk & ((value) << MCAN_RXF1A_F1AI_Pos)))
617 /* -------- MCAN_RXESC : (MCAN Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register -------- */
618 #define MCAN_RXESC_F0DS_Pos 0
619 #define MCAN_RXESC_F0DS_Msk (0x7u << MCAN_RXESC_F0DS_Pos)
620 #define MCAN_RXESC_F0DS(value) ((MCAN_RXESC_F0DS_Msk & ((value) << MCAN_RXESC_F0DS_Pos)))
621 #define MCAN_RXESC_F0DS_8_BYTE (0x0u << 0)
622 #define MCAN_RXESC_F0DS_12_BYTE (0x1u << 0)
623 #define MCAN_RXESC_F0DS_16_BYTE (0x2u << 0)
624 #define MCAN_RXESC_F0DS_20_BYTE (0x3u << 0)
625 #define MCAN_RXESC_F0DS_24_BYTE (0x4u << 0)
626 #define MCAN_RXESC_F0DS_32_BYTE (0x5u << 0)
627 #define MCAN_RXESC_F0DS_48_BYTE (0x6u << 0)
628 #define MCAN_RXESC_F0DS_64_BYTE (0x7u << 0)
629 #define MCAN_RXESC_F1DS_Pos 4
630 #define MCAN_RXESC_F1DS_Msk (0x7u << MCAN_RXESC_F1DS_Pos)
631 #define MCAN_RXESC_F1DS(value) ((MCAN_RXESC_F1DS_Msk & ((value) << MCAN_RXESC_F1DS_Pos)))
632 #define MCAN_RXESC_F1DS_8_BYTE (0x0u << 4)
633 #define MCAN_RXESC_F1DS_12_BYTE (0x1u << 4)
634 #define MCAN_RXESC_F1DS_16_BYTE (0x2u << 4)
635 #define MCAN_RXESC_F1DS_20_BYTE (0x3u << 4)
636 #define MCAN_RXESC_F1DS_24_BYTE (0x4u << 4)
637 #define MCAN_RXESC_F1DS_32_BYTE (0x5u << 4)
638 #define MCAN_RXESC_F1DS_48_BYTE (0x6u << 4)
639 #define MCAN_RXESC_F1DS_64_BYTE (0x7u << 4)
640 #define MCAN_RXESC_RBDS_Pos 8
641 #define MCAN_RXESC_RBDS_Msk (0x7u << MCAN_RXESC_RBDS_Pos)
642 #define MCAN_RXESC_RBDS(value) ((MCAN_RXESC_RBDS_Msk & ((value) << MCAN_RXESC_RBDS_Pos)))
643 #define MCAN_RXESC_RBDS_8_BYTE (0x0u << 8)
644 #define MCAN_RXESC_RBDS_12_BYTE (0x1u << 8)
645 #define MCAN_RXESC_RBDS_16_BYTE (0x2u << 8)
646 #define MCAN_RXESC_RBDS_20_BYTE (0x3u << 8)
647 #define MCAN_RXESC_RBDS_24_BYTE (0x4u << 8)
648 #define MCAN_RXESC_RBDS_32_BYTE (0x5u << 8)
649 #define MCAN_RXESC_RBDS_48_BYTE (0x6u << 8)
650 #define MCAN_RXESC_RBDS_64_BYTE (0x7u << 8)
651 /* -------- MCAN_TXBC : (MCAN Offset: 0xC0) Transmit Buffer Configuration Register -------- */
652 #define MCAN_TXBC_TBSA_Pos 2
653 #define MCAN_TXBC_TBSA_Msk (0x3fffu << MCAN_TXBC_TBSA_Pos)
654 #define MCAN_TXBC_TBSA(value) ((MCAN_TXBC_TBSA_Msk & ((value) << MCAN_TXBC_TBSA_Pos)))
655 #define MCAN_TXBC_NDTB_Pos 16
656 #define MCAN_TXBC_NDTB_Msk (0x3fu << MCAN_TXBC_NDTB_Pos)
657 #define MCAN_TXBC_NDTB(value) ((MCAN_TXBC_NDTB_Msk & ((value) << MCAN_TXBC_NDTB_Pos)))
658 #define MCAN_TXBC_TFQS_Pos 24
659 #define MCAN_TXBC_TFQS_Msk (0x3fu << MCAN_TXBC_TFQS_Pos)
660 #define MCAN_TXBC_TFQS(value) ((MCAN_TXBC_TFQS_Msk & ((value) << MCAN_TXBC_TFQS_Pos)))
661 #define MCAN_TXBC_TFQM (0x1u << 30)
662 /* -------- MCAN_TXFQS : (MCAN Offset: 0xC4) Transmit FIFO/Queue Status Register -------- */
663 #define MCAN_TXFQS_TFFL_Pos 0
664 #define MCAN_TXFQS_TFFL_Msk (0x3fu << MCAN_TXFQS_TFFL_Pos)
665 #define MCAN_TXFQS_TFGI_Pos 8
666 #define MCAN_TXFQS_TFGI_Msk (0x1fu << MCAN_TXFQS_TFGI_Pos)
667 #define MCAN_TXFQS_TFQPI_Pos 16
668 #define MCAN_TXFQS_TFQPI_Msk (0x1fu << MCAN_TXFQS_TFQPI_Pos)
669 #define MCAN_TXFQS_TFQF (0x1u << 21)
670 /* -------- MCAN_TXESC : (MCAN Offset: 0xC8) Transmit Buffer Element Size Configuration Register -------- */
671 #define MCAN_TXESC_TBDS_Pos 0
672 #define MCAN_TXESC_TBDS_Msk (0x7u << MCAN_TXESC_TBDS_Pos)
673 #define MCAN_TXESC_TBDS(value) ((MCAN_TXESC_TBDS_Msk & ((value) << MCAN_TXESC_TBDS_Pos)))
674 #define MCAN_TXESC_TBDS_8_BYTE (0x0u << 0)
675 #define MCAN_TXESC_TBDS_12_BYTE (0x1u << 0)
676 #define MCAN_TXESC_TBDS_16_BYTE (0x2u << 0)
677 #define MCAN_TXESC_TBDS_20_BYTE (0x3u << 0)
678 #define MCAN_TXESC_TBDS_24_BYTE (0x4u << 0)
679 #define MCAN_TXESC_TBDS_32_BYTE (0x5u << 0)
680 #define MCAN_TXESC_TBDS_48_BYTE (0x6u << 0)
681 #define MCAN_TXESC_TBDS_64_BYTE (0x7u << 0)
682 /* -------- MCAN_TXBRP : (MCAN Offset: 0xCC) Transmit Buffer Request Pending Register -------- */
683 #define MCAN_TXBRP_TRP0 (0x1u << 0)
684 #define MCAN_TXBRP_TRP1 (0x1u << 1)
685 #define MCAN_TXBRP_TRP2 (0x1u << 2)
686 #define MCAN_TXBRP_TRP3 (0x1u << 3)
687 #define MCAN_TXBRP_TRP4 (0x1u << 4)
688 #define MCAN_TXBRP_TRP5 (0x1u << 5)
689 #define MCAN_TXBRP_TRP6 (0x1u << 6)
690 #define MCAN_TXBRP_TRP7 (0x1u << 7)
691 #define MCAN_TXBRP_TRP8 (0x1u << 8)
692 #define MCAN_TXBRP_TRP9 (0x1u << 9)
693 #define MCAN_TXBRP_TRP10 (0x1u << 10)
694 #define MCAN_TXBRP_TRP11 (0x1u << 11)
695 #define MCAN_TXBRP_TRP12 (0x1u << 12)
696 #define MCAN_TXBRP_TRP13 (0x1u << 13)
697 #define MCAN_TXBRP_TRP14 (0x1u << 14)
698 #define MCAN_TXBRP_TRP15 (0x1u << 15)
699 #define MCAN_TXBRP_TRP16 (0x1u << 16)
700 #define MCAN_TXBRP_TRP17 (0x1u << 17)
701 #define MCAN_TXBRP_TRP18 (0x1u << 18)
702 #define MCAN_TXBRP_TRP19 (0x1u << 19)
703 #define MCAN_TXBRP_TRP20 (0x1u << 20)
704 #define MCAN_TXBRP_TRP21 (0x1u << 21)
705 #define MCAN_TXBRP_TRP22 (0x1u << 22)
706 #define MCAN_TXBRP_TRP23 (0x1u << 23)
707 #define MCAN_TXBRP_TRP24 (0x1u << 24)
708 #define MCAN_TXBRP_TRP25 (0x1u << 25)
709 #define MCAN_TXBRP_TRP26 (0x1u << 26)
710 #define MCAN_TXBRP_TRP27 (0x1u << 27)
711 #define MCAN_TXBRP_TRP28 (0x1u << 28)
712 #define MCAN_TXBRP_TRP29 (0x1u << 29)
713 #define MCAN_TXBRP_TRP30 (0x1u << 30)
714 #define MCAN_TXBRP_TRP31 (0x1u << 31)
715 /* -------- MCAN_TXBAR : (MCAN Offset: 0xD0) Transmit Buffer Add Request Register -------- */
716 #define MCAN_TXBAR_AR0 (0x1u << 0)
717 #define MCAN_TXBAR_AR1 (0x1u << 1)
718 #define MCAN_TXBAR_AR2 (0x1u << 2)
719 #define MCAN_TXBAR_AR3 (0x1u << 3)
720 #define MCAN_TXBAR_AR4 (0x1u << 4)
721 #define MCAN_TXBAR_AR5 (0x1u << 5)
722 #define MCAN_TXBAR_AR6 (0x1u << 6)
723 #define MCAN_TXBAR_AR7 (0x1u << 7)
724 #define MCAN_TXBAR_AR8 (0x1u << 8)
725 #define MCAN_TXBAR_AR9 (0x1u << 9)
726 #define MCAN_TXBAR_AR10 (0x1u << 10)
727 #define MCAN_TXBAR_AR11 (0x1u << 11)
728 #define MCAN_TXBAR_AR12 (0x1u << 12)
729 #define MCAN_TXBAR_AR13 (0x1u << 13)
730 #define MCAN_TXBAR_AR14 (0x1u << 14)
731 #define MCAN_TXBAR_AR15 (0x1u << 15)
732 #define MCAN_TXBAR_AR16 (0x1u << 16)
733 #define MCAN_TXBAR_AR17 (0x1u << 17)
734 #define MCAN_TXBAR_AR18 (0x1u << 18)
735 #define MCAN_TXBAR_AR19 (0x1u << 19)
736 #define MCAN_TXBAR_AR20 (0x1u << 20)
737 #define MCAN_TXBAR_AR21 (0x1u << 21)
738 #define MCAN_TXBAR_AR22 (0x1u << 22)
739 #define MCAN_TXBAR_AR23 (0x1u << 23)
740 #define MCAN_TXBAR_AR24 (0x1u << 24)
741 #define MCAN_TXBAR_AR25 (0x1u << 25)
742 #define MCAN_TXBAR_AR26 (0x1u << 26)
743 #define MCAN_TXBAR_AR27 (0x1u << 27)
744 #define MCAN_TXBAR_AR28 (0x1u << 28)
745 #define MCAN_TXBAR_AR29 (0x1u << 29)
746 #define MCAN_TXBAR_AR30 (0x1u << 30)
747 #define MCAN_TXBAR_AR31 (0x1u << 31)
748 /* -------- MCAN_TXBCR : (MCAN Offset: 0xD4) Transmit Buffer Cancellation Request Register -------- */
749 #define MCAN_TXBCR_CR0 (0x1u << 0)
750 #define MCAN_TXBCR_CR1 (0x1u << 1)
751 #define MCAN_TXBCR_CR2 (0x1u << 2)
752 #define MCAN_TXBCR_CR3 (0x1u << 3)
753 #define MCAN_TXBCR_CR4 (0x1u << 4)
754 #define MCAN_TXBCR_CR5 (0x1u << 5)
755 #define MCAN_TXBCR_CR6 (0x1u << 6)
756 #define MCAN_TXBCR_CR7 (0x1u << 7)
757 #define MCAN_TXBCR_CR8 (0x1u << 8)
758 #define MCAN_TXBCR_CR9 (0x1u << 9)
759 #define MCAN_TXBCR_CR10 (0x1u << 10)
760 #define MCAN_TXBCR_CR11 (0x1u << 11)
761 #define MCAN_TXBCR_CR12 (0x1u << 12)
762 #define MCAN_TXBCR_CR13 (0x1u << 13)
763 #define MCAN_TXBCR_CR14 (0x1u << 14)
764 #define MCAN_TXBCR_CR15 (0x1u << 15)
765 #define MCAN_TXBCR_CR16 (0x1u << 16)
766 #define MCAN_TXBCR_CR17 (0x1u << 17)
767 #define MCAN_TXBCR_CR18 (0x1u << 18)
768 #define MCAN_TXBCR_CR19 (0x1u << 19)
769 #define MCAN_TXBCR_CR20 (0x1u << 20)
770 #define MCAN_TXBCR_CR21 (0x1u << 21)
771 #define MCAN_TXBCR_CR22 (0x1u << 22)
772 #define MCAN_TXBCR_CR23 (0x1u << 23)
773 #define MCAN_TXBCR_CR24 (0x1u << 24)
774 #define MCAN_TXBCR_CR25 (0x1u << 25)
775 #define MCAN_TXBCR_CR26 (0x1u << 26)
776 #define MCAN_TXBCR_CR27 (0x1u << 27)
777 #define MCAN_TXBCR_CR28 (0x1u << 28)
778 #define MCAN_TXBCR_CR29 (0x1u << 29)
779 #define MCAN_TXBCR_CR30 (0x1u << 30)
780 #define MCAN_TXBCR_CR31 (0x1u << 31)
781 /* -------- MCAN_TXBTO : (MCAN Offset: 0xD8) Transmit Buffer Transmission Occurred Register -------- */
782 #define MCAN_TXBTO_TO0 (0x1u << 0)
783 #define MCAN_TXBTO_TO1 (0x1u << 1)
784 #define MCAN_TXBTO_TO2 (0x1u << 2)
785 #define MCAN_TXBTO_TO3 (0x1u << 3)
786 #define MCAN_TXBTO_TO4 (0x1u << 4)
787 #define MCAN_TXBTO_TO5 (0x1u << 5)
788 #define MCAN_TXBTO_TO6 (0x1u << 6)
789 #define MCAN_TXBTO_TO7 (0x1u << 7)
790 #define MCAN_TXBTO_TO8 (0x1u << 8)
791 #define MCAN_TXBTO_TO9 (0x1u << 9)
792 #define MCAN_TXBTO_TO10 (0x1u << 10)
793 #define MCAN_TXBTO_TO11 (0x1u << 11)
794 #define MCAN_TXBTO_TO12 (0x1u << 12)
795 #define MCAN_TXBTO_TO13 (0x1u << 13)
796 #define MCAN_TXBTO_TO14 (0x1u << 14)
797 #define MCAN_TXBTO_TO15 (0x1u << 15)
798 #define MCAN_TXBTO_TO16 (0x1u << 16)
799 #define MCAN_TXBTO_TO17 (0x1u << 17)
800 #define MCAN_TXBTO_TO18 (0x1u << 18)
801 #define MCAN_TXBTO_TO19 (0x1u << 19)
802 #define MCAN_TXBTO_TO20 (0x1u << 20)
803 #define MCAN_TXBTO_TO21 (0x1u << 21)
804 #define MCAN_TXBTO_TO22 (0x1u << 22)
805 #define MCAN_TXBTO_TO23 (0x1u << 23)
806 #define MCAN_TXBTO_TO24 (0x1u << 24)
807 #define MCAN_TXBTO_TO25 (0x1u << 25)
808 #define MCAN_TXBTO_TO26 (0x1u << 26)
809 #define MCAN_TXBTO_TO27 (0x1u << 27)
810 #define MCAN_TXBTO_TO28 (0x1u << 28)
811 #define MCAN_TXBTO_TO29 (0x1u << 29)
812 #define MCAN_TXBTO_TO30 (0x1u << 30)
813 #define MCAN_TXBTO_TO31 (0x1u << 31)
814 /* -------- MCAN_TXBCF : (MCAN Offset: 0xDC) Transmit Buffer Cancellation Finished Register -------- */
815 #define MCAN_TXBCF_CF0 (0x1u << 0)
816 #define MCAN_TXBCF_CF1 (0x1u << 1)
817 #define MCAN_TXBCF_CF2 (0x1u << 2)
818 #define MCAN_TXBCF_CF3 (0x1u << 3)
819 #define MCAN_TXBCF_CF4 (0x1u << 4)
820 #define MCAN_TXBCF_CF5 (0x1u << 5)
821 #define MCAN_TXBCF_CF6 (0x1u << 6)
822 #define MCAN_TXBCF_CF7 (0x1u << 7)
823 #define MCAN_TXBCF_CF8 (0x1u << 8)
824 #define MCAN_TXBCF_CF9 (0x1u << 9)
825 #define MCAN_TXBCF_CF10 (0x1u << 10)
826 #define MCAN_TXBCF_CF11 (0x1u << 11)
827 #define MCAN_TXBCF_CF12 (0x1u << 12)
828 #define MCAN_TXBCF_CF13 (0x1u << 13)
829 #define MCAN_TXBCF_CF14 (0x1u << 14)
830 #define MCAN_TXBCF_CF15 (0x1u << 15)
831 #define MCAN_TXBCF_CF16 (0x1u << 16)
832 #define MCAN_TXBCF_CF17 (0x1u << 17)
833 #define MCAN_TXBCF_CF18 (0x1u << 18)
834 #define MCAN_TXBCF_CF19 (0x1u << 19)
835 #define MCAN_TXBCF_CF20 (0x1u << 20)
836 #define MCAN_TXBCF_CF21 (0x1u << 21)
837 #define MCAN_TXBCF_CF22 (0x1u << 22)
838 #define MCAN_TXBCF_CF23 (0x1u << 23)
839 #define MCAN_TXBCF_CF24 (0x1u << 24)
840 #define MCAN_TXBCF_CF25 (0x1u << 25)
841 #define MCAN_TXBCF_CF26 (0x1u << 26)
842 #define MCAN_TXBCF_CF27 (0x1u << 27)
843 #define MCAN_TXBCF_CF28 (0x1u << 28)
844 #define MCAN_TXBCF_CF29 (0x1u << 29)
845 #define MCAN_TXBCF_CF30 (0x1u << 30)
846 #define MCAN_TXBCF_CF31 (0x1u << 31)
847 /* -------- MCAN_TXBTIE : (MCAN Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register -------- */
848 #define MCAN_TXBTIE_TIE0 (0x1u << 0)
849 #define MCAN_TXBTIE_TIE1 (0x1u << 1)
850 #define MCAN_TXBTIE_TIE2 (0x1u << 2)
851 #define MCAN_TXBTIE_TIE3 (0x1u << 3)
852 #define MCAN_TXBTIE_TIE4 (0x1u << 4)
853 #define MCAN_TXBTIE_TIE5 (0x1u << 5)
854 #define MCAN_TXBTIE_TIE6 (0x1u << 6)
855 #define MCAN_TXBTIE_TIE7 (0x1u << 7)
856 #define MCAN_TXBTIE_TIE8 (0x1u << 8)
857 #define MCAN_TXBTIE_TIE9 (0x1u << 9)
858 #define MCAN_TXBTIE_TIE10 (0x1u << 10)
859 #define MCAN_TXBTIE_TIE11 (0x1u << 11)
860 #define MCAN_TXBTIE_TIE12 (0x1u << 12)
861 #define MCAN_TXBTIE_TIE13 (0x1u << 13)
862 #define MCAN_TXBTIE_TIE14 (0x1u << 14)
863 #define MCAN_TXBTIE_TIE15 (0x1u << 15)
864 #define MCAN_TXBTIE_TIE16 (0x1u << 16)
865 #define MCAN_TXBTIE_TIE17 (0x1u << 17)
866 #define MCAN_TXBTIE_TIE18 (0x1u << 18)
867 #define MCAN_TXBTIE_TIE19 (0x1u << 19)
868 #define MCAN_TXBTIE_TIE20 (0x1u << 20)
869 #define MCAN_TXBTIE_TIE21 (0x1u << 21)
870 #define MCAN_TXBTIE_TIE22 (0x1u << 22)
871 #define MCAN_TXBTIE_TIE23 (0x1u << 23)
872 #define MCAN_TXBTIE_TIE24 (0x1u << 24)
873 #define MCAN_TXBTIE_TIE25 (0x1u << 25)
874 #define MCAN_TXBTIE_TIE26 (0x1u << 26)
875 #define MCAN_TXBTIE_TIE27 (0x1u << 27)
876 #define MCAN_TXBTIE_TIE28 (0x1u << 28)
877 #define MCAN_TXBTIE_TIE29 (0x1u << 29)
878 #define MCAN_TXBTIE_TIE30 (0x1u << 30)
879 #define MCAN_TXBTIE_TIE31 (0x1u << 31)
880 /* -------- MCAN_TXBCIE : (MCAN Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register -------- */
881 #define MCAN_TXBCIE_CFIE0 (0x1u << 0)
882 #define MCAN_TXBCIE_CFIE1 (0x1u << 1)
883 #define MCAN_TXBCIE_CFIE2 (0x1u << 2)
884 #define MCAN_TXBCIE_CFIE3 (0x1u << 3)
885 #define MCAN_TXBCIE_CFIE4 (0x1u << 4)
886 #define MCAN_TXBCIE_CFIE5 (0x1u << 5)
887 #define MCAN_TXBCIE_CFIE6 (0x1u << 6)
888 #define MCAN_TXBCIE_CFIE7 (0x1u << 7)
889 #define MCAN_TXBCIE_CFIE8 (0x1u << 8)
890 #define MCAN_TXBCIE_CFIE9 (0x1u << 9)
891 #define MCAN_TXBCIE_CFIE10 (0x1u << 10)
892 #define MCAN_TXBCIE_CFIE11 (0x1u << 11)
893 #define MCAN_TXBCIE_CFIE12 (0x1u << 12)
894 #define MCAN_TXBCIE_CFIE13 (0x1u << 13)
895 #define MCAN_TXBCIE_CFIE14 (0x1u << 14)
896 #define MCAN_TXBCIE_CFIE15 (0x1u << 15)
897 #define MCAN_TXBCIE_CFIE16 (0x1u << 16)
898 #define MCAN_TXBCIE_CFIE17 (0x1u << 17)
899 #define MCAN_TXBCIE_CFIE18 (0x1u << 18)
900 #define MCAN_TXBCIE_CFIE19 (0x1u << 19)
901 #define MCAN_TXBCIE_CFIE20 (0x1u << 20)
902 #define MCAN_TXBCIE_CFIE21 (0x1u << 21)
903 #define MCAN_TXBCIE_CFIE22 (0x1u << 22)
904 #define MCAN_TXBCIE_CFIE23 (0x1u << 23)
905 #define MCAN_TXBCIE_CFIE24 (0x1u << 24)
906 #define MCAN_TXBCIE_CFIE25 (0x1u << 25)
907 #define MCAN_TXBCIE_CFIE26 (0x1u << 26)
908 #define MCAN_TXBCIE_CFIE27 (0x1u << 27)
909 #define MCAN_TXBCIE_CFIE28 (0x1u << 28)
910 #define MCAN_TXBCIE_CFIE29 (0x1u << 29)
911 #define MCAN_TXBCIE_CFIE30 (0x1u << 30)
912 #define MCAN_TXBCIE_CFIE31 (0x1u << 31)
913 /* -------- MCAN_TXEFC : (MCAN Offset: 0xF0) Transmit Event FIFO Configuration Register -------- */
914 #define MCAN_TXEFC_EFSA_Pos 2
915 #define MCAN_TXEFC_EFSA_Msk (0x3fffu << MCAN_TXEFC_EFSA_Pos)
916 #define MCAN_TXEFC_EFSA(value) ((MCAN_TXEFC_EFSA_Msk & ((value) << MCAN_TXEFC_EFSA_Pos)))
917 #define MCAN_TXEFC_EFS_Pos 16
918 #define MCAN_TXEFC_EFS_Msk (0x3fu << MCAN_TXEFC_EFS_Pos)
919 #define MCAN_TXEFC_EFS(value) ((MCAN_TXEFC_EFS_Msk & ((value) << MCAN_TXEFC_EFS_Pos)))
920 #define MCAN_TXEFC_EFWM_Pos 24
921 #define MCAN_TXEFC_EFWM_Msk (0x3fu << MCAN_TXEFC_EFWM_Pos)
922 #define MCAN_TXEFC_EFWM(value) ((MCAN_TXEFC_EFWM_Msk & ((value) << MCAN_TXEFC_EFWM_Pos)))
923 /* -------- MCAN_TXEFS : (MCAN Offset: 0xF4) Transmit Event FIFO Status Register -------- */
924 #define MCAN_TXEFS_EFFL_Pos 0
925 #define MCAN_TXEFS_EFFL_Msk (0x3fu << MCAN_TXEFS_EFFL_Pos)
926 #define MCAN_TXEFS_EFGI_Pos 8
927 #define MCAN_TXEFS_EFGI_Msk (0x1fu << MCAN_TXEFS_EFGI_Pos)
928 #define MCAN_TXEFS_EFPI_Pos 16
929 #define MCAN_TXEFS_EFPI_Msk (0x1fu << MCAN_TXEFS_EFPI_Pos)
930 #define MCAN_TXEFS_EFF (0x1u << 24)
931 #define MCAN_TXEFS_TEFL (0x1u << 25)
932 /* -------- MCAN_TXEFA : (MCAN Offset: 0xF8) Transmit Event FIFO Acknowledge Register -------- */
933 #define MCAN_TXEFA_EFAI_Pos 0
934 #define MCAN_TXEFA_EFAI_Msk (0x1fu << MCAN_TXEFA_EFAI_Pos)
935 #define MCAN_TXEFA_EFAI(value) ((MCAN_TXEFA_EFAI_Msk & ((value) << MCAN_TXEFA_EFAI_Pos)))
936 
940 #endif /* _SAME70_MCAN_COMPONENT_ */
__I uint32_t MCAN_HPMS
(Mcan Offset: 0x94) High Priority Message Status Register
__IO uint32_t MCAN_XIDAM
(Mcan Offset: 0x90) Extended ID AND Mask Register
__I uint32_t MCAN_RXF0S
(Mcan Offset: 0xA4) Receive FIFO 0 Status Register
__I uint32_t MCAN_TXBTO
(Mcan Offset: 0xD8) Transmit Buffer Transmission Occurred Register
__IO uint32_t MCAN_TXBCR
(Mcan Offset: 0xD4) Transmit Buffer Cancellation Request Register
__IO uint32_t MCAN_TXBAR
(Mcan Offset: 0xD0) Transmit Buffer Add Request Register
__IO uint32_t MCAN_TXBCIE
(Mcan Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register ...
__I uint32_t MCAN_TXBRP
(Mcan Offset: 0xCC) Transmit Buffer Request Pending Register
__IO uint32_t MCAN_IE
(Mcan Offset: 0x54) Interrupt Enable Register
__I uint32_t MCAN_CREL
(Mcan Offset: 0x00) Core Release Register
#define __IO
Definition: core_cm7.h:266
Mcan hardware registers.
__IO uint32_t MCAN_RXBC
(Mcan Offset: 0xAC) Receive Rx Buffer Configuration Register
__IO uint32_t MCAN_TEST
(Mcan Offset: 0x10) Test Register
__IO uint32_t MCAN_TOCV
(Mcan Offset: 0x2C) Timeout Counter Value Register
__IO uint32_t MCAN_SIDFC
(Mcan Offset: 0x84) Standard ID Filter Configuration Register
__I uint32_t MCAN_TXFQS
(Mcan Offset: 0xC4) Transmit FIFO/Queue Status Register
__IO uint32_t MCAN_RXF0C
(Mcan Offset: 0xA0) Receive FIFO 0 Configuration Register
__IO uint32_t MCAN_FBTP
(Mcan Offset: 0x0C) Fast Bit Timing and Prescaler Register
__IO uint32_t MCAN_CUST
(Mcan Offset: 0x08) Customer Register
__IO uint32_t MCAN_NDAT2
(Mcan Offset: 0x9C) New Data 2 Register
__IO uint32_t MCAN_TXBC
(Mcan Offset: 0xC0) Transmit Buffer Configuration Register
__IO uint32_t MCAN_ILS
(Mcan Offset: 0x58) Interrupt Line Select Register
__IO uint32_t MCAN_ILE
(Mcan Offset: 0x5C) Interrupt Line Enable Register
__IO uint32_t MCAN_TSCC
(Mcan Offset: 0x20) Timestamp Counter Configuration Register
__IO uint32_t MCAN_CCCR
(Mcan Offset: 0x18) CC Control Register
__IO uint32_t MCAN_RXESC
(Mcan Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register
__IO uint32_t MCAN_XIDFC
(Mcan Offset: 0x88) Extended ID Filter Configuration Register
__I uint32_t MCAN_ECR
(Mcan Offset: 0x40) Error Counter Register
__I uint32_t MCAN_TXBCF
(Mcan Offset: 0xDC) Transmit Buffer Cancellation Finished Register
__IO uint32_t MCAN_RXF1A
(Mcan Offset: 0xB8) Receive FIFO 1 Acknowledge Register
__IO uint32_t MCAN_RXF0A
(Mcan Offset: 0xA8) Receive FIFO 0 Acknowledge Register
__IO uint32_t MCAN_TOCC
(Mcan Offset: 0x28) Timeout Counter Configuration Register
__IO uint32_t MCAN_IR
(Mcan Offset: 0x50) Interrupt Register
__IO uint32_t MCAN_BTP
(Mcan Offset: 0x1C) Bit Timing and Prescaler Register
__IO uint32_t MCAN_TSCV
(Mcan Offset: 0x24) Timestamp Counter Value Register
__I uint32_t MCAN_RXF1S
(Mcan Offset: 0xB4) Receive FIFO 1 Status Register
__IO uint32_t MCAN_TXBTIE
(Mcan Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register
__IO uint32_t MCAN_NDAT1
(Mcan Offset: 0x98) New Data 1 Register
__IO uint32_t MCAN_TXEFA
(Mcan Offset: 0xF8) Transmit Event FIFO Acknowledge Register
__I uint32_t MCAN_PSR
(Mcan Offset: 0x44) Protocol Status Register
__IO uint32_t MCAN_RXF1C
(Mcan Offset: 0xB0) Receive FIFO 1 Configuration Register
__IO uint32_t MCAN_GFC
(Mcan Offset: 0x80) Global Filter Configuration Register
__I uint32_t MCAN_TXEFS
(Mcan Offset: 0xF4) Transmit Event FIFO Status Register
__I uint32_t MCAN_ENDN
(Mcan Offset: 0x04) Endian Register
__IO uint32_t MCAN_RWD
(Mcan Offset: 0x14) RAM Watchdog Register
#define __I
Definition: core_cm7.h:263
__IO uint32_t MCAN_TXEFC
(Mcan Offset: 0xF0) Transmit Event FIFO Configuration Register
__IO uint32_t MCAN_TXESC
(Mcan Offset: 0xC8) Transmit Buffer Element Size Configuration Register


inertial_sense_ros
Author(s):
autogenerated on Sat Sep 19 2020 03:19:04