Public Attributes | List of all members
Mcan Struct Reference

Mcan hardware registers. More...

#include <mcan.h>

Public Attributes

__IO uint32_t MCAN_BTP
 (Mcan Offset: 0x1C) Bit Timing and Prescaler Register More...
 
__IO uint32_t MCAN_CCCR
 (Mcan Offset: 0x18) CC Control Register More...
 
__I uint32_t MCAN_CREL
 (Mcan Offset: 0x00) Core Release Register More...
 
__IO uint32_t MCAN_CUST
 (Mcan Offset: 0x08) Customer Register More...
 
__I uint32_t MCAN_ECR
 (Mcan Offset: 0x40) Error Counter Register More...
 
__I uint32_t MCAN_ENDN
 (Mcan Offset: 0x04) Endian Register More...
 
__IO uint32_t MCAN_FBTP
 (Mcan Offset: 0x0C) Fast Bit Timing and Prescaler Register More...
 
__IO uint32_t MCAN_GFC
 (Mcan Offset: 0x80) Global Filter Configuration Register More...
 
__I uint32_t MCAN_HPMS
 (Mcan Offset: 0x94) High Priority Message Status Register More...
 
__IO uint32_t MCAN_IE
 (Mcan Offset: 0x54) Interrupt Enable Register More...
 
__IO uint32_t MCAN_ILE
 (Mcan Offset: 0x5C) Interrupt Line Enable Register More...
 
__IO uint32_t MCAN_ILS
 (Mcan Offset: 0x58) Interrupt Line Select Register More...
 
__IO uint32_t MCAN_IR
 (Mcan Offset: 0x50) Interrupt Register More...
 
__IO uint32_t MCAN_NDAT1
 (Mcan Offset: 0x98) New Data 1 Register More...
 
__IO uint32_t MCAN_NDAT2
 (Mcan Offset: 0x9C) New Data 2 Register More...
 
__I uint32_t MCAN_PSR
 (Mcan Offset: 0x44) Protocol Status Register More...
 
__IO uint32_t MCAN_RWD
 (Mcan Offset: 0x14) RAM Watchdog Register More...
 
__IO uint32_t MCAN_RXBC
 (Mcan Offset: 0xAC) Receive Rx Buffer Configuration Register More...
 
__IO uint32_t MCAN_RXESC
 (Mcan Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register More...
 
__IO uint32_t MCAN_RXF0A
 (Mcan Offset: 0xA8) Receive FIFO 0 Acknowledge Register More...
 
__IO uint32_t MCAN_RXF0C
 (Mcan Offset: 0xA0) Receive FIFO 0 Configuration Register More...
 
__I uint32_t MCAN_RXF0S
 (Mcan Offset: 0xA4) Receive FIFO 0 Status Register More...
 
__IO uint32_t MCAN_RXF1A
 (Mcan Offset: 0xB8) Receive FIFO 1 Acknowledge Register More...
 
__IO uint32_t MCAN_RXF1C
 (Mcan Offset: 0xB0) Receive FIFO 1 Configuration Register More...
 
__I uint32_t MCAN_RXF1S
 (Mcan Offset: 0xB4) Receive FIFO 1 Status Register More...
 
__IO uint32_t MCAN_SIDFC
 (Mcan Offset: 0x84) Standard ID Filter Configuration Register More...
 
__IO uint32_t MCAN_TEST
 (Mcan Offset: 0x10) Test Register More...
 
__IO uint32_t MCAN_TOCC
 (Mcan Offset: 0x28) Timeout Counter Configuration Register More...
 
__IO uint32_t MCAN_TOCV
 (Mcan Offset: 0x2C) Timeout Counter Value Register More...
 
__IO uint32_t MCAN_TSCC
 (Mcan Offset: 0x20) Timestamp Counter Configuration Register More...
 
__IO uint32_t MCAN_TSCV
 (Mcan Offset: 0x24) Timestamp Counter Value Register More...
 
__IO uint32_t MCAN_TXBAR
 (Mcan Offset: 0xD0) Transmit Buffer Add Request Register More...
 
__IO uint32_t MCAN_TXBC
 (Mcan Offset: 0xC0) Transmit Buffer Configuration Register More...
 
__I uint32_t MCAN_TXBCF
 (Mcan Offset: 0xDC) Transmit Buffer Cancellation Finished Register More...
 
__IO uint32_t MCAN_TXBCIE
 (Mcan Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register More...
 
__IO uint32_t MCAN_TXBCR
 (Mcan Offset: 0xD4) Transmit Buffer Cancellation Request Register More...
 
__I uint32_t MCAN_TXBRP
 (Mcan Offset: 0xCC) Transmit Buffer Request Pending Register More...
 
__IO uint32_t MCAN_TXBTIE
 (Mcan Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register More...
 
__I uint32_t MCAN_TXBTO
 (Mcan Offset: 0xD8) Transmit Buffer Transmission Occurred Register More...
 
__IO uint32_t MCAN_TXEFA
 (Mcan Offset: 0xF8) Transmit Event FIFO Acknowledge Register More...
 
__IO uint32_t MCAN_TXEFC
 (Mcan Offset: 0xF0) Transmit Event FIFO Configuration Register More...
 
__I uint32_t MCAN_TXEFS
 (Mcan Offset: 0xF4) Transmit Event FIFO Status Register More...
 
__IO uint32_t MCAN_TXESC
 (Mcan Offset: 0xC8) Transmit Buffer Element Size Configuration Register More...
 
__I uint32_t MCAN_TXFQS
 (Mcan Offset: 0xC4) Transmit FIFO/Queue Status Register More...
 
__IO uint32_t MCAN_XIDAM
 (Mcan Offset: 0x90) Extended ID AND Mask Register More...
 
__IO uint32_t MCAN_XIDFC
 (Mcan Offset: 0x88) Extended ID Filter Configuration Register More...
 
__I uint32_t Reserved1 [4]
 
__I uint32_t Reserved2 [2]
 
__I uint32_t Reserved3 [8]
 
__I uint32_t Reserved4 [1]
 
__I uint32_t Reserved5 [2]
 

Detailed Description

Mcan hardware registers.

Definition at line 46 of file utils/cmsis/same70/include/component/mcan.h.

Member Data Documentation

◆ MCAN_BTP

__IO uint32_t Mcan::MCAN_BTP

(Mcan Offset: 0x1C) Bit Timing and Prescaler Register

Definition at line 61 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_CCCR

__IO uint32_t Mcan::MCAN_CCCR

(Mcan Offset: 0x18) CC Control Register

Definition at line 57 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_CREL

__I uint32_t Mcan::MCAN_CREL

(Mcan Offset: 0x00) Core Release Register

Definition at line 47 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_CUST

__IO uint32_t Mcan::MCAN_CUST

(Mcan Offset: 0x08) Customer Register

Definition at line 49 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_ECR

__I uint32_t Mcan::MCAN_ECR

(Mcan Offset: 0x40) Error Counter Register

Definition at line 68 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_ENDN

__I uint32_t Mcan::MCAN_ENDN

(Mcan Offset: 0x04) Endian Register

Definition at line 48 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_FBTP

__IO uint32_t Mcan::MCAN_FBTP

(Mcan Offset: 0x0C) Fast Bit Timing and Prescaler Register

Definition at line 53 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_GFC

__IO uint32_t Mcan::MCAN_GFC

(Mcan Offset: 0x80) Global Filter Configuration Register

Definition at line 81 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_HPMS

__I uint32_t Mcan::MCAN_HPMS

(Mcan Offset: 0x94) High Priority Message Status Register

Definition at line 86 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_IE

__IO uint32_t Mcan::MCAN_IE

(Mcan Offset: 0x54) Interrupt Enable Register

Definition at line 77 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_ILE

__IO uint32_t Mcan::MCAN_ILE

(Mcan Offset: 0x5C) Interrupt Line Enable Register

Definition at line 79 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_ILS

__IO uint32_t Mcan::MCAN_ILS

(Mcan Offset: 0x58) Interrupt Line Select Register

Definition at line 78 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_IR

__IO uint32_t Mcan::MCAN_IR

(Mcan Offset: 0x50) Interrupt Register

Definition at line 76 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_NDAT1

__IO uint32_t Mcan::MCAN_NDAT1

(Mcan Offset: 0x98) New Data 1 Register

Definition at line 87 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_NDAT2

__IO uint32_t Mcan::MCAN_NDAT2

(Mcan Offset: 0x9C) New Data 2 Register

Definition at line 88 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_PSR

__I uint32_t Mcan::MCAN_PSR

(Mcan Offset: 0x44) Protocol Status Register

Definition at line 69 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_RWD

__IO uint32_t Mcan::MCAN_RWD

(Mcan Offset: 0x14) RAM Watchdog Register

Definition at line 56 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_RXBC

__IO uint32_t Mcan::MCAN_RXBC

(Mcan Offset: 0xAC) Receive Rx Buffer Configuration Register

Definition at line 92 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_RXESC

__IO uint32_t Mcan::MCAN_RXESC

(Mcan Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register

Definition at line 96 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_RXF0A

__IO uint32_t Mcan::MCAN_RXF0A

(Mcan Offset: 0xA8) Receive FIFO 0 Acknowledge Register

Definition at line 91 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_RXF0C

__IO uint32_t Mcan::MCAN_RXF0C

(Mcan Offset: 0xA0) Receive FIFO 0 Configuration Register

Definition at line 89 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_RXF0S

__I uint32_t Mcan::MCAN_RXF0S

(Mcan Offset: 0xA4) Receive FIFO 0 Status Register

Definition at line 90 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_RXF1A

__IO uint32_t Mcan::MCAN_RXF1A

(Mcan Offset: 0xB8) Receive FIFO 1 Acknowledge Register

Definition at line 95 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_RXF1C

__IO uint32_t Mcan::MCAN_RXF1C

(Mcan Offset: 0xB0) Receive FIFO 1 Configuration Register

Definition at line 93 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_RXF1S

__I uint32_t Mcan::MCAN_RXF1S

(Mcan Offset: 0xB4) Receive FIFO 1 Status Register

Definition at line 94 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_SIDFC

__IO uint32_t Mcan::MCAN_SIDFC

(Mcan Offset: 0x84) Standard ID Filter Configuration Register

Definition at line 82 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_TEST

__IO uint32_t Mcan::MCAN_TEST

(Mcan Offset: 0x10) Test Register

Definition at line 55 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_TOCC

__IO uint32_t Mcan::MCAN_TOCC

(Mcan Offset: 0x28) Timeout Counter Configuration Register

Definition at line 65 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_TOCV

__IO uint32_t Mcan::MCAN_TOCV

(Mcan Offset: 0x2C) Timeout Counter Value Register

Definition at line 66 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_TSCC

__IO uint32_t Mcan::MCAN_TSCC

(Mcan Offset: 0x20) Timestamp Counter Configuration Register

Definition at line 63 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_TSCV

__IO uint32_t Mcan::MCAN_TSCV

(Mcan Offset: 0x24) Timestamp Counter Value Register

Definition at line 64 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_TXBAR

__IO uint32_t Mcan::MCAN_TXBAR

(Mcan Offset: 0xD0) Transmit Buffer Add Request Register

Definition at line 101 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_TXBC

__IO uint32_t Mcan::MCAN_TXBC

(Mcan Offset: 0xC0) Transmit Buffer Configuration Register

Definition at line 97 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_TXBCF

__I uint32_t Mcan::MCAN_TXBCF

(Mcan Offset: 0xDC) Transmit Buffer Cancellation Finished Register

Definition at line 104 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_TXBCIE

__IO uint32_t Mcan::MCAN_TXBCIE

(Mcan Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register

Definition at line 106 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_TXBCR

__IO uint32_t Mcan::MCAN_TXBCR

(Mcan Offset: 0xD4) Transmit Buffer Cancellation Request Register

Definition at line 102 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_TXBRP

__I uint32_t Mcan::MCAN_TXBRP

(Mcan Offset: 0xCC) Transmit Buffer Request Pending Register

Definition at line 100 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_TXBTIE

__IO uint32_t Mcan::MCAN_TXBTIE

(Mcan Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register

Definition at line 105 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_TXBTO

__I uint32_t Mcan::MCAN_TXBTO

(Mcan Offset: 0xD8) Transmit Buffer Transmission Occurred Register

Definition at line 103 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_TXEFA

__IO uint32_t Mcan::MCAN_TXEFA

(Mcan Offset: 0xF8) Transmit Event FIFO Acknowledge Register

Definition at line 110 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_TXEFC

__IO uint32_t Mcan::MCAN_TXEFC

(Mcan Offset: 0xF0) Transmit Event FIFO Configuration Register

Definition at line 108 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_TXEFS

__I uint32_t Mcan::MCAN_TXEFS

(Mcan Offset: 0xF4) Transmit Event FIFO Status Register

Definition at line 109 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_TXESC

__IO uint32_t Mcan::MCAN_TXESC

(Mcan Offset: 0xC8) Transmit Buffer Element Size Configuration Register

Definition at line 99 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_TXFQS

__I uint32_t Mcan::MCAN_TXFQS

(Mcan Offset: 0xC4) Transmit FIFO/Queue Status Register

Definition at line 98 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_XIDAM

__IO uint32_t Mcan::MCAN_XIDAM

(Mcan Offset: 0x90) Extended ID AND Mask Register

Definition at line 85 of file utils/cmsis/same70/include/component/mcan.h.

◆ MCAN_XIDFC

__IO uint32_t Mcan::MCAN_XIDFC

(Mcan Offset: 0x88) Extended ID Filter Configuration Register

Definition at line 83 of file utils/cmsis/same70/include/component/mcan.h.

◆ Reserved1

__I uint32_t Mcan::Reserved1[4]

Definition at line 67 of file utils/cmsis/same70/include/component/mcan.h.

◆ Reserved2

__I uint32_t Mcan::Reserved2[2]

Definition at line 74 of file utils/cmsis/same70/include/component/mcan.h.

◆ Reserved3

__I uint32_t Mcan::Reserved3[8]

Definition at line 80 of file utils/cmsis/same70/include/component/mcan.h.

◆ Reserved4

__I uint32_t Mcan::Reserved4[1]

Definition at line 84 of file utils/cmsis/same70/include/component/mcan.h.

◆ Reserved5

__I uint32_t Mcan::Reserved5[2]

Definition at line 107 of file utils/cmsis/same70/include/component/mcan.h.


The documentation for this struct was generated from the following file:


inertial_sense_ros
Author(s):
autogenerated on Sat Sep 19 2020 03:19:09