19 #define QDEC_USE_INDEX 0 133 tc_init(timercounter, timerchannel,
147 tc_start(timercounter, timerchannel);
187 cv =
QE0_POS->TC_CHANNEL[0].TC_CV;
191 cv =
QE1_POS->TC_CHANNEL[0].TC_CV;
219 #if 1 //quadEnc testing 246 dirL ?
'R':
'F', chL, (
int)speedL,
247 dirR ?
'R':
'F', chR, (
int)speedR);
253 #endif //END quadEnc testing #define TC_BMR_QDEN
(TC_BMR) Quadrature Decoder Enabled
#define TC_BMR_EDGPHA
(TC_BMR) Edge on PHA Count Mode
#define PIN_TCCAP1_SPD_MUX
#define PIN_QE1_POS_PHA_MUX
static void ioport_set_pin_mode(ioport_pin_t pin, ioport_mode_t mode)
Set pin mode for one single IOPORT pin.
void quadEncInit(void)
Initialize quadrature encoder driver.
static uint32_t speed_capture_timeMs
void pmc_enable_pck(uint32_t ul_id)
Enable the specified programmable clock.
#define taskEXIT_CRITICAL()
void TCCAP1_SPD_Handler(void)
#define TC_IER_COVFS
(TC_IER) Counter Overflow
void quadEncReadSpeedAll(uint32_t *speed0, uint32_t *speed1)
uint32_t pmc_is_pck_enabled(uint32_t ul_id)
Check if the specified programmable clock is enabled.
#define TC_QISR_DIR
(TC_QISR) Direction
static void quadEncSetModeSpeed(Tc *const timercounter, int timerchannel, int timerirq, uint32_t ID_timercounter)
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
static uint32_t speed_capture[2]
void quadEncReadPositionAll(int *pos0, bool *dir0, int *pos1, bool *dir1)
Reads the current position of the encoders.
#define TC_IER_LDRAS
(TC_IER) RA Loading
#define TC_CMR_ETRGEDG_EDGE
(TC_CMR) Each edge
#define TC_CMR_ETRGEDG_RISING
(TC_CMR) Rising edge
#define PIN_TCCAP0_SPD_MUX
void tc_start(Tc *p_tc, uint32_t ul_channel)
Start the TC clock on the specified channel.
void pmc_disable_pck(uint32_t ul_id)
Disable the specified programmable clock.
static void quadEncSetModePosition(Tc *const timercounter, uint32_t ID_timercounter)
#define PIN_QE1_POS_PHB_MUX
iram_size_t udi_cdc_write_buf(const void *buf, iram_size_t size)
Writes a RAM buffer on CDC line.
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
#define TC_CMR_LDRA_EDGE
(TC_CMR) Each edge of TIOA
#define TC_CMR_TCCLKS_XC0
(TC_CMR) Clock selected: XC0
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
void tc_init(Tc *p_tc, uint32_t ul_channel, uint32_t ul_mode)
Configure TC for timer, waveform generation, or capture.
#define PIN_QE0_POS_PHA_MUX
#define TC_BMR_MAXFILT_Pos
#define TC_SR_LDRAS
(TC_SR) RA Loading Status (cleared on read)
#define TC_SR_COVFS
(TC_SR) Counter Overflow Status (cleared on read)
uint32_t tc_read_ra(Tc *p_tc, uint32_t ul_channel)
Read TC Register A (RA) on the specified channel.
#define PMC_PCK_PRES(value)
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
#define PIN_QE0_POS_PHB_MUX
uint32_t tc_get_status(Tc *p_tc, uint32_t ul_channel)
Get the current status for the specified TC channel.
#define TCCAP1_SPD_CHANNEL
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY
#define TC_BMR_POSEN
(TC_BMR) Position Enabled
#define taskENTER_CRITICAL()
void tc_enable_interrupt(Tc *p_tc, uint32_t ul_channel, uint32_t ul_sources)
Enable the TC interrupts on the specified channel.
void test_quad_encoders(void)
#define TCCAP0_SPD_CHANNEL
uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres)
Switch programmable clock source selection to main clock.
void vTaskDelay(const TickType_t xTicksToDelay) PRIVILEGED_FUNCTION
static void sysclk_enable_peripheral_clock(uint32_t ul_id)
Enable a peripheral's clock.
Autogenerated API include file for the Atmel Software Framework (ASF)
void TCCAP0_SPD_Handler(void)
static void ioport_disable_pin(ioport_pin_t pin)
Disable IOPORT pin, based on a pin created with IOPORT_CREATE_PIN().
void tc_set_block_mode(Tc *p_tc, uint32_t ul_blockmode)
Configure the TC Block mode.
#define TC_CMR_ABETRG
(TC_CMR) TIOA or TIOB External Trigger Selection
#define TC_CMR_TCCLKS_TIMER_CLOCK1
(TC_CMR) Clock selected: internal PCK6 clock signal (from PMC)