utils/cmsis/same70/include/component/tc.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_TC_COMPONENT_
36 #define _SAME70_TC_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __O uint32_t TC_CCR;
48  __IO uint32_t TC_CMR;
49  __IO uint32_t TC_SMMR;
50  __I uint32_t TC_RAB;
51  __I uint32_t TC_CV;
52  __IO uint32_t TC_RA;
53  __IO uint32_t TC_RB;
54  __IO uint32_t TC_RC;
55  __I uint32_t TC_SR;
56  __O uint32_t TC_IER;
57  __O uint32_t TC_IDR;
58  __I uint32_t TC_IMR;
59  __IO uint32_t TC_EMR;
60  __I uint32_t Reserved1[3];
61 } TcChannel;
63 #define TCCHANNEL_NUMBER 3
64 typedef struct {
66  __O uint32_t TC_BCR;
67  __IO uint32_t TC_BMR;
68  __O uint32_t TC_QIER;
69  __O uint32_t TC_QIDR;
70  __I uint32_t TC_QIMR;
71  __I uint32_t TC_QISR;
72  __IO uint32_t TC_FMR;
73  __I uint32_t Reserved1[2];
74  __IO uint32_t TC_WPMR;
75  __I uint32_t Reserved2[5];
76  __I uint32_t TC_VER;
77 } Tc;
78 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
79 /* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
80 #define TC_CCR_CLKEN (0x1u << 0)
81 #define TC_CCR_CLKDIS (0x1u << 1)
82 #define TC_CCR_SWTRG (0x1u << 2)
83 /* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
84 #define TC_CMR_TCCLKS_Pos 0
85 #define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos)
86 #define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos)))
87 #define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0)
88 #define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0)
89 #define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0)
90 #define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0)
91 #define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0)
92 #define TC_CMR_TCCLKS_XC0 (0x5u << 0)
93 #define TC_CMR_TCCLKS_XC1 (0x6u << 0)
94 #define TC_CMR_TCCLKS_XC2 (0x7u << 0)
95 #define TC_CMR_CLKI (0x1u << 3)
96 #define TC_CMR_BURST_Pos 4
97 #define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos)
98 #define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos)))
99 #define TC_CMR_BURST_NONE (0x0u << 4)
100 #define TC_CMR_BURST_XC0 (0x1u << 4)
101 #define TC_CMR_BURST_XC1 (0x2u << 4)
102 #define TC_CMR_BURST_XC2 (0x3u << 4)
103 #define TC_CMR_LDBSTOP (0x1u << 6)
104 #define TC_CMR_LDBDIS (0x1u << 7)
105 #define TC_CMR_ETRGEDG_Pos 8
106 #define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos)
107 #define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos)))
108 #define TC_CMR_ETRGEDG_NONE (0x0u << 8)
109 #define TC_CMR_ETRGEDG_RISING (0x1u << 8)
110 #define TC_CMR_ETRGEDG_FALLING (0x2u << 8)
111 #define TC_CMR_ETRGEDG_EDGE (0x3u << 8)
112 #define TC_CMR_ABETRG (0x1u << 10)
113 #define TC_CMR_CPCTRG (0x1u << 14)
114 #define TC_CMR_WAVE (0x1u << 15)
115 #define TC_CMR_LDRA_Pos 16
116 #define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos)
117 #define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos)))
118 #define TC_CMR_LDRA_NONE (0x0u << 16)
119 #define TC_CMR_LDRA_RISING (0x1u << 16)
120 #define TC_CMR_LDRA_FALLING (0x2u << 16)
121 #define TC_CMR_LDRA_EDGE (0x3u << 16)
122 #define TC_CMR_LDRB_Pos 18
123 #define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos)
124 #define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos)))
125 #define TC_CMR_LDRB_NONE (0x0u << 18)
126 #define TC_CMR_LDRB_RISING (0x1u << 18)
127 #define TC_CMR_LDRB_FALLING (0x2u << 18)
128 #define TC_CMR_LDRB_EDGE (0x3u << 18)
129 #define TC_CMR_SBSMPLR_Pos 20
130 #define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos)
131 #define TC_CMR_SBSMPLR(value) ((TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos)))
132 #define TC_CMR_SBSMPLR_ONE (0x0u << 20)
133 #define TC_CMR_SBSMPLR_HALF (0x1u << 20)
134 #define TC_CMR_SBSMPLR_FOURTH (0x2u << 20)
135 #define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20)
136 #define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20)
137 #define TC_CMR_CPCSTOP (0x1u << 6)
138 #define TC_CMR_CPCDIS (0x1u << 7)
139 #define TC_CMR_EEVTEDG_Pos 8
140 #define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos)
141 #define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos)))
142 #define TC_CMR_EEVTEDG_NONE (0x0u << 8)
143 #define TC_CMR_EEVTEDG_RISING (0x1u << 8)
144 #define TC_CMR_EEVTEDG_FALLING (0x2u << 8)
145 #define TC_CMR_EEVTEDG_EDGE (0x3u << 8)
146 #define TC_CMR_EEVT_Pos 10
147 #define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos)
148 #define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos)))
149 #define TC_CMR_EEVT_TIOB (0x0u << 10)
150 #define TC_CMR_EEVT_XC0 (0x1u << 10)
151 #define TC_CMR_EEVT_XC1 (0x2u << 10)
152 #define TC_CMR_EEVT_XC2 (0x3u << 10)
153 #define TC_CMR_ENETRG (0x1u << 12)
154 #define TC_CMR_WAVSEL_Pos 13
155 #define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos)
156 #define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos)))
157 #define TC_CMR_WAVSEL_UP (0x0u << 13)
158 #define TC_CMR_WAVSEL_UPDOWN (0x1u << 13)
159 #define TC_CMR_WAVSEL_UP_RC (0x2u << 13)
160 #define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13)
161 #define TC_CMR_ACPA_Pos 16
162 #define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos)
163 #define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos)))
164 #define TC_CMR_ACPA_NONE (0x0u << 16)
165 #define TC_CMR_ACPA_SET (0x1u << 16)
166 #define TC_CMR_ACPA_CLEAR (0x2u << 16)
167 #define TC_CMR_ACPA_TOGGLE (0x3u << 16)
168 #define TC_CMR_ACPC_Pos 18
169 #define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos)
170 #define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos)))
171 #define TC_CMR_ACPC_NONE (0x0u << 18)
172 #define TC_CMR_ACPC_SET (0x1u << 18)
173 #define TC_CMR_ACPC_CLEAR (0x2u << 18)
174 #define TC_CMR_ACPC_TOGGLE (0x3u << 18)
175 #define TC_CMR_AEEVT_Pos 20
176 #define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos)
177 #define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos)))
178 #define TC_CMR_AEEVT_NONE (0x0u << 20)
179 #define TC_CMR_AEEVT_SET (0x1u << 20)
180 #define TC_CMR_AEEVT_CLEAR (0x2u << 20)
181 #define TC_CMR_AEEVT_TOGGLE (0x3u << 20)
182 #define TC_CMR_ASWTRG_Pos 22
183 #define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos)
184 #define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos)))
185 #define TC_CMR_ASWTRG_NONE (0x0u << 22)
186 #define TC_CMR_ASWTRG_SET (0x1u << 22)
187 #define TC_CMR_ASWTRG_CLEAR (0x2u << 22)
188 #define TC_CMR_ASWTRG_TOGGLE (0x3u << 22)
189 #define TC_CMR_BCPB_Pos 24
190 #define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos)
191 #define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos)))
192 #define TC_CMR_BCPB_NONE (0x0u << 24)
193 #define TC_CMR_BCPB_SET (0x1u << 24)
194 #define TC_CMR_BCPB_CLEAR (0x2u << 24)
195 #define TC_CMR_BCPB_TOGGLE (0x3u << 24)
196 #define TC_CMR_BCPC_Pos 26
197 #define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos)
198 #define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos)))
199 #define TC_CMR_BCPC_NONE (0x0u << 26)
200 #define TC_CMR_BCPC_SET (0x1u << 26)
201 #define TC_CMR_BCPC_CLEAR (0x2u << 26)
202 #define TC_CMR_BCPC_TOGGLE (0x3u << 26)
203 #define TC_CMR_BEEVT_Pos 28
204 #define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos)
205 #define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos)))
206 #define TC_CMR_BEEVT_NONE (0x0u << 28)
207 #define TC_CMR_BEEVT_SET (0x1u << 28)
208 #define TC_CMR_BEEVT_CLEAR (0x2u << 28)
209 #define TC_CMR_BEEVT_TOGGLE (0x3u << 28)
210 #define TC_CMR_BSWTRG_Pos 30
211 #define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos)
212 #define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos)))
213 #define TC_CMR_BSWTRG_NONE (0x0u << 30)
214 #define TC_CMR_BSWTRG_SET (0x1u << 30)
215 #define TC_CMR_BSWTRG_CLEAR (0x2u << 30)
216 #define TC_CMR_BSWTRG_TOGGLE (0x3u << 30)
217 /* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
218 #define TC_SMMR_GCEN (0x1u << 0)
219 #define TC_SMMR_DOWN (0x1u << 1)
220 /* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */
221 #define TC_RAB_RAB_Pos 0
222 #define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos)
223 /* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
224 #define TC_CV_CV_Pos 0
225 #define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos)
226 /* -------- TC_RA : (TC Offset: N/A) Register A -------- */
227 #define TC_RA_RA_Pos 0
228 #define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos)
229 #define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
230 /* -------- TC_RB : (TC Offset: N/A) Register B -------- */
231 #define TC_RB_RB_Pos 0
232 #define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos)
233 #define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
234 /* -------- TC_RC : (TC Offset: N/A) Register C -------- */
235 #define TC_RC_RC_Pos 0
236 #define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos)
237 #define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
238 /* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
239 #define TC_SR_COVFS (0x1u << 0)
240 #define TC_SR_LOVRS (0x1u << 1)
241 #define TC_SR_CPAS (0x1u << 2)
242 #define TC_SR_CPBS (0x1u << 3)
243 #define TC_SR_CPCS (0x1u << 4)
244 #define TC_SR_LDRAS (0x1u << 5)
245 #define TC_SR_LDRBS (0x1u << 6)
246 #define TC_SR_ETRGS (0x1u << 7)
247 #define TC_SR_CLKSTA (0x1u << 16)
248 #define TC_SR_MTIOA (0x1u << 17)
249 #define TC_SR_MTIOB (0x1u << 18)
250 /* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
251 #define TC_IER_COVFS (0x1u << 0)
252 #define TC_IER_LOVRS (0x1u << 1)
253 #define TC_IER_CPAS (0x1u << 2)
254 #define TC_IER_CPBS (0x1u << 3)
255 #define TC_IER_CPCS (0x1u << 4)
256 #define TC_IER_LDRAS (0x1u << 5)
257 #define TC_IER_LDRBS (0x1u << 6)
258 #define TC_IER_ETRGS (0x1u << 7)
259 /* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
260 #define TC_IDR_COVFS (0x1u << 0)
261 #define TC_IDR_LOVRS (0x1u << 1)
262 #define TC_IDR_CPAS (0x1u << 2)
263 #define TC_IDR_CPBS (0x1u << 3)
264 #define TC_IDR_CPCS (0x1u << 4)
265 #define TC_IDR_LDRAS (0x1u << 5)
266 #define TC_IDR_LDRBS (0x1u << 6)
267 #define TC_IDR_ETRGS (0x1u << 7)
268 /* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
269 #define TC_IMR_COVFS (0x1u << 0)
270 #define TC_IMR_LOVRS (0x1u << 1)
271 #define TC_IMR_CPAS (0x1u << 2)
272 #define TC_IMR_CPBS (0x1u << 3)
273 #define TC_IMR_CPCS (0x1u << 4)
274 #define TC_IMR_LDRAS (0x1u << 5)
275 #define TC_IMR_LDRBS (0x1u << 6)
276 #define TC_IMR_ETRGS (0x1u << 7)
277 /* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */
278 #define TC_EMR_TRIGSRCA_Pos 0
279 #define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos)
280 #define TC_EMR_TRIGSRCA(value) ((TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos)))
281 #define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0)
282 #define TC_EMR_TRIGSRCA_PWMx (0x1u << 0)
283 #define TC_EMR_TRIGSRCB_Pos 4
284 #define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos)
285 #define TC_EMR_TRIGSRCB(value) ((TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos)))
286 #define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4)
287 #define TC_EMR_TRIGSRCB_PWMx (0x1u << 4)
288 #define TC_EMR_NODIVCLK (0x1u << 8)
289 /* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
290 #define TC_BCR_SYNC (0x1u << 0)
291 /* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
292 #define TC_BMR_TC0XC0S_Pos 0
293 #define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos)
294 #define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos)))
295 #define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0)
296 #define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0)
297 #define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0)
298 #define TC_BMR_TC1XC1S_Pos 2
299 #define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos)
300 #define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos)))
301 #define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2)
302 #define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2)
303 #define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2)
304 #define TC_BMR_TC2XC2S_Pos 4
305 #define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos)
306 #define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos)))
307 #define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4)
308 #define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4)
309 #define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4)
310 #define TC_BMR_QDEN (0x1u << 8)
311 #define TC_BMR_POSEN (0x1u << 9)
312 #define TC_BMR_SPEEDEN (0x1u << 10)
313 #define TC_BMR_QDTRANS (0x1u << 11)
314 #define TC_BMR_EDGPHA (0x1u << 12)
315 #define TC_BMR_INVA (0x1u << 13)
316 #define TC_BMR_INVB (0x1u << 14)
317 #define TC_BMR_INVIDX (0x1u << 15)
318 #define TC_BMR_SWAP (0x1u << 16)
319 #define TC_BMR_IDXPHB (0x1u << 17)
320 #define TC_BMR_MAXFILT_Pos 20
321 #define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos)
322 #define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
323 /* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
324 #define TC_QIER_IDX (0x1u << 0)
325 #define TC_QIER_DIRCHG (0x1u << 1)
326 #define TC_QIER_QERR (0x1u << 2)
327 /* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
328 #define TC_QIDR_IDX (0x1u << 0)
329 #define TC_QIDR_DIRCHG (0x1u << 1)
330 #define TC_QIDR_QERR (0x1u << 2)
331 /* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
332 #define TC_QIMR_IDX (0x1u << 0)
333 #define TC_QIMR_DIRCHG (0x1u << 1)
334 #define TC_QIMR_QERR (0x1u << 2)
335 /* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
336 #define TC_QISR_IDX (0x1u << 0)
337 #define TC_QISR_DIRCHG (0x1u << 1)
338 #define TC_QISR_QERR (0x1u << 2)
339 #define TC_QISR_DIR (0x1u << 8)
340 /* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */
341 #define TC_FMR_ENCF0 (0x1u << 0)
342 #define TC_FMR_ENCF1 (0x1u << 1)
343 /* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */
344 #define TC_WPMR_WPEN (0x1u << 0)
345 #define TC_WPMR_WPKEY_Pos 8
346 #define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos)
347 #define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))
348 #define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8)
349 /* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */
350 #define TC_VER_VERSION_Pos 0
351 #define TC_VER_VERSION_Msk (0xfffu << TC_VER_VERSION_Pos)
352 #define TC_VER_MFN_Pos 16
353 #define TC_VER_MFN_Msk (0x7u << TC_VER_MFN_Pos)
356 
357 
358 #endif /* _SAME70_TC_COMPONENT_ */
__O uint32_t TC_QIER
(Tc Offset: 0xC8) QDEC Interrupt Enable Register
#define TCCHANNEL_NUMBER
Tc hardware registers.
#define __IO
Definition: core_cm7.h:266
#define __O
Definition: core_cm7.h:265
__IO uint32_t TC_FMR
(Tc Offset: 0xD8) Fault Mode Register
__IO uint32_t TC_EMR
(TcChannel Offset: 0x30) Extended Mode Register
__IO uint32_t TC_RA
(TcChannel Offset: 0x14) Register A
__I uint32_t TC_CV
(TcChannel Offset: 0x10) Counter Value
__I uint32_t TC_RAB
(TcChannel Offset: 0xC) Register AB
__I uint32_t TC_QIMR
(Tc Offset: 0xD0) QDEC Interrupt Mask Register
__O uint32_t TC_QIDR
(Tc Offset: 0xCC) QDEC Interrupt Disable Register
TcChannel hardware registers.
__IO uint32_t TC_SMMR
(TcChannel Offset: 0x8) Stepper Motor Mode Register
__I uint32_t TC_IMR
(TcChannel Offset: 0x2C) Interrupt Mask Register
__I uint32_t TC_SR
(TcChannel Offset: 0x20) Status Register
__IO uint32_t TC_BMR
(Tc Offset: 0xC4) Block Mode Register
__I uint32_t TC_VER
(Tc Offset: 0xFC) Version Register
__O uint32_t TC_CCR
(TcChannel Offset: 0x0) Channel Control Register
__IO uint32_t TC_RC
(TcChannel Offset: 0x1C) Register C
__I uint32_t TC_QISR
(Tc Offset: 0xD4) QDEC Interrupt Status Register
__IO uint32_t TC_RB
(TcChannel Offset: 0x18) Register B
__O uint32_t TC_IDR
(TcChannel Offset: 0x28) Interrupt Disable Register
__IO uint32_t TC_CMR
(TcChannel Offset: 0x4) Channel Mode Register
__IO uint32_t TC_WPMR
(Tc Offset: 0xE4) Write Protection Mode Register
__O uint32_t TC_IER
(TcChannel Offset: 0x24) Interrupt Enable Register
__O uint32_t TC_BCR
(Tc Offset: 0xC0) Block Control Register
#define __I
Definition: core_cm7.h:263


inertial_sense_ros
Author(s):
autogenerated on Sat Sep 19 2020 03:19:05