stm32f4xx_dac.c
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1 
130 /* Includes ------------------------------------------------------------------*/
131 #include "stm32f4xx_dac.h"
132 #include "stm32f4xx_rcc.h"
133 
143 /* Private typedef -----------------------------------------------------------*/
144 /* Private define ------------------------------------------------------------*/
145 
146 /* CR register Mask */
147 #define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
148 
149 /* DAC Dual Channels SWTRIG masks */
150 #define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
151 #define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
152 
153 /* DHR registers offsets */
154 #define DHR12R1_OFFSET ((uint32_t)0x00000008)
155 #define DHR12R2_OFFSET ((uint32_t)0x00000014)
156 #define DHR12RD_OFFSET ((uint32_t)0x00000020)
157 
158 /* DOR register offset */
159 #define DOR_OFFSET ((uint32_t)0x0000002C)
160 
161 /* Private macro -------------------------------------------------------------*/
162 /* Private variables ---------------------------------------------------------*/
163 /* Private function prototypes -----------------------------------------------*/
164 /* Private functions ---------------------------------------------------------*/
165 
187 void DAC_DeInit(void)
188 {
189  /* Enable DAC reset state */
191  /* Release DAC from reset state */
193 }
194 
206 void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
207 {
208  uint32_t tmpreg1 = 0, tmpreg2 = 0;
209 
210  /* Check the DAC parameters */
211  assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
215 
216 /*---------------------------- DAC CR Configuration --------------------------*/
217  /* Get the DAC CR value */
218  tmpreg1 = DAC->CR;
219  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
220  tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
221  /* Configure for the selected DAC channel: buffer output, trigger,
222  wave generation, mask/amplitude for wave generation */
223  /* Set TSELx and TENx bits according to DAC_Trigger value */
224  /* Set WAVEx bits according to DAC_WaveGeneration value */
225  /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
226  /* Set BOFFx bit according to DAC_OutputBuffer value */
227  tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
228  DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \
229  DAC_InitStruct->DAC_OutputBuffer);
230  /* Calculate CR register value depending on DAC_Channel */
231  tmpreg1 |= tmpreg2 << DAC_Channel;
232  /* Write to DAC CR */
233  DAC->CR = tmpreg1;
234 }
235 
242 void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
243 {
244 /*--------------- Reset DAC init structure parameters values -----------------*/
245  /* Initialize the DAC_Trigger member */
246  DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
247  /* Initialize the DAC_WaveGeneration member */
249  /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
251  /* Initialize the DAC_OutputBuffer member */
252  DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
253 }
254 
266 void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
267 {
268  /* Check the parameters */
269  assert_param(IS_DAC_CHANNEL(DAC_Channel));
271 
272  if (NewState != DISABLE)
273  {
274  /* Enable the selected DAC channel */
275  DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
276  }
277  else
278  {
279  /* Disable the selected DAC channel */
280  DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
281  }
282 }
283 
294 void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
295 {
296  /* Check the parameters */
297  assert_param(IS_DAC_CHANNEL(DAC_Channel));
299 
300  if (NewState != DISABLE)
301  {
302  /* Enable software trigger for the selected DAC channel */
303  DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
304  }
305  else
306  {
307  /* Disable software trigger for the selected DAC channel */
308  DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
309  }
310 }
311 
319 {
320  /* Check the parameters */
322 
323  if (NewState != DISABLE)
324  {
325  /* Enable software trigger for both DAC channels */
326  DAC->SWTRIGR |= DUAL_SWTRIG_SET;
327  }
328  else
329  {
330  /* Disable software trigger for both DAC channels */
331  DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
332  }
333 }
334 
349 void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
350 {
351  /* Check the parameters */
352  assert_param(IS_DAC_CHANNEL(DAC_Channel));
353  assert_param(IS_DAC_WAVE(DAC_Wave));
355 
356  if (NewState != DISABLE)
357  {
358  /* Enable the selected wave generation for the selected DAC channel */
359  DAC->CR |= DAC_Wave << DAC_Channel;
360  }
361  else
362  {
363  /* Disable the selected wave generation for the selected DAC channel */
364  DAC->CR &= ~(DAC_Wave << DAC_Channel);
365  }
366 }
367 
378 void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
379 {
380  __IO uint32_t tmp = 0;
381 
382  /* Check the parameters */
383  assert_param(IS_DAC_ALIGN(DAC_Align));
384  assert_param(IS_DAC_DATA(Data));
385 
386  tmp = (uint32_t)DAC_BASE;
387  tmp += DHR12R1_OFFSET + DAC_Align;
388 
389  /* Set the DAC channel1 selected data holding register */
390  *(__IO uint32_t *) tmp = Data;
391 }
392 
403 void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
404 {
405  __IO uint32_t tmp = 0;
406 
407  /* Check the parameters */
408  assert_param(IS_DAC_ALIGN(DAC_Align));
409  assert_param(IS_DAC_DATA(Data));
410 
411  tmp = (uint32_t)DAC_BASE;
412  tmp += DHR12R2_OFFSET + DAC_Align;
413 
414  /* Set the DAC channel2 selected data holding register */
415  *(__IO uint32_t *)tmp = Data;
416 }
417 
431 void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
432 {
433  uint32_t data = 0, tmp = 0;
434 
435  /* Check the parameters */
436  assert_param(IS_DAC_ALIGN(DAC_Align));
437  assert_param(IS_DAC_DATA(Data1));
438  assert_param(IS_DAC_DATA(Data2));
439 
440  /* Calculate and set dual DAC data holding register value */
441  if (DAC_Align == DAC_Align_8b_R)
442  {
443  data = ((uint32_t)Data2 << 8) | Data1;
444  }
445  else
446  {
447  data = ((uint32_t)Data2 << 16) | Data1;
448  }
449 
450  tmp = (uint32_t)DAC_BASE;
451  tmp += DHR12RD_OFFSET + DAC_Align;
452 
453  /* Set the dual DAC selected data holding register */
454  *(__IO uint32_t *)tmp = data;
455 }
456 
465 uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
466 {
467  __IO uint32_t tmp = 0;
468 
469  /* Check the parameters */
470  assert_param(IS_DAC_CHANNEL(DAC_Channel));
471 
472  tmp = (uint32_t) DAC_BASE ;
473  tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
474 
475  /* Returns the DAC channel data output register value */
476  return (uint16_t) (*(__IO uint32_t*) tmp);
477 }
510 void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
511 {
512  /* Check the parameters */
513  assert_param(IS_DAC_CHANNEL(DAC_Channel));
515 
516  if (NewState != DISABLE)
517  {
518  /* Enable the selected DAC channel DMA request */
519  DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
520  }
521  else
522  {
523  /* Disable the selected DAC channel DMA request */
524  DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
525  }
526 }
558 void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
559 {
560  /* Check the parameters */
561  assert_param(IS_DAC_CHANNEL(DAC_Channel));
563  assert_param(IS_DAC_IT(DAC_IT));
564 
565  if (NewState != DISABLE)
566  {
567  /* Enable the selected DAC interrupts */
568  DAC->CR |= (DAC_IT << DAC_Channel);
569  }
570  else
571  {
572  /* Disable the selected DAC interrupts */
573  DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
574  }
575 }
576 
590 FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
591 {
592  FlagStatus bitstatus = RESET;
593  /* Check the parameters */
594  assert_param(IS_DAC_CHANNEL(DAC_Channel));
595  assert_param(IS_DAC_FLAG(DAC_FLAG));
596 
597  /* Check the status of the specified DAC flag */
598  if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
599  {
600  /* DAC_FLAG is set */
601  bitstatus = SET;
602  }
603  else
604  {
605  /* DAC_FLAG is reset */
606  bitstatus = RESET;
607  }
608  /* Return the DAC_FLAG status */
609  return bitstatus;
610 }
611 
625 void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
626 {
627  /* Check the parameters */
628  assert_param(IS_DAC_CHANNEL(DAC_Channel));
629  assert_param(IS_DAC_FLAG(DAC_FLAG));
630 
631  /* Clear the selected DAC flags */
632  DAC->SR = (DAC_FLAG << DAC_Channel);
633 }
634 
648 ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
649 {
650  ITStatus bitstatus = RESET;
651  uint32_t enablestatus = 0;
652 
653  /* Check the parameters */
654  assert_param(IS_DAC_CHANNEL(DAC_Channel));
655  assert_param(IS_DAC_IT(DAC_IT));
656 
657  /* Get the DAC_IT enable bit status */
658  enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
659 
660  /* Check the status of the specified DAC interrupt */
661  if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
662  {
663  /* DAC_IT is set */
664  bitstatus = SET;
665  }
666  else
667  {
668  /* DAC_IT is reset */
669  bitstatus = RESET;
670  }
671  /* Return the DAC_IT status */
672  return bitstatus;
673 }
674 
688 void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
689 {
690  /* Check the parameters */
691  assert_param(IS_DAC_CHANNEL(DAC_Channel));
692  assert_param(IS_DAC_IT(DAC_IT));
693 
694  /* Clear the selected DAC interrupt pending bits */
695  DAC->SR = (DAC_IT << DAC_Channel);
696 }
697 
714 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
Returns the last data output value of the selected DAC channel.
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the selected DAC channel software trigger.
FlagStatus
Definition: stm32f4xx.h:706
#define DAC_BASE
Definition: stm32f4xx.h:1920
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
Set the specified data holding register value for dual channel DAC.
uint32_t DAC_OutputBuffer
Definition: stm32f4xx_dac.h:67
FunctionalState
Definition: stm32f4xx.h:708
#define DAC_Align_8b_R
#define DAC_OutputBuffer_Enable
#define DAC_Trigger_None
Definition: stm32f4xx_dac.h:81
#define DAC_SWTRIGR_SWTRIG1
Definition: stm32f4xx.h:3972
#define DUAL_SWTRIG_RESET
#define IS_DAC_FLAG(FLAG)
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE)
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
Enables or disables the selected DAC channel wave generation.
#define DHR12R1_OFFSET
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel1.
#define DUAL_SWTRIG_SET
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
Clears the DAC channel&#39;s interrupt pending bits.
void assert_param(int val)
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
Enables or disables simultaneously the two DAC channels software triggers.
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
Checks whether the specified DAC flag is set or not.
#define IS_DAC_WAVE(WAVE)
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
#define DAC_CR_EN1
Definition: stm32f4xx.h:3930
#define DAC_CR_DMAEN1
Definition: stm32f4xx.h:3949
This file contains all the functions prototypes for the DAC firmware library.
Definition: stm32f4xx.h:706
enum FlagStatus ITStatus
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
void DAC_DeInit(void)
Deinitializes the DAC peripheral registers to their default reset values.
#define __IO
Definition: core_cm0.h:198
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
Checks whether the specified DAC interrupt has occurred or not.
#define DAC_LFSRUnmask_Bit0
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
Enables or disables the specified DAC interrupts.
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel2.
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel DMA request.
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel.
#define DOR_OFFSET
uint32_t DAC_LFSRUnmask_TriangleAmplitude
Definition: stm32f4xx_dac.h:63
#define IS_DAC_IT(IT)
uint32_t DAC_Trigger
Definition: stm32f4xx_dac.h:56
#define IS_DAC_ALIGN(ALIGN)
#define IS_DAC_GENERATE_WAVE(WAVE)
void DAC_StructInit(DAC_InitTypeDef *DAC_InitStruct)
Fills each DAC_InitStruct member with its default value.
#define IS_DAC_DATA(DATA)
DAC Init structure definition.
Definition: stm32f4xx_dac.h:54
#define DHR12R2_OFFSET
#define DHR12RD_OFFSET
#define IS_DAC_CHANNEL(CHANNEL)
#define CR_CLEAR_MASK
uint32_t DAC_WaveGeneration
Definition: stm32f4xx_dac.h:59
#define DAC
Definition: stm32f4xx.h:2075
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
Clears the DAC channel&#39;s pending flags.
#define IS_DAC_TRIGGER(TRIGGER)
Definition: stm32f4xx_dac.h:94
#define DAC_WaveGeneration_None


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19