Macros
Peripheral_memory_map
Collaboration diagram for Peripheral_memory_map:

Macros

#define ADC1_BASE   (APB2PERIPH_BASE + 0x2400)
 
#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000)
 
#define ADC2_BASE   (APB2PERIPH_BASE + 0x2800)
 
#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100)
 
#define ADC3_BASE   (APB2PERIPH_BASE + 0x3C00)
 
#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200)
 
#define ADC_BASE   (APB2PERIPH_BASE + 0x2300)
 
#define AFIO_BASE   (APB2PERIPH_BASE + 0x0000)
 
#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000)
 
#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000)
 
#define AHBPERIPH_BASE   (PERIPH_BASE + 0x20000)
 
#define APB1PERIPH_BASE   PERIPH_BASE
 
#define APB1PERIPH_BASE   PERIPH_BASE
 
#define APB2PERIPH_BASE   (PERIPH_BASE + 0x10000)
 
#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000)
 
#define BKP_BASE   (APB1PERIPH_BASE + 0x6C00)
 
#define BKPSRAM_BASE   ((uint32_t)0x40024000)
 
#define BKPSRAM_BB_BASE   ((uint32_t)0x42024000)
 
#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400)
 
#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400)
 
#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800)
 
#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800)
 
#define CCMDATARAM_BASE   ((uint32_t)0x10000000)
 
#define CCMDATARAM_BB_BASE   ((uint32_t)0x12000000)
 
#define CEC_BASE   (APB1PERIPH_BASE + 0x7800)
 
#define CRC_BASE   (AHBPERIPH_BASE + 0x3000)
 
#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000)
 
#define CRYP_BASE   (AHB2PERIPH_BASE + 0x60000)
 
#define DAC_BASE   (APB1PERIPH_BASE + 0x7400)
 
#define DAC_BASE   (APB1PERIPH_BASE + 0x7400)
 
#define DBGMCU_BASE   ((uint32_t)0xE0042000)
 
#define DBGMCU_BASE   ((uint32_t )0xE0042000)
 
#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000)
 
#define DMA1_BASE   (AHBPERIPH_BASE + 0x0000)
 
#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000)
 
#define DMA1_Channel1_BASE   (AHBPERIPH_BASE + 0x0008)
 
#define DMA1_Channel2_BASE   (AHBPERIPH_BASE + 0x001C)
 
#define DMA1_Channel3_BASE   (AHBPERIPH_BASE + 0x0030)
 
#define DMA1_Channel4_BASE   (AHBPERIPH_BASE + 0x0044)
 
#define DMA1_Channel5_BASE   (AHBPERIPH_BASE + 0x0058)
 
#define DMA1_Channel6_BASE   (AHBPERIPH_BASE + 0x006C)
 
#define DMA1_Channel7_BASE   (AHBPERIPH_BASE + 0x0080)
 
#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010)
 
#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028)
 
#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040)
 
#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058)
 
#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070)
 
#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088)
 
#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0)
 
#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8)
 
#define DMA2_BASE   (AHBPERIPH_BASE + 0x0400)
 
#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400)
 
#define DMA2_Channel1_BASE   (AHBPERIPH_BASE + 0x0408)
 
#define DMA2_Channel2_BASE   (AHBPERIPH_BASE + 0x041C)
 
#define DMA2_Channel3_BASE   (AHBPERIPH_BASE + 0x0430)
 
#define DMA2_Channel4_BASE   (AHBPERIPH_BASE + 0x0444)
 
#define DMA2_Channel5_BASE   (AHBPERIPH_BASE + 0x0458)
 
#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010)
 
#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028)
 
#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040)
 
#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058)
 
#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070)
 
#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088)
 
#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0)
 
#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8)
 
#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000)
 
#define ETH_BASE   (AHBPERIPH_BASE + 0x8000)
 
#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000)
 
#define ETH_DMA_BASE   (ETH_BASE + 0x1000)
 
#define ETH_DMA_BASE   (ETH_BASE + 0x1000)
 
#define ETH_MAC_BASE   (ETH_BASE)
 
#define ETH_MAC_BASE   (ETH_BASE)
 
#define ETH_MMC_BASE   (ETH_BASE + 0x0100)
 
#define ETH_MMC_BASE   (ETH_BASE + 0x0100)
 
#define ETH_PTP_BASE   (ETH_BASE + 0x0700)
 
#define ETH_PTP_BASE   (ETH_BASE + 0x0700)
 
#define EXTI_BASE   (APB2PERIPH_BASE + 0x0400)
 
#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00)
 
#define FLASH_BASE   ((uint32_t)0x08000000)
 
#define FLASH_BASE   ((uint32_t)0x08000000)
 
#define FLASH_R_BASE   (AHBPERIPH_BASE + 0x2000)
 
#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00)
 
#define FSMC_Bank1_R_BASE   (FSMC_R_BASE + 0x0000)
 
#define FSMC_Bank1E_R_BASE   (FSMC_R_BASE + 0x0104)
 
#define FSMC_Bank2_R_BASE   (FSMC_R_BASE + 0x0060)
 
#define FSMC_Bank3_R_BASE   (FSMC_R_BASE + 0x0080)
 
#define FSMC_Bank4_R_BASE   (FSMC_R_BASE + 0x00A0)
 
#define FSMC_R_BASE   ((uint32_t)0xA0000000)
 
#define GPIOA_BASE   (APB2PERIPH_BASE + 0x0800)
 
#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000)
 
#define GPIOB_BASE   (APB2PERIPH_BASE + 0x0C00)
 
#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400)
 
#define GPIOC_BASE   (APB2PERIPH_BASE + 0x1000)
 
#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800)
 
#define GPIOD_BASE   (APB2PERIPH_BASE + 0x1400)
 
#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00)
 
#define GPIOE_BASE   (APB2PERIPH_BASE + 0x1800)
 
#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000)
 
#define GPIOF_BASE   (APB2PERIPH_BASE + 0x1C00)
 
#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400)
 
#define GPIOG_BASE   (APB2PERIPH_BASE + 0x2000)
 
#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800)
 
#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00)
 
#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000)
 
#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400)
 
#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800)
 
#define HASH_BASE   (AHB2PERIPH_BASE + 0x60400)
 
#define HASH_DIGEST_BASE   (AHB2PERIPH_BASE + 0x60710)
 
#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400)
 
#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400)
 
#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800)
 
#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800)
 
#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00)
 
#define I2S2ext_BASE   (APB1PERIPH_BASE + 0x3400)
 
#define I2S3ext_BASE   (APB1PERIPH_BASE + 0x4000)
 
#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000)
 
#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000)
 
#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800)
 
#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84)
 
#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104)
 
#define OB_BASE   ((uint32_t)0x1FFFF800)
 
#define PERIPH_BASE   ((uint32_t)0x40000000)
 
#define PERIPH_BASE   ((uint32_t)0x40000000)
 
#define PERIPH_BB_BASE   ((uint32_t)0x42000000)
 
#define PERIPH_BB_BASE   ((uint32_t)0x42000000)
 
#define PWR_BASE   (APB1PERIPH_BASE + 0x7000)
 
#define PWR_BASE   (APB1PERIPH_BASE + 0x7000)
 
#define RCC_BASE   (AHBPERIPH_BASE + 0x1000)
 
#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800)
 
#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800)
 
#define RTC_BASE   (APB1PERIPH_BASE + 0x2800)
 
#define RTC_BASE   (APB1PERIPH_BASE + 0x2800)
 
#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800)
 
#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004)
 
#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024)
 
#define SDIO_BASE   (PERIPH_BASE + 0x18000)
 
#define SDIO_BASE   (APB2PERIPH_BASE + 0x2C00)
 
#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000)
 
#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000)
 
#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800)
 
#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800)
 
#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00)
 
#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00)
 
#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400)
 
#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000)
 
#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400)
 
#define SRAM1_BASE   ((uint32_t)0x20000000)
 
#define SRAM1_BB_BASE   ((uint32_t)0x22000000)
 
#define SRAM2_BASE   ((uint32_t)0x2001C000)
 
#define SRAM2_BB_BASE   ((uint32_t)0x2201C000)
 
#define SRAM3_BASE   ((uint32_t)0x20020000)
 
#define SRAM3_BB_BASE   ((uint32_t)0x22400000)
 
#define SRAM_BASE   ((uint32_t)0x20000000)
 
#define SRAM_BASE   SRAM1_BASE
 
#define SRAM_BB_BASE   ((uint32_t)0x22000000)
 
#define SRAM_BB_BASE   SRAM1_BB_BASE
 
#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800)
 
#define TIM10_BASE   (APB2PERIPH_BASE + 0x5000)
 
#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400)
 
#define TIM11_BASE   (APB2PERIPH_BASE + 0x5400)
 
#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800)
 
#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800)
 
#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800)
 
#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00)
 
#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00)
 
#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000)
 
#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000)
 
#define TIM15_BASE   (APB2PERIPH_BASE + 0x4000)
 
#define TIM16_BASE   (APB2PERIPH_BASE + 0x4400)
 
#define TIM17_BASE   (APB2PERIPH_BASE + 0x4800)
 
#define TIM1_BASE   (APB2PERIPH_BASE + 0x2C00)
 
#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000)
 
#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000)
 
#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000)
 
#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400)
 
#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400)
 
#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800)
 
#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800)
 
#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00)
 
#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00)
 
#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000)
 
#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000)
 
#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400)
 
#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400)
 
#define TIM8_BASE   (APB2PERIPH_BASE + 0x3400)
 
#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400)
 
#define TIM9_BASE   (APB2PERIPH_BASE + 0x4C00)
 
#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000)
 
#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00)
 
#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00)
 
#define UART5_BASE   (APB1PERIPH_BASE + 0x5000)
 
#define UART5_BASE   (APB1PERIPH_BASE + 0x5000)
 
#define UART7_BASE   (APB1PERIPH_BASE + 0x7800)
 
#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00)
 
#define USART1_BASE   (APB2PERIPH_BASE + 0x3800)
 
#define USART1_BASE   (APB2PERIPH_BASE + 0x1000)
 
#define USART2_BASE   (APB1PERIPH_BASE + 0x4400)
 
#define USART2_BASE   (APB1PERIPH_BASE + 0x4400)
 
#define USART3_BASE   (APB1PERIPH_BASE + 0x4800)
 
#define USART3_BASE   (APB1PERIPH_BASE + 0x4800)
 
#define USART6_BASE   (APB2PERIPH_BASE + 0x1400)
 
#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00)
 
#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00)
 

Detailed Description

Macro Definition Documentation

#define ADC1_BASE   (APB2PERIPH_BASE + 0x2400)

Definition at line 1322 of file stm32f10x.h.

#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000)

Definition at line 1929 of file stm32f4xx.h.

#define ADC2_BASE   (APB2PERIPH_BASE + 0x2800)

Definition at line 1323 of file stm32f10x.h.

#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100)

Definition at line 1930 of file stm32f4xx.h.

#define ADC3_BASE   (APB2PERIPH_BASE + 0x3C00)

Definition at line 1328 of file stm32f10x.h.

#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200)

Definition at line 1931 of file stm32f4xx.h.

#define ADC_BASE   (APB2PERIPH_BASE + 0x2300)

Definition at line 1932 of file stm32f4xx.h.

#define AFIO_BASE   (APB2PERIPH_BASE + 0x0000)

Definition at line 1313 of file stm32f10x.h.

#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000)

Definition at line 1878 of file stm32f4xx.h.

#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000)

APB1 peripherals

Definition at line 1879 of file stm32f4xx.h.

#define AHBPERIPH_BASE   (PERIPH_BASE + 0x20000)

Definition at line 1284 of file stm32f10x.h.

#define APB1PERIPH_BASE   PERIPH_BASE

Definition at line 1282 of file stm32f10x.h.

#define APB1PERIPH_BASE   PERIPH_BASE

Definition at line 1876 of file stm32f4xx.h.

#define APB2PERIPH_BASE   (PERIPH_BASE + 0x10000)

Definition at line 1283 of file stm32f10x.h.

#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000)

Definition at line 1877 of file stm32f4xx.h.

#define BKP_BASE   (APB1PERIPH_BASE + 0x6C00)

Definition at line 1308 of file stm32f10x.h.

#define BKPSRAM_BASE   ((uint32_t)0x40024000)

Backup SRAM(4 KB) base address in the alias region

Definition at line 1849 of file stm32f4xx.h.

#define BKPSRAM_BB_BASE   ((uint32_t)0x42024000)

Backup SRAM(4 KB) base address in the bit-band region

Definition at line 1868 of file stm32f4xx.h.

#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400)

Definition at line 1306 of file stm32f10x.h.

#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400)

Definition at line 1914 of file stm32f4xx.h.

#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800)

Definition at line 1307 of file stm32f10x.h.

#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800)

Definition at line 1915 of file stm32f4xx.h.

#define CCMDATARAM_BASE   ((uint32_t)0x10000000)

CCM(core coupled memory) data RAM(64 KB) base address in the alias region

Definition at line 1844 of file stm32f4xx.h.

#define CCMDATARAM_BB_BASE   ((uint32_t)0x12000000)

CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region

Definition at line 1863 of file stm32f4xx.h.

#define CEC_BASE   (APB1PERIPH_BASE + 0x7800)

Definition at line 1311 of file stm32f10x.h.

#define CRC_BASE   (AHBPERIPH_BASE + 0x3000)

Definition at line 1353 of file stm32f10x.h.

#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000)

Definition at line 1970 of file stm32f4xx.h.

#define CRYP_BASE   (AHB2PERIPH_BASE + 0x60000)

Definition at line 2000 of file stm32f4xx.h.

#define DAC_BASE   (APB1PERIPH_BASE + 0x7400)

Definition at line 1310 of file stm32f10x.h.

#define DAC_BASE   (APB1PERIPH_BASE + 0x7400)

Definition at line 1920 of file stm32f4xx.h.

#define DBGMCU_BASE   ((uint32_t)0xE0042000)

Debug MCU registers base address

Definition at line 1370 of file stm32f10x.h.

#define DBGMCU_BASE   ((uint32_t )0xE0042000)

Definition at line 2025 of file stm32f4xx.h.

#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000)

Definition at line 1999 of file stm32f4xx.h.

#define DMA1_BASE   (AHBPERIPH_BASE + 0x0000)

Definition at line 1338 of file stm32f10x.h.

#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000)

Definition at line 1973 of file stm32f4xx.h.

#define DMA1_Channel1_BASE   (AHBPERIPH_BASE + 0x0008)

Definition at line 1339 of file stm32f10x.h.

#define DMA1_Channel2_BASE   (AHBPERIPH_BASE + 0x001C)

Definition at line 1340 of file stm32f10x.h.

#define DMA1_Channel3_BASE   (AHBPERIPH_BASE + 0x0030)

Definition at line 1341 of file stm32f10x.h.

#define DMA1_Channel4_BASE   (AHBPERIPH_BASE + 0x0044)

Definition at line 1342 of file stm32f10x.h.

#define DMA1_Channel5_BASE   (AHBPERIPH_BASE + 0x0058)

Definition at line 1343 of file stm32f10x.h.

#define DMA1_Channel6_BASE   (AHBPERIPH_BASE + 0x006C)

Definition at line 1344 of file stm32f10x.h.

#define DMA1_Channel7_BASE   (AHBPERIPH_BASE + 0x0080)

Definition at line 1345 of file stm32f10x.h.

#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010)

Definition at line 1974 of file stm32f4xx.h.

#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028)

Definition at line 1975 of file stm32f4xx.h.

#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040)

Definition at line 1976 of file stm32f4xx.h.

#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058)

Definition at line 1977 of file stm32f4xx.h.

#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070)

Definition at line 1978 of file stm32f4xx.h.

#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088)

Definition at line 1979 of file stm32f4xx.h.

#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0)

Definition at line 1980 of file stm32f4xx.h.

#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8)

Definition at line 1981 of file stm32f4xx.h.

#define DMA2_BASE   (AHBPERIPH_BASE + 0x0400)

Definition at line 1346 of file stm32f10x.h.

#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400)

Definition at line 1982 of file stm32f4xx.h.

#define DMA2_Channel1_BASE   (AHBPERIPH_BASE + 0x0408)

Definition at line 1347 of file stm32f10x.h.

#define DMA2_Channel2_BASE   (AHBPERIPH_BASE + 0x041C)

Definition at line 1348 of file stm32f10x.h.

#define DMA2_Channel3_BASE   (AHBPERIPH_BASE + 0x0430)

Definition at line 1349 of file stm32f10x.h.

#define DMA2_Channel4_BASE   (AHBPERIPH_BASE + 0x0444)

Definition at line 1350 of file stm32f10x.h.

#define DMA2_Channel5_BASE   (AHBPERIPH_BASE + 0x0458)

Definition at line 1351 of file stm32f10x.h.

#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010)

Definition at line 1983 of file stm32f4xx.h.

#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028)

Definition at line 1984 of file stm32f4xx.h.

#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040)

Definition at line 1985 of file stm32f4xx.h.

#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058)

Definition at line 1986 of file stm32f4xx.h.

#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070)

Definition at line 1987 of file stm32f4xx.h.

#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088)

Definition at line 1988 of file stm32f4xx.h.

#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0)

Definition at line 1989 of file stm32f4xx.h.

#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8)

Definition at line 1990 of file stm32f4xx.h.

#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000)

AHB2 peripherals

Definition at line 1996 of file stm32f4xx.h.

#define ETH_BASE   (AHBPERIPH_BASE + 0x8000)

Definition at line 1358 of file stm32f10x.h.

#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000)

Definition at line 1991 of file stm32f4xx.h.

#define ETH_DMA_BASE   (ETH_BASE + 0x1000)

Definition at line 1362 of file stm32f10x.h.

#define ETH_DMA_BASE   (ETH_BASE + 0x1000)

Definition at line 1995 of file stm32f4xx.h.

#define ETH_MAC_BASE   (ETH_BASE)

Definition at line 1359 of file stm32f10x.h.

#define ETH_MAC_BASE   (ETH_BASE)

Definition at line 1992 of file stm32f4xx.h.

#define ETH_MMC_BASE   (ETH_BASE + 0x0100)

Definition at line 1360 of file stm32f10x.h.

#define ETH_MMC_BASE   (ETH_BASE + 0x0100)

Definition at line 1993 of file stm32f4xx.h.

#define ETH_PTP_BASE   (ETH_BASE + 0x0700)

Definition at line 1361 of file stm32f10x.h.

#define ETH_PTP_BASE   (ETH_BASE + 0x0700)

Definition at line 1994 of file stm32f4xx.h.

#define EXTI_BASE   (APB2PERIPH_BASE + 0x0400)

Definition at line 1314 of file stm32f10x.h.

#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00)

Definition at line 1937 of file stm32f4xx.h.

#define FLASH_BASE   ((uint32_t)0x08000000)

FLASH base address in the alias region

Definition at line 1272 of file stm32f10x.h.

#define FLASH_BASE   ((uint32_t)0x08000000)

FLASH(up to 1 MB) base address in the alias region

Definition at line 1843 of file stm32f4xx.h.

#define FLASH_R_BASE   (AHBPERIPH_BASE + 0x2000)

Flash registers base address

Definition at line 1355 of file stm32f10x.h.

#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00)

Definition at line 1972 of file stm32f4xx.h.

#define FSMC_Bank1_R_BASE   (FSMC_R_BASE + 0x0000)

FSMC Bank1 registers base address

Definition at line 1364 of file stm32f10x.h.

#define FSMC_Bank1E_R_BASE   (FSMC_R_BASE + 0x0104)

FSMC Bank1E registers base address

Definition at line 1365 of file stm32f10x.h.

#define FSMC_Bank2_R_BASE   (FSMC_R_BASE + 0x0060)

FSMC Bank2 registers base address

Definition at line 1366 of file stm32f10x.h.

#define FSMC_Bank3_R_BASE   (FSMC_R_BASE + 0x0080)

FSMC Bank3 registers base address

Definition at line 1367 of file stm32f10x.h.

#define FSMC_Bank4_R_BASE   (FSMC_R_BASE + 0x00A0)

FSMC Bank4 registers base address

Definition at line 1368 of file stm32f10x.h.

#define FSMC_R_BASE   ((uint32_t)0xA0000000)

FSMC registers base address Peripheral memory map

Definition at line 1279 of file stm32f10x.h.

#define GPIOA_BASE   (APB2PERIPH_BASE + 0x0800)

Definition at line 1315 of file stm32f10x.h.

#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000)

< AHB1 peripherals

Definition at line 1959 of file stm32f4xx.h.

#define GPIOB_BASE   (APB2PERIPH_BASE + 0x0C00)

Definition at line 1316 of file stm32f10x.h.

#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400)

Definition at line 1960 of file stm32f4xx.h.

#define GPIOC_BASE   (APB2PERIPH_BASE + 0x1000)

Definition at line 1317 of file stm32f10x.h.

#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800)

Definition at line 1961 of file stm32f4xx.h.

#define GPIOD_BASE   (APB2PERIPH_BASE + 0x1400)

Definition at line 1318 of file stm32f10x.h.

#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00)

Definition at line 1962 of file stm32f4xx.h.

#define GPIOE_BASE   (APB2PERIPH_BASE + 0x1800)

Definition at line 1319 of file stm32f10x.h.

#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000)

Definition at line 1963 of file stm32f4xx.h.

#define GPIOF_BASE   (APB2PERIPH_BASE + 0x1C00)

Definition at line 1320 of file stm32f10x.h.

#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400)

Definition at line 1964 of file stm32f4xx.h.

#define GPIOG_BASE   (APB2PERIPH_BASE + 0x2000)

Definition at line 1321 of file stm32f10x.h.

#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800)

Definition at line 1965 of file stm32f4xx.h.

#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00)

Definition at line 1966 of file stm32f4xx.h.

#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000)

Definition at line 1967 of file stm32f4xx.h.

#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400)

Definition at line 1968 of file stm32f4xx.h.

#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800)

Definition at line 1969 of file stm32f4xx.h.

#define HASH_BASE   (AHB2PERIPH_BASE + 0x60400)

Definition at line 2001 of file stm32f4xx.h.

#define HASH_DIGEST_BASE   (AHB2PERIPH_BASE + 0x60710)

Definition at line 2002 of file stm32f4xx.h.

#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400)

Definition at line 1304 of file stm32f10x.h.

#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400)

Definition at line 1908 of file stm32f4xx.h.

#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800)

Definition at line 1305 of file stm32f10x.h.

#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800)

Definition at line 1909 of file stm32f4xx.h.

#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00)

Definition at line 1910 of file stm32f4xx.h.

#define I2S2ext_BASE   (APB1PERIPH_BASE + 0x3400)

Definition at line 1897 of file stm32f4xx.h.

#define I2S3ext_BASE   (APB1PERIPH_BASE + 0x4000)

Definition at line 1903 of file stm32f4xx.h.

#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000)

Definition at line 1297 of file stm32f10x.h.

#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000)

Definition at line 1896 of file stm32f4xx.h.

#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800)

Definition at line 1951 of file stm32f4xx.h.

#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84)

Definition at line 1952 of file stm32f4xx.h.

#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104)

Definition at line 1953 of file stm32f4xx.h.

#define OB_BASE   ((uint32_t)0x1FFFF800)

Flash Option Bytes base address

Definition at line 1356 of file stm32f10x.h.

#define PERIPH_BASE   ((uint32_t)0x40000000)

Peripheral base address in the alias region

Definition at line 1274 of file stm32f10x.h.

#define PERIPH_BASE   ((uint32_t)0x40000000)

Peripheral base address in the alias region

Definition at line 1848 of file stm32f4xx.h.

#define PERIPH_BB_BASE   ((uint32_t)0x42000000)

Peripheral base address in the bit-band region

Definition at line 1277 of file stm32f10x.h.

#define PERIPH_BB_BASE   ((uint32_t)0x42000000)

Peripheral base address in the bit-band region

Definition at line 1867 of file stm32f4xx.h.

#define PWR_BASE   (APB1PERIPH_BASE + 0x7000)

Definition at line 1309 of file stm32f10x.h.

#define PWR_BASE   (APB1PERIPH_BASE + 0x7000)

Definition at line 1919 of file stm32f4xx.h.

#define RCC_BASE   (AHBPERIPH_BASE + 0x1000)

Definition at line 1352 of file stm32f10x.h.

#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800)

Definition at line 1971 of file stm32f4xx.h.

#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800)

Definition at line 2003 of file stm32f4xx.h.

#define RTC_BASE   (APB1PERIPH_BASE + 0x2800)

Definition at line 1295 of file stm32f10x.h.

#define RTC_BASE   (APB1PERIPH_BASE + 0x2800)

Definition at line 1894 of file stm32f4xx.h.

#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800)

Definition at line 1943 of file stm32f4xx.h.

#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004)

Definition at line 1944 of file stm32f4xx.h.

#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024)

Definition at line 1945 of file stm32f4xx.h.

#define SDIO_BASE   (PERIPH_BASE + 0x18000)

Definition at line 1336 of file stm32f10x.h.

#define SDIO_BASE   (APB2PERIPH_BASE + 0x2C00)

Definition at line 1933 of file stm32f4xx.h.

#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000)

Definition at line 1325 of file stm32f10x.h.

#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000)

Definition at line 1934 of file stm32f4xx.h.

#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800)

Definition at line 1298 of file stm32f10x.h.

#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800)

Definition at line 1898 of file stm32f4xx.h.

#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00)

Definition at line 1299 of file stm32f10x.h.

#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00)

Definition at line 1899 of file stm32f4xx.h.

#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400)

Definition at line 1935 of file stm32f4xx.h.

#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000)

Definition at line 1941 of file stm32f4xx.h.

#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400)

Definition at line 1942 of file stm32f4xx.h.

#define SRAM1_BASE   ((uint32_t)0x20000000)

SRAM1(112 KB) base address in the alias region

Definition at line 1845 of file stm32f4xx.h.

#define SRAM1_BB_BASE   ((uint32_t)0x22000000)

SRAM1(112 KB) base address in the bit-band region

Definition at line 1864 of file stm32f4xx.h.

#define SRAM2_BASE   ((uint32_t)0x2001C000)

SRAM2(16 KB) base address in the alias region

Definition at line 1846 of file stm32f4xx.h.

#define SRAM2_BB_BASE   ((uint32_t)0x2201C000)

SRAM2(16 KB) base address in the bit-band region

Definition at line 1865 of file stm32f4xx.h.

#define SRAM3_BASE   ((uint32_t)0x20020000)

SRAM3(64 KB) base address in the alias region

Definition at line 1847 of file stm32f4xx.h.

#define SRAM3_BB_BASE   ((uint32_t)0x22400000)

SRAM3(64 KB) base address in the bit-band region

Definition at line 1866 of file stm32f4xx.h.

#define SRAM_BASE   ((uint32_t)0x20000000)

SRAM base address in the alias region

Definition at line 1273 of file stm32f10x.h.

#define SRAM_BASE   SRAM1_BASE

Definition at line 1871 of file stm32f4xx.h.

#define SRAM_BB_BASE   ((uint32_t)0x22000000)

SRAM base address in the bit-band region

Definition at line 1276 of file stm32f10x.h.

#define SRAM_BB_BASE   SRAM1_BB_BASE

Peripheral memory map

Definition at line 1872 of file stm32f4xx.h.

#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800)

Definition at line 1936 of file stm32f4xx.h.

#define TIM10_BASE   (APB2PERIPH_BASE + 0x5000)

Definition at line 1333 of file stm32f10x.h.

#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400)

Definition at line 1939 of file stm32f4xx.h.

#define TIM11_BASE   (APB2PERIPH_BASE + 0x5400)

Definition at line 1334 of file stm32f10x.h.

#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800)

Definition at line 1940 of file stm32f4xx.h.

#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800)

Definition at line 1292 of file stm32f10x.h.

#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800)

Definition at line 1891 of file stm32f4xx.h.

#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00)

Definition at line 1293 of file stm32f10x.h.

#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00)

Definition at line 1892 of file stm32f4xx.h.

#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000)

Definition at line 1294 of file stm32f10x.h.

#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000)

Definition at line 1893 of file stm32f4xx.h.

#define TIM15_BASE   (APB2PERIPH_BASE + 0x4000)

Definition at line 1329 of file stm32f10x.h.

#define TIM16_BASE   (APB2PERIPH_BASE + 0x4400)

Definition at line 1330 of file stm32f10x.h.

#define TIM17_BASE   (APB2PERIPH_BASE + 0x4800)

Definition at line 1331 of file stm32f10x.h.

#define TIM1_BASE   (APB2PERIPH_BASE + 0x2C00)

Definition at line 1324 of file stm32f10x.h.

#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000)

Definition at line 1925 of file stm32f4xx.h.

#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000)

Definition at line 1286 of file stm32f10x.h.

#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000)

Definition at line 1882 of file stm32f4xx.h.

#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400)

Definition at line 1287 of file stm32f10x.h.

#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400)

Definition at line 1883 of file stm32f4xx.h.

#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800)

Definition at line 1288 of file stm32f10x.h.

#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800)

Definition at line 1884 of file stm32f4xx.h.

#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00)

Definition at line 1289 of file stm32f10x.h.

#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00)

Definition at line 1885 of file stm32f4xx.h.

#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000)

Definition at line 1290 of file stm32f10x.h.

#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000)

Definition at line 1886 of file stm32f4xx.h.

#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400)

Definition at line 1291 of file stm32f10x.h.

#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400)

Definition at line 1887 of file stm32f4xx.h.

#define TIM8_BASE   (APB2PERIPH_BASE + 0x3400)

Definition at line 1326 of file stm32f10x.h.

#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400)

Definition at line 1926 of file stm32f4xx.h.

#define TIM9_BASE   (APB2PERIPH_BASE + 0x4C00)

Definition at line 1332 of file stm32f10x.h.

#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000)

Definition at line 1938 of file stm32f4xx.h.

#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00)

Definition at line 1302 of file stm32f10x.h.

#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00)

Definition at line 1906 of file stm32f4xx.h.

#define UART5_BASE   (APB1PERIPH_BASE + 0x5000)

Definition at line 1303 of file stm32f10x.h.

#define UART5_BASE   (APB1PERIPH_BASE + 0x5000)

Definition at line 1907 of file stm32f4xx.h.

#define UART7_BASE   (APB1PERIPH_BASE + 0x7800)

Definition at line 1921 of file stm32f4xx.h.

#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00)

APB2 peripherals

Definition at line 1922 of file stm32f4xx.h.

#define USART1_BASE   (APB2PERIPH_BASE + 0x3800)

Definition at line 1327 of file stm32f10x.h.

#define USART1_BASE   (APB2PERIPH_BASE + 0x1000)

Definition at line 1927 of file stm32f4xx.h.

#define USART2_BASE   (APB1PERIPH_BASE + 0x4400)

Definition at line 1300 of file stm32f10x.h.

#define USART2_BASE   (APB1PERIPH_BASE + 0x4400)

Definition at line 1904 of file stm32f4xx.h.

#define USART3_BASE   (APB1PERIPH_BASE + 0x4800)

Definition at line 1301 of file stm32f10x.h.

#define USART3_BASE   (APB1PERIPH_BASE + 0x4800)

Definition at line 1905 of file stm32f4xx.h.

#define USART6_BASE   (APB2PERIPH_BASE + 0x1400)

Definition at line 1928 of file stm32f4xx.h.

#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00)

Definition at line 1296 of file stm32f10x.h.

#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00)

Definition at line 1895 of file stm32f4xx.h.



rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:23