stm32f4xx_adc.c
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1 
105 /* Includes ------------------------------------------------------------------*/
106 #include "stm32f4xx_adc.h"
107 #include "stm32f4xx_rcc.h"
108 
118 /* Private typedef -----------------------------------------------------------*/
119 /* Private define ------------------------------------------------------------*/
120 
121 /* ADC DISCNUM mask */
122 #define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)
123 
124 /* ADC AWDCH mask */
125 #define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0)
126 
127 /* ADC Analog watchdog enable mode mask */
128 #define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF)
129 
130 /* CR1 register Mask */
131 #define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF)
132 
133 /* ADC EXTEN mask */
134 #define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF)
135 
136 /* ADC JEXTEN mask */
137 #define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF)
138 
139 /* ADC JEXTSEL mask */
140 #define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF)
141 
142 /* CR2 register Mask */
143 #define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)
144 
145 /* ADC SQx mask */
146 #define SQR3_SQ_SET ((uint32_t)0x0000001F)
147 #define SQR2_SQ_SET ((uint32_t)0x0000001F)
148 #define SQR1_SQ_SET ((uint32_t)0x0000001F)
149 
150 /* ADC L Mask */
151 #define SQR1_L_RESET ((uint32_t)0xFF0FFFFF)
152 
153 /* ADC JSQx mask */
154 #define JSQR_JSQ_SET ((uint32_t)0x0000001F)
155 
156 /* ADC JL mask */
157 #define JSQR_JL_SET ((uint32_t)0x00300000)
158 #define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF)
159 
160 /* ADC SMPx mask */
161 #define SMPR1_SMP_SET ((uint32_t)0x00000007)
162 #define SMPR2_SMP_SET ((uint32_t)0x00000007)
163 
164 /* ADC JDRx registers offset */
165 #define JDR_OFFSET ((uint8_t)0x28)
166 
167 /* ADC CDR register base address */
168 #define CDR_ADDRESS ((uint32_t)0x40012308)
169 
170 /* ADC CCR register Mask */
171 #define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0)
172 
173 /* Private macro -------------------------------------------------------------*/
174 /* Private variables ---------------------------------------------------------*/
175 /* Private function prototypes -----------------------------------------------*/
176 /* Private functions ---------------------------------------------------------*/
177 
213 void ADC_DeInit(void)
214 {
215  /* Enable all ADCs reset state */
217 
218  /* Release all ADCs from reset state */
220 }
221 
235 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
236 {
237  uint32_t tmpreg1 = 0;
238  uint8_t tmpreg2 = 0;
239  /* Check the parameters */
241  assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution));
246  assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
248 
249  /*---------------------------- ADCx CR1 Configuration -----------------*/
250  /* Get the ADCx CR1 value */
251  tmpreg1 = ADCx->CR1;
252 
253  /* Clear RES and SCAN bits */
254  tmpreg1 &= CR1_CLEAR_MASK;
255 
256  /* Configure ADCx: scan conversion mode and resolution */
257  /* Set SCAN bit according to ADC_ScanConvMode value */
258  /* Set RES bit according to ADC_Resolution value */
259  tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \
260  ADC_InitStruct->ADC_Resolution);
261  /* Write to ADCx CR1 */
262  ADCx->CR1 = tmpreg1;
263  /*---------------------------- ADCx CR2 Configuration -----------------*/
264  /* Get the ADCx CR2 value */
265  tmpreg1 = ADCx->CR2;
266 
267  /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */
268  tmpreg1 &= CR2_CLEAR_MASK;
269 
270  /* Configure ADCx: external trigger event and edge, data alignment and
271  continuous conversion mode */
272  /* Set ALIGN bit according to ADC_DataAlign value */
273  /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */
274  /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
275  /* Set CONT bit according to ADC_ContinuousConvMode value */
276  tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \
277  ADC_InitStruct->ADC_ExternalTrigConv |
278  ADC_InitStruct->ADC_ExternalTrigConvEdge | \
279  ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
280 
281  /* Write to ADCx CR2 */
282  ADCx->CR2 = tmpreg1;
283  /*---------------------------- ADCx SQR1 Configuration -----------------*/
284  /* Get the ADCx SQR1 value */
285  tmpreg1 = ADCx->SQR1;
286 
287  /* Clear L bits */
288  tmpreg1 &= SQR1_L_RESET;
289 
290  /* Configure ADCx: regular channel sequence length */
291  /* Set L bits according to ADC_NbrOfConversion value */
292  tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);
293  tmpreg1 |= ((uint32_t)tmpreg2 << 20);
294 
295  /* Write to ADCx SQR1 */
296  ADCx->SQR1 = tmpreg1;
297 }
298 
310 void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
311 {
312  /* Initialize the ADC_Mode member */
313  ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
314 
315  /* initialize the ADC_ScanConvMode member */
316  ADC_InitStruct->ADC_ScanConvMode = DISABLE;
317 
318  /* Initialize the ADC_ContinuousConvMode member */
319  ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
320 
321  /* Initialize the ADC_ExternalTrigConvEdge member */
323 
324  /* Initialize the ADC_ExternalTrigConv member */
326 
327  /* Initialize the ADC_DataAlign member */
328  ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
329 
330  /* Initialize the ADC_NbrOfConversion member */
331  ADC_InitStruct->ADC_NbrOfConversion = 1;
332 }
333 
341 void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
342 {
343  uint32_t tmpreg1 = 0;
344  /* Check the parameters */
345  assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode));
346  assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));
347  assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode));
349  /*---------------------------- ADC CCR Configuration -----------------*/
350  /* Get the ADC CCR value */
351  tmpreg1 = ADC->CCR;
352 
353  /* Clear MULTI, DELAY, DMA and ADCPRE bits */
354  tmpreg1 &= CR_CLEAR_MASK;
355 
356  /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler,
357  and DMA access mode for multimode */
358  /* Set MULTI bits according to ADC_Mode value */
359  /* Set ADCPRE bits according to ADC_Prescaler value */
360  /* Set DMA bits according to ADC_DMAAccessMode value */
361  /* Set DELAY bits according to ADC_TwoSamplingDelay value */
362  tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode |
363  ADC_CommonInitStruct->ADC_Prescaler |
364  ADC_CommonInitStruct->ADC_DMAAccessMode |
365  ADC_CommonInitStruct->ADC_TwoSamplingDelay);
366 
367  /* Write to ADC CCR */
368  ADC->CCR = tmpreg1;
369 }
370 
377 void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
378 {
379  /* Initialize the ADC_Mode member */
380  ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent;
381 
382  /* initialize the ADC_Prescaler member */
383  ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2;
384 
385  /* Initialize the ADC_DMAAccessMode member */
386  ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
387 
388  /* Initialize the ADC_TwoSamplingDelay member */
389  ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
390 }
391 
399 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
400 {
401  /* Check the parameters */
404  if (NewState != DISABLE)
405  {
406  /* Set the ADON bit to wake up the ADC from power down mode */
407  ADCx->CR2 |= (uint32_t)ADC_CR2_ADON;
408  }
409  else
410  {
411  /* Disable the selected ADC peripheral */
412  ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);
413  }
414 }
455 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
456 {
457  uint32_t tmpreg = 0;
458  /* Check the parameters */
460  assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
461 
462  /* Get the old register value */
463  tmpreg = ADCx->CR1;
464 
465  /* Clear AWDEN, JAWDEN and AWDSGL bits */
466  tmpreg &= CR1_AWDMode_RESET;
467 
468  /* Set the analog watchdog enable mode */
469  tmpreg |= ADC_AnalogWatchdog;
470 
471  /* Store the new register value */
472  ADCx->CR1 = tmpreg;
473 }
474 
484 void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
485  uint16_t LowThreshold)
486 {
487  /* Check the parameters */
489  assert_param(IS_ADC_THRESHOLD(HighThreshold));
490  assert_param(IS_ADC_THRESHOLD(LowThreshold));
491 
492  /* Set the ADCx high threshold */
493  ADCx->HTR = HighThreshold;
494 
495  /* Set the ADCx low threshold */
496  ADCx->LTR = LowThreshold;
497 }
498 
525 void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
526 {
527  uint32_t tmpreg = 0;
528  /* Check the parameters */
530  assert_param(IS_ADC_CHANNEL(ADC_Channel));
531 
532  /* Get the old register value */
533  tmpreg = ADCx->CR1;
534 
535  /* Clear the Analog watchdog channel select bits */
536  tmpreg &= CR1_AWDCH_RESET;
537 
538  /* Set the Analog watchdog channel */
539  tmpreg |= ADC_Channel;
540 
541  /* Store the new register value */
542  ADCx->CR1 = tmpreg;
543 }
590 {
591  /* Check the parameters */
593  if (NewState != DISABLE)
594  {
595  /* Enable the temperature sensor and Vrefint channel*/
596  ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;
597  }
598  else
599  {
600  /* Disable the temperature sensor and Vrefint channel*/
601  ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);
602  }
603 }
604 
612 {
613  /* Check the parameters */
615  if (NewState != DISABLE)
616  {
617  /* Enable the VBAT channel*/
618  ADC->CCR |= (uint32_t)ADC_CCR_VBATE;
619  }
620  else
621  {
622  /* Disable the VBAT channel*/
623  ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE);
624  }
625 }
626 
711 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
712 {
713  uint32_t tmpreg1 = 0, tmpreg2 = 0;
714  /* Check the parameters */
716  assert_param(IS_ADC_CHANNEL(ADC_Channel));
718  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
719 
720  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
721  if (ADC_Channel > ADC_Channel_9)
722  {
723  /* Get the old register value */
724  tmpreg1 = ADCx->SMPR1;
725 
726  /* Calculate the mask to clear */
727  tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10));
728 
729  /* Clear the old sample time */
730  tmpreg1 &= ~tmpreg2;
731 
732  /* Calculate the mask to set */
733  tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
734 
735  /* Set the new sample time */
736  tmpreg1 |= tmpreg2;
737 
738  /* Store the new register value */
739  ADCx->SMPR1 = tmpreg1;
740  }
741  else /* ADC_Channel include in ADC_Channel_[0..9] */
742  {
743  /* Get the old register value */
744  tmpreg1 = ADCx->SMPR2;
745 
746  /* Calculate the mask to clear */
747  tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
748 
749  /* Clear the old sample time */
750  tmpreg1 &= ~tmpreg2;
751 
752  /* Calculate the mask to set */
753  tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
754 
755  /* Set the new sample time */
756  tmpreg1 |= tmpreg2;
757 
758  /* Store the new register value */
759  ADCx->SMPR2 = tmpreg1;
760  }
761  /* For Rank 1 to 6 */
762  if (Rank < 7)
763  {
764  /* Get the old register value */
765  tmpreg1 = ADCx->SQR3;
766 
767  /* Calculate the mask to clear */
768  tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1));
769 
770  /* Clear the old SQx bits for the selected rank */
771  tmpreg1 &= ~tmpreg2;
772 
773  /* Calculate the mask to set */
774  tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
775 
776  /* Set the SQx bits for the selected rank */
777  tmpreg1 |= tmpreg2;
778 
779  /* Store the new register value */
780  ADCx->SQR3 = tmpreg1;
781  }
782  /* For Rank 7 to 12 */
783  else if (Rank < 13)
784  {
785  /* Get the old register value */
786  tmpreg1 = ADCx->SQR2;
787 
788  /* Calculate the mask to clear */
789  tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7));
790 
791  /* Clear the old SQx bits for the selected rank */
792  tmpreg1 &= ~tmpreg2;
793 
794  /* Calculate the mask to set */
795  tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
796 
797  /* Set the SQx bits for the selected rank */
798  tmpreg1 |= tmpreg2;
799 
800  /* Store the new register value */
801  ADCx->SQR2 = tmpreg1;
802  }
803  /* For Rank 13 to 16 */
804  else
805  {
806  /* Get the old register value */
807  tmpreg1 = ADCx->SQR1;
808 
809  /* Calculate the mask to clear */
810  tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13));
811 
812  /* Clear the old SQx bits for the selected rank */
813  tmpreg1 &= ~tmpreg2;
814 
815  /* Calculate the mask to set */
816  tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
817 
818  /* Set the SQx bits for the selected rank */
819  tmpreg1 |= tmpreg2;
820 
821  /* Store the new register value */
822  ADCx->SQR1 = tmpreg1;
823  }
824 }
825 
832 {
833  /* Check the parameters */
835 
836  /* Enable the selected ADC conversion for regular group */
837  ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;
838 }
839 
846 {
847  FlagStatus bitstatus = RESET;
848  /* Check the parameters */
850 
851  /* Check the status of SWSTART bit */
852  if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
853  {
854  /* SWSTART bit is set */
855  bitstatus = SET;
856  }
857  else
858  {
859  /* SWSTART bit is reset */
860  bitstatus = RESET;
861  }
862 
863  /* Return the SWSTART bit status */
864  return bitstatus;
865 }
866 
867 
876 {
877  /* Check the parameters */
880 
881  if (NewState != DISABLE)
882  {
883  /* Enable the selected ADC EOC rising on each regular channel conversion */
884  ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS;
885  }
886  else
887  {
888  /* Disable the selected ADC EOC rising on each regular channel conversion */
889  ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS);
890  }
891 }
892 
901 {
902  /* Check the parameters */
905 
906  if (NewState != DISABLE)
907  {
908  /* Enable the selected ADC continuous conversion mode */
909  ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;
910  }
911  else
912  {
913  /* Disable the selected ADC continuous conversion mode */
914  ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);
915  }
916 }
917 
926 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
927 {
928  uint32_t tmpreg1 = 0;
929  uint32_t tmpreg2 = 0;
930 
931  /* Check the parameters */
934 
935  /* Get the old register value */
936  tmpreg1 = ADCx->CR1;
937 
938  /* Clear the old discontinuous mode channel count */
939  tmpreg1 &= CR1_DISCNUM_RESET;
940 
941  /* Set the discontinuous mode channel count */
942  tmpreg2 = Number - 1;
943  tmpreg1 |= tmpreg2 << 13;
944 
945  /* Store the new register value */
946  ADCx->CR1 = tmpreg1;
947 }
948 
959 {
960  /* Check the parameters */
963 
964  if (NewState != DISABLE)
965  {
966  /* Enable the selected ADC regular discontinuous mode */
967  ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN;
968  }
969  else
970  {
971  /* Disable the selected ADC regular discontinuous mode */
972  ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);
973  }
974 }
975 
982 {
983  /* Check the parameters */
985 
986  /* Return the selected ADC conversion value */
987  return (uint16_t) ADCx->DR;
988 }
989 
1003 {
1004  /* Return the multi mode conversion value */
1005  return (*(__IO uint32_t *) CDR_ADDRESS);
1006 }
1049 {
1050  /* Check the parameters */
1052  assert_param(IS_FUNCTIONAL_STATE(NewState));
1053  if (NewState != DISABLE)
1054  {
1055  /* Enable the selected ADC DMA request */
1056  ADCx->CR2 |= (uint32_t)ADC_CR2_DMA;
1057  }
1058  else
1059  {
1060  /* Disable the selected ADC DMA request */
1061  ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA);
1062  }
1063 }
1064 
1073 {
1074  /* Check the parameters */
1076  assert_param(IS_FUNCTIONAL_STATE(NewState));
1077  if (NewState != DISABLE)
1078  {
1079  /* Enable the selected ADC DMA request after last transfer */
1080  ADCx->CR2 |= (uint32_t)ADC_CR2_DDS;
1081  }
1082  else
1083  {
1084  /* Disable the selected ADC DMA request after last transfer */
1085  ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS);
1086  }
1087 }
1088 
1100 {
1101  /* Check the parameters */
1102  assert_param(IS_FUNCTIONAL_STATE(NewState));
1103  if (NewState != DISABLE)
1104  {
1105  /* Enable the selected ADC DMA request after last transfer */
1106  ADC->CCR |= (uint32_t)ADC_CCR_DDS;
1107  }
1108  else
1109  {
1110  /* Disable the selected ADC DMA request after last transfer */
1111  ADC->CCR &= (uint32_t)(~ADC_CCR_DDS);
1112  }
1113 }
1186 void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
1187 {
1188  uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
1189  /* Check the parameters */
1191  assert_param(IS_ADC_CHANNEL(ADC_Channel));
1193  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
1194  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
1195  if (ADC_Channel > ADC_Channel_9)
1196  {
1197  /* Get the old register value */
1198  tmpreg1 = ADCx->SMPR1;
1199  /* Calculate the mask to clear */
1200  tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10));
1201  /* Clear the old sample time */
1202  tmpreg1 &= ~tmpreg2;
1203  /* Calculate the mask to set */
1204  tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
1205  /* Set the new sample time */
1206  tmpreg1 |= tmpreg2;
1207  /* Store the new register value */
1208  ADCx->SMPR1 = tmpreg1;
1209  }
1210  else /* ADC_Channel include in ADC_Channel_[0..9] */
1211  {
1212  /* Get the old register value */
1213  tmpreg1 = ADCx->SMPR2;
1214  /* Calculate the mask to clear */
1215  tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
1216  /* Clear the old sample time */
1217  tmpreg1 &= ~tmpreg2;
1218  /* Calculate the mask to set */
1219  tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
1220  /* Set the new sample time */
1221  tmpreg1 |= tmpreg2;
1222  /* Store the new register value */
1223  ADCx->SMPR2 = tmpreg1;
1224  }
1225  /* Rank configuration */
1226  /* Get the old register value */
1227  tmpreg1 = ADCx->JSQR;
1228  /* Get JL value: Number = JL+1 */
1229  tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20;
1230  /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
1231  tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
1232  /* Clear the old JSQx bits for the selected rank */
1233  tmpreg1 &= ~tmpreg2;
1234  /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
1235  tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
1236  /* Set the JSQx bits for the selected rank */
1237  tmpreg1 |= tmpreg2;
1238  /* Store the new register value */
1239  ADCx->JSQR = tmpreg1;
1240 }
1241 
1250 {
1251  uint32_t tmpreg1 = 0;
1252  uint32_t tmpreg2 = 0;
1253  /* Check the parameters */
1256 
1257  /* Get the old register value */
1258  tmpreg1 = ADCx->JSQR;
1259 
1260  /* Clear the old injected sequence length JL bits */
1261  tmpreg1 &= JSQR_JL_RESET;
1262 
1263  /* Set the injected sequence length JL bits */
1264  tmpreg2 = Length - 1;
1265  tmpreg1 |= tmpreg2 << 20;
1266 
1267  /* Store the new register value */
1268  ADCx->JSQR = tmpreg1;
1269 }
1270 
1284 void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
1285 {
1286  __IO uint32_t tmp = 0;
1287  /* Check the parameters */
1289  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
1290  assert_param(IS_ADC_OFFSET(Offset));
1291 
1292  tmp = (uint32_t)ADCx;
1293  tmp += ADC_InjectedChannel;
1294 
1295  /* Set the selected injected channel data offset */
1296  *(__IO uint32_t *) tmp = (uint32_t)Offset;
1297 }
1298 
1322 void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
1323 {
1324  uint32_t tmpreg = 0;
1325  /* Check the parameters */
1327  assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
1328 
1329  /* Get the old register value */
1330  tmpreg = ADCx->CR2;
1331 
1332  /* Clear the old external event selection for injected group */
1333  tmpreg &= CR2_JEXTSEL_RESET;
1334 
1335  /* Set the external event selection for injected group */
1336  tmpreg |= ADC_ExternalTrigInjecConv;
1337 
1338  /* Store the new register value */
1339  ADCx->CR2 = tmpreg;
1340 }
1341 
1356 void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
1357 {
1358  uint32_t tmpreg = 0;
1359  /* Check the parameters */
1361  assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge));
1362  /* Get the old register value */
1363  tmpreg = ADCx->CR2;
1364  /* Clear the old external trigger edge for injected group */
1365  tmpreg &= CR2_JEXTEN_RESET;
1366  /* Set the new external trigger edge for injected group */
1367  tmpreg |= ADC_ExternalTrigInjecConvEdge;
1368  /* Store the new register value */
1369  ADCx->CR2 = tmpreg;
1370 }
1371 
1378 {
1379  /* Check the parameters */
1381  /* Enable the selected ADC conversion for injected group */
1382  ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART;
1383 }
1384 
1391 {
1392  FlagStatus bitstatus = RESET;
1393  /* Check the parameters */
1395 
1396  /* Check the status of JSWSTART bit */
1397  if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
1398  {
1399  /* JSWSTART bit is set */
1400  bitstatus = SET;
1401  }
1402  else
1403  {
1404  /* JSWSTART bit is reset */
1405  bitstatus = RESET;
1406  }
1407  /* Return the JSWSTART bit status */
1408  return bitstatus;
1409 }
1410 
1420 {
1421  /* Check the parameters */
1423  assert_param(IS_FUNCTIONAL_STATE(NewState));
1424  if (NewState != DISABLE)
1425  {
1426  /* Enable the selected ADC automatic injected group conversion */
1427  ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO;
1428  }
1429  else
1430  {
1431  /* Disable the selected ADC automatic injected group conversion */
1432  ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);
1433  }
1434 }
1435 
1446 {
1447  /* Check the parameters */
1449  assert_param(IS_FUNCTIONAL_STATE(NewState));
1450  if (NewState != DISABLE)
1451  {
1452  /* Enable the selected ADC injected discontinuous mode */
1453  ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN;
1454  }
1455  else
1456  {
1457  /* Disable the selected ADC injected discontinuous mode */
1458  ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN);
1459  }
1460 }
1461 
1473 uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
1474 {
1475  __IO uint32_t tmp = 0;
1476 
1477  /* Check the parameters */
1479  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
1480 
1481  tmp = (uint32_t)ADCx;
1482  tmp += ADC_InjectedChannel + JDR_OFFSET;
1483 
1484  /* Returns the selected injected channel conversion data value */
1485  return (uint16_t) (*(__IO uint32_t*) tmp);
1486 }
1580 void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
1581 {
1582  uint32_t itmask = 0;
1583  /* Check the parameters */
1585  assert_param(IS_FUNCTIONAL_STATE(NewState));
1586  assert_param(IS_ADC_IT(ADC_IT));
1587 
1588  /* Get the ADC IT index */
1589  itmask = (uint8_t)ADC_IT;
1590  itmask = (uint32_t)0x01 << itmask;
1591 
1592  if (NewState != DISABLE)
1593  {
1594  /* Enable the selected ADC interrupts */
1595  ADCx->CR1 |= itmask;
1596  }
1597  else
1598  {
1599  /* Disable the selected ADC interrupts */
1600  ADCx->CR1 &= (~(uint32_t)itmask);
1601  }
1602 }
1603 
1617 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
1618 {
1619  FlagStatus bitstatus = RESET;
1620  /* Check the parameters */
1622  assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
1623 
1624  /* Check the status of the specified ADC flag */
1625  if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
1626  {
1627  /* ADC_FLAG is set */
1628  bitstatus = SET;
1629  }
1630  else
1631  {
1632  /* ADC_FLAG is reset */
1633  bitstatus = RESET;
1634  }
1635  /* Return the ADC_FLAG status */
1636  return bitstatus;
1637 }
1638 
1652 void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
1653 {
1654  /* Check the parameters */
1656  assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
1657 
1658  /* Clear the selected ADC flags */
1659  ADCx->SR = ~(uint32_t)ADC_FLAG;
1660 }
1661 
1673 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
1674 {
1675  ITStatus bitstatus = RESET;
1676  uint32_t itmask = 0, enablestatus = 0;
1677 
1678  /* Check the parameters */
1680  assert_param(IS_ADC_IT(ADC_IT));
1681 
1682  /* Get the ADC IT index */
1683  itmask = ADC_IT >> 8;
1684 
1685  /* Get the ADC_IT enable bit status */
1686  enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ;
1687 
1688  /* Check the status of the specified ADC interrupt */
1689  if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
1690  {
1691  /* ADC_IT is set */
1692  bitstatus = SET;
1693  }
1694  else
1695  {
1696  /* ADC_IT is reset */
1697  bitstatus = RESET;
1698  }
1699  /* Return the ADC_IT status */
1700  return bitstatus;
1701 }
1702 
1714 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
1715 {
1716  uint8_t itmask = 0;
1717  /* Check the parameters */
1719  assert_param(IS_ADC_IT(ADC_IT));
1720  /* Get the ADC IT index */
1721  itmask = (uint8_t)(ADC_IT >> 8);
1722  /* Clear the selected ADC interrupt pending bits */
1723  ADCx->SR = ~(uint32_t)itmask;
1724 }
1741 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
#define IS_ADC_INJECTED_RANK(RANK)
void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
Enables or disables the analog watchdog on single/all regular or injected channels.
#define IS_ADC_MODE(MODE)
void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADC DMA request after last transfer (Single-ADC mode)
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx)
Gets the selected ADC Software start injected conversion Status.
FlagStatus
Definition: stm32f4xx.h:706
#define IS_ADC_INJECTED_CHANNEL(CHANNEL)
uint32_t ADC_ExternalTrigConv
Definition: stm32f4xx_adc.h:68
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG)
#define IS_ADC_EXT_TRIG_EDGE(EDGE)
#define JDR_OFFSET
#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE)
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv)
Configures the ADCx external trigger for injected channels conversion.
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length)
Configures the sequencer length for injected channels.
FunctionalState
Definition: stm32f4xx.h:708
#define CR1_AWDCH_RESET
#define CR2_JEXTSEL_RESET
ADC Init structure definition.
Definition: stm32f4xx_adc.h:53
#define ADC_TwoSamplingDelay_5Cycles
Analog to Digital Converter.
Definition: stm32f4xx.h:725
#define ADC_Mode_Independent
#define ADC_DMAAccessMode_Disabled
__IO uint32_t SMPR2
Definition: stm32f4xx.h:731
#define ADC_CR1_JAUTO
Definition: stm32f4xx.h:2210
__IO uint32_t SMPR1
Definition: stm32f4xx.h:730
FunctionalState ADC_ContinuousConvMode
Definition: stm32f4xx_adc.h:61
void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC peripheral.
#define IS_ADC_DMA_ACCESS_MODE(MODE)
__IO uint32_t SR
Definition: stm32f4xx.h:727
void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the EOC on each regular channel conversion.
#define CR2_CLEAR_MASK
#define IS_ADC_CHANNEL(CHANNEL)
#define IS_ADC_GET_FLAG(FLAG)
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER)
#define IS_ADC_REGULAR_RANK(RANK)
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
Configures the high and low thresholds of the analog watchdog.
void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode on regular group channel for the specified ADC...
#define ADC_CR1_JDISCEN
Definition: stm32f4xx.h:2212
void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode for injected group channel for the specified ADC...
void assert_param(int val)
void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number)
Configures the discontinuous mode for the selected ADC regular group channel.
void ADC_CommonStructInit(ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Fills each ADC_CommonInitStruct member with its default value.
uint32_t ADC_GetMultiModeConversionValue(void)
Returns the last ADC1, ADC2 and ADC3 regular conversions results data in the selected multi mode...
__IO uint32_t SQR3
Definition: stm32f4xx.h:740
#define IS_ADC_RESOLUTION(RESOLUTION)
__IO uint32_t SQR2
Definition: stm32f4xx.h:739
void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState)
Enables or disables the specified ADC interrupts.
#define IS_ADC_THRESHOLD(THRESHOLD)
#define ADC_Prescaler_Div2
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
#define CDR_ADDRESS
void ADC_SoftwareStartConv(ADC_TypeDef *ADCx)
Enables the selected ADC software start conversion of the regular channels.
void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT)
Clears the ADCx&#39;s interrupt pending bits.
This file contains all the functions prototypes for the ADC firmware library.
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx)
Gets the selected ADC Software start regular conversion Status.
#define CR2_JEXTEN_RESET
Definition: stm32f4xx.h:706
ADC Common Init structure definition.
Definition: stm32f4xx_adc.h:84
#define ADC_CCR_VBATE
Definition: stm32f4xx.h:2539
#define ADC_Channel_9
__IO uint32_t JSQR
Definition: stm32f4xx.h:741
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel)
Configures the analog watchdog guarded single channel.
#define SQR1_L_RESET
void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC DMA request.
enum FlagStatus ITStatus
#define CR1_AWDMode_RESET
#define ADC_CR1_DISCEN
Definition: stm32f4xx.h:2211
void ADC_SoftwareStartInjectedConv(ADC_TypeDef *ADCx)
Enables the selected ADC software start conversion of the injected channels.
#define SQR1_SQ_SET
uint32_t ADC_DataAlign
Definition: stm32f4xx_adc.h:72
#define ADC_CR2_DMA
Definition: stm32f4xx.h:2227
#define JSQR_JL_SET
#define __IO
Definition: core_cm0.h:198
#define ADC_ExternalTrigConv_T1_CC1
#define ADC_CR2_ADON
Definition: stm32f4xx.h:2225
#define IS_ADC_PRESCALER(PRESCALER)
#define ADC_CR2_SWSTART
Definition: stm32f4xx.h:2248
#define IS_ADC_CLEAR_FLAG(FLAG)
FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
Checks whether the specified ADC flag is set or not.
#define SMPR1_SMP_SET
#define ADC
Definition: stm32f4xx.h:2082
#define IS_ADC_SAMPLE_TIME(TIME)
uint8_t ADC_NbrOfConversion
Definition: stm32f4xx_adc.h:75
void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC injected channel its corresponding rank in the sequencer and its samp...
#define JSQR_JSQ_SET
uint32_t ADC_TwoSamplingDelay
Definition: stm32f4xx_adc.h:96
__IO uint32_t DR
Definition: stm32f4xx.h:746
#define IS_ADC_IT(IT)
#define CR1_CLEAR_MASK
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG)
__IO uint32_t SQR1
Definition: stm32f4xx.h:738
void ADC_DeInit(void)
Deinitializes all ADCs peripherals registers to their default reset values.
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
#define IS_ADC_OFFSET(OFFSET)
#define ADC_Resolution_12b
void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct)
Fills each ADC_InitStruct member with its default value.
#define ADC_ExternalTrigConvEdge_None
__IO uint32_t LTR
Definition: stm32f4xx.h:737
void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState)
Enables or disables the ADC DMA request after last transfer in multi ADC mode.
#define IS_ADC_INJECTED_LENGTH(LENGTH)
FunctionalState ADC_ScanConvMode
Definition: stm32f4xx_adc.h:57
#define CR_CLEAR_MASK
uint32_t ADC_Resolution
Definition: stm32f4xx_adc.h:55
ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT)
Checks whether the specified ADC interrupt has occurred or not.
#define ADC_CR2_EOCS
Definition: stm32f4xx.h:2229
void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
Set the injected channels conversion value offset.
__IO uint32_t CR1
Definition: stm32f4xx.h:728
#define SQR3_SQ_SET
#define JSQR_JL_RESET
__IO uint32_t HTR
Definition: stm32f4xx.h:736
#define ADC_CCR_TSVREFE
Definition: stm32f4xx.h:2540
void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct.
void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
Clears the ADCx&#39;s pending flags.
#define SMPR2_SMP_SET
void ADC_ContinuousModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADC continuous conversion mode.
#define IS_ADC_DATA_ALIGN(ALIGN)
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel)
Returns the ADC injected channel conversion result.
#define SQR2_SQ_SET
#define ADC_CR2_CONT
Definition: stm32f4xx.h:2226
#define IS_ADC_ALL_PERIPH(PERIPH)
void ADC_TempSensorVrefintCmd(FunctionalState NewState)
Enables or disables the temperature sensor and Vrefint channels.
void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sampl...
void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
Configures the ADCx external trigger edge for injected channels conversion.
#define ADC_DataAlign_Right
uint32_t ADC_ExternalTrigConvEdge
Definition: stm32f4xx_adc.h:64
uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx)
Returns the last ADCx conversion result data for regular channel.
void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC automatic injected group conversion after regular one...
#define IS_ADC_REGULAR_LENGTH(LENGTH)
void ADC_CommonInit(ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initializes the ADCs peripherals according to the specified parameters in the ADC_CommonInitStruct.
#define CR1_DISCNUM_RESET
#define ADC_CR2_JSWSTART
Definition: stm32f4xx.h:2239
#define IS_ADC_SAMPLING_DELAY(DELAY)
void ADC_VBATCmd(FunctionalState NewState)
Enables or disables the VBAT (Voltage Battery) channel.
#define IS_ADC_EXT_TRIG(REGTRIG)
#define ADC_CR2_DDS
Definition: stm32f4xx.h:2228
#define ADC_CCR_DDS
Definition: stm32f4xx.h:2532
__IO uint32_t CR2
Definition: stm32f4xx.h:729


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19