stm32f30x_dma.c
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1 
73 /* Includes ------------------------------------------------------------------*/
74 #include "stm32f30x_dma.h"
75 
85 /* Private typedef -----------------------------------------------------------*/
86 /* Private define ------------------------------------------------------------*/
87 #define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */
88 #define FLAG_Mask ((uint32_t)0x10000000) /* DMA2 FLAG mask */
89 
90 
91 /* DMA1 Channelx interrupt pending bit masks */
92 #define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
93 #define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
94 #define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
95 #define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
96 #define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
97 #define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
98 #define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
99 
100 /* DMA2 Channelx interrupt pending bit masks */
101 #define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
102 #define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
103 #define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
104 #define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
105 #define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
106 
107 /* Private macro -------------------------------------------------------------*/
108 /* Private variables ---------------------------------------------------------*/
109 /* Private function prototypes -----------------------------------------------*/
110 /* Private functions ---------------------------------------------------------*/
111 
141 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
142 {
143  /* Check the parameters */
144  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
145 
146  /* Disable the selected DMAy Channelx */
147  DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
148 
149  /* Reset DMAy Channelx control register */
150  DMAy_Channelx->CCR = 0;
151 
152  /* Reset DMAy Channelx remaining bytes register */
153  DMAy_Channelx->CNDTR = 0;
154 
155  /* Reset DMAy Channelx peripheral address register */
156  DMAy_Channelx->CPAR = 0;
157 
158  /* Reset DMAy Channelx memory address register */
159  DMAy_Channelx->CMAR = 0;
160 
161  if (DMAy_Channelx == DMA1_Channel1)
162  {
163  /* Reset interrupt pending bits for DMA1 Channel1 */
164  DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
165  }
166  else if (DMAy_Channelx == DMA1_Channel2)
167  {
168  /* Reset interrupt pending bits for DMA1 Channel2 */
169  DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
170  }
171  else if (DMAy_Channelx == DMA1_Channel3)
172  {
173  /* Reset interrupt pending bits for DMA1 Channel3 */
174  DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
175  }
176  else if (DMAy_Channelx == DMA1_Channel4)
177  {
178  /* Reset interrupt pending bits for DMA1 Channel4 */
179  DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
180  }
181  else if (DMAy_Channelx == DMA1_Channel5)
182  {
183  /* Reset interrupt pending bits for DMA1 Channel5 */
184  DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
185  }
186  else if (DMAy_Channelx == DMA1_Channel6)
187  {
188  /* Reset interrupt pending bits for DMA1 Channel6 */
189  DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
190  }
191  else if (DMAy_Channelx == DMA1_Channel7)
192  {
193  /* Reset interrupt pending bits for DMA1 Channel7 */
194  DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
195  }
196  else if (DMAy_Channelx == DMA2_Channel1)
197  {
198  /* Reset interrupt pending bits for DMA2 Channel1 */
199  DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK;
200  }
201  else if (DMAy_Channelx == DMA2_Channel2)
202  {
203  /* Reset interrupt pending bits for DMA2 Channel2 */
204  DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK;
205  }
206  else if (DMAy_Channelx == DMA2_Channel3)
207  {
208  /* Reset interrupt pending bits for DMA2 Channel3 */
209  DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK;
210  }
211  else if (DMAy_Channelx == DMA2_Channel4)
212  {
213  /* Reset interrupt pending bits for DMA2 Channel4 */
214  DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK;
215  }
216  else
217  {
218  if (DMAy_Channelx == DMA2_Channel5)
219  {
220  /* Reset interrupt pending bits for DMA2 Channel5 */
221  DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK;
222  }
223  }
224 }
225 
235 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
236 {
237  uint32_t tmpreg = 0;
238 
239  /* Check the parameters */
240  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
241  assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
246  assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
247  assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
248  assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
249 
250 /*--------------------------- DMAy Channelx CCR Configuration ----------------*/
251  /* Get the DMAy_Channelx CCR value */
252  tmpreg = DMAy_Channelx->CCR;
253 
254  /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
255  tmpreg &= CCR_CLEAR_MASK;
256 
257  /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
258  /* Set DIR bit according to DMA_DIR value */
259  /* Set CIRC bit according to DMA_Mode value */
260  /* Set PINC bit according to DMA_PeripheralInc value */
261  /* Set MINC bit according to DMA_MemoryInc value */
262  /* Set PSIZE bits according to DMA_PeripheralDataSize value */
263  /* Set MSIZE bits according to DMA_MemoryDataSize value */
264  /* Set PL bits according to DMA_Priority value */
265  /* Set the MEM2MEM bit according to DMA_M2M value */
266  tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
267  DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
268  DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
269  DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
270 
271  /* Write to DMAy Channelx CCR */
272  DMAy_Channelx->CCR = tmpreg;
273 
274 /*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
275  /* Write to DMAy Channelx CNDTR */
276  DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
277 
278 /*--------------------------- DMAy Channelx CPAR Configuration ---------------*/
279  /* Write to DMAy Channelx CPAR */
280  DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
281 
282 /*--------------------------- DMAy Channelx CMAR Configuration ---------------*/
283  /* Write to DMAy Channelx CMAR */
284  DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
285 }
286 
293 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
294 {
295 /*-------------- Reset DMA init structure parameters values ------------------*/
296  /* Initialize the DMA_PeripheralBaseAddr member */
297  DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
298  /* Initialize the DMA_MemoryBaseAddr member */
299  DMA_InitStruct->DMA_MemoryBaseAddr = 0;
300  /* Initialize the DMA_DIR member */
301  DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
302  /* Initialize the DMA_BufferSize member */
303  DMA_InitStruct->DMA_BufferSize = 0;
304  /* Initialize the DMA_PeripheralInc member */
306  /* Initialize the DMA_MemoryInc member */
307  DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
308  /* Initialize the DMA_PeripheralDataSize member */
310  /* Initialize the DMA_MemoryDataSize member */
312  /* Initialize the DMA_Mode member */
313  DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
314  /* Initialize the DMA_Priority member */
315  DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
316  /* Initialize the DMA_M2M member */
317  DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
318 }
319 
328 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
329 {
330  /* Check the parameters */
331  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
333 
334  if (NewState != DISABLE)
335  {
336  /* Enable the selected DMAy Channelx */
337  DMAy_Channelx->CCR |= DMA_CCR_EN;
338  }
339  else
340  {
341  /* Disable the selected DMAy Channelx */
342  DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
343  }
344 }
345 
387 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
388 {
389  /* Check the parameters */
390  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
391 
392 /*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
393  /* Write to DMAy Channelx CNDTR */
394  DMAy_Channelx->CNDTR = DataNumber;
395 }
396 
406 {
407  /* Check the parameters */
408  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
409  /* Return the number of remaining data units for DMAy Channelx */
410  return ((uint16_t)(DMAy_Channelx->CNDTR));
411 }
412 
481 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
482 {
483  /* Check the parameters */
484  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
487 
488  if (NewState != DISABLE)
489  {
490  /* Enable the selected DMA interrupts */
491  DMAy_Channelx->CCR |= DMA_IT;
492  }
493  else
494  {
495  /* Disable the selected DMA interrupts */
496  DMAy_Channelx->CCR &= ~DMA_IT;
497  }
498 }
499 
561 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
562 {
563  FlagStatus bitstatus = RESET;
564  uint32_t tmpreg = 0;
565 
566  /* Check the parameters */
567  assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
568 
569  /* Calculate the used DMAy */
570  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
571  {
572  /* Get DMA2 ISR register value */
573  tmpreg = DMA2->ISR ;
574  }
575  else
576  {
577  /* Get DMA1 ISR register value */
578  tmpreg = DMA1->ISR ;
579  }
580 
581  /* Check the status of the specified DMAy flag */
582  if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
583  {
584  /* DMAy_FLAG is set */
585  bitstatus = SET;
586  }
587  else
588  {
589  /* DMAy_FLAG is reset */
590  bitstatus = RESET;
591  }
592 
593  /* Return the DMAy_FLAG status */
594  return bitstatus;
595 }
596 
657 void DMA_ClearFlag(uint32_t DMAy_FLAG)
658 {
659  /* Check the parameters */
660  assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
661 
662 /* Calculate the used DMAy */
663  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
664  {
665  /* Clear the selected DMAy flags */
666  DMA2->IFCR = DMAy_FLAG;
667  }
668  else
669  {
670  /* Clear the selected DMAy flags */
671  DMA1->IFCR = DMAy_FLAG;
672  }
673 }
674 
736 ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
737 {
738  ITStatus bitstatus = RESET;
739  uint32_t tmpreg = 0;
740 
741  /* Check the parameters */
742  assert_param(IS_DMA_GET_IT(DMAy_IT));
743 
744  /* Calculate the used DMA */
745  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
746  {
747  /* Get DMA2 ISR register value */
748  tmpreg = DMA2->ISR;
749  }
750  else
751  {
752  /* Get DMA1 ISR register value */
753  tmpreg = DMA1->ISR;
754  }
755 
756  /* Check the status of the specified DMAy interrupt */
757  if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
758  {
759  /* DMAy_IT is set */
760  bitstatus = SET;
761  }
762  else
763  {
764  /* DMAy_IT is reset */
765  bitstatus = RESET;
766  }
767  /* Return the DMAy_IT status */
768  return bitstatus;
769 }
770 
832 void DMA_ClearITPendingBit(uint32_t DMAy_IT)
833 {
834  /* Check the parameters */
835  assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
836 
837  /* Calculate the used DMAy */
838  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
839  {
840  /* Clear the selected DMAy interrupt pending bits */
841  DMA2->IFCR = DMAy_IT;
842  }
843  else
844  {
845  /* Clear the selected DMAy interrupt pending bits */
846  DMA1->IFCR = DMAy_IT;
847  }
848 }
849 
866 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
#define DMA1_Channel1
Definition: stm32f10x.h:1431
uint32_t DMA_MemoryInc
Definition: stm32f4xx_dma.h:76
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
Sets the number of data units in the current DMAy Channelx transfer.
FlagStatus
Definition: stm32f4xx.h:706
#define DMA_Priority_Low
#define DMA2_Channel4
Definition: stm32f10x.h:1441
FunctionalState
Definition: stm32f4xx.h:708
DMA Init structure definition.
Definition: stm32f4xx_dma.h:54
#define DMA_MemoryDataSize_Byte
#define DMA1_Channel4
Definition: stm32f10x.h:1434
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define DMA1_Channel2
Definition: stm32f10x.h:1432
#define DMA_PeripheralInc_Disable
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
Enables or disables the specified DMAy Channelx.
#define DMA1_Channel3
Definition: stm32f10x.h:1433
uint32_t DMA_MemoryDataSize
Definition: stm32f4xx_dma.h:82
#define IS_DMA_PERIPHERAL_INC_STATE(STATE)
void assert_param(int val)
#define IS_DMA_MEMORY_INC_STATE(STATE)
uint32_t DMA_DIR
Definition: stm32f4xx_dma.h:65
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
Clears the DMAy Channelx's interrupt pending bits.
uint32_t DMA_PeripheralInc
Definition: stm32f4xx_dma.h:73
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
uint32_t DMA_PeripheralDataSize
Definition: stm32f4xx_dma.h:79
#define IS_DMA_DIR(DIR)
#define DMA_M2M_Disable
#define DMA2_CHANNEL5_IT_MASK
__IO uint32_t CMAR
Definition: stm32f10x.h:803
uint32_t DMA_MemoryBaseAddr
Definition: stm32f10x_dma.h:54
Definition: stm32f4xx.h:706
#define CCR_CLEAR_MASK
Definition: stm32f30x_dma.c:87
#define DMA2_CHANNEL3_IT_MASK
#define DMA2_CHANNEL1_IT_MASK
enum FlagStatus ITStatus
#define DMA2_Channel5
Definition: stm32f10x.h:1442
#define IS_DMA_GET_IT(IT)
#define DMA1_Channel6
Definition: stm32f10x.h:1436
#define IS_DMA_MEMORY_DATA_SIZE(SIZE)
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
Fills each DMA_InitStruct member with its default value.
#define DMA2_Channel1
Definition: stm32f10x.h:1438
uint32_t DMA_PeripheralBaseAddr
Definition: stm32f4xx_dma.h:59
#define DMA1_Channel7
Definition: stm32f10x.h:1437
uint32_t DMA_M2M
Definition: stm32f10x_dma.h:83
#define DMA1_CHANNEL1_IT_MASK
Definition: stm32f30x_dma.c:92
#define DMA2_Channel2
Definition: stm32f10x.h:1439
#define DMA_DIR_PeripheralSRC
#define DMA1_CHANNEL5_IT_MASK
Definition: stm32f30x_dma.c:96
#define DMA1_CHANNEL3_IT_MASK
Definition: stm32f30x_dma.c:94
#define DMA2_CHANNEL4_IT_MASK
#define DMA1_Channel5
Definition: stm32f10x.h:1435
#define DMA_Mode_Normal
#define DMA1_CHANNEL2_IT_MASK
Definition: stm32f30x_dma.c:93
#define IS_DMA_M2M_STATE(STATE)
#define DMA2_CHANNEL2_IT_MASK
#define IS_DMA_MODE(MODE)
#define IS_DMA_ALL_PERIPH(PERIPH)
#define DMA2_Channel3
Definition: stm32f10x.h:1440
#define DMA_PeripheralDataSize_Byte
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
Initializes the DMAy Channelx according to the specified parameters in the DMA_InitStruct.
#define IS_DMA_CLEAR_FLAG(FLAG)
DMA Controller.
Definition: stm32f10x.h:798
#define IS_DMA_CONFIG_IT(IT)
__IO uint32_t CPAR
Definition: stm32f10x.h:802
#define DMA_MemoryInc_Disable
uint32_t DMA_Mode
Definition: stm32f4xx_dma.h:85
#define IS_DMA_CLEAR_IT(IT)
#define DMA1
Definition: stm32f4xx.h:2124
void DMA_ClearFlag(uint32_t DMAy_FLAG)
Clears the DMAy Channelx's pending flags.
__IO uint32_t CCR
Definition: stm32f10x.h:800
#define DMA1_CHANNEL4_IT_MASK
Definition: stm32f30x_dma.c:95
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
Checks whether the specified DMAy Channelx flag is set or not.
uint32_t DMA_BufferSize
Definition: stm32f4xx_dma.h:69
__IO uint32_t CNDTR
Definition: stm32f10x.h:801
uint32_t DMA_Priority
Definition: stm32f4xx_dma.h:90
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx)
Deinitializes the DMAy Channelx registers to their default reset values.
#define IS_DMA_PRIORITY(PRIORITY)
#define DMA1_CHANNEL6_IT_MASK
Definition: stm32f30x_dma.c:97
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
Checks whether the specified DMAy Channelx interrupt has occurred or not.
#define FLAG_Mask
Definition: stm32f30x_dma.c:88
#define IS_DMA_GET_FLAG(FLAG)
#define DMA2
Definition: stm32f4xx.h:2133
#define DMA1_CHANNEL7_IT_MASK
Definition: stm32f30x_dma.c:98
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
Enables or disables the specified DMAy Channelx interrupts.
This file contains all the functions prototypes for the DMA firmware library.
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx)
Returns the number of remaining data units in the current DMAy Channelx transfer. ...


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19