stm32f10x_dma.c
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1 
22 /* Includes ------------------------------------------------------------------*/
23 #include "stm32f10x_dma.h"
24 #include "stm32f10x_rcc.h"
25 
47 /* DMA1 Channelx interrupt pending bit masks */
48 #define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
49 #define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
50 #define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
51 #define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
52 #define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
53 #define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
54 #define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
55 
56 /* DMA2 Channelx interrupt pending bit masks */
57 #define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
58 #define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
59 #define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
60 #define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
61 #define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
62 
63 /* DMA2 FLAG mask */
64 #define FLAG_Mask ((uint32_t)0x10000000)
65 
66 /* DMA registers Masks */
67 #define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
68 
108 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
109 {
110  /* Check the parameters */
111  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
112 
113  /* Disable the selected DMAy Channelx */
114  DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
115 
116  /* Reset DMAy Channelx control register */
117  DMAy_Channelx->CCR = 0;
118 
119  /* Reset DMAy Channelx remaining bytes register */
120  DMAy_Channelx->CNDTR = 0;
121 
122  /* Reset DMAy Channelx peripheral address register */
123  DMAy_Channelx->CPAR = 0;
124 
125  /* Reset DMAy Channelx memory address register */
126  DMAy_Channelx->CMAR = 0;
127 
128  if (DMAy_Channelx == DMA1_Channel1)
129  {
130  /* Reset interrupt pending bits for DMA1 Channel1 */
131  DMA1->IFCR |= DMA1_Channel1_IT_Mask;
132  }
133  else if (DMAy_Channelx == DMA1_Channel2)
134  {
135  /* Reset interrupt pending bits for DMA1 Channel2 */
136  DMA1->IFCR |= DMA1_Channel2_IT_Mask;
137  }
138  else if (DMAy_Channelx == DMA1_Channel3)
139  {
140  /* Reset interrupt pending bits for DMA1 Channel3 */
141  DMA1->IFCR |= DMA1_Channel3_IT_Mask;
142  }
143  else if (DMAy_Channelx == DMA1_Channel4)
144  {
145  /* Reset interrupt pending bits for DMA1 Channel4 */
146  DMA1->IFCR |= DMA1_Channel4_IT_Mask;
147  }
148  else if (DMAy_Channelx == DMA1_Channel5)
149  {
150  /* Reset interrupt pending bits for DMA1 Channel5 */
151  DMA1->IFCR |= DMA1_Channel5_IT_Mask;
152  }
153  else if (DMAy_Channelx == DMA1_Channel6)
154  {
155  /* Reset interrupt pending bits for DMA1 Channel6 */
156  DMA1->IFCR |= DMA1_Channel6_IT_Mask;
157  }
158  else if (DMAy_Channelx == DMA1_Channel7)
159  {
160  /* Reset interrupt pending bits for DMA1 Channel7 */
161  DMA1->IFCR |= DMA1_Channel7_IT_Mask;
162  }
163  else if (DMAy_Channelx == DMA2_Channel1)
164  {
165  /* Reset interrupt pending bits for DMA2 Channel1 */
166  DMA2->IFCR |= DMA2_Channel1_IT_Mask;
167  }
168  else if (DMAy_Channelx == DMA2_Channel2)
169  {
170  /* Reset interrupt pending bits for DMA2 Channel2 */
171  DMA2->IFCR |= DMA2_Channel2_IT_Mask;
172  }
173  else if (DMAy_Channelx == DMA2_Channel3)
174  {
175  /* Reset interrupt pending bits for DMA2 Channel3 */
176  DMA2->IFCR |= DMA2_Channel3_IT_Mask;
177  }
178  else if (DMAy_Channelx == DMA2_Channel4)
179  {
180  /* Reset interrupt pending bits for DMA2 Channel4 */
181  DMA2->IFCR |= DMA2_Channel4_IT_Mask;
182  }
183  else
184  {
185  if (DMAy_Channelx == DMA2_Channel5)
186  {
187  /* Reset interrupt pending bits for DMA2 Channel5 */
188  DMA2->IFCR |= DMA2_Channel5_IT_Mask;
189  }
190  }
191 }
192 
202 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
203 {
204  uint32_t tmpreg = 0;
205 
206  /* Check the parameters */
207  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
208  assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
214  assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
215  assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
216  assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
217 
218 /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
219  /* Get the DMAy_Channelx CCR value */
220  tmpreg = DMAy_Channelx->CCR;
221  /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
222  tmpreg &= CCR_CLEAR_Mask;
223  /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
224  /* Set DIR bit according to DMA_DIR value */
225  /* Set CIRC bit according to DMA_Mode value */
226  /* Set PINC bit according to DMA_PeripheralInc value */
227  /* Set MINC bit according to DMA_MemoryInc value */
228  /* Set PSIZE bits according to DMA_PeripheralDataSize value */
229  /* Set MSIZE bits according to DMA_MemoryDataSize value */
230  /* Set PL bits according to DMA_Priority value */
231  /* Set the MEM2MEM bit according to DMA_M2M value */
232  tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
233  DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
234  DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
235  DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
236 
237  /* Write to DMAy Channelx CCR */
238  DMAy_Channelx->CCR = tmpreg;
239 
240 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
241  /* Write to DMAy Channelx CNDTR */
242  DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
243 
244 /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
245  /* Write to DMAy Channelx CPAR */
246  DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
247 
248 /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
249  /* Write to DMAy Channelx CMAR */
250  DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
251 }
252 
259 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
260 {
261 /*-------------- Reset DMA init structure parameters values ------------------*/
262  /* Initialize the DMA_PeripheralBaseAddr member */
263  DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
264  /* Initialize the DMA_MemoryBaseAddr member */
265  DMA_InitStruct->DMA_MemoryBaseAddr = 0;
266  /* Initialize the DMA_DIR member */
267  DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
268  /* Initialize the DMA_BufferSize member */
269  DMA_InitStruct->DMA_BufferSize = 0;
270  /* Initialize the DMA_PeripheralInc member */
272  /* Initialize the DMA_MemoryInc member */
273  DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
274  /* Initialize the DMA_PeripheralDataSize member */
276  /* Initialize the DMA_MemoryDataSize member */
278  /* Initialize the DMA_Mode member */
279  DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
280  /* Initialize the DMA_Priority member */
281  DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
282  /* Initialize the DMA_M2M member */
283  DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
284 }
285 
294 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
295 {
296  /* Check the parameters */
297  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
299 
300  if (NewState != DISABLE)
301  {
302  /* Enable the selected DMAy Channelx */
303  DMAy_Channelx->CCR |= DMA_CCR1_EN;
304  }
305  else
306  {
307  /* Disable the selected DMAy Channelx */
308  DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
309  }
310 }
311 
326 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
327 {
328  /* Check the parameters */
329  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
332  if (NewState != DISABLE)
333  {
334  /* Enable the selected DMA interrupts */
335  DMAy_Channelx->CCR |= DMA_IT;
336  }
337  else
338  {
339  /* Disable the selected DMA interrupts */
340  DMAy_Channelx->CCR &= ~DMA_IT;
341  }
342 }
343 
353 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
354 {
355  /* Check the parameters */
356  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
357 
358 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
359  /* Write to DMAy Channelx CNDTR */
360  DMAy_Channelx->CNDTR = DataNumber;
361 }
362 
372 {
373  /* Check the parameters */
374  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
375  /* Return the number of remaining data units for DMAy Channelx */
376  return ((uint16_t)(DMAy_Channelx->CNDTR));
377 }
378 
433 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
434 {
435  FlagStatus bitstatus = RESET;
436  uint32_t tmpreg = 0;
437 
438  /* Check the parameters */
439  assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
440 
441  /* Calculate the used DMAy */
442  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
443  {
444  /* Get DMA2 ISR register value */
445  tmpreg = DMA2->ISR ;
446  }
447  else
448  {
449  /* Get DMA1 ISR register value */
450  tmpreg = DMA1->ISR ;
451  }
452 
453  /* Check the status of the specified DMAy flag */
454  if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
455  {
456  /* DMAy_FLAG is set */
457  bitstatus = SET;
458  }
459  else
460  {
461  /* DMAy_FLAG is reset */
462  bitstatus = RESET;
463  }
464 
465  /* Return the DMAy_FLAG status */
466  return bitstatus;
467 }
468 
523 void DMA_ClearFlag(uint32_t DMAy_FLAG)
524 {
525  /* Check the parameters */
526  assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
527 
528  /* Calculate the used DMAy */
529  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
530  {
531  /* Clear the selected DMAy flags */
532  DMA2->IFCR = DMAy_FLAG;
533  }
534  else
535  {
536  /* Clear the selected DMAy flags */
537  DMA1->IFCR = DMAy_FLAG;
538  }
539 }
540 
595 ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
596 {
597  ITStatus bitstatus = RESET;
598  uint32_t tmpreg = 0;
599 
600  /* Check the parameters */
601  assert_param(IS_DMA_GET_IT(DMAy_IT));
602 
603  /* Calculate the used DMA */
604  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
605  {
606  /* Get DMA2 ISR register value */
607  tmpreg = DMA2->ISR;
608  }
609  else
610  {
611  /* Get DMA1 ISR register value */
612  tmpreg = DMA1->ISR;
613  }
614 
615  /* Check the status of the specified DMAy interrupt */
616  if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
617  {
618  /* DMAy_IT is set */
619  bitstatus = SET;
620  }
621  else
622  {
623  /* DMAy_IT is reset */
624  bitstatus = RESET;
625  }
626  /* Return the DMA_IT status */
627  return bitstatus;
628 }
629 
684 void DMA_ClearITPendingBit(uint32_t DMAy_IT)
685 {
686  /* Check the parameters */
687  assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
688 
689  /* Calculate the used DMAy */
690  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
691  {
692  /* Clear the selected DMAy interrupt pending bits */
693  DMA2->IFCR = DMAy_IT;
694  }
695  else
696  {
697  /* Clear the selected DMAy interrupt pending bits */
698  DMA1->IFCR = DMAy_IT;
699  }
700 }
701 
714 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
#define DMA1_Channel1
Definition: stm32f10x.h:1431
uint32_t DMA_MemoryInc
Definition: stm32f4xx_dma.h:76
#define FLAG_Mask
Definition: stm32f10x_dma.c:64
FlagStatus
Definition: stm32f4xx.h:706
#define DMA_Priority_Low
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
Enables or disables the specified DMAy Channelx.
#define DMA2_Channel4
Definition: stm32f10x.h:1441
FunctionalState
Definition: stm32f4xx.h:708
DMA Init structure definition.
Definition: stm32f4xx_dma.h:54
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
Sets the number of data units in the current DMAy Channelx transfer.
#define DMA_MemoryDataSize_Byte
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
Clears the DMAy Channelx's interrupt pending bits.
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx)
Deinitializes the DMAy Channelx registers to their default reset values.
#define DMA1_Channel1_IT_Mask
Definition: stm32f10x_dma.c:48
#define DMA1_Channel4
Definition: stm32f10x.h:1434
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define DMA1_Channel2
Definition: stm32f10x.h:1432
#define DMA_PeripheralInc_Disable
#define DMA1_Channel3
Definition: stm32f10x.h:1433
uint32_t DMA_MemoryDataSize
Definition: stm32f4xx_dma.h:82
#define IS_DMA_PERIPHERAL_INC_STATE(STATE)
void assert_param(int val)
#define IS_DMA_MEMORY_INC_STATE(STATE)
uint32_t DMA_DIR
Definition: stm32f4xx_dma.h:65
uint32_t DMA_PeripheralInc
Definition: stm32f4xx_dma.h:73
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
#define DMA1_Channel6_IT_Mask
Definition: stm32f10x_dma.c:53
#define DMA1_Channel2_IT_Mask
Definition: stm32f10x_dma.c:49
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
Enables or disables the specified DMAy Channelx interrupts.
#define DMA2_Channel3_IT_Mask
Definition: stm32f10x_dma.c:59
#define DMA2_Channel4_IT_Mask
Definition: stm32f10x_dma.c:60
uint32_t DMA_PeripheralDataSize
Definition: stm32f4xx_dma.h:79
#define IS_DMA_DIR(DIR)
#define DMA_M2M_Disable
__IO uint32_t CMAR
Definition: stm32f10x.h:803
uint32_t DMA_MemoryBaseAddr
Definition: stm32f10x_dma.h:54
Definition: stm32f4xx.h:706
enum FlagStatus ITStatus
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
Initializes the DMAy Channelx according to the specified parameters in the DMA_InitStruct.
#define DMA2_Channel5
Definition: stm32f10x.h:1442
#define IS_DMA_GET_IT(IT)
#define DMA1_Channel6
Definition: stm32f10x.h:1436
#define DMA1_Channel7_IT_Mask
Definition: stm32f10x_dma.c:54
#define IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define DMA2_Channel1
Definition: stm32f10x.h:1438
uint32_t DMA_PeripheralBaseAddr
Definition: stm32f4xx_dma.h:59
#define DMA1_Channel7
Definition: stm32f10x.h:1437
uint32_t DMA_M2M
Definition: stm32f10x_dma.h:83
#define DMA2_Channel2
Definition: stm32f10x.h:1439
#define DMA_DIR_PeripheralSRC
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx)
Returns the number of remaining data units in the current DMAy Channelx transfer. ...
This file contains all the functions prototypes for the RCC firmware library.
#define IS_DMA_BUFFER_SIZE(SIZE)
#define DMA_CCR1_EN
Definition: stm32f10x.h:3463
#define DMA1_Channel5
Definition: stm32f10x.h:1435
#define DMA_Mode_Normal
#define DMA1_Channel4_IT_Mask
Definition: stm32f10x_dma.c:51
#define IS_DMA_M2M_STATE(STATE)
#define IS_DMA_MODE(MODE)
#define IS_DMA_ALL_PERIPH(PERIPH)
#define DMA2_Channel3
Definition: stm32f10x.h:1440
#define DMA_PeripheralDataSize_Byte
#define DMA1_Channel5_IT_Mask
Definition: stm32f10x_dma.c:52
#define IS_DMA_CLEAR_FLAG(FLAG)
DMA Controller.
Definition: stm32f10x.h:798
#define IS_DMA_CONFIG_IT(IT)
#define CCR_CLEAR_Mask
Definition: stm32f10x_dma.c:67
__IO uint32_t CPAR
Definition: stm32f10x.h:802
#define DMA_MemoryInc_Disable
uint32_t DMA_Mode
Definition: stm32f4xx_dma.h:85
#define IS_DMA_CLEAR_IT(IT)
This file contains all the functions prototypes for the DMA firmware library.
#define DMA1
Definition: stm32f4xx.h:2124
void DMA_ClearFlag(uint32_t DMAy_FLAG)
Clears the DMAy Channelx's pending flags.
__IO uint32_t CCR
Definition: stm32f10x.h:800
#define DMA1_Channel3_IT_Mask
Definition: stm32f10x_dma.c:50
uint32_t DMA_BufferSize
Definition: stm32f4xx_dma.h:69
__IO uint32_t CNDTR
Definition: stm32f10x.h:801
uint32_t DMA_Priority
Definition: stm32f4xx_dma.h:90
#define IS_DMA_PRIORITY(PRIORITY)
#define DMA2_Channel5_IT_Mask
Definition: stm32f10x_dma.c:61
#define IS_DMA_GET_FLAG(FLAG)
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
Checks whether the specified DMAy Channelx flag is set or not.
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
Checks whether the specified DMAy Channelx interrupt has occurred or not.
#define DMA2_Channel2_IT_Mask
Definition: stm32f10x_dma.c:58
#define DMA2
Definition: stm32f4xx.h:2133
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
Fills each DMA_InitStruct member with its default value.
#define DMA2_Channel1_IT_Mask
Definition: stm32f10x_dma.c:57


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19